Electrostatic protection circuit, IO circuit and electronic equipment

Abstract

The invention provides an electrostatic protection circuit, an IO circuit and electronic equipment. A first end of a first protection unit is connected with a chip power supply, and a second end of the first protection unit is connected with a chip reference ground; the first end of the second protection unit is connected with the IO interface, and the second end of the second protection unit is connected with the chip reference ground; the first end of the third protection unit is connected with the chip power supply, and the second end of the third protection unit is connected with the IO interface; the protection unit is used for switching to a conducting state when the voltage difference between the first end and the second end of the protection unit is larger than a starting threshold value, and the conducting direction is from the high voltage end to the low voltage end. When electrostatic discharge occurs, two discharge paths are formed, so that the clamping voltage of the pin corresponding to the IO bus under the condition of electrostatic discharge is greatly reduced, the possibility that the clamping voltage is higher than the breakdown voltage of a chip system is reduced, an internal circuit of the chip is protected, and normal operation of the internal circuit is guaranteed.

Description

Technical Field

[0001] The present invention relates to the field of chips, and in particular to an electrostatic protection circuit, an IO circuit and an electronic device. Background Art

[0002] With the progress of science and the development of society, the application of integrated circuits (ICs) products is becoming more and more popular, involving more and more fields, and has brought positive effects on improving people's lives and improving work and study efficiency. In integrated circuits, the impact of electrostatic discharge (ESD) on chip reliability cannot be ignored, especially in today's deep submicron and nanotechnology, the destructive impact of electrostatic discharge from the external environment, human body, machinery, radiation field, etc. on IC is more significant.

[0003] Electrostatic discharge is the main factor causing electronic devices or circuit systems to be damaged by excessive electrical stress. This damage can cause permanent damage to the integrated circuit, thus affecting the circuit function and causing the electronic product to malfunction.

[0004] However, electrostatic discharge is usually caused by human or environmental factors and is difficult to avoid completely. Therefore, in addition to strengthening the control of static electricity accumulation in the workplace, it is necessary to add ESD protection structures to the integrated circuit to ensure the safety of the integrated circuit in the case of ESD. Summary of the invention

[0005] The object of the present invention is to provide an electrostatic protection circuit, an IO circuit and an electronic device to improve the above-mentioned problem.

[0006] In order to achieve the above purpose, the technical solution adopted by the embodiment of the present invention is as follows: In a first aspect, an embodiment of the present invention provides an electrostatic protection circuit, wherein the electrostatic protection circuit includes three protection units, namely a first protection unit, a second protection unit, and a third protection unit; A first end of the first protection unit is connected to a chip power supply, and a second end of the first protection unit is connected to a chip reference ground; A first end of the second protection unit is connected to the IO interface, and a second end of the second protection unit is connected to the chip reference ground; A first end of the third protection unit is connected to the chip power supply, and a second end of the third protection unit is connected to the IO interface; The protection unit is used to switch to a conducting state when the voltage difference between the first end and the second end of the protection unit is greater than a turn-on threshold, and the conducting direction is from the high voltage end to the low voltage end.

[0007] It should be noted that when electrostatic discharge occurs, by forming two discharge paths, the clamping voltage of the pin (PIN) corresponding to the IO bus in the case of electrostatic discharge is greatly reduced, reducing the possibility of the clamping voltage being higher than the breakdown voltage of the chip system, protecting the internal circuit of the chip and ensuring its normal operation.

[0008] It should also be noted that the activation threshold of the third protection unit is greater than the supply voltage of the chip power supply VDD. Therefore, under normal working conditions, even if the IO bus has power, the current on the IO bus can be prevented from flowing back to the chip power supply VDD through the third protection unit, thereby playing a role in preventing backflow.

[0009] Optionally, the third protection unit includes a first MOS tube and a second MOS tube; the gate of the first MOS tube and the first end of the first MOS tube are connected to the IO interface; the second end of the first MOS tube is connected to the first end of the second MOS tube; the gate of the second MOS tube and the second end of the second MOS tube are connected to the chip power supply. The first MOS tube and the second MOS tube are cascaded to ensure that they can form a discharge path during electrostatic discharge and can play a role in preventing backflow during normal operation.

[0010] Optionally, the third protection unit further includes a first resistor and a second resistor; one end of the first resistor is connected to the gate of the first MOS tube, and the other end of the first resistor is connected to the first end of the first MOS tube; one end of the second resistor is connected to the gate of the second MOS tube, and the other end of the second resistor is connected to the second end of the second MOS tube. By setting the first resistor and the second resistor, the trigger voltage corresponding to the GGNMOS-like trigger state in the third protection unit can be flexibly adjusted (and thus the turn-on threshold can be changed), so as to achieve the function of flexibly adjusting the electrostatic protection.

[0011] Optionally, the third protection unit includes a first MOS tube and a second MOS tube; the first end of the first MOS tube is connected to the IO interface; the second end of the first MOS tube is connected to the first end of the second MOS tube; the gate of the first MOS tube and the gate of the second MOS tube are both connected between the second end of the first MOS tube and the first end of the second MOS tube; the second end of the second MOS tube is connected to the chip power supply. The first MOS tube and the second MOS tube are cascaded to ensure that they can form a discharge path during electrostatic discharge and can play a role in preventing backflow during normal operation.

[0012] Optionally, the third protection unit further includes a first resistor and a second resistor; one end of the first resistor is connected to the gate of the first MOS tube, and one end of the second resistor is connected to the gate of the second MOS tube; the other end of the first resistor and the other end of the second resistor are both connected between the second end of the first MOS tube and the first end of the second MOS tube. By setting the first resistor and the second resistor, the trigger voltage corresponding to the GGNMOS-like trigger state in the third protection unit can be flexibly adjusted (and thus the turn-on threshold can be changed), so as to achieve the function of flexibly adjusting the electrostatic protection.

[0013] In a second aspect, an embodiment of the present invention provides an IO circuit, wherein the IO circuit includes an IO bus and the above-mentioned electrostatic protection circuit.

[0014] In a third aspect, an embodiment of the present invention provides an electronic device, and the electronic device includes: the above-mentioned IO circuit.

[0015] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0017] Figure 1 This is one of the structural schematic diagrams of the electrostatic protection circuit provided by an embodiment of the present invention.

[0018] Figure 2 The second structural schematic diagram of the electrostatic protection circuit provided in the embodiment of the present invention.

[0019] Figure 3 The third structural schematic diagram of the electrostatic protection circuit provided in the embodiment of the present invention.

[0020] Figure 4 The fourth structural schematic diagram of the electrostatic protection circuit provided in an embodiment of the present invention.

[0021] Figure 5 This is one of the structural schematic diagrams of the second protection unit provided in an embodiment of the present invention.

[0022] Figure 6 This is one of the structural schematic diagrams of the first protection unit provided in an embodiment of the present invention.

[0023] In the figure: 10 - first protection unit; 20 - second protection unit; 30 - third protection unit. DETAILED DESCRIPTION

[0024] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0025] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0026] It should be noted that similar reference numerals and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in the subsequent drawings. At the same time, in the description of the present invention, the terms "first", "second", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0027] It should be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0028] Some embodiments of the present invention are described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0029] In order to cope with the electrostatic discharge phenomenon, an embodiment of the present invention provides an electrostatic protection circuit, which can form two discharge paths between the chip power supply and the IO interface in both PD mode (Positive to VDD, the IO bus supplies positive electricity to the chip power supply) and ND mode (Negative to VDD, the IO bus supplies negative electricity to the chip power supply), thereby greatly reducing the clamping voltage of the pin (PIN) corresponding to the IO bus under electrostatic discharge conditions, reducing the possibility that the clamping voltage is higher than the breakdown voltage of the chip system, protecting the internal circuit of the chip, and ensuring its normal operation.

[0030] Specifically, please refer to Figure 1 and Figure 2 , Figure 1 One of the structural schematic diagrams of the electrostatic protection circuit provided by an embodiment of the present invention, Figure 2 The second structural diagram of the electrostatic protection circuit provided by the embodiment of the present invention. In the embodiment of the present invention, ① represents the first end of the corresponding device, and ② represents the second end of the corresponding device, which will not be described in detail hereinafter.

[0031] The electrostatic protection circuit includes three protection units, namely a first protection unit 10 , a second protection unit 20 and a third protection unit 30 .

[0032] A first terminal of the first protection unit 10 is connected to the chip power supply VDD, and a second terminal of the first protection unit 10 is connected to the chip reference ground VSS.

[0033] A first end of the second protection unit 20 is connected to the IO interface, and a second end of the second protection unit 20 is connected to the chip reference ground VSS.

[0034] A first end of the third protection unit 30 is connected to the chip power supply VDD, and a second end of the third protection unit 30 is connected to the IO interface.

[0035] The protection unit is used to switch to a conducting state when the voltage difference between the first terminal and the second terminal of the protection unit is greater than a turn-on threshold, and the conducting direction is from the high voltage terminal to the low voltage terminal.

[0036] It should be noted that the opening thresholds corresponding to different protection units may be different. Optionally, the opening thresholds corresponding to each protection unit are greater than the supply voltage of the chip power supply VDD. Optionally, the opening threshold is greater than 1.5 times the supply voltage of the chip power supply VDD.

[0037] like Figure 1 and Figure 2As shown, when the chip power supply VDD is in a power-off state, if the voltage difference between the IO interface and the chip power supply VDD is greater than the turn-on threshold, or the voltage difference between the chip power supply VDD and the IO interface is greater than the turn-on threshold, the first protection unit 10, the second protection unit 20 and the third protection unit 30 will all switch to the on state.

[0038] When the voltage difference between the IO interface and the chip power supply VDD is greater than the turn-on threshold, two PD current paths (PD1 and PD2 shown in the figure respectively) are formed between the IO interface and the chip power supply VDD as discharge paths; when the voltage difference between the chip power supply VDD and the IO interface is greater than the turn-on threshold, two ND current paths (ND1 and ND2 shown in the figure respectively) are formed between the IO interface and the chip power supply VDD as discharge paths. Among them, the current path PD1 and the current path ND1 are formed by the third protection unit 30, and the current path PD2 and the current path ND2 are formed by the first protection unit 10 and the second protection unit 20.

[0039] In the electrostatic protection circuit provided in the embodiment of the present invention, when electrostatic discharge occurs, two discharge paths are formed to greatly reduce the clamping voltage of the pin (PIN) corresponding to the IO bus under electrostatic discharge conditions, reduce the possibility of the clamping voltage being higher than the breakdown voltage of the chip system, protect the internal circuit of the chip, and ensure its normal operation.

[0040] It should also be noted that the turn-on threshold is greater than the supply voltage of the chip power supply VDD, so that under normal working conditions, even if the IO bus has power, the current on the IO bus can be prevented from flowing back to the chip power supply VDD through the third protection unit 30, thereby playing a role in preventing backflow.

[0041] Regarding the structure of the third protection unit 30, how to ensure that it can form a discharge path during electrostatic discharge and can play a role in preventing backflow during normal operation. The embodiment of the present invention also provides an optional implementation method, please continue to refer to Figure 1 .

[0042] The third protection unit 30 includes a first MOS transistor M1 and a second MOS transistor M2 .

[0043] The gate of the first MOS transistor M1 and the first end (either the source or the drain) of the first MOS transistor M1 are connected to the IO interface.

[0044] Optionally, a connection terminal is led out from the connection between the gate of the first MOS tube M1 and the first end of the first MOS tube M1 to serve as the second end of the third protection unit 30 and connected to the IO interface.

[0045] The second end (the other of the source and the drain) of the first MOS transistor M1 is connected to the first end (either of the source and the drain) of the second MOS transistor M2.

[0046] The gate of the second MOS transistor M2 and the second end (the other of the source and the drain) of the second MOS transistor M2 are connected to the chip power supply VDD.

[0047] Optionally, the gate of the second MOS transistor M2 and the second end of the second MOS transistor M2 are connected to the chip power supply VDD as the first end of the third protection unit 30 .

[0048] like Figure 1 As shown, when the voltage difference between the IO interface and the chip power supply VDD is greater than the turn-on threshold, the first MOS tube M1 works in the MOS tube conduction state, the second MOS tube M2 works in the GGNMOS-like trigger state, and the discharge path formed by the third protection unit 30 is PD1.

[0049] When the voltage difference between the chip power supply VDD and the IO interface is greater than the turn-on threshold, the second MOS tube M2 works in the MOS tube conduction state, the first MOS tube M1 works in the GGNMOS-like trigger state, and the discharge path formed by the third protection unit 30 is ND1.

[0050] It should be noted that, in the embodiment of the present invention, the trigger voltage corresponding to the GGNMOS-like trigger state is greater than the supply voltage of the chip power supply VDD, thereby avoiding the problem of current backflow under normal working conditions. It should be noted that the turn-on threshold of the protection unit is related to the trigger voltage corresponding to the GGNMOS-like trigger state therein.

[0051] exist Figure 1 On the basis of how to flexibly adjust the electrostatic protection capability, the embodiment of the present invention also provides an optional implementation method, please refer to Figure 3 , Figure 3 The third structural schematic diagram of the electrostatic protection circuit provided in the embodiment of the present invention.

[0052] The third protection unit 30 further includes a first resistor R1 and a second resistor R2.

[0053] One end of the first resistor R1 is connected to the gate of the first MOS transistor M1 , and the other end of the first resistor R1 is connected to the first end of the first MOS transistor M1 .

[0054] One end of the second resistor R2 is connected to the gate of the second MOS transistor M2 , and the other end of the second resistor R2 is connected to the second end of the second MOS transistor M2 .

[0055] In the embodiment of the present invention, by setting the first resistor R1 and the second resistor R2, the trigger voltage corresponding to the GGNMOS-like trigger state in the third protection unit is flexibly adjusted (and thus the turn-on threshold is changed), thereby achieving the function of flexibly adjusting electrostatic protection.

[0056] Regarding the structure of the third protection unit 30, how to ensure that it can form a discharge path during electrostatic discharge and can play a role in preventing backflow during normal operation. The embodiment of the present invention also provides an optional implementation method, please continue to refer to Figure 2 .

[0057] The third protection unit 30 includes a first MOS transistor M1 and a second MOS transistor M2 .

[0058] A first end (either a source or a drain) of the first MOS transistor M1 is connected to the IO interface.

[0059] Optionally, the first end of the first MOS transistor M1 serves as the second end of the third protection unit 30 and is connected to the IO interface.

[0060] The second end (the other of the source and the drain) of the first MOS transistor M1 is connected to the first end (either of the source and the drain) of the second MOS transistor M2.

[0061] The gate of the first MOS tube M1 and the gate of the second MOS tube M2 are both connected between the second end of the first MOS tube M1 and the first end of the second MOS tube M2.

[0062] The second end (the other of the source and the drain) of the second MOS transistor M2 is connected to the chip power supply VDD.

[0063] Optionally, the second end of the second MOS transistor M2 serves as the first end of the third protection unit 30 and is connected to the chip power supply VDD.

[0064] like Figure 2 As shown, when the voltage difference between the IO interface and the chip power supply VDD is greater than the turn-on threshold, the first MOS tube M1 works in a GGNMOS-like trigger state, the second MOS tube M2 works in a MOS tube conduction state, and the discharge path formed by the third protection unit 30 is PD1.

[0065] When the voltage difference between the chip power supply VDD and the IO interface is greater than the turn-on threshold, the second MOS tube M2 works in a GGNMOS-like trigger state, the first MOS tube M1 works in a MOS tube conduction state, and the discharge path formed by the third protection unit 30 is ND1.

[0066] It should be noted that, in the embodiment of the present invention, the trigger voltage corresponding to the GGNMOS-like trigger state is greater than the supply voltage of the chip power supply VDD, thereby avoiding the problem of current backflow under normal working conditions.

[0067] exist Figure 2 On the basis of how to flexibly adjust the electrostatic protection capability, the embodiment of the present invention also provides an optional implementation method, please refer to Figure 4 , Figure 4 The fourth structural schematic diagram of the electrostatic protection circuit provided in an embodiment of the present invention.

[0068] The third protection unit 30 further includes a first resistor R1 and a second resistor R2.

[0069] One end of the first resistor R1 is connected to the gate of the first MOS transistor M1, and one end of the second resistor R2 is connected to the gate of the second MOS transistor M2; The other end of the first resistor R1 and the other end of the second resistor R2 are both connected between the second end of the first MOS transistor M1 and the first end of the second MOS transistor M2.

[0070] In the embodiment of the present invention, by setting the first resistor R1 and the second resistor R2, the trigger voltage corresponding to the GGNMOS-like trigger state in the third protection unit is flexibly adjusted (and thus the turn-on threshold is changed), thereby achieving the function of flexibly adjusting electrostatic protection.

[0071] Please continue to refer to Figures 1 to 4 In an optional implementation, the substrate of the first MOS transistor M1 and the substrate of the second MOS transistor M2 are both connected to the chip reference ground VSS.

[0072] Optionally, the second protection unit 20 uses any one of a GGNMOS, a bipolar junction transistor (BJT) and a silicon controlled rectifier (SCR). GGNMOS is a grounded NMOS, generally referring to a MOS tube with a gate-source short circuit.

[0073] like Figures 1 to 4 As shown, the second protection unit 20 uses the fifth MOS tube M5, and the fifth MOS tube M5 is a GGNMOS tube. The gate of the fifth MOS tube M5 is connected to the first end (source) of the fifth MOS tube M5, and a connection terminal is led out at the connection between the two, as the second end of the second protection unit 20, connected to the chip reference ground VSS, and the second end (drain) of the fifth MOS tube M5 is used as the first end of the second protection unit 20, connected to the IO interface. The substrate of the fifth MOS tube M5 is connected to the chip reference ground VSS.

[0074] Please refer to Figure 5 , Figure 5 FIG. 1 is a schematic diagram of the structure of the second protection unit provided in an embodiment of the present invention. Figure 5 As shown, the second protection unit 20 may also adopt a first transistor BJT1 or a first SCR device SCR1.

[0075] A connection terminal is led out from the connection between the base of the first transistor BJT1 and the emitter of the first transistor BJT1 as the second end of the second protection unit 20, connected to the chip reference ground VSS; the collector of the first transistor BJT1 serves as the first end of the second protection unit 20, connected to the IO interface.

[0076] The first end of the first SCR device SCR1 serves as the first end of the second protection unit 20 and is connected to the IO interface; the second end of the first SCR device SCR1 serves as the second end of the second protection unit 20 and is connected to the chip reference ground VSS.

[0077] Based on the above, regarding the structure of the first protection unit, the embodiment of the present invention also provides an optional implementation method, please refer to Figure 6 , Figure 6 This is one of the structural schematic diagrams of the first protection unit provided in an embodiment of the present invention.

[0078] The first protection unit 10 includes a third MOS transistor M3, an inverter U1, a third resistor R3 and a first capacitor C1.

[0079] A connection terminal is connected between the positive power terminal of the inverter U1, one end of the third resistor R3 and the first end (source) of the third MOS tube M3, as the first end of the first protection unit 10, and is connected to the chip power supply VDD. The substrate of the third MOS tube M3 is connected to the chip reference ground VSS.

[0080] The positive electrode of the first capacitor C1 is connected to the other end of the third resistor R3, the input end of the inverter U1 is connected between the first capacitor C1 and the third resistor R3, and the output end of the inverter U1 is connected to the gate of the third MOS tube M3.

[0081] A connection terminal is led out from the connection of the negative power supply terminal of the inverter U1, the negative electrode of the first capacitor C1 and the second end (drain) of the third MOS tube M3 to serve as the second end of the first protection unit 10 and connected to the chip reference ground VSS.

[0082] The inverter U1 is used to output a high level when the voltage difference between the chip power supply VDD and the IO interface is greater than the turn-on threshold, and control the third MOS tube M3 to be turned on to form a current path ND2 as a discharge path.

[0083] The inverter U1 is used to output a low level when the voltage difference between the core IO interface and the chip power supply VDD is greater than the turn-on threshold, and the parasitic diode (parasitic diode) of the third MOS tube M3 is turned on to form a current path PD2 as a discharge path.

[0084] Please continue to refer to Figures 1 to 4 Optionally, the first protection unit 10 includes a fourth MOS tube M4 and a fourth resistor R4; The first end (drain) of the fourth MOS transistor M4 serves as the first end of the first protection unit 10 and is connected to the chip power supply VDD.

[0085] One end of the fourth resistor R4 is connected to the gate of the fourth MOS transistor M4 , and the other end of the fourth resistor R4 is connected to the second end (source) of the fourth MOS transistor M4 .

[0086] At the connection point between the fourth resistor R4 and the second end of the fourth MOS transistor M4, a connection terminal is led out to serve as the second end of the first protection unit 10, which is connected to the chip reference ground VSS.

[0087] It should be noted that, when the voltage difference between the IO interface and the chip power supply VDD is greater than the turn-on threshold, the parasitic diode (parasitic diode) of the fourth MOS tube M4 is turned on; when the voltage difference between the chip power supply VDD and the IO interface is greater than the turn-on threshold, the fourth MOS tube M4 works in a GGNMOS-like trigger state, which can ensure that the first protection unit 10 is in a conduction state.

[0088] An embodiment of the present invention further provides an IO circuit, which includes an IO bus and the above-mentioned electrostatic protection circuit, and the electrostatic protection circuit is connected to an IO interface on the IO bus.

[0089] An embodiment of the present invention further provides an electronic device, the electronic device comprising: the above-mentioned IO circuit. The electronic device may be a mobile phone device, a computer device, a drone device, etc., which are not limited here.

[0090] In summary, an electrostatic protection circuit, an IO circuit and an electronic device provided by an embodiment of the present invention, wherein the electrostatic protection circuit includes three protection units, namely a first protection unit, a second protection unit and a third protection unit; the first end of the first protection unit is connected to the chip power supply, and the second end of the first protection unit is connected to the chip reference ground; the first end of the second protection unit is connected to the IO interface, and the second end of the second protection unit is connected to the chip reference ground; the first end of the third protection unit is connected to the chip power supply, and the second end of the third protection unit is connected to the IO interface; the protection unit is used to switch to a conducting state when the voltage difference between its own first end and the second end is greater than the turn-on threshold, and the conduction direction is from the high voltage end to the low voltage end. When electrostatic discharge occurs, by forming two discharge paths, the clamping voltage of the pins corresponding to the IO bus in the case of electrostatic discharge is greatly reduced, and the possibility of the clamping voltage being higher than the breakdown voltage of the chip system is reduced, and the internal circuit of the chip is protected to ensure its normal operation.

[0091] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

[0092] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

Claims

1. An electrostatic protection circuit, characterized in that: The electrostatic protection circuit includes three protection units, namely a first protection unit, a second protection unit and a third protection unit; A first end of the first protection unit is connected to a chip power supply, and a second end of the first protection unit is connected to a chip reference ground; A first end of the second protection unit is connected to the IO interface, and a second end of the second protection unit is connected to the chip reference ground; A first end of the third protection unit is connected to the chip power supply, and a second end of the third protection unit is connected to the IO interface; The protection unit is used to switch to a conducting state when the voltage difference between the first end and the second end of the protection unit is greater than a turn-on threshold, and the conducting direction is from the high voltage end to the low voltage end.

2. The electrostatic protection circuit according to claim 1, characterized in that: The third protection unit includes a first MOS tube and a second MOS tube; The gate of the first MOS transistor and the first end of the first MOS transistor are connected to the IO interface; The second end of the first MOS tube is connected to the first end of the second MOS tube; The gate of the second MOS tube and the second end of the second MOS tube are connected to the chip power supply.

3. The electrostatic protection circuit according to claim 2, characterized in that: The third protection unit also includes a first resistor and a second resistor; One end of the first resistor is connected to the gate of the first MOS transistor, and the other end of the first resistor is connected to the first end of the first MOS transistor; One end of the second resistor is connected to the gate of the second MOS transistor, and the other end of the second resistor is connected to the second end of the second MOS transistor.

4. The electrostatic protection circuit according to claim 1, characterized in that: The third protection unit includes a first MOS tube and a second MOS tube; The first end of the first MOS tube is connected to the IO interface; The second end of the first MOS tube is connected to the first end of the second MOS tube; The gate of the first MOS tube and the gate of the second MOS tube are both connected between the second end of the first MOS tube and the first end of the second MOS tube; The second end of the second MOS tube is connected to the chip power supply.

5. The electrostatic protection circuit according to claim 4, characterized in that: The third protection unit also includes a first resistor and a second resistor; One end of the first resistor is connected to the gate of the first MOS transistor, and one end of the second resistor is connected to the gate of the second MOS transistor; The other end of the first resistor and the other end of the second resistor are both connected between the second end of the first MOS transistor and the first end of the second MOS transistor.

6. The electrostatic protection circuit according to claim 1, characterized in that: The second protection unit adopts any one of a GGNMOS tube, a BJT device or a SCR device.

7. The electrostatic protection circuit according to claim 1, characterized in that: The first protection unit includes a third MOS tube, an inverter, a third resistor and a first capacitor; A connection terminal is led out from the connection between the positive power supply terminal of the inverter, one end of the third resistor and the first end of the third MOS tube, as the first end of the first protection unit, and connected to the chip power supply; The positive electrode of the first capacitor is connected to the other end of the third resistor, the input end of the inverter is connected between the first capacitor and the third resistor, and the output end of the inverter is connected to the gate of the third MOS tube; A connection terminal is led out from the connection of the negative power supply terminal of the inverter, the negative electrode of the first capacitor and the second end of the third MOS tube as the second end of the first protection unit, which is connected to the chip reference ground.

8. The electrostatic protection circuit according to claim 1, characterized in that: The first protection unit includes a fourth MOS tube and a fourth resistor; The first end of the fourth MOS tube serves as the first end of the first protection unit and is connected to the chip power supply; One end of the fourth resistor is connected to the gate of the fourth MOS transistor, and the other end of the fourth resistor is connected to the second end of the fourth MOS transistor; A connection terminal is led out at the connection between the fourth resistor and the second end of the fourth MOS tube, serving as the second end of the first protection unit, and connected to the chip reference ground.

9. An IO circuit, characterized in that: The IO circuit includes an IO bus and the electrostatic protection circuit according to any one of claims 1 to 8.

10. An electronic device, characterized in that: The electronic device comprises: the IO circuit as claimed in claim 9.

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