Multi-mode power factor correction circuit, control circuit and self-adaptive switching method

Abstract

The invention provides a multi-mode boost power factor correction circuit and a control circuit and a self-adaptive switching method thereof. The control circuit comprises a current reference signal generation circuit which generates a current reference signal based on an input voltage feedback signal and a load feedback signal of a power factor correction circuit; and the driving control circuit is used for controlling the main power switch tube based on the current reference signal, so that the input current of the boost power factor correction circuit is changed along with the change of the current reference signal, and the boost power factor correction circuit is adaptively switched among a continuous current mode, a critical current mode and an intermittent current mode. Smooth transition of different modes can be achieved under different conditions, THD performance is optimized, and efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the field of electronics, and in particular but not limited to, a multi-mode boost power factor correction circuit, a control circuit thereof, and an adaptive switching method. Background Art

[0002] Figure 1 The boost PFC (step-up power factor correction) circuit diagram is shown. Traditional boost PFCs typically operate in either critical current mode (CRM) or continuous current mode (CCM) control, while operating in discontinuous current mode (DCM) at light loads.

[0003] When operating in critical current mode, a fixed on-time control is typically used. When operating in DCM at light loads, additional compensation is used to optimize total harmonic distortion (THD). Due to the discontinuous current, critical current mode control minimizes switching losses and freewheeling diode reverse recovery losses. However, when the load is high, the peak current increases, increasing power MOSFET losses, making it suitable for low-power applications.

[0004] Continuous current mode (CCM) operation typically uses single-cycle control. When operating in DCM at light loads, no additional THD optimization is performed. Because the current is continuous, CCM control increases switching losses and places high demands on the reverse recovery characteristics of the freewheeling diode, but it can relatively reduce peak current.

[0005] Whether choosing the CRM model or the CCM model, there are flaws.

[0006] In view of this, it is necessary to provide a new structure or control method to solve at least part of the above problems. Summary of the Invention

[0007] In response to at least one or more of the problems in the background technology, the present invention proposes a multi-mode boost PFC control method and circuit that can adaptively select an operating mode, which can adaptively switch between critical current mode, continuous current mode or discontinuous current mode to optimize circuit efficiency.

[0008] According to one aspect of the present invention, a control circuit for controlling a boost-type power factor correction circuit is proposed. The boost-type power factor correction circuit includes an inductor, a main power switch tube and a rectifier tube, wherein the first end of the inductor is coupled to the input end of the boost-type power factor correction circuit, the second end of the inductor is coupled to the first end of the main power switch tube and the first end of the rectifier tube, and the second end of the rectifier tube is coupled to the output end of the boost-type power factor correction circuit. The control circuit controls the conduction and shutdown of the main power switch tube. The control circuit includes: a current reference signal generating circuit, which generates a current reference signal based on an input voltage feedback signal, wherein the input voltage feedback signal represents the input voltage of the input end of the boost-type power factor correction circuit; and a drive control circuit, which controls the conduction of the main power switch tube based on the conduction control signal and controls the shutdown of the main power switch tube based on the current reference signal, so that the input current of the boost-type power factor correction circuit changes with the current reference signal, thereby realizing the adaptive switching of the boost-type power factor correction circuit between continuous current mode, critical current mode and discontinuous current mode.

[0009] In one embodiment, the drive control circuit includes: a conduction control circuit, which generates a conduction control signal, and turns on the main power switch tube when the inductor is demagnetized or the periodic signal is valid and is not limited by the maximum frequency; a shutdown control circuit, which receives a current detection signal and a current reference signal and outputs a shutdown control signal, wherein the current detection signal represents the current flowing through the inductor; and a trigger circuit, wherein a first input terminal of the trigger circuit is coupled to the output terminal of the conduction control circuit, a second input terminal of the trigger circuit is coupled to the output terminal of the shutdown control circuit, and the output terminal of the trigger circuit provides a switch control signal for controlling the conduction and shutdown of the main power switch tube.

[0010] In one embodiment, the conduction control circuit includes: an OR gate, wherein the first input terminal of the OR gate receives a demagnetization detection signal, and the second input terminal of the OR gate receives a periodic signal; and an AND gate, wherein the first input terminal of the AND gate is coupled to the output terminal of the OR gate, the second input terminal of the AND gate receives a maximum frequency control signal, and the output terminal of the AND gate provides a conduction control signal.

[0011] In one embodiment, the periodic signal is a clock signal, the current reference signal is a peak current reference signal, and the shutdown control circuit includes a current comparison circuit, which compares the current feedback signal and the peak current reference signal and outputs a shutdown control signal, wherein the current feedback signal is a superimposed signal of the current detection signal and the ramp signal.

[0012] In one embodiment, the periodic signal is a maximum off-time signal, the current reference signal is a peak current reference signal, the shutdown control circuit includes a current comparison circuit, the current comparison circuit compares the current detection signal and the peak current reference signal and outputs a shutdown control signal, and the period length of the maximum off-time signal is proportional to the input voltage of the boost power factor correction circuit.

[0013] In one embodiment, the current detection signal is proportional to the voltage drop across the current detection resistor.

[0014] In one embodiment, the current reference signal generating circuit further generates the current reference signal based on a load feedback signal, where the load feedback signal represents the load size at the output end of the boost power factor correction circuit.

[0015] In one embodiment, the load feedback signal is an integrated signal of the output voltage feedback signal.

[0016] In one embodiment, the current reference signal generating circuit includes an average current reference signal generating circuit, whose input terminal receives an input voltage feedback signal and a load feedback signal, and whose output terminal provides an average current reference signal, which is proportional to the input voltage feedback signal.

[0017] In one embodiment, the current reference signal generating circuit further includes: a peak current reference signal generating circuit, having an input terminal coupled to an output terminal of the average current reference signal generating circuit for receiving the average current reference signal Vcs_ref, and an output terminal providing a peak current reference signal Vcs_pk; wherein the average current reference signal Vcs_ref satisfies: Vcs_ref = K0*Vint*Vlfb / Vin_pk^2, where K0 is a constant, Vint is an input voltage feedback signal, Vlfb is a load feedback signal, and Vin_pk is an input voltage peak feedback signal; and the peak current reference signal satisfies: Vcs_pk = 2*Vcs_ref / Dc-Vcs_min, where Dc is an on-duty cycle when the inductor current is greater than zero in a switching cycle, and Vcs_min represents a minimum value of the inductor current in the switching cycle. When the current feedback signal reaches the peak current reference signal, the main power switch is turned off.

[0018] In one embodiment, the current reference signal generating circuit further includes an error compensation circuit, a first input terminal of which receives an average current reference signal, and a second input terminal of which receives a current detection signal. The error compensation circuit compensates and controls the error value between the average current reference signal and the current detection signal and outputs a current reference signal. When the current feedback signal reaches the current reference signal, the main power switch tube is turned off, wherein the average current reference signal Vcs_ref satisfies Vcs_ref = K0*Vint*Vlfb / Vin_pk^2, where K0 is a constant, Vint is the input voltage feedback signal, Vlfb is the load feedback signal, and Vin_pk is the input voltage peak feedback signal.

[0019] In one embodiment, the current reference signal generating circuit includes: a voltage divider circuit for sampling the voltage at the first end of the main power switch tube by voltage division; a voltage follower, whose input end is coupled to the output end of the voltage divider circuit; a low-pass filter circuit, whose input end is coupled to the output end of the voltage follower, and whose output end provides an input voltage feedback signal; and a peak sampling and holding circuit, whose input end is coupled to the output end of the low-pass filter circuit, and the peak sampling and holding circuit is used to sample and hold the peak value of the output end voltage of the low-pass filter circuit as the input voltage peak feedback signal.

[0020] In one embodiment, the current reference signal generating circuit further includes a comparison circuit for comparing the voltage at the output end of the voltage follower with the voltage at the output end of the low-pass filter circuit, and outputting a demagnetization detection signal.

[0021] In one embodiment, the current reference signal generating circuit includes a minimum current detection circuit, an input end of which receives a current detection signal, the current detection signal being proportional to the current flowing through the inductor, and the minimum current detection circuit includes a sample-and-hold circuit, which is configured to sample and hold the current detection signal when the main power switch tube switches from off to on, so as to obtain the minimum value of the inductor current in the switching cycle.

[0022] In one embodiment, the current reference signal generating circuit includes a duty cycle detection circuit, which includes: a first trigger, wherein a set input terminal of the first trigger receives a switch control signal, a reset input terminal of the first trigger receives a demagnetization detection signal, and an output terminal of the first trigger provides a time signal when the inductor current is greater than zero; and a calculation circuit, which receives the time signal Ton+Tdem when the inductor current is greater than zero and a switching period signal T, and obtains a conduction duty cycle Dc=(Ton+Tdem) / T.

[0023] According to another aspect of the present invention, a control circuit for controlling a boost-type power factor correction circuit is proposed. The boost-type power factor correction circuit includes an inductor, a main power switch tube and a rectifier tube, wherein the first end of the inductor is coupled to the input end of the boost-type power factor correction circuit, the second end of the inductor is coupled to the first end of the main power switch tube and the first end of the rectifier tube, and the second end of the rectifier tube is coupled to the output end of the boost-type power factor correction circuit. The control circuit controls the conduction and shutdown of the main power switch tube. The control circuit includes: a current reference signal generating circuit, which generates a current reference signal based on an input voltage feedback signal and a load feedback signal, wherein the input voltage feedback signal represents the input voltage of the input end of the boost-type power factor correction circuit, and the load feedback signal represents the load size of the output end of the boost-type power factor correction circuit; and a drive control circuit, which controls the conduction of the main power switch tube based on a demagnetization detection signal and a periodic signal, and controls the shutdown of the main power switch tube based on the current reference signal, wherein when the demagnetization detection signal or the periodic signal is valid and is not limited by the maximum frequency, the main power switch tube is turned on.

[0024] According to a third aspect of the present invention, a boost power factor correction circuit is provided, comprising a main power switch tube and a control circuit as described in any one of the above embodiments.

[0025] According to a fourth aspect of the present invention, an adaptive switching method for a multi-mode boost power factor correction circuit is proposed, the adaptive switching method comprising: generating a current reference signal based on an input voltage feedback signal and a load feedback signal, wherein the input voltage feedback signal represents the voltage at the input end of the boost power factor correction circuit, and the load feedback signal represents the load size at the output end of the boost power factor correction circuit; and generating a switch control signal based on the current reference signal for controlling the main power switch tube, so that the input current of the boost power factor correction circuit changes with the current reference signal, and the boost power factor correction circuit adaptively switches between continuous current mode, critical current mode and discontinuous current mode.

[0026] In one embodiment, the method further includes turning on the power switch tube when either the demagnetization detection signal or the periodic signal is valid and not limited by the maximum frequency, and turning off the power switch tube when the current feedback signal reaches the current reference signal.

[0027] In one embodiment, the method further includes obtaining a current reference signal Vcs_pk by the following calculation: Vcs_pk=2*Vcs_ref / Dc-Vcs_min, where Vcs_ref=K0*Vint*Vlfb / Vin_pk^2, Dc is the on-duty cycle of the inductor current greater than zero in the switching cycle, Vcs_min is the minimum value of the inductor current in the switching cycle, K0 is a constant, Vint is the input voltage feedback signal, Vlfb is the load feedback signal, and Vin_pk is the input voltage peak feedback signal; and when the current feedback signal reaches the current reference signal, the main power switch is turned off.

[0028] In one embodiment, the method further includes compensating and controlling the error value between the average current reference signal and the current detection signal to generate a current reference signal, wherein the average current reference signal Vcs_ref = K0*Vint*Vlfb / Vin_pk^2, K0 is a constant, Vint is the input voltage feedback signal, Vlfb is the load feedback signal, and Vin_pk is the input voltage peak feedback signal. When the current feedback signal reaches the current reference signal, the main power switch tube is turned off.

[0029] The multi-mode boost power factor correction circuit, its control circuit, and adaptive switching method proposed in the present invention do not require first determining the operating mode and then controlling it separately according to the operating mode. Instead, they achieve adaptive switching of the operating mode according to the input voltage and load status. They can automatically optimize the selection of each operating mode under different conditions to improve efficiency, reduce the characteristic requirements of the freewheeling diode, achieve smooth transition between different modes, and optimize THD performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The accompanying drawings are used to provide a further understanding of the present invention and, together with the description, to explain the embodiments of the present invention, but do not constitute a limitation of the present invention. In the accompanying drawings:

[0031] Figure 1 A boost power factor correction circuit is shown;

[0032] Figure 2 A boost power factor correction circuit according to an embodiment of the present invention is shown;

[0033] Figure 3 shows a driving control circuit according to an embodiment of the present invention;

[0034] Figure 4 A driving control circuit according to a specific embodiment of the present invention is shown;

[0035] Figure 5 shows a driving control circuit according to another embodiment of the present invention;

[0036] Figure 6 A boost power factor correction circuit system according to an embodiment of the present invention is shown;

[0037] Figure 7 The inductor current waveforms under different current modes in the boost power factor correction circuit are shown;

[0038] Figure 8 A current reference signal generating circuit according to an embodiment of the present invention is shown;

[0039] Figure 9 A feedback signal generating circuit according to an embodiment of the present invention is shown;

[0040] Figure 10 A minimum current detection circuit according to an embodiment of the present invention is shown;

[0041] Figure 11 A duty cycle detection circuit according to an embodiment of the present invention is shown;

[0042] Figure 12 shows a current reference signal generating circuit according to another embodiment of the present invention;

[0043] Figure 13 A flow chart of an adaptive switching method for a multi-mode boost power factor correction circuit according to an embodiment of the present invention is shown;

[0044] Figure 14 FIG. 4 shows a working waveform diagram according to an embodiment of the present invention. DETAILED DESCRIPTION

[0045] In order to further understand the present invention, preferred embodiments of the present invention are described below in conjunction with examples. However, it should be understood that these descriptions are only for further illustrating the features and advantages of the present invention, rather than limiting the claims of the present invention.

[0046] The description in this section focuses on a few typical embodiments only, and the present invention is not limited to the scope of the embodiments described. Combinations of different embodiments, replacement of certain technical features in different embodiments, and replacement of certain technical features in the embodiments with the same or similar prior art methods are also within the scope of the present invention.

[0047] "Coupled" or "connected" in this specification encompasses both direct and indirect connections. An indirect connection is a connection through an intermediate medium, such as a connection through an electrically conductive medium like a conductor, which may contain parasitic inductance or capacitance, or a connection through an intermediate circuit or component as described in the embodiments of this specification. An indirect connection may also include a connection through other active or passive devices that achieve the same or similar functions, such as a connection through circuits or components such as switches, signal amplifiers, and follower circuits. "Multiple" or "many" refers to two or more.

[0048] "Adaptive switching between continuous current mode, critical current mode, and discontinuous current mode" means there's no need to first determine the operating mode and then implement control based on the selected current operating mode. Adaptive mode adaptively switches between multiple modes without determining the operating mode. In contrast, in non-adaptive mode switching, the desired current operating mode must be determined based on conditions, and then control is performed based on the selected current operating mode. For example, in non-adaptive mode switching, a mode determination signal is used to determine the operating mode. For example, a logic signal is used to represent the current operating mode. When the logic signal is 1, CCM mode is selected and control is performed accordingly. When the logic signal is 0, DCM mode is selected and control is performed accordingly. When the logic signal is in a high-impedance state, CRM mode is selected, etc. Alternatively, other signals are used to indicate the selected operating mode and control is performed based on the selected operating mode. Adaptive mode, on the other hand, eliminates the need for mode indication signals, such as the logic signals described above, which indicate the operating mode and implement control accordingly. In AC-driven systems, it offers advantages such as smooth transitions between current operating modes.

[0049] Figure 2A boost power factor correction circuit 200 according to an embodiment of the present invention is shown. The boost power factor correction circuit 200 includes an inductor Lm, a main power switch Q1, a rectifier D1, an output capacitor Cout, and a control circuit 20. A first end of the inductor Lm is coupled to the input of the boost power factor correction circuit for obtaining an input voltage Vin. A second end of the inductor Lm is coupled to the first end of the main power switch Q1 and the first end of the rectifier D1. The second end of the main power switch Q1 is coupled to ground GND. A second end of the rectifier D1 is coupled to the output of the boost power factor correction circuit for providing an output voltage Vout, which is used to power a load Road. The output capacitor Cout is coupled in parallel between the second end of the rectifier D1 and the system ground GND. The rectifier D1 can be a diode, with the first end of the rectifier D1 serving as an anode and the second end of the rectifier D2 serving as a cathode. The rectifier D1 can also be a synchronous rectifier, such as a metal oxide semiconductor field effect transistor (MOSFET). The second terminal of the main power transistor Q1 is connected to ground GND, or to ground GND through a current sensing resistor. The main power transistor Q1 can be a MOSFET or other type of power transistor. The control terminal of the main power transistor Q1 is coupled to the output terminal of the control circuit 20. In the illustrated embodiment, the main power transistor Q1 is an N-type MOSFET, with a first terminal of the main power transistor Q1 being a drain, a second terminal of the main power transistor Q1 being a source, and a control terminal of the main power transistor Q1 being a gate. The control circuit 20 controls the on and off state of the main power switch Q1. The control circuit 20 includes a current reference signal generating circuit 21 and a drive control circuit 22. The current reference signal generating circuit 21 generates a current reference signal CS_ref based on an input voltage feedback signal Vint and a load feedback signal Vlfb. The input voltage feedback signal Vint represents the voltage at the input terminal of the boost power factor correction circuit, i.e., the input voltage Vin. The load feedback signal Vlfb represents the load at the output terminal of the boost power factor correction circuit. In one embodiment, the load feedback signal Vlfb can be obtained by detecting the average value of the output current Iload flowing through the load Road. In another embodiment, the load feedback signal Vlfb is an integral signal of the output voltage feedback signal. The driver control circuit 22 controls the turn-on timing of the main power switch Q1 based on the conduction control signal and controls the turn-off timing of the main power switch Q1 based on the current reference signal CS_ref, so that the input current of the boost power factor correction circuit 200 (such as the average or peak value of the current flowing through the inductor Lm) varies with the current reference signal CS_ref, thereby achieving a PFC function. In one embodiment, the current reference signal CS_ref is a peak current reference signal of the inductor. The driver control circuit 22 controls the turn-off of the main power switch based on the peak current reference signal, so that the peak value of the input current of the boost power factor correction circuit varies with the peak current reference signal.In another embodiment, the current reference signal CS_ref is an average current reference signal of the input current. The driver control circuit 22 controls the shutdown of the main power switch based on the average current reference signal, so that the average value of the input current of the boost power factor correction circuit changes with the average current reference signal. The driver control circuit 22 can also derive a peak current reference signal based on the average current reference signal.

[0050] In another embodiment, the current reference signal generating circuit may generate the current reference signal without receiving the load feedback signal.

[0051] Figure 3The present invention illustrates a drive control circuit 300 according to an embodiment of the present invention, which is configured to generate a switch control signal PWM based on a current reference signal CS_ref, a current detection signal CS, and a demagnetization detection signal ZCD to control the on and off of the main power switch Q1. The drive control circuit 300 includes a conduction control circuit 31, a shutdown control circuit 32, and a trigger circuit 33. The conduction control circuit 31 generates a conduction control signal DT, which is configured to set the trigger circuit 33 when the conduction control signal DT switches from an inactive state to an active state (e.g., a low level switches to a high level), thereby turning on the main power switch Q1. The shutdown control circuit 32 generates a shutdown control signal GD, which is configured to reset the trigger circuit 33 when the shutdown control signal GD switches from an inactive state to an active state (e.g., a low level switches to a high level), thereby turning off the main power switch Q1. The conduction control circuit 31 includes a logic circuit for receiving the demagnetization detection signal ZCD, a periodic signal, and a maximum frequency control signal fsmax, and generating a conduction control signal DT. The conduction control circuit 31 is configured to output a valid conduction control signal DT when the demagnetization detection signal ZCD or the periodic signal is valid and not subject to the maximum frequency limit, and when the maximum frequency control signal fsmax is valid. This signal is used to trigger the main power switch to conduct. The demagnetization detection signal ZCD indicates the moment when the current in the inductor Lm drops to zero, and the maximum frequency control signal fsmax limits the maximum switching frequency. When the maximum frequency control signal fsmax is in an inactive state, such as a low level, the main power switch is prohibited from conducting, otherwise the frequency will be too high. When the maximum frequency control signal fsmax is valid, the main power switch is permitted to conduct. The conduction control circuit 31 includes an OR gate 311 and an AND gate 312. The first input of OR gate 311 receives the demagnetization detection signal ZCD, the second input of OR gate 311 receives the periodic signal, and the output of OR gate 312 is coupled to the input of AND gate 312. The first input of AND gate 312 is coupled to the output of OR gate 311, the second input of AND gate 312 receives the maximum frequency control signal fsmax, and the output of AND gate 312 provides the conduction control signal DT. When either the demagnetization detection signal ZCD or the periodic signal is active, OR gate 311 outputs a valid value. If the maximum frequency control signal fsmax is active, the conduction condition is met, and a valid conduction control signal DT is output to turn on the main power switch Q1. If the first valid periodic signal triggers the switch to turn on, it operates in continuous current mode (CCM). If the first valid demagnetization detection signal ZCD triggers the switch to turn on, it operates in critical current mode (CRM). If the maximum frequency control signal fsmax is in an invalid state when the ZCD or periodic signal is in an effective state, the switch tube Q1 is turned on when the maximum frequency control signal fsmax is effective and the subsequent demagnetization detection signal ZCD is in an effective state, and then the system operates in a discontinuous current mode (DCM).Through such control logic, the system can automatically operate in one of the continuous current mode, critical current mode, or discontinuous current mode without having to determine the operating mode by judging the load size or other conditions, and can achieve adaptive switching between the three different current modes during the switching cycle. The "adaptive" here means that there is no need to first determine the specific current mode to operate in and then adopt different controls based on the current mode. The adaptive mode does not require the generation of a specific mode indication signal and can achieve seamless switching between the continuous current mode, critical current mode, and discontinuous current mode according to specific control. Of course, those skilled in the art will appreciate that the logic circuit in the conduction control circuit 31 can also use other logical transformation forms to achieve essentially the same logical function, so that when the inductor is demagnetized or the periodic signal is valid and is not limited by the maximum frequency, the main power switch tube is turned on.

[0052] The shutdown control circuit 32 receives the current sense signal CS and the current reference signal CS_ref and generates a shutdown control signal GD for controlling the shutdown of the main power switch. The current sense signal CS represents the current flowing through the inductor Lm. Preferably, the current sense signal is proportional to the current flowing through the inductor Lm. In one embodiment, the shutdown control circuit 32 may include a current comparison circuit for comparing the current feedback signal with a peak current reference signal and outputting the shutdown control signal GD. The current feedback signal is generated based on the current sense signal CS, so that the input current of the boost power factor correction circuit varies with the current reference signal. The first input terminal (set input terminal) of the trigger circuit 33 is coupled to the output terminal of the AND gate 312, that is, the output terminal of the conduction control circuit 31 for receiving the conduction control signal DT. The second input terminal (reset input terminal) of the trigger circuit 33 is coupled to the output terminal of the current comparison circuit for receiving the shutdown control signal GD. The output terminal of the trigger circuit 33 provides a switch control signal PWM for controlling the conduction and shutdown of the main power switch tube. When the conduction control signal DT is valid, the switch control signal PWM is in a first state (such as a high level) to control the conduction of the main power switch tube. When the shutdown control signal GD is switched to valid, the switch control signal PWM is in a second state (such as a low level) to control the shutdown of the main power switch tube. A driving circuit may be further included between the trigger circuit 33 and the control terminal of the main power switch tube for amplifying or converting the voltage value of the switch control signal PWM to generate a control signal (such as a low level) suitable for turning on and off the main power switch tube. Figure 6 The GATE terminal voltage shown in FIG1 has a waveform corresponding to the PWM signal waveform.

[0053] Figure 4 FIG. 4 shows a driving control circuit 400 according to a specific embodiment of the present invention. This embodiment is a fixed frequency solution. Figure 3In the drive control circuit 300 shown, the periodic signal in the drive control circuit 400 is a clock signal Clock. The shutdown control circuit compares the peak current reference signal Vcs_pk with the current feedback signal Vcsf to control the shutdown of the main power switch tube. In this embodiment, the current feedback signal Vcsf is a superimposed signal of the current detection signal and the ramp signal, wherein the current detection signal represents the current flowing through the inductor. In one embodiment, the current detection signal is proportional to the current flowing through the inductor. Specifically, the drive control circuit 400 includes an OR gate 411, an AND gate 412, a signal conversion circuit 421, an addition circuit 422, a current comparison circuit 423 and a trigger circuit 43. The OR gate 411 and the AND gate 412 constitute a conduction control circuit or a part of the conduction control circuit; the signal conversion circuit 421, the addition circuit 422 and the current comparison circuit 423 constitute a shutdown control circuit or a part of the shutdown control circuit. The first input of OR gate 411 receives the demagnetization detection signal ZCD, and the second input of OR gate 411 receives the clock signal Clock. The output of OR gate 411 is coupled to the first input of AND gate 412, the second input of AND gate 412 receives the maximum frequency control signal fsmax, and the output of AND gate 412 provides a conduction control signal. The clock signal Clock can be generated by a crystal oscillator circuit. The maximum frequency control signal fsmax can be generated by a preset delay based on the rising edge of the PWM signal, or by other techniques known in the art, to limit the switching frequency to a preset value. The conduction timing of the main power switch in the system determines the operating mode. If the system is turned on by the fixed-frequency logic clock signal Clock, the system operates in CCM mode. If the system is turned on by the demagnetization detection signal ZCD, and if it turns on during the first demagnetization, it operates in CRM mode. If the first demagnetization detection signal ZCD is valid, the conduction control signal is not switched to the valid state due to the maximum frequency control signal fsmax limiting the conduction control signal, and the ZCD signal subsequently triggers the conduction, the system operates in DCM mode. In addition, it is preferred that the peak current control of the fixed frequency system needs to add slope compensation. Figure 4The slope signal shown must be added to the current detection signal to ensure stable operation of the system. The DC component of the slope compensation is processed to 0, and no DC bias is formed on the peak current sampling value. The signal conversion circuit 421 is coupled to the current detection resistor to obtain a current detection signal representing the current flowing through the inductor. The current detection signal is input to the first input terminal of the adder circuit 422, and the slope signal (such as a periodic triangular wave slope with the same frequency as the clock signal Clock) is input to the second input terminal of the adder circuit 422. The output terminal of the adder circuit 422 is coupled to the first input terminal of the current comparison circuit 423 to provide a current feedback signal Vcsf. The second input terminal of the current comparison circuit 423 receives the peak current reference signal Vcs_pk provided by the current reference signal generation circuit. The current comparison circuit 423 is used to compare the current feedback signal Vcsf with the peak current reference signal Vcs_pk and output a shutdown control signal. When the current feedback signal Vcsf is greater than the peak current reference signal Vcs_pk, the shutdown control signal becomes valid, the trigger circuit 33 is reset, and the switch control signal PWM is converted from a high level to a low level, thereby shutting down the main power switch. In another embodiment, the signal conversion circuit 421 may not be included, and one input terminal of the adding circuit 422 may be directly electrically coupled to the current sensing terminal CS to obtain the current sensing signal.

[0054] Figure 5 FIG4 shows a drive control circuit 500 according to another embodiment of the present invention. Compared with the drive control circuit 400, the periodic signal received by the OR gate 511 in the drive control circuit 500 is the maximum off-time signal Toff_max, and the first input terminal of the current comparison circuit 522 receives the current detection signal Vcs directly proportional to the voltage drop CS on the current detection resistor. The current detection signal Vcs here can also be called a current feedback signal. Figure 4Like the current feedback signal Vcsf in , both are generated based on the inductor current flowing through the inductor. The period length of the maximum off-time signal Toff_max is proportional to the voltage Vint at the input terminal of the boost power factor correction circuit. The off-time control of this embodiment can ensure system stability without slope compensation. In one embodiment, the maximum off-time generation circuit includes a constant current source I0, a switch S3, a capacitor C0 and a comparison circuit 512. The constant current source I0 and the switch S3 are coupled in series between the voltage source VDD and the ground, and the control end of the switch S3 is controlled by the switch control signal PWM. The first end of the capacitor C0 is coupled to the coupling node of the constant current source I0 and the switch S3 and the first input terminal of the comparison circuit 512, the second end of the capacitor C0 is grounded, the second input terminal of the comparison circuit 512 receives the input voltage feedback signal Vint, and the output terminal of the comparison circuit 512 provides the maximum off-time signal Toff_max. When PWM switches from a high level to a low level, that is, when the main power switch is turned off, the constant current source I0 begins to charge the capacitor C0. When the voltage on the capacitor C0 exceeds the input voltage feedback signal Vint, the comparison circuit 512 outputs a high-level maximum off-time signal Toff_max. Thus, the maximum off-time signal Toff_max corresponds to an off-time Toff = C0 * Vint / I0. If the demagnetization time signal ZCD causes the conduction control signal DT to switch to an active state, the system operates in CRM mode. If the maximum off-time signal Toff_max changes to an effective value, triggering the conduction control signal DT to switch to an active state, the system operates in CCM mode. If the maximum frequency control signal fsmax is inactive when the ZCD or the maximum off-time signal Toff_max is active, the switch Q1 is turned on when the maximum frequency control signal fsmax is active and the demagnetization detection signal ZCD is subsequently active, and the system operates in DCM mode. If the output voltage of the boost PFC circuit is Vo, and the sampling signal is Vfb which is proportional to Vo, then according to the inductor volt-second balance principle, Vin*Ton=(Vo-Vin)*Toff, then Ton+Toff=Vo*Toff / Vin, combined with the above relationship, we have: Ton+Toff=(Vo*C0 / I0)*Vint / Vin=Ts. Obviously, Vo, C0, I0 are constant values, and Vint / Vin is a fixed ratio, then Ts is a constant value, that is, through Figure 5 The system implemented by the toff control logic is also close to the fixed-frequency system, but lacks slope compensation.

[0055] Figure 6A boost power factor correction circuit system according to an embodiment of the present invention is shown. The boost power factor correction circuit system includes an EMI (electromagnetic interference) filter circuit 61, a rectifier circuit 62, an input capacitor Cin, a boost power factor correction circuit 60, and an output capacitor Cout. The input end of the EMI filter circuit 61 inputs the AC power signal AC IN, and the output end of the EMI filter circuit 61 is coupled to the two input ends of the rectifier circuit 62. The two output ends of the rectifier circuit 62 are coupled to the two ends of the input capacitor Cin. The input capacitor Cin provides the input voltage Vin for the boost power factor correction circuit 60. The input voltage Vin is in the shape of a steamed bun wave. The rectifier circuit 62 shown in the figure includes a full-bridge rectifier circuit for converting an AC signal into a DC signal. The boost power factor correction circuit 60 utilizes a boost circuit (Boost), which includes an inductor Lm, a main power switch Q1, a rectifier D1, a control circuit 601 for controlling the main power switch Q1, an output voltage feedback circuit for sampling the output voltage Vout, and a sampling resistor Rcs for sampling the current flowing through the inductor Lm. A first end of the inductor Lm is coupled to the input of the boost power factor correction circuit 60 for receiving the input voltage Vin. A second end of the inductor Lm is coupled to the first end of the main power switch Q1 and the first end of the rectifier D1. A second end of the main power switch Q1 is coupled to ground GND. A second end of the rectifier D1 is coupled to the output capacitor Cout and constitutes the output of the boost power factor correction circuit 60 for providing the output voltage Vout. In the illustrated embodiment, a first end of the sampling resistor Rcs is coupled to the ground GND of the control circuit 601, and a second end of the sampling resistor Rcs is coupled to the low-side voltage terminal of the input capacitor Cin. Thus, the voltage at the second terminal of the sampling resistor Rcs is proportional to the current flowing through the inductor Lm and serves as the current sampling signal. In another embodiment, the sampling resistor may be coupled between the second terminal of the main power switch Q1 and ground GND. The output voltage Vout is controlled by the switching duty cycle of the main power switch Q1: Vout = Vin / (1-D), where D is the switching duty cycle of the main power switch Q1 during the switching cycle. The output voltage feedback circuit, consisting of voltage divider resistors R1 and R2, is used to generate an output voltage feedback signal proportional to the output voltage Vout. The control circuit 601 may have multiple ports: DRAIN, FB, GND, CS, and GATE. In the illustrated embodiment, port DRAIN is coupled to the second terminal of the inductor Lm, i.e., the first terminal of the main power switch Q1, and the first terminal of the rectifier D1, to obtain an input voltage feedback signal representing the value of the input voltage Vin based on the voltage at the first terminal of the main power switch Q1. In other embodiments, the control circuit may also be coupled to the first terminal of the inductor Lm to directly sample Vin to obtain the input voltage feedback signal. The port FB is used to obtain an output voltage feedback signal representing the output voltage Vout.Port GND is used to connect to the ground terminal GND, and port CS is used to obtain a current detection signal that is proportional to the current value flowing through the inductor Lm. Port GATE is used to provide a switch drive signal based on the input voltage feedback signal received by port DRAIN, the output voltage feedback signal received by port FB, and the current detection signal received by port CS, to control the on and off states of the main power switch tube Q1, and to adjust the input current and output voltage. The core of the power factor correction circuit is to control the input current amplitude to follow the change of the input AC voltage AC IN amplitude, so that the equivalent input impedance is in a purely resistive state. The present application generates a current reference signal based on the input voltage feedback signal and the load feedback signal, and then controls the corresponding current signal of the power factor correction circuit, such as the peak value of the inductor current or the average value in the switching cycle, to follow the current reference signal to achieve the power factor correction function.

[0056] In one embodiment, the control circuit obtains a load feedback signal based on the output voltage feedback signal. The load feedback signal is used to indicate the load magnitude. In one embodiment, the load feedback signal Vlfb is an integral signal of the output voltage feedback signal. The load feedback signal can also be a signal reflecting the load magnitude obtained by any method. To achieve a high power factor and optimize efficiency, an average current reference signal Vcs_ref representing the average inductor current value during one or several switching cycles can be used as a current reference signal and can satisfy the following formula:

[0057] Vcs_ref=K0* Vint*Vlfb / Vin_pk^2 (1)

[0058] Where K0 is a constant, Vint is the input voltage feedback signal, and Vin_pk is the input voltage peak feedback signal, representing the input voltage peak value, obtained based on the input voltage feedback signal. In one embodiment, the input voltage peak feedback signal Vin_pk is the input voltage peak value from half the power frequency to several power frequency cycles. The input voltage feedback signal Vint varies within a power frequency cycle, causing the average current reference signal Vcs_ref to track the changes in the input voltage Vin, thereby achieving power factor correction.

[0059] In other embodiments, the average current reference signal representing the average inductor current may be calculated differently from the method in Equation 1. While being proportional to the input voltage feedback signal Vint, the remaining calculation components may vary. For example, the exponent of the divisor portion of the input voltage peak feedback signal Vin_pk may not be equal to 2. In another embodiment, the input voltage peak feedback signal Vin_pk may be replaced by the average value of the input voltage Vin or another value representing the input voltage level, allowing the current reference signal Vcs_ref to vary with the average input voltage to achieve feedforward compensation. The current reference signal in Equation 1 may also include other compensation components, such as Vcs_ref = K0*Vint*Vlfb / Vin_pk^2 + Vbc, where Vbc is the signal used for compensation.

[0060] Figure 7 The inductor current waveform Vcs in different current modes in the boost power factor correction circuit is shown in FIG. Figure 2 The absolute value of the current sampling signal in the three different current modes. In all three current modes, the average inductor current satisfies the formula Vcs_ref = (Vcs_pk + Vcs_min) * Dc / 2. Vcs_pk is the peak current of the inductor, Vcs_min is the valley current immediately before the main power switch turns on, i.e., when the GATE signal at the control terminal of the main power switch switches from a low level to a high level (at time t0), and Dc is the current conduction duty cycle when the current is greater than zero.

[0061] In CCM mode (the first set of waveforms), the current conduction duty cycle Dc is 1, and the average current Vcs_ref = (Vcs_pk + Vcs_min) / 2, where Vcs_min is the Vcs signal immediately before the main power switch is turned on (when the signal GATE switches from a low level to a high level, time t0 in the figure).

[0062] In the CRM mode (the second set of waveforms), the current conduction duty cycle Dc is close to 1, Vcs_min=0, and the average current Vcs_ref=Vcs_pk / 2.

[0063] In DCM mode (the third set of waveforms), the current conduction duty cycle is Dc = (Ton + Tdem) / Ts, Vcs_min = 0, and the average current Vcs_ref = Vcs_pk * (Ton + Tdem) / Ts / 2, where Vcs_min is the Vcs signal sampled just before the main power switch is turned on (at time t0 in the figure), and at this time Vcs_min is close to 0.

[0064] In the above three current modes, the peak current Vcs_pk=2*Vcs_ref / Dc-Vcs_min(2)

[0065] Formula (2) combined with formula (1) above can achieve PFC by controlling the peak current reference value and controlling the turn-off moment of the main power switch based on the peak current reference value. There is no need to deliberately distinguish specific operating modes; only Dc, Vcs_min, and Vcs_ref need to be accurately sampled or calculated to automatically achieve adaptive switching and perfect unification of the three operating modes, and a smooth transition can be achieved within one power frequency cycle or half a power frequency cycle.

[0066] Figure 8 A current reference signal generating circuit 800 according to an embodiment of the present invention is shown. The current reference signal generating circuit 800 includes an average current reference signal generating circuit 81 and a peak current reference signal generating circuit 82. The average current reference signal generating circuit 81 receives an input voltage feedback signal Vint, a load feedback signal Vlfb, and an input voltage peak feedback signal Vin_pk at its input terminal, and provides an average current reference signal Vcs_ref at its output terminal. The average current reference signal Vcs_ref is proportional to the input voltage feedback signal Vint. The current reference signal generating circuit 800 may further include a feedback signal generating circuit for detecting and outputting an input voltage feedback signal Vint reflecting the input voltage Vin and an input voltage peak feedback signal Vin_pk reflecting the input voltage peak. The input voltage peak feedback signal Vin_pk may be generated based on the input voltage feedback signal Vint. The current reference signal generating circuit 800 may further include a load feedback signal generating circuit for providing a load feedback signal Vlfb representing the load magnitude. In one embodiment, the average current reference signal Vcs_ref satisfies: Vcs_ref=K0*Vint*Vlfb / Vin_pk^2, where K0 is a constant.

[0067] An input terminal of the peak current reference signal generating circuit 82 is coupled to the output terminal of the average current reference signal generating circuit 81 for receiving the average current reference signal Vcs_ref. A second input terminal and a third input terminal of the peak current reference signal generating circuit 82 receive the on-duty cycle signal Dc and the minimum current detection signal Vcs_min. The output terminal of the peak current reference signal generating circuit 82 provides a peak current reference signal Vcs_pk. The current reference signal generating circuit 800 may further include a minimum current detection circuit for detecting and outputting a minimum current detection signal Vcs_min representing the minimum value of the inductor current during a switching cycle. The minimum current is typically the current immediately before the main power switch turns on. The current reference signal generating circuit 800 may further include a duty cycle detection circuit for generating an on-duty cycle signal Dc representing the on-duty cycle of the inductor current greater than zero during the switching cycle. In one embodiment, the Vcs_pk peak current reference signal satisfies the following equation: Vcs_pk = 2*Vcs_ref / Dc - Vcs_min. When the current flowing through the inductor reaches the value corresponding to the peak current reference signal Vcs_pk, that is, when the current feedback signal ( Figure 4 Vcsf or Figure 5 When the Vcs (in the middle) reaches the peak current reference signal Vcs_pk, the main power switch tube is turned off.

[0068] Figure 9 FIG. 1 shows a feedback signal generating circuit 900 according to an embodiment of the present invention, which is used to generate an input voltage feedback signal Vint, an input voltage peak feedback signal Vin_pk, and a demagnetization detection signal ZCD. The feedback signal generating circuit 900 is coupled to the first terminal DRAIN (e.g., Figure 6The circuit 900 detects the voltage at the first terminal of the main power switch and obtains an input voltage feedback signal Vint, an input voltage peak feedback signal Vin_pk, and a demagnetization detection signal ZCD based on the voltage detected at the first terminal of the main power switch. In the illustrated embodiment, the feedback signal generating circuit 900 includes a voltage divider circuit (shown as resistors R3 and R4), a voltage follower 91, a low-pass filter circuit (composed of R5 and C1), a peak sample-and-hold circuit 93, and a comparison circuit 92. The voltage divider circuit is used to divide and sample the voltage DRAIN at the first terminal of the main power switch. The input of the voltage divider circuit is coupled to the first terminal DRAIN of the main power switch, and the output of the voltage divider circuit is coupled to the input of the voltage follower 91. The output of the voltage follower 91 provides a voltage signal Vdrain proportional to the voltage at the first terminal DRAIN of the main power switch. The output of the voltage follower 91 is coupled to the input of the low-pass filter circuit. The voltage signal Vdrain is low-pass filtered by the low-pass filter circuit to obtain the average voltage at the first input terminal of the inductor Lm during the switching cycle. The input voltage feedback signal Vint is provided at the output of the low-pass filter circuit. The output of the low-pass filter circuit is coupled to the input of a peak sampling and holding circuit 93. Peak sampling and holding circuit 93 samples and holds the peak value of the input voltage feedback signal Vint. The output of peak sampling and holding circuit 93 provides an input voltage peak feedback signal Vin_pk. This peak value can be a peak value within half a power frequency cycle, or a peak value within one or more power frequency cycles. A first input of a comparison circuit 92 is coupled to the output of a voltage follower 91, and a second input of the comparison circuit 92 is coupled to the output of the low-pass filter circuit. The comparison circuit 92 compares the voltage at the output of the voltage follower 91 with the voltage at the output of the low-pass filter circuit and outputs a demagnetization detection signal ZCD. During a switching cycle, when the detection voltage Vdrain at the DRAIN terminal of the main power switch tube equals the switching cycle average voltage Vint, indicating the moment when the inductor current drops to zero, the comparison circuit 92 outputs the demagnetization detection signal ZCD. In alternative embodiments, the resistor divider circuit can also be omitted.

[0069] Figure 10 FIG. 1 shows a minimum current detection circuit 1000 according to an embodiment of the present invention. The minimum current detection circuit 1000 is based on Figure 6In the illustrated embodiment, the current detection signal CS captures the minimum value of the inductor current during a switching cycle. The current detection signal CS is negative relative to ground GND. Therefore, the minimum current detection circuit 1000 includes a signal conversion circuit 101 that inverts the current detection signal CS into a positive voltage signal. This positive current detection signal is proportional to the current flowing through the inductor. The signal conversion circuit 101 includes resistors R6 and R7, and an op amp U1. A first end of resistor R6 is coupled to the current detection terminal CS for acquiring the current detection signal. A second end of resistor R6 is coupled to a first input terminal of the op amp U1 and a first end of resistor R7. The second input terminal of the op amp U1 is grounded. A second end of resistor R7 is connected to the output terminal of the op amp U1 and provides an inverted positive current detection signal proportional to the value of R7 / R6. The output terminal of the signal conversion circuit 101 is connected to the first end of the first switch S1. The second end of the first switch S1 is coupled to the first end of the second switch S2 and the first end of the capacitor C2. The second end of the capacitor C2 is grounded. The second end of the second switch S2 is coupled to the first end of the capacitor C3. The second end of the capacitor C3 is grounded. The control terminal of the first switch S1 is coupled to the output terminal of the inverter circuit 102, and the input terminal of the inverter circuit 102 receives the switch control signal PWM. The control terminal of the second switch S2 is controlled by the switch control signal PWM. The switch S2 and the capacitor C3 form a sample-and-hold circuit. When the switch control signal PWM is zero, that is, when the main power switch Q1 is off, the switch S1 is turned on and the positive current detection signal is sampled. When the PWM signal switches from zero to "1", that is, when Q1 switches from off to on (corresponding to Figure 7 At time t0), the switch S1 is turned off, the switch S2 is turned on, and the sample-and-hold circuit samples and holds the forward current detection signal at this time through the capacitor C3 to obtain the minimum current detection signal Vcs_min.

[0070] Figure 11The figure shows a duty cycle detection circuit 1100 according to an embodiment of the present invention. The duty cycle detection circuit 1100 is used to detect the on-duty cycle. The duty cycle detection circuit 1100 includes a trigger circuit 111 (or a first trigger) and a calculation circuit 112. The set input terminal of the trigger circuit 111 receives the switch control signal PWM, and the reset input terminal of the trigger circuit 111 receives the demagnetization detection signal ZCD. When the PWM signal switches from a low level to a high level and the main power switch tube is turned on, the output terminal of the trigger circuit 111 is set high until the demagnetization detection signal ZCD switches from a low level to a high level, that is, the inductor current drops to zero. In this way, the output terminal of the trigger circuit 111 provides a time signal Ton+Tdem that represents the time when the current in the inductor is greater than zero. The input terminal of the calculation circuit 112 is coupled to the output terminal of the trigger circuit 111 for receiving the time signal Ton+Tdem indicating that the inductor current is greater than zero, and the switching period signal T. The calculation circuit 112 calculates the ratio of Ton+Tdem to the switching period duration T to obtain the on-duty ratio Dc=(Ton+Tdem) / T. The switching period signal T can be obtained by receiving the switching control signal PWM.

[0071] The circuits 900 - 1100 in the above embodiments are for illustration only, and each detection circuit or calculation circuit may have other forms.

[0072] The current reference signal generation circuit can calculate an average current reference signal and a peak current reference signal based on the signals Vint, Vlfb, Vin_pk, Vcs_min, and Dc obtained by the aforementioned circuit. The average current reference signal Vcs_ref satisfies the following equation: Vcs_ref = K0 * Vint * Vlfb / Vin_pk^2, and the peak current reference signal satisfies the following equation: Vcs_pk = 2 * Vcs_ref / Dc - Vcs_min = K * Vint * Vlfb / Vin_pk^2 / Dc - Vcs_min, where K = 2K0. This calculation can be performed using any suitable circuit, such as an FPGA or other digital circuit, or an analog calculation circuit. A current comparison circuit then compares the peak current reference signal Vcs_pk with the current feedback signal to control the turn-off timing of the main power switch, ensuring that the peak value of the input current varies in accordance with the peak current reference signal.

[0073] Figure 12 FIG. 1 shows another current reference signal generating circuit 1200 according to an embodiment of the present invention. The current reference signal generating circuit 1200 includes an average current reference signal generating circuit 1201 and an error compensation circuit 1202. The average current reference signal generating circuit 1201 can refer to Figure 8 and Figure 9In one embodiment, the average current reference signal Vcs_ref = K0*Vint*Vlfb / Vin_pk^2, where K0 is a constant, Vint is the input voltage feedback signal, Vlfb is the load feedback signal, and Vin_pk is the input voltage peak feedback signal. Of course, the average current reference signal Vcs_ref can also be calculated using different methods so that it is proportional to the input voltage feedback signal Vint. The first input terminal of the error compensation circuit 1202 receives the average current reference signal Vcs_ref, and the second input terminal receives the current detection signal CS. In the illustrated embodiment, the error compensation circuit 1202 includes an error amplifier 1221 and a capacitor C1 coupled to the output terminal of the error amplifier 1221. The error compensation circuit 1202 amplifies and compensates the error value between the average current reference signal Vcs_ref and the current detection signal CS, and outputs a current reference signal Vcs_pk. The current reference signal Vcs_pk is a peak current reference signal. When the current flowing through the inductor reaches the value corresponding to the peak current reference signal Vcs_pk, that is, when the current feedback signal ( Figure 4 Vcsf or Figure 5 When the Vcs (in the middle) reaches the peak current reference signal Vcs_pk, the main power switch tube is turned off.

[0074] Figure 13 FIG1 shows a flow chart of an adaptive switching method for a multi-mode boost power factor correction circuit according to an embodiment of the present invention. Preferably, the boost power factor correction circuit may include: Figure 2The inductor Lm, main power switch Q1 and rectifier D1 are shown, wherein the first end of the inductor Lm is coupled to the input end of the boost power factor correction circuit for obtaining the input voltage Vin, the second end of the inductor Lm is coupled to the first end of the main power switch Q1 and the first end of the rectifier D1, and the second end of the rectifier D1 is coupled to the output end of the boost power factor correction circuit for providing the output voltage Vout. The adaptive switching method includes step 1301: generating a current reference signal CS_ref based on the input voltage feedback signal Vint and the load feedback signal Vlfb, wherein the input voltage feedback signal Vint represents the input voltage at the input end of the boost power factor correction circuit, and the load feedback signal Vlfb represents the load size at the output end of the boost power factor correction circuit. Preferably, the current reference signal CS_ref is the peak current reference signal Vcs_pk. In other embodiments, the current reference signal CS_ref can also be an average current signal or a current reference signal at a specific moment in the switching cycle. In one embodiment, the peak current reference signal Vcs_pk can be obtained by the following calculation: Vcs_pk = 2*Vcs_ref / Dc-Vcs_min, where Vcs_ref is the average current reference signal. In one embodiment, Vcs_ref = K0*Vint*Vlfb / Vin_pk / Vin_pk, where Vint is the input voltage feedback signal and Vin_pk is the input voltage peak feedback signal, which can be obtained by Figure 9 The circuit shown in the figure is obtained. Vlfb is the load feedback signal, which can be obtained by integrating the output voltage feedback signal. Dc is the conduction duty cycle of the inductor current greater than zero in the switching cycle, which can be obtained by Figure 11 Vcs_min is the minimum value of the inductor current in the switching cycle, which can be obtained by Figure 10 The circuit shown in FIG. K0 is a constant. Based on the above signals, a calculation circuit calculates a peak current reference signal. When the current flowing through the inductor reaches the value corresponding to the peak current reference signal, the main power switch is turned off. In another embodiment, the average current reference signal and the current detection signal can also be error-compensated to obtain the peak current reference signal.

[0075] The adaptive switching method includes, in step 1302: generating a switch control signal PWM based on a current reference signal CS_ref for controlling the turn-off moment of the main power switch tube, so that the input current of the boost power factor correction circuit changes with the change of the current reference signal CS_ref, and the boost power factor correction circuit adaptively switches between continuous current mode, critical current mode and discontinuous current mode. In one embodiment, generating the switch control signal PWM includes turning on the power switch tube when either the demagnetization detection signal or the periodic signal is valid and is not within the maximum frequency limit, and turning off the power switch tube when the current feedback signal reaches the current reference signal. For a specific embodiment, see Figure 4 and Figure 5 Example of .

[0076] Through the above control method, it is possible to automatically and seamlessly switch between the continuous current mode, the critical current mode and the discontinuous current mode according to the load state without explicitly determining the current mode in which the system needs to work.

[0077] Figure 14 The working waveform diagram according to an embodiment of the present invention is shown. The first signal Vin is the bus voltage after rectification and filtering of the industrial frequency AC mains, which serves as the input voltage Vin of the boost power factor correction circuit; the second signal is the current waveform Vcs flowing through the inductor Lm corresponding to different input voltages Vin. By zooming in on the time axis of the time periods under different input voltages Vin in half a power frequency cycle (corresponding to a steamed bun wave), the main power switch tube control terminal signal GATE, input signal Vin and current signal Vcs in multiple switching cycles can be seen. When the input signal Vin is low, the boost power factor correction circuit operates in discontinuous current mode (DCM). In an application embodiment, when operating in the first 5% and last 5% of the half power frequency cycle, the boost power factor correction circuit operates in DCM mode. When operating in the middle stage of the half power frequency cycle, the input signal Vin is in the highest value range, and the boost power factor correction circuit operates in continuous current mode CCM. When the input signal Vin is at an appropriate intermediate value, at a stage between CCM and DCM, the boost power factor correction circuit operates in critical current mode (CRM). In this way, when the input voltage Vin continuously changes, the boost power factor correction circuit adaptively transitions and switches smoothly between DCM, CRM, and CCM.

[0078] The adaptive mode of the above embodiment allows for minimal variation between adjacent switching cycles within half a power frequency cycle, ensuring good continuity and stable control, enabling smooth transitions between different modes and optimizing THD performance. This embodiment offers the advantages of CCM operation under heavy loads and CRM / DCM operation under light loads. It optimizes the selection of each operating mode under different conditions, thereby improving efficiency and reducing the requirements for the freewheeling diode's characteristics.

[0079] Those skilled in the art should know that the logic controls such as "high level" and "low level", "set" and "reset", "AND gate" and "OR gate", "non-inverting input terminal" and "inverting input terminal" in the logic control involved in the specification or drawings can be interchanged or changed, and the same function or purpose as the above embodiment can be achieved by adjusting the subsequent logic control. For example, the AND gate may include a typical logic circuit that can execute the "AND" relationship, or it may include a combination logic circuit that can execute the "AND" relationship formed by combining multiple types of logic circuits. Similar expressions such as "when..." in this application are intended to illustrate the control logic. In order to eliminate signal glitches or to stabilize the control, the execution of the previous and next features in the actual control may be delayed for a certain period of time or be mixed with other controls.

[0080] The description and application of the present invention here are illustrative and are not intended to limit the scope of the present invention to the above-mentioned embodiments. The relevant descriptions of the effects or advantages involved in the specification may not be reflected in the actual experimental examples due to the uncertainty of specific condition parameters or other factors, and the relevant descriptions of the effects or advantages are not used to limit the scope of the invention. Variations and changes to the embodiments disclosed here are possible, and the replacement of the embodiments and various equivalent components are well known to those of ordinary skill in the art. It should be clear to those skilled in the art that, without departing from the spirit or essential characteristics of the present invention, the present invention can be implemented in other forms, structures, arrangements, proportions, and with other components, materials and parts. Without departing from the scope and spirit of the present invention, other variations and changes can be made to the embodiments disclosed here.

Claims

1. A control circuit for controlling a boost power factor correction circuit, the boost power factor correction circuit comprising an inductor, a main power switch tube and a rectifier tube, wherein a first end of the inductor is coupled to an input end of the boost power factor correction circuit, a second end of the inductor is coupled to a first end of the main power switch tube and a first end of the rectifier tube, and a second end of the rectifier tube is coupled to an output end of the boost power factor correction circuit, the control circuit controls the on and off of the main power switch tube, and the control circuit comprises: A current reference signal generating circuit generates a current reference signal based on an input voltage feedback signal, wherein the input voltage feedback signal represents an input voltage at an input end of the boost power factor correction circuit; as well as The driving control circuit controls the conduction of the main power switch tube based on the conduction control signal, and controls the shutdown of the main power switch tube based on the current reference signal, so that the input current of the boost power factor correction circuit changes with the current reference signal, and realizes the adaptive switching of the boost power factor correction circuit among the continuous current mode, the critical current mode and the discontinuous current mode.

2. The control circuit as claimed in claim 1, wherein the drive control circuit comprises: The conduction control circuit generates a conduction control signal, and when the inductor is demagnetized or the periodic signal is valid and not subject to the maximum frequency limit, the main power switch tube is turned on; A shutdown control circuit receives a current detection signal and a current reference signal, and outputs a shutdown control signal, wherein the current detection signal represents a current flowing through the inductor; as well as A trigger circuit, wherein the first input terminal of the trigger circuit is coupled to the output terminal of the conduction control circuit, the second input terminal of the trigger circuit is coupled to the output terminal of the shutdown control circuit, and the output terminal of the trigger circuit provides a switch control signal for controlling the conduction and shutdown of the main power switch tube.

3. The control circuit as claimed in claim 2, wherein the conduction control circuit comprises: An OR gate, wherein a first input terminal of the OR gate receives a demagnetization detection signal, and a second input terminal of the OR gate receives a periodic signal; as well as The AND gate has a first input terminal coupled to the output terminal of the OR gate, a second input terminal of the AND gate receiving a highest frequency control signal, and an output terminal of the AND gate providing a conduction control signal.

4. The control circuit as described in claim 2, wherein the periodic signal is a clock signal, the current reference signal is a peak current reference signal, the shutdown control circuit includes a current comparison circuit, the current comparison circuit compares the current feedback signal and the peak current reference signal and outputs a shutdown control signal, wherein the current feedback signal is a superposition signal of the current detection signal and the ramp signal.

5. A control circuit as described in claim 2, wherein the periodic signal is a maximum off-time signal, the current reference signal is a peak current reference signal, the off-control circuit includes a current comparison circuit, the current comparison circuit compares the current detection signal and the peak current reference signal and outputs a off-control signal, and the period length of the maximum off-time signal is proportional to the input voltage of the boost power factor correction circuit.

6. The control circuit as claimed in claim 1, wherein the current reference signal generating circuit further generates the current reference signal based on a load feedback signal, and the load feedback signal represents the load size at the output end of the boost power factor correction circuit.

7. The control circuit as described in claim 1, wherein the current reference signal generating circuit includes an average current reference signal generating circuit, the input end of the average current reference signal generating circuit receives an input voltage feedback signal and a load feedback signal, and the output end of the average current reference signal generating circuit provides an average current reference signal, and the average current reference signal is proportional to the input voltage feedback signal.

8. The control circuit as claimed in claim 7, wherein the current reference signal generating circuit further comprises: A peak current reference signal generating circuit, whose input terminal is coupled to the output terminal of the average current reference signal generating circuit for receiving the average current reference signal Vcs_ref, and whose output terminal provides a peak current reference signal Vcs_pk; The average current reference signal Vcs_ref satisfies: Vcs_ref = K0*Vint*Vlfb / Vin_pk^2, where K0 is a constant, Vint is the input voltage feedback signal, Vlfb is the load feedback signal, Vin_pk is the input voltage peak feedback signal, and the peak current reference signal satisfies: Vcs_pk = 2*Vcs_ref / Dc-Vcs_min, where Dc is the on-duty cycle of the inductor current greater than zero in the switching cycle, and Vcs_min represents the minimum value of the inductor current in the switching cycle. When the current feedback signal reaches the peak current reference signal, the main power switch tube is turned off, and the current feedback signal is generated based on the inductor current.

9. The control circuit as claimed in claim 7, wherein the current reference signal generating circuit further comprises: An error compensation circuit, wherein a first input terminal thereof receives an average current reference signal, and a second input terminal thereof receives a current detection signal. The error compensation circuit performs compensation control on an error value between the average current reference signal and the current detection signal and outputs a current reference signal. When the current feedback signal reaches the current reference signal, the main power switch tube is turned off, wherein the current feedback signal is generated based on the inductor current. The average current reference signal Vcs_ref satisfies Vcs_ref=K0*Vint*Vlfb / Vin_pk^2, wherein K0 is a constant, Vint is an input voltage feedback signal, Vlfb is a load feedback signal, and Vin_pk is an input voltage peak feedback signal.

10. The control circuit as claimed in claim 8, wherein the current reference signal generating circuit comprises: A voltage divider circuit is used to divide and sample the voltage at the first end of the main power switch tube; A voltage follower, an input end of which is coupled to the output end of the voltage divider circuit; A low-pass filter circuit, whose input terminal is coupled to the output terminal of the voltage follower, and whose output terminal provides an input voltage feedback signal; as well as The peak sampling and holding circuit has an input end coupled to the output end of the low-pass filtering circuit. The peak sampling and holding circuit is used to sample and hold the peak value of the output end voltage of the low-pass filtering circuit as an input voltage peak feedback signal.

11. The control circuit as claimed in claim 10, wherein the current reference signal generating circuit further comprises a comparison circuit for comparing the voltage at the output end of the voltage follower with the voltage at the output end of the low-pass filter circuit to output a demagnetization detection signal.

12. The control circuit as claimed in claim 1, wherein the current reference signal generating circuit comprises a minimum current detection circuit, an input end of the minimum current detection circuit receives a current detection signal, the current detection signal is proportional to the current flowing through the inductor, and the minimum current detection circuit comprises a sampling and holding circuit, the sampling and holding circuit is used to sample and hold the current detection signal when the main power switch tube switches from off to on, so as to obtain the minimum value of the inductor current in the switching cycle.

13. The control circuit of claim 1 , wherein the current reference signal generating circuit comprises a duty cycle detection circuit, the duty cycle detection circuit comprising: a first trigger, wherein a set input terminal of the first trigger receives a switch control signal, a reset input terminal of the first trigger receives a demagnetization detection signal, and an output terminal of the first trigger provides a time signal when the inductor current is greater than zero; as well as The calculation circuit receives the time signal Ton+Tdem when the inductor current is greater than zero and the switch period signal T, and obtains the on-duty ratio Dc=(Ton+Tdem) / T.

14. A control circuit for controlling a boost power factor correction circuit, the boost power factor correction circuit comprising an inductor, a main power switch tube and a rectifier tube, wherein a first end of the inductor is coupled to an input end of the boost power factor correction circuit, a second end of the inductor is coupled to a first end of the main power switch tube and a first end of the rectifier tube, and a second end of the rectifier tube is coupled to an output end of the boost power factor correction circuit, the control circuit controls the on and off of the main power switch tube, and the control circuit comprises: A current reference signal generating circuit generates a current reference signal based on an input voltage feedback signal and a load feedback signal, wherein the input voltage feedback signal represents an input voltage at an input end of the boost power factor correction circuit, and the load feedback signal represents a load size at an output end of the boost power factor correction circuit; as well as The driving control circuit controls the conduction of the main power switch tube based on the demagnetization detection signal and the periodic signal, and controls the shutoff of the main power switch tube based on the current reference signal, wherein the main power switch tube is turned on when the demagnetization detection signal or the periodic signal is valid and is not limited by the maximum frequency.

15. A boost power factor correction circuit, comprising a main power switch tube and a control circuit as claimed in any one of claims 1 to 14.

16. An adaptive switching method for a multi-mode boost power factor correction circuit, the boost power factor correction circuit comprising an inductor, a main power switch tube and a rectifier tube, wherein a first end of the inductor is coupled to an input end of the boost power factor correction circuit, a second end of the inductor is coupled to a first end of the main power switch tube and a first end of the rectifier tube, a second end of the main power switch tube is coupled to a ground, and a second end of the rectifier tube is coupled to an output end of the boost power factor correction circuit, the adaptive switching method comprising: Generate a current reference signal based on an input voltage feedback signal and a load feedback signal, wherein the input voltage feedback signal represents the voltage at the input end of the boost power factor correction circuit, and the load feedback signal represents the load size at the output end of the boost power factor correction circuit; as well as A switch control signal is generated based on the current reference signal to control the main power switch tube, so that the input current of the boost power factor correction circuit changes with the current reference signal, and the boost power factor correction circuit adaptively switches between continuous current mode, critical current mode and discontinuous current mode.

17. The adaptive switching method as described in claim 16 further includes turning on the power switch tube when either the demagnetization detection signal or the periodic signal is valid and is not limited by the maximum frequency, and turning off the power switch tube when the current feedback signal reaches the current reference signal.

18. The adaptive switching method as claimed in claim 16, further comprising obtaining a current reference signal Vcs_pk by the following calculation: Vcs_pk=2*Vcs_ref / Dc-Vcs_min, wherein Vcs_ref=K0*Vint*Vlfb / Vin_pk^2, Dc is the on-duty ratio of the inductor current greater than zero in the switching cycle, Vcs_min is the minimum value of the inductor current in the switching cycle, K0 is a constant, Vint is an input voltage feedback signal, Vlfb is a load feedback signal, Vin_pk is an input voltage peak feedback signal, and when the current feedback signal reaches the current reference signal, the main power switch tube is turned off, wherein the current feedback signal is generated based on the inductor current.

19. The adaptive switching method as described in claim 16 further includes compensating and controlling the error value of the average current reference signal and the current detection signal to generate a current reference signal, wherein the average current reference signal Vcs_ref = K0*Vint*Vlfb / Vin_pk^2, K0 is a constant, Vint is an input voltage feedback signal, Vlfb is a load feedback signal, Vin_pk is an input voltage peak feedback signal, and when the current feedback signal reaches the current reference signal, the main power switch tube is turned off, wherein the current feedback signal is generated based on the inductor current.

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