High-voltage-to-low-voltage circuit and power management unit

Abstract

The invention relates to the technical field of semiconductor integrated circuits, and provides a high-voltage-to-low-voltage circuit and a power management unit.The high-voltage-to-low-voltage circuit comprises a PMOS driving tube, an NMOS driving tube, a first NMOS tube, a first PMOS tube, a first resistor, a second resistor, a third resistor, a first Zener tube and a second Zener tube; one end of the first resistor is connected to the drain electrode of the NMOS driving tube, the source electrode of the first PMOS tube, the source electrode of the PMOS driving tube and one end of the second resistor, and the first resistor is used for inputting power supply voltage; the other end of the first resistor is connected to the grid electrode of the first NMOS tube, the grid electrode of the NMOS driving tube and the cathode of the first Zener tube; the source electrode of the first NMOS tube and the anode of the first Zener tube are grounded; the drain electrode of the first NMOS tube is connected to the other end of the second resistor and the grid electrode of the first PMOS tube; the drain electrode of the first PMOS tube is connected to the grid electrode of the PMOS driving tube and is grounded through a third resistor; the drain electrode of the PMOS driving tube is connected with the source electrode of the NMOS driving tube and the cathode of the second Zener tube, and the PMOS driving tube is used for outputting analog voltage.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor integrated circuits, and in particular to a high-voltage to low-voltage conversion circuit and a power management unit. Background Art

[0002] The Power Management Unit (PMU) is an important and indispensable component of most chips; PMU is generally composed of one or N LDOs (linear regulators), Bandgap (bandgap reference circuits), overvoltage protection, undervoltage protection and other circuits, providing a stable voltage source, reference voltage (current), and some overvoltage and undervoltage protection functions for other circuit modules of the chip. An important indicator for considering PMU is its operating voltage range. The minimum operating voltage of the traditional PMU is generally around 4V. In some automotive electronic applications, such as a certain automotive motor application, the power supply voltage is required to be as low as 2V, and the internal SRAM data can still be saved (SRAM is powered by 1.5V LDO), which means that the minimum operating voltage of the PMU needs to be further reduced to 2V.

[0003] Therefore, how to reduce the minimum operating voltage of the PMU has become a focus of those skilled in the art. Summary of the invention

[0004] The purpose of the present invention is to provide a high voltage to low voltage circuit and a power management unit, which can reduce the minimum operating voltage of the power management unit.

[0005] In order to achieve the above object, the present invention provides a high voltage to low voltage conversion circuit, comprising: A PMOS driving tube, an NMOS driving tube, a first NMOS tube, a first PMOS tube, a first resistor, a second resistor, a third resistor, a first Zener tube, and a second Zener tube; One end of the first resistor is connected to the drain of the NMOS driver tube, the source of the first PMOS driver tube, the source of the PMOS driver tube and one end of the second resistor, and is used to input a power supply voltage; the other end of the first resistor is connected to the gate of the first NMOS driver tube, the gate of the NMOS driver tube and the cathode of the first Zener tube; The source of the first NMOS tube and the anode of the first Zener tube are grounded; the drain of the first NMOS tube is connected to the other end of the second resistor and the gate of the first PMOS tube; The drain of the first PMOS tube is connected to the gate of the PMOS driving tube and is grounded through the third resistor; The drain of the PMOS driving tube is connected to the source of the NMOS driving tube and the cathode of the second Zener tube, and is used to output an analog voltage; the anode of the second Zener tube is grounded.

[0006] In an optional solution, the high-voltage to low-voltage circuit further includes a first overshoot suppression circuit; the first overshoot suppression circuit includes: a second PMOS tube, a third PMOS tube, a fourth resistor and a third Zener tube; The gate and drain of the second PMOS tube are short-circuited and connected to the gate of the third PMOS tube and one end of the fourth resistor; the other end of the fourth resistor is grounded through the third Zener tube; The source of the second PMOS tube is connected to the source of the third PMOS tube and is used to input a power supply voltage; the drain of the third PMOS tube is connected to the drain of the first PMOS tube.

[0007] In an optional solution, the high-voltage to low-voltage circuit further includes a second overshoot suppression circuit; the second overshoot suppression circuit includes: a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube and a capacitor; The source of the fourth PMOS tube is connected to the source of the fifth PMOS tube and is used to input a power supply voltage; the gate of the fourth PMOS tube is connected to the gate of the fifth PMOS tube; The drain of the fourth PMOS tube is connected to the source of the sixth PMOS tube and one end of the capacitor, and the other end of the capacitor is connected to the source of the NMOS driving tube; The drain of the fifth PMOS tube is connected to the source of the seventh PMOS tube; the gate of the sixth PMOS tube is connected to the gate of the seventh PMOS tube; the drain of the sixth PMOS tube is connected to the gate of the fourth NMOS tube and the drain of the third NMOS tube; the drain of the seventh PMOS tube is connected to the gate of the third NMOS tube and the drain and gate of the second NMOS tube; The drain of the fourth NMOS tube is connected to the source of the NMOS driving tube; the sources of the second NMOS tube, the third NMOS tube and the fourth NMOS tube are all grounded.

[0008] The present invention also provides a power management unit, comprising the above-mentioned high-voltage to low-voltage circuit.

[0009] In an optional solution, the power management unit further includes: a voltage detection circuit, a bandgap reference circuit, a first linear regulator circuit, and a second linear regulator circuit; The output of the high voltage to low voltage conversion circuit is used as the input of the voltage detection circuit and the bandgap reference circuit; The voltage detection circuit outputs an enable signal to the bandgap reference circuit, the first linear regulator circuit, and the second linear regulator circuit; The bandgap reference circuit provides a first bias voltage to the first linear regulator circuit and provides a second bias voltage to the second linear regulator circuit; The first linear regulator circuit inputs the power supply voltage and provides a voltage to the second linear regulator circuit; A first threshold and a second threshold are set, and the first threshold is greater than the second threshold; when the output voltage of the high-voltage to low-voltage circuit is higher than the first threshold, the enable signal is high, and when the output voltage of the high-voltage to low-voltage circuit is lower than the second threshold, the enable signal is low.

[0010] In an optional solution, the first threshold is less than 2V, and the second threshold is greater than 1.5V.

[0011] In an optional solution, when the power supply voltage is less than the first threshold value and greater than 0, the enable signal is low, and the output voltage of the first linear regulator circuit and the second linear regulator circuit is 0; When the power supply voltage is less than 5V and greater than the first threshold, the enable signal is high, the output value of the first linear regulator circuit follows the power supply voltage, and the output voltage of the second linear regulator circuit is 1.5V; When the power supply voltage is greater than 5V, the enable signal is high, the output voltage of the first linear regulator circuit is 5V, and the output voltage of the second linear regulator circuit is 1.5V.

[0012] The beneficial effects of the present invention are: The present invention can reduce the minimum operating voltage of a power management unit (PMU). BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The above and other objects, features and advantages of the present invention will become more apparent through a more detailed description of exemplary embodiments of the present invention in conjunction with the accompanying drawings, in which like reference numerals generally represent like components.

[0014] Figure 1 FIG. 4 is a circuit diagram of a high voltage to low voltage converter in one embodiment of the present invention.

[0015] Figure 2 FIG. 4 is a diagram showing the relationship between the input power supply voltage and the output analog voltage in one embodiment of the present invention.

[0016] Figure 3FIG. 4 is a schematic diagram of a power management unit according to an embodiment of the present invention.

[0017] Figure 4 FIG. 4 is a timing diagram of a power management unit in an embodiment of the present invention. DETAILED DESCRIPTION

[0018] The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. According to the following description and drawings, the advantages and features of the present invention will become clearer. However, it should be noted that the concept of the technical solution of the present invention can be implemented in a variety of different forms and is not limited to the specific embodiments described herein. The drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0019] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there may be no intervening elements or layers. It should be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below may be represented as a second element, component, region, layer or part.

[0020] Spatially relative terms such as "under," "below," "below," "under," "above," "above," etc., may be used herein for ease of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, then the elements or features described as "under other elements" or "under" or "under" will be oriented as "on" the other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0021] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present invention. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0022] Example 1 Reference Figure 1 and Figure 2 This embodiment provides a high-voltage to low-voltage circuit, which converts a high-voltage power supply voltage VBAT into a low-voltage analog voltage AVDD. The circuit includes: A PMOS driving tube MP0, an NMOS driving tube MN0, a first NMOS tube MN1, a first PMOS tube MP1, a first resistor R1, a second resistor R2, a third resistor R3, a first Zener tube Z1 and a second Zener tube Z2; One end of the first resistor R1 is connected to the drain of the NMOS driver tube MN0, the source of the first PMOS driver tube MP1, the source of the PMOS driver tube MP0 and one end of the second resistor R2, and is used to input the power supply voltage VBAT; the other end of the first resistor R1 is connected to the gate of the first NMOS driver tube MN1, the gate of the NMOS driver tube MN0 and the cathode of the first Zener tube Z1; The source of the first NMOS transistor MN1 and the anode of the first Zener transistor Z1 are grounded GND; the drain of the first NMOS transistor MN1 is connected to the other end of the second resistor R2 and the gate of the first PMOS transistor MP1; The drain of the first PMOS transistor MP1 is connected to the gate of the PMOS driving transistor MP0 and is grounded GND through the third resistor R3; The drain of the PMOS driving tube MP0 is connected to the source of the NMOS driving tube MN0 and the cathode of the second Zener tube Z2 and is used to output the analog voltage AVDD; the anode of the second Zener tube Z2 is grounded GND.

[0023] Specifically, when the input power supply voltage VBAT is low, the current flowing through the second resistor R2 is extremely small or even zero, the voltage across the second resistor R2 is less than the turn-on voltage of the first PMOS tube MP1, the first PMOS tube MP1 is in the cut-off region, V2=0V, V2 represents the drain voltage of the first PMOS tube MP1. The PMOS driver tube MP0 works in the deep linear region, at which time the output analog voltage AVDD is completely driven by the PMOS driver tube MP0: AVDD=VBAT, the advantage of this is that when the power supply voltage VBAT is at a low voltage, the output analog voltage AVDD follows the power supply voltage VBAT, and the circuit connected to the analog voltage AVDD can work at a lower power supply voltage VBAT.

[0024] 2. When the power supply voltage VBAT gradually increases, when the voltage across the second resistor R2 is greater than the turn-on voltage of the first PMOS tube MP1, the drain voltage V2 of the first PMOS tube MP1 will be pulled up to the power supply voltage VBAT, the second PMOS tube MP2 is turned off, and the NMOS driver tube MN0 works in the source follower state. At this time, the analog voltage AVDD is completely driven by the NMOS driver tube MN0: AVDD=VBAT-VGSN0, VGSN0 is the gate-source voltage of the NMOS driver tube, and the power supply voltage VBAT corresponding to the PMOS driver tube MP0 switching to the NMOS driver tube MN0 is recorded as the switching voltage VBTA_S.

[0025] 3. When the power supply voltage VBAT further increases to be greater than the breakdown voltage Vz of the first Zener tube Z1, the breakdown voltage Vz is clamped. At this time: AVDD=Vz-VGSN0. The purpose of this is to make the maximum voltage of the analog voltage AVDD lower than the breakdown voltage of the first Zener tube Z1, thereby protecting the low-voltage circuit connected to the analog voltage AVDD. The above is the DC (direct current) output relationship between the output analog voltage AVDD and the input power supply voltage VBAT.

[0026] In practical applications, such as when a car is cold-started, the power supply voltage VBAT may surge, that is, the power supply voltage VBAT rises from 0V to 40V or even higher at a very fast speed, and the speed at which the PMOS driver tube MP0 switches to the NMOS driver tube MN0 is not fast enough (this is mainly because the parasitic capacitance CGS1 and CGD1 of the first PMOS tube MP1 and the parasitic capacitance CGS0 and CGD0 of the PMOS driver tube MP0 cause switching delays). As a result, the power supply voltage VBAT is much larger than the breakdown voltage Vz, but the PMOS driver tube MP0 is not turned off in time, and the high voltage of the power supply voltage VBAT will be transmitted to the analog voltage AVDD through the PMOS driver tube MP0, damaging the low-voltage circuit connected to the analog voltage AVDD.

[0027] In order to solve the above problem, in this embodiment, the high-voltage to low-voltage circuit also includes a first overshoot suppression circuit; the first overshoot suppression circuit includes: a second PMOS tube MP2, a third PMOS tube MP3, a fourth resistor R4 and a third Zener tube Z3; the gate and the drain of the second PMOS tube MP2 are short-circuited and connected to the gate of the third PMOS tube MP3 and one end of the fourth resistor R4; the other end of the fourth resistor R4 is grounded GND through the third Zener tube Z3; the source of the second PMOS tube MP2 is connected to the source of the third PMOS tube MP3 and is used to input the power supply voltage VBAT; the drain of the third PMOS tube MP3 is connected to the drain of the first PMOS tube MP1.

[0028] When VBAT>Vz+VGSMP2, VGSMP2 represents the gate-source voltage of the second PMOS tube MP2, the second PMOS tube MP2 will be turned on, the third PMOS tube MP3 mirrors the current of the second PMOS tube MP2 to pull up the drain voltage V2 of the first PMOS tube MP1 and turn off the PMOS driver tube MP0, and the overshoot is reduced by monitoring the value of the power supply voltage VBAT. In order to increase the pull-up speed of the third PMOS tube MP3, the size of the third PMOS tube MP3 will be set much larger than the second PMOS tube MP2, so the speed of pulling up the drain voltage V2 of the first PMOS tube MP1 can be fast enough to turn off the PMOS driver tube MP0 in time and reduce the overshoot of the output analog voltage AVDD. This method detects the power supply voltage VBAT and reduces the overshoot of the output analog voltage AVDD by turning off the PMOS driver tube MP0.

[0029] Sometimes, only the first overshoot suppression circuit cannot completely suppress the output overshoot. Therefore, in this embodiment, the high-voltage to low-voltage circuit further includes a second overshoot suppression circuit; the second overshoot suppression circuit includes: a fourth PMOS tube MP4, a fifth PMOS tube MP5, a sixth PMOS tube MP6, a seventh PMOS tube MP7, a second NMOS tube MN2, a third NMOS tube MN3, a fourth NMOS tube MN4 and a capacitor C0; the source of the fourth PMOS tube MP4 is connected to the source of the fifth PMOS tube MP5 and is used to input the power supply voltage VBAT; the gate of the fourth PMOS tube MP4 is connected to the gate of the fifth PMOS tube MP5; the drain of the fourth PMOS tube MP4 is connected to the source of the sixth PMOS tube MP6 and one end of the capacitor C0, and the capacitor C0 ... The other end of capacitor C0 is connected to the source of the NMOS driving tube MN0; the drain of the fifth PMOS tube MP5 is connected to the source of the seventh PMOS tube MP7; the gate of the sixth PMOS tube MP6 is connected to the gate of the seventh PMOS tube MP7; the drain of the sixth PMOS tube MP6 is connected to the gate of the fourth NMOS tube MN4 and the drain of the third NMOS tube MN3; the drain of the seventh PMOS tube MP7 is connected to the gate of the third NMOS tube MN3 and the drain and gate of the second NMOS tube MN2; the drain of the fourth NMOS tube MN4 is connected to the source of the NMOS driving tube MN0; the sources of the second NMOS tube MN2, the third NMOS tube MN3 and the fourth NMOS tube MN4 are all grounded GND.

[0030] The fourth PMOS tube MP4 has the same size as the fifth PMOS tube MP5, and the gate bias voltage is VB1. The sixth PMOS tube MP6 has the same size as the seventh PMOS tube MP7, and the gate bias voltage is VB2. The third NMOS tube MN3 is slightly larger than the second NMOS tube MN2. Then, in the DC (direct current) state, the current of the sixth PMOS tube MP6 is equal to the current of the third NMOS tube MN3, and the third NMOS tube MN3 will work in the deep linear region, the drain voltage V4 of the third NMOS tube MN3 is close to 0V, and the fourth NMOS tube MN4 is in the cut-off state. When a surge occurs, the overshoot voltage generated by the analog voltage AVDD is coupled to V3 through the capacitor C0, and V3 represents the drain voltage of the fourth PMOS tube MP4. Then V3 will also generate an overshoot at the same time, and then the current of the sixth PMOS tube MP6 will be instantly greater than the current of the third NMOS tube MN3, the drain voltage V4 of the third NMOS tube is pulled up, and the fourth NMOS tube MN4 is turned on to discharge the overshoot voltage of the analog voltage AVDD. This method directly detects the overshoot of the analog voltage AVDD and discharges the overshoot voltage through the fourth NMOS tube MN4.

[0031] The high-voltage to low-voltage circuit of this embodiment can reduce the minimum operating voltage of the chip when AVDD=VBAT at an extremely low voltage, and simultaneously detect VBAT and AVDD to reduce the output overshoot voltage.

[0032] Example 2 Reference Figure 3 and Figure 4 , this embodiment provides a power management unit, including the high-voltage to low-voltage circuit of embodiment 1 (converting the high-voltage power supply voltage VBAT into the low-voltage analog voltage AVDD), and also including: a voltage detection circuit, a bandgap reference circuit, a first linear regulator circuit and a second linear regulator circuit; The output of the high-voltage to low-voltage conversion circuit is used as the input of the voltage detection circuit and the bandgap reference circuit to provide an analog voltage AVDD; The voltage detection circuit outputs an enable signal EN to the bandgap reference circuit, the first linear regulator circuit and the second linear regulator circuit; The bandgap reference circuit provides a first bias voltage VREF1 to the first linear regulator circuit and provides a second bias voltage VREF2 to the second linear regulator circuit; The first linear regulator circuit inputs the power supply voltage VBAT and provides a voltage to the second linear regulator circuit; A first threshold value VTH1 and a second threshold value VTH2 are set, and the first threshold value VTH1 is greater than the second threshold value VTH2; when the output voltage of the high-voltage to low-voltage circuit is higher than the first threshold value VTH1, the enable signal EN is high, and when the output voltage of the high-voltage to low-voltage circuit is lower than the second threshold value VTH2, the enable signal EN is low.

[0033] Specifically, in this embodiment, the first linear regulator circuit is a 5V LDO, which is used to power other analog modules of the chip, such as 1.5V LDO, ADC, DAC, etc. The second linear regulator circuit is a 1.5V LDO, which mainly powers digital circuits, such as SRAM, flash, etc. In this embodiment, 1.5V<VTH2<VTH1<2V. The bandgap reference circuit can operate at a very low AVDD voltage (about 1.4V). When the power supply voltage VBAT is less than the first threshold value VTH1 and greater than 0, the enable signal EN is low, and the output voltages of the first linear voltage regulator circuit and the second linear voltage regulator circuit are 0; when the power supply voltage VBAT is less than 5V and greater than the first threshold value VTH1, the enable signal EN is high, the output value of the first linear voltage regulator circuit follows the power supply voltage VBAT, and the output voltage of the second linear voltage regulator circuit is 1.5V; when the power supply voltage VBAT is greater than 5V, the enable signal EN is high, the output voltage of the first linear voltage regulator circuit is 5V, and the output voltage of the second linear voltage regulator circuit is 1.5V.

[0034] Reference Figure 4 , power supply voltage VBAT power-on process: 1. When 0<VBAT<VTH1, the enable signal EN is low, the low-voltage bandgap reference circuit cannot work, the output VREF1 (VREF2) = 0, and the output VDD5V of the first linear regulator circuit and the output VDD1V5 of the second linear regulator circuit are both 0V.

[0035] 2. When VTH1<VBAT<5V, the enable signal EN is high, the low-voltage bandgap reference circuit works normally, and the output VREF1 (VREF2) is normal. The output VDD5V of the first linear regulator circuit will follow VBAT, that is, VDD5V=VBAT, and the output VDD1V5 of the second linear regulator circuit normally outputs a 1.5V voltage.

[0036] 3. When 5<VBAT<40V, the enable signal EN is high, the low-voltage bandgap reference circuit works normally, and the output VREF1 (VREF2) is normal. The output VDD5V of the first linear regulator circuit is fixed to 5V, and the output VDD1V5 of the second linear regulator circuit outputs 1.5V voltage normally.

[0037] It can be seen that when VTH1<VBAT, the output VDD1V5 of the second linear regulator circuit can normally output a voltage of 1.5V, reaching an extremely low operating voltage.

[0038] The power-off process of the power supply voltage VBAT: The power-off process is a mirror image of the power-on process. During the power-off process, VTH2 < VTH1. The purpose is to prevent the enable signal EN from flipping back and forth when VBAT jitters near VTH1.

[0039] The power management unit of this embodiment can output normally when the power supply voltage VBAT is as low as 2V, and can output 1.5V voltage normally within the range of 2V~40V.

[0040] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A high voltage to low voltage circuit, characterized in that: include: A PMOS driving tube, an NMOS driving tube, a first NMOS tube, a first PMOS tube, a first resistor, a second resistor, a third resistor, a first Zener tube and a second Zener tube; One end of the first resistor is connected to the drain of the NMOS driver tube, the source of the first PMOS driver tube, the source of the PMOS driver tube and one end of the second resistor, and is used to input a power supply voltage; the other end of the first resistor is connected to the gate of the first NMOS driver tube, the gate of the NMOS driver tube and the cathode of the first Zener tube; The source of the first NMOS tube and the anode of the first Zener tube are grounded; the drain of the first NMOS tube is connected to the other end of the second resistor and the gate of the first PMOS tube; The drain of the first PMOS tube is connected to the gate of the PMOS driving tube and is grounded through the third resistor; The drain of the PMOS driving tube is connected to the source of the NMOS driving tube and the cathode of the second Zener tube, and is used to output an analog voltage; the anode of the second Zener tube is grounded.

2. The high voltage to low voltage circuit according to claim 1, characterized in that: The high-voltage to low-voltage circuit further includes a first overshoot suppression circuit; the first overshoot suppression circuit includes: a second PMOS tube, a third PMOS tube, a fourth resistor and a third Zener tube; The gate and drain of the second PMOS tube are short-circuited and connected to the gate of the third PMOS tube and one end of the fourth resistor; the other end of the fourth resistor is grounded through the third Zener tube; The source of the second PMOS tube is connected to the source of the third PMOS tube and is used to input a power supply voltage; the drain of the third PMOS tube is connected to the drain of the first PMOS tube.

3. The high voltage to low voltage circuit according to claim 1 or 2, characterized in that: The high-voltage to low-voltage circuit further includes a second overshoot suppression circuit; the second overshoot suppression circuit includes: a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube and a capacitor; The source of the fourth PMOS tube is connected to the source of the fifth PMOS tube and is used to input a power supply voltage; the gate of the fourth PMOS tube is connected to the gate of the fifth PMOS tube; The drain of the fourth PMOS tube is connected to the source of the sixth PMOS tube and one end of the capacitor, and the other end of the capacitor is connected to the source of the NMOS driving tube; The drain of the fifth PMOS tube is connected to the source of the seventh PMOS tube; the gate of the sixth PMOS tube is connected to the gate of the seventh PMOS tube; the drain of the sixth PMOS tube is connected to the gate of the fourth NMOS tube and the drain of the third NMOS tube; the drain of the seventh PMOS tube is connected to the gate of the third NMOS tube and the drain and gate of the second NMOS tube; The drain of the fourth NMOS tube is connected to the source of the NMOS driving tube; the sources of the second NMOS tube, the third NMOS tube and the fourth NMOS tube are all grounded.

4. A power management unit, characterized in that: The invention comprises the high voltage to low voltage circuit as described in any one of claims 1 to 3.

5. The power management unit according to claim 4, characterized in that: The power management unit further includes: a voltage detection circuit, a bandgap reference circuit, a first linear voltage regulator circuit, and a second linear voltage regulator circuit; The output of the high voltage to low voltage conversion circuit is used as the input of the voltage detection circuit and the bandgap reference circuit; The voltage detection circuit outputs an enable signal to the bandgap reference circuit, the first linear regulator circuit, and the second linear regulator circuit; The bandgap reference circuit provides a first bias voltage to the first linear regulator circuit and provides a second bias voltage to the second linear regulator circuit; The first linear regulator circuit inputs the power supply voltage and provides a voltage to the second linear regulator circuit; A first threshold and a second threshold are set, and the first threshold is greater than the second threshold; when the output voltage of the high-voltage to low-voltage circuit is higher than the first threshold, the enable signal is high, and when the output voltage of the high-voltage to low-voltage circuit is lower than the second threshold, the enable signal is low.

6. The power management unit according to claim 5, characterized in that: The first threshold is less than 2V, and the second threshold is greater than 1.5V.

7. The power management unit according to claim 6, characterized in that: When the power supply voltage is less than the first threshold and greater than 0, the enable signal is low, and the output voltage of the first linear regulator circuit and the second linear regulator circuit is 0; When the power supply voltage is less than 5V and greater than the first threshold, the enable signal is high, the output value of the first linear regulator circuit follows the power supply voltage, and the output voltage of the second linear regulator circuit is 1.5V; When the power supply voltage is greater than 5V, the enable signal is high, the output voltage of the first linear regulator circuit is 5V, and the output voltage of the second linear regulator circuit is 1.5V.

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