Single sideband time modulator with ultra-wideband instantaneous bandwidth

Abstract

The invention discloses a single side band time modulator with ultra-wideband instantaneous bandwidth. The single side band time modulator is provided with an orthogonal generation unit, an I-path modulation unit, a Q-path modulation unit, an output buffer unit and a time sequence control unit. Radio frequency input differential signals RFin + and RFin-are connected with the orthogonal generation unit, the output of the orthogonal generation unit is connected with the I-path modulation unit and the Q-path modulation unit, then input signals are modulated in the I-path modulation unit and the Q-path modulation unit respectively, the output end of the output buffer unit is the output end of the single-side-band time modulator, a modulation signal RFout is output at a single end, and the output end of the output buffer unit is connected with the output end of the single-side-band time modulator. The digital time sequence unit controls the I-path modulation unit and the Q-path modulation unit to realize vector modulation, so that a single sideband time modulation function is realized, extremely high modulation frequency input is realized, and the ultra-wideband instantaneous bandwidth is realized.

Description

Technical Field

[0001] The invention belongs to the field of radio frequency microwave integrated circuit design, in particular to a single sideband time modulator with ultra-wideband instantaneous bandwidth. Background Art

[0002] Phased arrays play an important role in radar, wireless communications, and electronic reconnaissance systems. Broadband, low-complexity amplitude and phase control are essential for phased array systems. Time modulation technology is a periodic high-speed modulation of the switch unit to achieve control of the amplitude and phase of the RF signal. This technology provides a viable alternative to traditional phase shifters and attenuators. The application of time modulation technology has become the main method to achieve broadband and precise amplitude and phase control. The time modulator is the most important component in the time-modulated antenna array. It is mainly composed of the RF modulation circuit and its controller unit.

[0003] Early time modulation modules usually have the problem of low efficiency. Due to the fact that the signal in the off state is not modulated and the conduction and radiation losses between modules, the basic time modulator using a single-pole single-throw switch can only achieve a +1 harmonic efficiency of about 20%. In order to improve the harmonic efficiency, double-sideband time modulation and single-sideband time modulation technologies have been proposed one after another. By applying double-sideband time modulation technology, the fundamental component and 2k (k∈Z) harmonic components of the RF signal are suppressed, and the +1 harmonic efficiency is increased to 40%; in order to further increase the proportion of the +1 harmonic component, single-sideband time modulation technology is applied, which only retains the 8k+1 harmonic component of the RF signal. Therefore, the +1 harmonic efficiency is increased to more than 90%, and single-sideband time modulators have been more widely used. In the existing single-sideband time modulator, its modulation frequency f P Usually set to 100kHz or 1MHz, 4f P or 8f P The instantaneous bandwidth can be easily achieved, but is limited by the low modulation frequency f P These single-sideband time modulators have difficulty in achieving broadband instantaneous bandwidth, and the harmonic components beyond the 8k+1 harmonic are not completely suppressed. P There will still be undesirable harmonic components within the instantaneous bandwidth, which will have a negative impact on the harmonic efficiency and circuit efficiency. Summary of the invention

[0004] The purpose of the present invention is to provide a single-sideband time modulator with ultra-wideband instantaneous bandwidth, which solves the low modulation frequency problem of the time modulator, significantly improves the modulation frequency under the premise of low power consumption and low cost, and can achieve ultra-wideband instantaneous bandwidth, constant input impedance and high positive first harmonic efficiency and other performances, and is suitable for high-frequency and broadband communication applications.

[0005] The technical solution to achieve the purpose of the present invention is: a single-sideband time modulator with ultra-wideband instantaneous bandwidth, comprising: an orthogonal generation unit 1, an I-channel modulation unit 2, a Q-channel modulation unit 3, a timing control unit 4, an output buffer unit 5, a differential RF input signal RF in + and RF in -An orthogonal differential signal is output after passing through the orthogonal generating unit 1, and the output end of the orthogonal generating unit 1 is respectively connected to the differential input ends of the I-path modulation unit and the Q-path modulation unit, and the orthogonal differential signal is respectively input into the I-path modulation unit and the Q-path modulation unit for vector modulation, wherein the I-path signal outputs a modulation signal with a phase of 0° / 180° after passing through the I-path modulation unit 2, and the Q-path signal outputs a modulation signal with a phase of 90° / 270° after passing through the Q-path modulation unit 3, and the output ends of the I-path modulation unit and the Q-path modulation unit are connected to the input end of the output buffer unit 5.

[0006] Preferably, the I-path modulation unit 2 and the Q-path modulation unit 3 have the same structure, both comprising four transistor arrays, each of which comprises two N-2 For transistors with different gate widths, vector modulation is achieved by sine and cosine signals equivalent to N-1 step signals, where N is the number of bits of the modulator.

[0007] Preferably, 2 N-2 The gate widths of the transistors are:

[0008]

[0009] Where m = 0, 1, ... 2 N-2 -2, 2 N-2 -1.

[0010] Preferably, N is 3.

[0011] Preferably, the I-channel modulation unit 2 includes a capacitor C0, a capacitor C1, an NMOS tube M0, an NMOS tube M1, an NMOS tube M4, an NMOS tube M5, an NMOS tube M6, an NMOS tube M7, an NMOS tube M8, an NMOS tube M9, an NMOS tube M 10 、NMOS tube M 11 、NMOS tube M 12 、NMOS tube M 13 、NMOS tube M 14 、NMOS tube M 15 、NMOS tube M 16 、NMOS tube M 17 、NMOS tube M 18 、NMOS tube M 19The I-channel differential signal output by the orthogonal generation unit 1 is respectively connected to one end of the capacitor C0 and the capacitor C1 in the I-channel modulation unit 2, and the other end of the capacitor C0 and the capacitor C1 are respectively connected to the gate of the NMOS tube M0 and the NMOS tube M1, and the source of the NMOS tube M0 and the NMOS tube M1 is grounded, and the NMOS tubes M4, M5, M6, M7, M8, M9, and M1 are connected to the ground. 10 、NMOS tube M 11 The source of is connected to the drain of NMOS tube M0, and NMOS tube M 12 、NMOS tube M 13 、NMOS tube M 14 、NMOS tube M 15 、NMOS tube M 16 、NMOS tube M 17 、NMOS tube M 18 、NMOS tube M 19 The source of the NMOS tube M1 is connected to the drain of the NMOS tube M4, the NMOS tube M5, the NMOS tube M6, the NMOS tube M7, and the NMOS tube M 12 、NMOS tube M 13 、NMOS tube M 14 、NMOS tube M 15 The drain of the NMOS tube M8, the NMOS tube M9, and the NMOS tube M 10 、NMOS tube M 11 、NMOS tube M 16 、NMOS tube M 17 、NMOS tube M 18 、NMOS tube M 19 The drain is connected to the negative output end of the I-channel modulation unit 2.

[0012] Preferably, the NMOS tube M0, the NMOS tube M1, the NMOS tube M4, the NMOS tube M5, the NMOS tube M6, the NMOS tube M7, the NMOS tube M8, the NMOS tube M9, the NMOS tube M 10 、NMOS tube M 11 、NMOS tube M 12 、NMOS tube M 13 、NMOS tube M 14 、NMOS tube M 15 、NMOS tube M 16 、NMOS tube M 17 、NMOS tube M 18 、NMOS tube M 19 The gate lengths are equal.

[0013] Preferably, the Q-path modulation unit 3 includes a capacitor C2, a capacitor C3, an NMOS transistor M2, an NMOS transistor M3, an NMOS transistor M 20 、NMOS tube M 21 、NMOS tube M 22 、NMOS tube M 23 、NMOS tube M 24 、NMOS tube M 25 、NMOS tube M 26 、NMOS tube M 27 、NMOS tube M 28 、NMOS tube M 29 、NMOS tube M 30 、NMOS tube M 31 、NMOS tube M 32 、NMOS tube M 33 、NMOS tube M 34 、NMOS tube M 35 The Q-path differential signal output by the orthogonal generating unit 1 is connected to one end of the capacitor C2 and the capacitor C3 in the Q-path modulation unit 3 respectively, and the other ends of the capacitor C2 and the capacitor C3 are connected to the gates of the NMOS tube M2 and the NMOS tube M3 respectively, and the sources of the NMOS tube M2 and the NMOS tube M3 are grounded. 20 、NMOS tube M 21 、NMOS tube M 22 、NMOS tube M 23 、NMOS tube M 24 、NMOS tube M 25 、NMOS tube M 26 、NMOS tube M 27 The source of the NMOS tube M2 is connected to the drain of the NMOS tube M2. 28 、NMOS tube M 29 、NMOS tube M 30 、NMOS tube M 31 、NMOS tube M 32 、NMOS tube M 33 、NMOS tube M 34 、NMOS tube M 35 The source of the NMOS tube M3 is connected to the drain of the NMOS tube M4, the NMOS tube M5, the NMOS tube M6, the NMOS tube M7, and the NMOS tube M 12 、NMOS tube M 13 、NMOS tube M 14 、NMOS tube M 15 The drain of the NMOS tube M8, the NMOS tube M9, and the NMOS tube M 10 、NMOS tube M 11 、NMOS tube M16 、NMOS tube M 17 、NMOS tube M 18 、NMOS tube M 19 The drain is connected to the negative output end of the I-channel modulation unit 2.

[0014] Preferably, the NMOS tube M2, the NMOS tube M3, and the NMOS tube M 20 、NMOS tube M 21 、NMOS tube M 22 、NMOS tube M 23 、NMOS tube M 24 、NMOS tube M 25 、NMOS tube M 26 、NMOS tube M 27 、NMOS tube M 28 、NMOS tube M 29 、NMOS tube M 30 、NMOS tube M 31 、NMOS tube M 32 、NMOS tube M 33 、NMOS tube M 34 、NMOS tube M 35 The gate lengths are equal.

[0015] Preferably, the timing control unit 4 has 2 N The output end generates a square wave signal with a 50% duty cycle as a modulation signal and inputs it into the modulation signal input end of the I modulation unit 2 and the Q modulation unit 3. The period is T P , so that the gain control timing of the I-channel modulation unit 2 when performing vector modulation on the input signal presents an N-1-level step-type timing of a sine curve, and the gain control timing of the Q-channel modulation unit 3 when performing vector modulation on the input signal presents an N-1-level step-type timing of a cosine curve, so that the time t2, t1, t'2 and t'1 satisfy: t2-t1=t'2-t'1=T P / 2 and t1-t'1=T P / 4, where t1 and t'1 represent the positive moments of the gain control timing of the I and Q paths, respectively, and t2 and t'2 represent the negative moments of the gain control timing of the I and Q paths, respectively, and the pulse width τ1 with a normalized gain of sin[π / (2N)] satisfies: τ1=(2N-1)T P / (4N), the normalized gain is sin[π(N-1) / (2N)], the pulse width τ N-1 Satisfy: τ N-1 =3T P / (4N), the normalized gain is sin[πN / (2N)], the pulse width τ N Satisfy: τ N =TP / (4N).

[0016] Compared with the prior art, the present invention has the following significant advantages:

[0017] (1) Ultra-wideband instantaneous bandwidth. The active transistors used in the I-channel modulation unit and the Q-channel modulation unit of the present invention switch between the saturation region and the cutoff region. Compared with passive devices, the voltage change value of active devices when switching the working area is smaller, which improves the switching rate, which is conducive to increasing the modulation frequency; at the same time, a topology based on common source and common gate is used in the modulation unit, the RF signal is input from the common source transistor, and the modulation signal is input from the common gate transistor. The capacitor at the modulation signal input end and the resistor of the bias circuit constitute an RC high-pass filter structure, which can accommodate the passage of high-frequency signals. Therefore, the single-sideband time modulator realized by this patent can increase the modulation frequency to 1GHz, which is much higher than the common 1MHz modulation frequency.

[0018] (2) Constant input impedance. In the modulation unit, a 3-bit square wave signal with a duty cycle of 50% is used as the modulation signal input to control multiple MOS tubes of a specific size. At the same time, the total transconductance value of the transistors in the on state in the modulation unit is always constant, so the input impedance of the modulator is always constant for this time.

[0019] (3) High sideband suppression. The present invention is based on single-sideband time modulation technology and uses a 2-order staircase signal equivalent to a sine / cosine signal. It can completely suppress useless sidebands other than the 8k+1 sideband. At the same time, it can achieve a sideband suppression of 17dBc for the largest useless sidebands, namely the +9th sideband and the -7th sideband, thereby improving the +1st sideband efficiency.

[0020] (4) Low power consumption and low cost. The circuit topology of the present invention is simple, and only common passive devices such as resistors, capacitors and MOS tubes are used, and no inductor devices are used, which can save area. The present invention is classified as a Cartesian vector modulator. In addition to the relatively narrow bandwidth, the traditional modulator structure also has problems such as high power consumption and low linearity. The active structure based on the Gilbert unit used in the present invention can effectively improve these shortcomings. Therefore, the power consumption and cost of the present invention are reduced.

[0021] (5) The present invention significantly improves the modulation frequency under the premise of low power consumption and low cost, and can achieve ultra-wideband instantaneous bandwidth, which has advantages in high-frequency and broadband communication applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 The invention discloses a circuit schematic diagram of a single-sideband time modulator with ultra-wideband instantaneous bandwidth.

[0023] Figure 2 It is a circuit principle diagram of the I-channel modulation unit of the present invention.

[0024] Figure 3 It is a circuit principle diagram of the Q-path modulation unit of the present invention.

[0025] Figure 4 It is a square wave modulation signal waveform diagram generated by the timing control unit of the present invention.

[0026] Figure 5 So Figure 4 The period of the eight-way modulation signal is T P I / Q path gain control timing.

[0027] Figure 6 It is the correspondence between the control signal, the specific gate width transistor and the normalized gain control timing.

[0028] Figure 7 This is the output spectrum diagram of the present invention when the RF input signal frequency is 3 GHz and the modulation signal frequency is 100 MHz.

[0029] Figure 8 This is the output spectrum diagram of the present invention when the RF input signal frequency is 3 GHz and the modulation signal frequency is 1 GHz. DETAILED DESCRIPTION

[0030] See also Figure 1 , a single sideband time modulator with ultra-wideband instantaneous bandwidth, comprising: an orthogonal generation unit 1, an I-channel modulation unit 2, a Q-channel modulation unit 3, a timing control unit 4, and an output buffer unit 5. Differential RF input signal RF in + and RF in -After passing through the orthogonal generation unit 1, two orthogonal signals are output, and the two orthogonal signals are respectively input into the I-channel modulation unit 2 and the Q-channel modulation unit 3, wherein the I-channel signal outputs a modulation signal with a phase of 0° / 180° after passing through the I-channel modulation unit 2, and the Q-channel signal outputs a modulation signal with a phase of 90° / 270° after passing through the Q-channel modulation unit 3. Next, the two signals realize the conversion from differential signals to single-ended signals in the output buffer unit 5, and finally output the single-ended signal RF out The output end of the output buffer unit 5 is also the output end of the time modulator. The final single-ended output modulated signal RF out , the present invention can realize extremely high modulation frequency input, so the present invention has ultra-wideband instantaneous bandwidth.

[0031] RF input signal RF in + and RF in -Connected to the input end of the multi-phase filter in the orthogonal generation unit 1, the multi-phase filter outputs two orthogonal signals.

[0032] A single-sideband time modulator with ultra-wideband instantaneous bandwidth, wherein the I-channel modulation unit 2 and the Q-channel modulation unit 3 each have four transistor arrays, each of which has two N-2 transistors with different gate widths, vector modulation is achieved by using sine and cosine signals equivalent to N-1 step signals, N is the number of bits of the modulator, and the minimum gate width is set to 1μm. N-2 The gate width of this transistor can be expressed as

[0033]

[0034] In this embodiment, the I-channel modulation unit 2 and the Q-channel modulation unit 3 are both based on a 3-bit active vector modulator. Each modulation unit has four transistor arrays, each array has two transistors with different gate widths, and vector modulation is achieved by a sine and cosine signal equivalent to a two-step step signal. The gate widths of these two transistors can be expressed as 1-(√2 / 2):(√2 / 2), and the gate widths are set to 1μm and 2.4μm, respectively.

[0035] The I-channel modulation unit 2 includes a capacitor C0, a capacitor C1, an NMOS tube M0, an NMOS tube M1, an NMOS tube M4, an NMOS tube M5, an NMOS tube M6, an NMOS tube M7, an NMOS tube M8, an NMOS tube M9, an NMOS tube M 10 、NMOS tube M 11 、NMOS tube M 12 、NMOS tube M 13 、NMOS tube M 14 、NMOS tube M 15 、NMOS tube M 16 、NMOS tube M 17 、NMOS tube M 18 、NMOS tube M 19 .

[0036] The Q-path modulation unit 3 includes a capacitor C2, a capacitor C3, an NMOS tube M2, an NMOS tube M3, an NMOS tube M 20 、NMOS tube M 21 、NMOS tube M 22 、NMOS tube M 23 、NMOS tube M 24 、NMOS tube M 25 、NMOS tube M 26 、NMOS tube M 27 、NMOS tube M 28 、NMOS tube M 29 、NMOS tube M 30 、NMOS tube M 31 、NMOS tube M 32、NMOS tube M 33 、NMOS tube M 34 、NMOS tube M 35 .

[0037] Next, on the one hand, the I-channel differential signal output by the orthogonal generation unit 1 is respectively connected to one end of the capacitor C0 and the capacitor C1 in the I-channel modulation unit 2, and the other ends of the capacitor C0 and the capacitor C1 are respectively connected to the gates of the NMOS tube M0 and the NMOS tube M1, and the source electrodes of the NMOS tube M0 and the NMOS tube M1 are grounded, and the NMOS tubes M4, M5, M6, M7, M8, M9, and M1 are grounded. 10 、NMOS tube M 11 The source of is connected to the drain of NMOS tube M0, and NMOS tube M 12 、NMOS tube M 13 、NMOS tube M 14 、NMOS tube M 15 、NMOS tube M 16 、NMOS tube M 17 、NMOS tube M 18 、NMOS tube M 19 The source of is connected to the drain of NMOS tube M1;

[0038] In the I-channel modulation unit 2, NMOS tubes M4, M5, M6, M7, and M8 are connected. 12 、NMOS tube M 13 、NMOS tube M 14 、NMOS tube M 15 The drain of the NMOS tube M8, the NMOS tube M9, and the NMOS tube M 10 、NMOS tube M 11 、NMOS tube M 16 、NMOS tube M 17 、NMOS tube M 18 、NMOS tube M 19 The drain electrode is connected to the negative output terminal of the I-channel modulation unit 2;

[0039] In the I-channel modulation unit 2, the gate lengths of all MOS tubes are equal, and the gate lengths of NMOS tubes M6, M7, and M8 are equal. 10 、NMOS tube M 11 、NMOS tube M 14 、NMOS tube M 15 、NMOS tube M 18 、NMOS tube M 19have the same gate width, which is set to 1 μm; NMOS tube M4, NMOS tube M5, NMOS tube M8, NMOS tube M9, NMOS tube M 12 、NMOS tube M 13 、NMOS tube M 16 、NMOS tube M 17 The two gate widths have the same gate width, which is set to 2.4 μm; these two gate widths satisfy a proportional relationship of 1-(√2 / 2):(√2 / 2).

[0040] In the I-channel modulation unit 2, NMOS tube M4, NMOS tube M5, NMOS tube M6, NMOS tube M7, NMOS tube M8, NMOS tube M9, NMOS tube M 10 、NMOS tube M 11 The gates of the NMOS tubes M are connected to the output terminals of the timing control unit 4 through capacitors, and are connected to the timing control signals I2(t), I3(t), I1(t), I4(t), I6(t), I7(t), I5(t), and I8(t) respectively; similarly, the NMOS tubes M 12 、NMOS tube M 13 、NMOS tube M 14 、NMOS tube M 15 、NMOS tube M 16 、NMOS tube M 17 、NMOS tube M 18 、NMOS tube M 19 The gates of are connected to the output terminals of the timing control unit 4 through capacitors, and are connected to the timing control signals I2(t), I3(t), I1(t), I4(t), I6(t), I7(t), I5(t), and I8(t) respectively. These square wave signals are continuous in phase. Figure 4 , I1(t)~I8(t) are square wave signals with a duty cycle of 50%. These square wave signals control the I-channel modulation unit 2 to achieve vector modulation. Figure 6 , the figure shows the corresponding relationship between the control signal, two specific gate width transistors and the normalized gain control timing in a single transistor array. The square wave signal controls the on and off of the transistors in each array to continuously achieve different gain amplitudes. At a certain moment, when all these transistors are turned on, the normalized gain amplitude is 1; when all these transistors are turned off, the normalized gain amplitude is -1. By controlling the two specific gate width transistors, the I-channel modulation unit 2 can output a vector modulation signal controlled by a sine-cosine signal equivalent to a two-step step signal.

[0041] On the other hand, the Q-path differential signal output by the orthogonal generation unit 1 is connected to one end of the capacitor C2 and the capacitor C3 in the Q-path modulation unit 3 respectively, and the other ends of the capacitor C2 and the capacitor C3 are connected to the gates of the NMOS tube M2 and the NMOS tube M3 respectively, and the sources of the NMOS tube M2 and the NMOS tube M3 are grounded. 20 、NMOS tube M 21 、NMOS tube M 22 、NMOS tube M 23 、NMOS tube M 24 、NMOS tube M 25 、NMOS tube M 26 、NMOS tube M 27 The source of the NMOS tube M2 is connected to the drain of the NMOS tube M2. 28 、NMOS tube M 29 、NMOS tube M 30 、NMOS tube M 31 、NMOS tube M 32 、NMOS tube M 33 、NMOS tube M 34 、NMOS tube M 35 The source of is connected to the drain of NMOS tube M3;

[0042] In the Q-path modulation unit 3, the NMOS tube M 20 、NMOS tube M 21 、NMOS tube M 22 、NMOS tube M 23 、NMOS tube M 28 、NMOS tube M 29 、NMOS tube M 30 、NMOS tube M 31 The drain of the Q-path modulation unit 3 is connected to the positive output terminal, and the NMOS tube M 24 、NMOS tube M 25 、NMOS tube M 26 、NMOS tube M 27 、NMOS tube M 32 、NMOS tube M 33 、NMOS tube M 34 、NMOS tube M 35 The drain is connected to the negative output terminal of the Q-path modulation unit 3;

[0043] In the Q-path modulation unit 3, the gate lengths of all MOS tubes are equal, and the gate lengths of NMOS tubes M 22 、NMOS tube M 23 、NMOS tube M 26 、NMOS tube M 27 、NMOS tube M 30 、NMOS tube M31 、NMOS tube M 34 、NMOS tube M 35 The gate width of the NMOS tube M is set to 1 μm. 20 、NMOS tube M 21 、NMOS tube M 24 、NMOS tube M 25 、NMOS tube M 38 、NMOS tube M 29 、NMOS tube M 32 、NMOS tube M 33 The two gate widths have the same gate width, which is set to 2.4 μm; these two gate widths satisfy a proportional relationship of 1-(√2 / 2):(√2 / 2).

[0044] In the Q-path modulation unit 3, in order to realize 3-bit vector modulation, the NMOS tube M 20 、NMOS tube M 21 、NMOS tube M 22 、NMOS tube M 23 、NMOS tube M 24 、NMOS tube M 25 、NMOS tube M 26 、NMOS tube M 27 The gates of the NMOS tubes M are connected to the output terminals of the timing control unit 4 through capacitors, and are connected to the timing control signals I8(t), I1(t), I7(t), I2(t), I4(t), I5(t), I3(t), and I6(t) respectively; similarly, the NMOS tubes M 28 、NMOS tube M 29 、NMOS tube M 30 、NMOS tube M 31 、NMOS tube M 32 、NMOS tube M 33 、NMOS tube M 34 、NMOS tube M 35The gates are connected to the output ends of the timing control unit 4 through capacitors, and are respectively connected to the timing control signals I8(t), I1(t), I7(t), I2(t), I4(t), I5(t), I3(t), and I6(t), so that the Q-channel modulation unit 3 can output a vector modulation signal controlled by a sine-cosine signal equivalent to a 2-order step signal. The basic principle is the same as that of the I-channel control unit 2. In order to realize 3-bit vector modulation in the present invention, for the Q-path modulation unit 3, the input phase of the control signal I1(t)~I8(t) is different from that of the I-path modulation unit 2. This is to enable the normalized gain control timing of the I-path modulation unit 2 and the Q-path modulation unit 3 to present a phase difference of 90° in phase. In the I-path modulation unit 2 and the Q-path modulation unit 3, the timing control signals I1(t)~I8(t) are respectively input to the gate of the common-gate MOS tube after passing through a single capacitor. The capacitor in the modulation signal path and the resistor in the bias circuit together form an RC high-pass filter structure, which has high permeability to high-frequency modulation signals and can block low-frequency signals and reduce low-frequency interference.

[0045] The present invention uses a vector summing amplifier with constant input impedance in all output states, and uses a digital radio frequency unit of a specific size to achieve precise modulation. In the I-channel modulation unit 2 and the Q-channel modulation unit 3, a common source and common gate amplifier is used to control the generation of orthogonal components with adjustable amplitudes, the radio frequency signal is input from the common source stage, the modulation signal is input from the common gate stage, the transconductance value of the common source stage is determined, and the total transconductance value of the common gate stage is determined by the number of common gate stage MOS tubes that are in the on state at the same time.

[0046] For the single sideband time modulator in this patent, at a certain moment of signal modulation, for the I-channel modulation unit 2, at this time, the NMOS tubes M7, M8, M9, and M 10 、NMOS tube M 12 、NMOS tube M 13 、NMOS tube M 14 、NMOS tube M 19 In the on state, NMOS tubes M4, M5, M6, and M 11 、NMOS tube M 15 、NMOS tube M 16 、NMOS tube M 17 、NMOS tube M 18 In the cut-off state. NMOS tube M7 and NMOS tube M 14 At the same time, the RF input signal RF in + and RF in- is inverted, so their voltage gains relative to the positive output are offset. Similarly, the NMOS tube M in the on state 10 and NMOS tube M 19 The voltage gain relative to the negative output terminal is also offset. Since the periodic square wave signals I1(t)~I4(t) and I5(t)~I8(t) are inverted, for each modulation unit, there are only eight NMOS tubes controlled by the modulation signal in the on state at the same time, so the input impedance seen from the input end is always constant.

[0047] The positive input end of the output buffer unit 5 is connected to the positive output end of the I-channel modulation unit 2 and the positive output end of the Q-channel modulation unit 3 at the same time, and the negative input end of the output buffer unit 5 is connected to the negative output end of the I-channel modulation unit 2 and the negative output end of the Q-channel modulation unit 3 at the same time, so as to realize the conversion from the differential signal to the single-ended signal. Finally, the output buffer unit 5 outputs the single-ended RF signal RF out .

[0048] See also Figure 4 and Figure 5 Here are the eight-way control timing I1(t)~I8(t) output by the timing control unit 4 and the I / Q path gain timing (period is T P , frequency is f P ), where the negative sign of the I / Q path gain is achieved by a 180° phase shift, and the design principle of the control timing is to make the I path gain timing and the Q path gain timing present a secondary step-type timing that is similar to a sine curve and a cosine curve, respectively. Figure 5 , where t1 and t'1 represent the moments when the I / Q path gain is positive, and t2 and t'2 represent the moments when the I / Q path gain is negative, so that the moments t2, t1, t'2 and t'1 satisfy: t2-t1=t'2-t'1=T P / 2 and t1-t'1=T P / 4, and the pulse width τ1 with a normalized gain of 1 and the pulse width τ2 with a normalized gain of √2 / 2 satisfy: τ2=3τ1=3T P / 8. At this time, the total gain of the single-sideband time modulator can be expressed as: G I (t)-jG Q (t), after Fourier series expansion, we can get:

[0049]

[0050] In formula (2), A k is the kth sideband (kf P ) (k=0,±1,…,±∞), under the above timing conditions, its formula is derived as follows:

[0051]

[0052] From equation (3), we can see that in the required +1 sideband, the complex amplitude A k The modulus value is constant, The time-varying vector synthesis phase term of the present invention changes the value of time t1, when t1∈[-3T P / 16,13T P / 16], a full 360° phase coverage can be achieved linearly. In addition, the useless sidebands other than the 8l+1 sideband are effectively suppressed, and the power suppression ratio of the largest useless sideband (-7 sideband) reaches -17dBc.

[0053] Under the premise of low power consumption and low cost, the present invention significantly improves the modulation frequency, can achieve ultra-wideband instantaneous bandwidth, constant input impedance and high +1st harmonic efficiency and other performances, and has advantages in high-frequency and broadband communication applications.

[0054] See also Figure 7 visible, Figure 7 This is the output spectrum diagram when the RF input signal frequency is 3GHz and the modulation signal frequency is 100MHz. At this time, the output signal falls on the +1 sideband. The closest unwanted sidebands are the +9th and -7th order sidebands, and the power suppression ratio of these maximum useless sidebands reaches -17dBc. The useless sidebands outside the 8l+1 (l=0,±1,…,±∞) sidebands are effectively suppressed. Figure 8 The output spectrum diagram is shown when the RF input signal frequency is 3 GHz and the modulation signal frequency is 1 GHz. At this time, the output modulation signal achieves a high modulation frequency and an ultra-wideband instantaneous bandwidth. IN to f IN +2*f P There is no interference from any harmonic components within the frequency range, and only the desired signal located in the +1 sideband is retained. At the same time, within the RF input signal frequency range of 2 to 6 GHz, the present invention can correctly generate a modulated signal with an ultra-wideband instantaneous bandwidth.

[0055] The above description is only a specific implementation mode of the present invention. Any feature disclosed in this specification, unless otherwise stated, can be replaced by other alternative features that are equivalent or have similar purposes; all the disclosed features, or all the steps in the methods or processes, except for mutually exclusive features and / or steps, can be combined in any way.

Claims

1. A single sideband time modulator with ultra-wideband instantaneous bandwidth, characterized in that: include: Orthogonal generation unit 1, I-channel modulation unit 2, Q-channel modulation unit 3, timing control unit 4, output buffer unit 5, differential RF input signal RF in + and RF in -An orthogonal differential signal is output after passing through the orthogonal generating unit 1, and the output end of the orthogonal generating unit 1 is respectively connected to the differential input ends of the I-path modulation unit and the Q-path modulation unit, and the orthogonal differential signal is respectively input into the I-path modulation unit and the Q-path modulation unit for vector modulation, wherein the I-path signal outputs a modulation signal with a phase of 0° / 180° after passing through the I-path modulation unit 2, and the Q-path signal outputs a modulation signal with a phase of 90° / 270° after passing through the Q-path modulation unit 3, and the output ends of the I-path modulation unit and the Q-path modulation unit are connected to the input end of the output buffer unit 5.

2. The single sideband time modulator with ultra-wideband instantaneous bandwidth according to claim 1, characterized in that: The I-path modulation unit 2 and the Q-path modulation unit 3 have the same structure and both include 4 transistor arrays, each of which includes 2 N -2 Transistors with different gate widths are used to realize vector modulation by sine and cosine signals equivalent to N-1 step signals, where N is the number of bits of the modulator.

3. The single sideband time modulator with ultra-wideband instantaneous bandwidth according to claim 2, characterized in that: 2 N-2 The gate widths of the transistors are: Where m = 0, 1, ... 2 N-2 -2, 2 N-2 -1.

4. The single sideband time modulator with ultra-wideband instantaneous bandwidth according to claim 2, characterized in that: N is 3.

5. The single sideband time modulator with ultra-wideband instantaneous bandwidth according to claim 4, characterized in that: The I-channel modulation unit 2 includes a capacitor C0, a capacitor C1, an NMOS tube M0, an NMOS tube M1, an NMOS tube M4, an NMOS tube M5, an NMOS tube M6, an NMOS tube M7, an NMOS tube M8, an NMOS tube M9, an NMOS tube M 10 、NMOS tube M 11 、NMOS tube M 12 、NMOS tube M 13 、NMOS tube M 14 、NMOS tube M 15 、NMOS tube M 16 、NMOS tube M 17 、NMOS tube M 18 、NMOS tube M 19 The I-channel differential signal output by the orthogonal generation unit 1 is respectively connected to one end of the capacitor C0 and the capacitor C1 in the I-channel modulation unit 2, and the other end of the capacitor C0 and the capacitor C1 are respectively connected to the gate of the NMOS tube M0 and the NMOS tube M1, and the source of the NMOS tube M0 and the NMOS tube M1 is grounded, and the NMOS tubes M4, M5, M6, M7, M8, M9, and M1 are connected to the ground. 10 、NMOS tube M 11 The source of is connected to the drain of NMOS tube M0, and NMOS tube M 12 、NMOS tube M 13 、NMOS tube M 14 、NMOS tube M 15 、NMOS tube M 16 、NMOS tube M 17 、NMOS tube M 18 、NMOS tube M 19 The source of the NMOS tube M1 is connected to the drain of the NMOS tube M4, the NMOS tube M5, the NMOS tube M6, the NMOS tube M7, and the NMOS tube M 12 、NMOS tube M 13 、NMOS tube M 14 、NMOS tube M 15 The drain of the NMOS tube M8, the NMOS tube M9, and the NMOS tube M 10 、NMOS tube M 11 、NMOS tube M 16 、NMOS tube M 17 、NMOS tube M 18 、NMOS tube M 19 The drain is connected to the negative output end of the I-way modulation unit 2.

6. The single sideband time modulator with ultra-wideband instantaneous bandwidth according to claim 5, characterized in that: NMOS tube M0, NMOS tube M1, NMOS tube M4, NMOS tube M5, NMOS tube M6, NMOS tube M7, NMOS tube M8, NMOS tube M9, NMOS tube M 10 、NMOS tube M 11 、NMOS tube M 12 、NMOS tube M 13 、NMOS tube M 14 、NMOS tube M 15 、NMOS tube M 16 、NMOS tube M 17 、NMOS tube M 18 、NMOS tube M 19 The gate lengths are equal.

7. The single sideband time modulator with ultra-wideband instantaneous bandwidth according to claim 4, characterized in that: The Q-path modulation unit 3 includes a capacitor C2, a capacitor C3, an NMOS transistor M2, an NMOS transistor M3, an NMOS transistor M 20 、NMOS tube M 21 、NMOS tube M 22 、NMOS tube M 23 、NMOS tube M 24 、NMOS tube M 25 、NMOS tube M 26 、NMOS tube M 27 、NMOS tube M 28 、NMOS tube M 29 、NMOS tube M 30 、NMOS tube M 31 、NMOS tube M 32 、NMOS tube M 33 、NMOS tube M 34 、NMOS tube M 35 The Q-path differential signal output by the orthogonal generating unit 1 is connected to one end of the capacitor C2 and the capacitor C3 in the Q-path modulation unit 3 respectively, and the other ends of the capacitor C2 and the capacitor C3 are connected to the gates of the NMOS tube M2 and the NMOS tube M3 respectively, and the sources of the NMOS tube M2 and the NMOS tube M3 are grounded. 20 、NMOS tube M 21 、NMOS tube M 22 、NMOS tube M 23 、NMOS tube M 24 、NMOS tube M 25 、NMOS tube M 26 、NMOS tube M 27 The source of the NMOS tube M2 is connected to the drain of the NMOS tube M2. 28 、NMOS tube M 29 、NMOS tube M 30 、NMOS tube M 31 、NMOS tube M 32 、NMOS tube M 33 、NMOS tube M 34 、NMOS tube M 35 The source of the NMOS tube M3 is connected to the drain of the NMOS tube M4, the NMOS tube M5, the NMOS tube M6, the NMOS tube M7, and the NMOS tube M 12 、NMOS tube M 13 、NMOS tube M 14 、NMOS tube M 15 The drain of the NMOS tube M8, the NMOS tube M9, and the NMOS tube M 10 、NMOS tube M 11 、NMOS tube M 16 、NMOS tube M 17 、NMOS tube M 18 、NMOS tube M 19 The drain is connected to the negative output end of the I-way modulation unit 2.

8. The single sideband time modulator with ultra-wideband instantaneous bandwidth according to claim 7, characterized in that: NMOS tube M2, NMOS tube M3, NMOS tube M 20 、NMOS tube M 21 、NMOS tube M 22 、NMOS tube M 23 、NMOS tube M 24 、NMOS tube M 25 、NMOS tube M 26 、NMOS tube M 27 、NMOS tube M 28 、NMOS tube M 29 、NMOS tube M 30 、NMOS tube M 31 、NMOS tube M 32 、NMOS tube M 33 、NMOS tube M 34 、NMOS tube M 35 The gate lengths are equal.

9. The single sideband time modulator with ultra-wideband instantaneous bandwidth according to claim 2, characterized in that: The timing control unit 4 has 2 N The output end generates a square wave signal with a 50% duty cycle as a modulation signal and inputs it into the modulation signal input end of the I modulation unit 2 and the Q modulation unit 3. The period is T P , so that the gain control timing of the I-channel modulation unit 2 when performing vector modulation on the input signal presents an N-1-level step-type timing of a sine curve, and the gain control timing of the Q-channel modulation unit 3 when performing vector modulation on the input signal presents an N-1-level step-type timing of a cosine curve, so that the time t2, t1, t'2 and t'1 satisfy: t2-t1=t'2-t'1=T P / 2 and t1-t'1=T P / 4, where t1 and t'1 represent the positive moments of the gain control timing of the I and Q paths, respectively, and t2 and t'2 represent the negative moments of the gain control timing of the I and Q paths, respectively, and the pulse width τ1 with a normalized gain of sin[π / (2N)] satisfies: τ1=(2N-1)T P / (4N), the normalized gain is sin[π(N-1) / (2N)], the pulse width τ N-1 Satisfy: τ N-1 =3T P / (4N), the normalized gain is sin[πN / (2N)], the pulse width τ N Satisfy: τ N =T P / (4N).

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