A BUCK converter and a variable gain error amplifier circuit

Abstract

The present application provides a BUCK converter and a variable gain error amplifier circuit, which are applied to the technical fields of power supply chips and BUCK converters. By improving the error amplifier in the BUCK converter into a variable gain error amplifier, the error amplifier gain is switched by a feedback detection circuit to determine whether there is load switching (such as overshoot / undershoot) at the output end. For example, when it is detected that the output is in a load switching state, the error amplifier circuit quickly enters the overshoot / undershoot mode, increases the instantaneous current of the response branch, speeds up the response speed, and achieves a lower transient voltage, which has the characteristics of fast response, and can continue to maintain the advantage of high efficiency during normal operation.

Description

Technical Field

[0001] The present application relates to the technical field of power supply chips and BUCK converters, and in particular to a BUCK converter and a variable gain error amplifier circuit. Background Art

[0002] In people's daily lives, electronic products such as communication equipment, smart homes, photographic equipment and smart wearables can be seen everywhere. The functions of these electronic products are becoming more and more complex, and more and more diverse product functions are being developed, which requires the internal power supply system of the equipment to have a stronger load capacity, faster response speed, and more efficient conversion efficiency. When the electronic product is working, when the user switches the function, for the power supply system inside the device, it is equivalent to switching the output load current. At this time, the transient response of the power supply output is particularly critical. For example, the power supply system must have a fast response speed and a small transient response voltage to ensure the normal operation of the back-end load.

[0003] Among power management chips, step-down DC-DC converters (BUCK converters for short) are widely used in the power supply of various electronic devices due to their high efficiency, strong stability, strong load capacity, etc. Therefore, for the design of BUCK converters, it is particularly important to have a fast response speed when switching loads in circuit design. Summary of the invention

[0004] In view of this, the embodiments of the present specification provide a BUCK converter and a variable gain error amplifier circuit, in which the error amplifier is improved into a variable gain error amplifier in the BUCK converter, wherein the error amplification gain is switched based on whether there is load switching (such as overshoot / undershoot) at the output end through a feedback detection circuit. For example, when it is detected that the output is in a load switching state, the error amplifier circuit quickly enters the overshoot / undershoot mode, and increases the instantaneous current of the response branch to speed up the response speed and achieve a lower transient voltage, thereby having the characteristics of fast response, and can continue to maintain the advantage of high efficiency during normal operation.

[0005] The embodiments of this specification provide the following technical solutions:

[0006] The embodiment of this specification provides a variable gain error amplifier circuit, which is applied to a BUCK converter. The error amplifier circuit includes: a feedforward capacitor, a variable gain amplifier unit, a feedback detection circuit, and a delay timer;

[0007] One end of the feedforward capacitor is connected to the output end and the feedback voltage end of the BUCK converter;

[0008] The feedback detection circuit and the delay timer are connected in series between the feedback voltage terminal and the variable gain amplifier unit in sequence, wherein the feedback detection circuit is used to detect whether the change of the feedback voltage at the feedback voltage terminal exceeds a preset threshold value, and if so, output a trigger signal to the delay timer, so that the delay timer outputs a pulse control signal to the variable gain amplifier unit under the action of the trigger signal, and the pulse control signal is a pulse signal generated by the delay timer according to preset parameters after being triggered by the trigger signal;

[0009] The variable gain amplifier unit serves as an error amplifier of the BUCK converter, and is used to perform error amplification on the feedback voltage at the feedback voltage end and the reference reference with a first gain during the period when the pulse control signal is on, and to perform error amplification on the feedback voltage at the feedback voltage end and the reference reference with a second gain during the period when the pulse control signal is not on, wherein the first gain is greater than the second gain.

[0010] An embodiment of the present specification also provides a BUCK converter, including an error amplifier and an RC loop, wherein the error amplifier is a variable gain error amplifier circuit as described in any example in the present application; the RC loop is connected in parallel between the error amplification output terminal of the error amplifier and ground, and the RC loop includes a loop resistor and a loop capacitor connected in series; the error amplifier is used to operate in a first mode within a preset first time when an overshoot / undershoot is detected in the feedback voltage to provide a first charge and discharge current to the RC loop, and to restore to a second mode after the first mode ends to provide a second charge and discharge current to the RC loop, wherein the first mode is an operating mode for error amplification with a first gain, and the second mode is an operating mode for error amplification with a second gain, and the first gain is greater than the second gain, so that the first charge and discharge current is greater than the second charge and discharge current.

[0011] Compared with the prior art, the beneficial effects that can be achieved by at least one of the above technical solutions adopted in the embodiments of this specification include at least:

[0012] Compared with the existing methods for improving the response speed of the BUCK system loop at home and abroad, the present invention adopts an innovative transient gain enhancement path structure, in which the feedforward capacitor CFF and the feedback (FB) detection circuit are used together to detect whether the FB voltage is in a state of rapid decline or rise, and to judge whether the output is in a load switching state. When the circuit is in a load switching state, the FB detection circuit outputs a control signal to enter the overshoot / undershoot mode (abbreviated as UO mode) caused by load switching, and promptly increases the Gm of the error amplifier, increases the current charging VC, and the system loop responds quickly and quickly increases the transient bias current to obtain a smaller transient voltage. In the normal working period when the load is not switched, it has the advantage of high efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0014] Figure 1 It is a schematic diagram of a new structure of a BUCK converter based on a variable gain error amplifier circuit with fast response characteristics in the present application;

[0015] Figure 2 It is a schematic diagram of the transient response simulation results of the BUCK converter with a new structure in the present application when the load is switched from 1A to 1.5A;

[0016] Figure 3 It is a schematic diagram of the simulation result of the conversion efficiency curve of the BUCK converter with a new structure in this application;

[0017] Figure 4 is a schematic diagram of an undershoot detection circuit based on a transistor circuit in this application;

[0018] Figure 5 is a schematic diagram illustrating an overshoot / undershoot detection circuit based on a transistor circuit in the present application;

[0019] Figure 6 It is a schematic diagram of a variable gain amplifier unit circuit based on a transistor circuit in the present application. DETAILED DESCRIPTION

[0020] The embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0021] The following describes the implementation methods of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The present application can also be implemented or applied through other different specific implementation methods, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, in the absence of conflict, the following embodiments and the features in the embodiments can be combined with each other. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work belong to the scope of protection of the present application.

[0022] It should be noted that various aspects of the embodiments within the scope of the appended claims are described below. It should be apparent that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is merely illustrative. Based on the present application, it should be understood by those skilled in the art that an aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number and aspect described herein can be used to implement the device and / or practice the method. In addition, other structures and / or functionalities other than one or more of the aspects described herein can be used to implement this device and / or practice this method.

[0023] It should also be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present application. The drawings only show components related to the present application rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0024] Additionally, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, it will be understood by those skilled in the art that the examples can be practiced without these specific details.

[0025] In the BUCK architecture, there are two main approaches to improve the response speed during load switching:

[0026] The first is based on linear control theory design, which increases the bandwidth of the system and optimizes it in mainstream control architectures such as voltage or current mode. The advantages of this type of linear control theory architecture are small output ripple and good noise resistance, but the disadvantage is that a compensation circuit needs to be added to improve the response speed;

[0027] The other is to use a nonlinear control architecture, such as hysteresis control, which can obtain faster feedback when the load changes. However, since the operating frequency of this control mode is variable, it performs poorly in the electromagnetic interference index, and the output jitter of hysteresis control is large.

[0028] Combining the advantages and disadvantages of the above two architectures, the present application adopts a BUCK architecture with current mode control and innovates on the traditional BUCK architecture with current mode control.

[0029] In the current mode controlled BUCK architecture, there are several directions to improve the bandwidth:

[0030] 1. Shifting the main pole to the right can reduce the equivalent capacitance or equivalent resistance corresponding to the main pole; 2. Increasing the loop gain can increase the bandwidth by directly increasing the loop gain; 3. Adding appropriate zeros to the loop can expand the bandwidth and speed up the circuit response.

[0031] In order to speed up the response speed, a higher bandwidth is set, which is usually achieved at the expense of static power consumption, but the transient response speed cannot be increased indefinitely. For a BUCK structure with a fixed operating frequency, the system bandwidth is generally set at about one-tenth to one-sixth of the operating frequency. For the overall system, if a higher bandwidth is set, although the system response speed is accelerated and the transient voltage is reduced, the loop phase margin is sacrificed accordingly, and there is a risk of loop instability. Although a lower system bandwidth ensures the stability of the system, it will cause the system response speed to be too slow, and the corresponding transient voltage will be too large, which will affect the subsequent load.

[0032] Therefore, for the current mode controlled BUCK architecture, setting an appropriate system bandwidth requires a trade-off between the system's loop stability, transient response speed, and power consumption.

[0033] In summary, the present invention proposes a BUCK structure with fast response characteristics and high efficiency. The innovation of this structure is: based on the BUCK architecture of current mode control, a circuit for detecting the output voltage is added. When it is detected that the output is in a load switching state, the circuit quickly enters the Undershoot / Overshoot mode (abbreviated as UOmode), and by increasing the instantaneous current of the response branch, the response speed is accelerated, and a lower transient voltage is achieved. It has the characteristics of fast response, and when the system is working normally, it has the advantage of high efficiency.

[0034] refer to Figure 1As shown in the figure, the innovative structure proposed in the present application is as follows: based on the current mode, a feedforward capacitor CFF and a feedback detection circuit FB are used to control the switching of different modes, thereby forming a path for enhancing instantaneous gain and accelerating the circuit response speed.

[0035] The working principle is as follows: Figure 1 As shown in the figure, by detecting whether the FB voltage is in a state of rapid decline or rise, it is determined whether the output is in a load switching state. When the circuit is in a load switching state, the FB detection circuit outputs a control signal and enters UO mode, increasing the transconductance (Gm) of the error amplifier and increasing the capacitance C VC The charging current, when the converter is in the load switching state (UO mode), quickly responds to the impact of load switching, which significantly reduces the amplitude of overshoot / undershoot and improves the load response characteristics of the converter. When the converter is working normally, that is, no-load conversion, it returns to the original efficient rectification and voltage regulation state, maintaining the high efficiency advantage of the converter.

[0036] The structure proposed in this application has obvious advantages over the traditional current mode control structure when verifying transient response performance.

[0037] Figure 2 The new structure proposed in this application is shown (reference Figure 1 The simulation conditions for transient response are as follows: V IN =12V, V OUT =5V, L=2.2μH, C OUT =22μF, R TOP =1MΩ, R BOT =187kΩ, C FF =10pF, operating frequency is around 2.2MHz, load current I LOAD Switches between 1A and 1.5A at a rate of 1A / μs. Figure 2 The curves shown are the results of the following three different situations: First, the traditional current mode control architecture does not set the feedforward capacitor C FF , the curve result corresponds to no C FF (Without CFF) curve; the second is the traditional current mode control architecture with feedforward capacitor C FF The slightly improved structure of the curve results in this case is C FF (WithCFF) curve; the third is the new structure proposed in this application, and the curve result corresponds to the curve of the optimized and improved new structure (this work).

[0038] Therefore, the new structure proposed in this application reduces the transient voltage of overshoot and undershoot by about 43% and 65% respectively. It can be seen that the innovative structure proposed in this application can significantly improve the response speed of the loop, thereby effectively reducing the amplitude of undershoot / overshoot voltage.

[0039] Figure 3 The converter efficiency curve of the new structure of this application is shown, and the conversion efficiency simulation curve of the new structure proposed in this application under different input voltages and load currents can be seen. The simulation conditions are as follows: Set V OUT =5V, L=2.2μH, C OUT =22μF, given different input voltage V IN And the load I LOAD The simulation shows that the peak efficiency is 96.09% at V IN =6.5V, I LOAD =0.75A.

[0040] In summary, the structure proposed in the present application can significantly improve the transient response speed during load switching while ensuring the advantage of high efficiency, thereby improving the overall performance of the converter.

[0041] The technical solutions provided by various embodiments of the present application are described below in conjunction with the accompanying drawings.

[0042] like Figure 1 As shown, in the variable gain error amplifier circuit proposed in the present application, the conventional error gain amplifier is improved into a new structure error amplifier (Proposed Error Amplifier) ​​to meet the design requirements of the overshoot / undershoot situation that may occur in the switching load of the converter and need to respond quickly. That is, in addition to introducing the feedforward capacitor C FF In addition, two additional functions are added: an FB detection circuit for detecting whether the load is switched, and a control mode (also known as UO mode, Under / Overshoot Mode) of the error amplifier working mechanism that quickly changes the error amplifier working gain according to the detection result. Therefore, by combining the feedforward capacitor CFF and the FB detection circuit, different amplification gain modes are controlled between load switching and non-switching, so that the error amplifier can form a path for instantaneous gain enhancement, thereby providing an instantaneous increase in charge and discharge current for the loop (such as the RC loop at the output end of the error amplifier), thereby speeding up the circuit response speed.

[0043] refer to Figure 1 As shown in the figure, the feedforward capacitor C is introduced FF The voltage divider resistor R connected across the feedback circuit TOP The two ends, namely the feedforward capacitor C FFOne end of the feedforward capacitor C is connected to the output end of the BUCK converter and the feedback voltage end FB. If there is load switching, the feedforward capacitor C FF The load switching can be sensed quickly, thereby providing a sensing signal to the feedback detection circuit (FB Detecting Circuit).

[0044] A feedback detection circuit and a delay timer (COUNT) are connected in series between the feedback voltage terminal FB and the variable gain amplifier unit in sequence, wherein the feedback detection circuit is used to detect whether the change of the feedback voltage of the feedback voltage terminal FB exceeds a preset threshold value, and if so, outputs a trigger signal to the delay timer, so that the delay timer outputs a pulse control signal to the variable gain amplifier unit under the action of the trigger signal, and the pulse control signal is a pulse signal generated by the delay timer according to preset parameters after being triggered by the trigger signal.

[0045] In implementation, the feedback detection circuit may be a circuit for detecting a signal. For example, since overshoot / undershoot is a signal superimposed on the output voltage Vout, and the signal has a certain amplitude and width, a peak detection circuit may be used to complete the detection. Specifically, by setting a detection threshold, it is determined that an overshoot / undershoot exists after the peak amplitude exceeds the threshold, thereby triggering a delay timer to generate a pulse control signal.

[0046] In implementation, the delay timer may be a circuit that automatically generates a preset pulse width signal after being triggered, such as a steady-state analog circuit, a timer circuit, or other circuit forms.

[0047] In implementation, the variable gain amplifier unit serves as an error amplifier of the BUCK converter, and is used to perform error amplification on the feedback voltage at the feedback voltage end and the reference reference with a first gain during the period when the pulse control signal is on, and to perform error amplification on the feedback voltage at the feedback voltage end and the reference reference with a second gain during the period when the pulse control signal is not on, wherein the first gain is greater than the second gain.

[0048] In implementation, the variable gain amplifier unit is different from the original error amplifier. The variable gain amplifier unit can work in different modes, that is, under the control of the pulse control signal output by the feedback detection circuit, it can work in different modes: normal mode (Normal Mode) and UO mode (UO Mode, Under / Over shoot Mode), wherein the normal mode can be a working mode in which the second gain is used for error amplification, and the UO mode can be a working mode in which the first gain is used for error amplification, and the first gain is greater than the second gain, so that the error amplification gain is temporarily increased in the UO mode to form a larger error amplification result, thereby providing a loop outside the error amplifier (for example, with RVC , C VC The RC loop formed by the capacitor provides a larger instantaneous charge and discharge current.

[0049] It should be noted that the variable gain amplifier unit is still the same as the original error amplifier, which is used to adjust the feedback voltage of the feedback voltage terminal FB and the reference voltage V REF Error amplification is performed to provide the error amplification voltage V to the loop C .

[0050] refer to Figure 1 As shown in the figure, the FB detection circuit can be divided into three parts: Undershoot detecting circuit, overshoot detecting circuit and delay timer (U / OCOUNT, the delay timer can be implemented using a monostable circuit).

[0051] During implementation, the overshoot detection circuit is used to detect whether the feedback voltage at the feedback voltage end overshoots to a first preset threshold value, and if so, outputs the trigger signal; the undershoot detection circuit is used to detect whether the feedback voltage at the feedback voltage end undershoots to a second preset threshold value, and if so, outputs the trigger signal.

[0052] In some embodiments, the undershoot detection circuit of FB is as follows Figure 4 As shown: the undershoot detection circuit includes a first coupling capacitor C1, a first bootstrap resistor R1, a first current mirror (for example, a current mirror composed of a current source and MP0 and MP1), and a first amplifier NM1; the first coupling capacitor C1 is used to couple the feedback voltage of the feedback voltage terminal FB to the gate of the first amplifier NM1, the drain of the first amplifier NM1 is provided with a working current by the first current mirror, the source of the first amplifier NM1 is grounded, and the first bootstrap resistor R1 is connected across the drain and the gate of the first amplifier NM1.

[0053] In some implementations, since the overshoot / undershoot is usually of a smaller magnitude (relative to the output terminal Vout), more stages of amplifier tubes may be used for amplification and detection.

[0054] For example, the undershoot detection circuit also includes a third amplifier tube NM2 and a third current mirror (for example, a current mirror composed of a current source and MP0 and MP2), wherein the third amplifier tube NM2 is used to amplify the trigger signal output by the first amplifier tube NM1, and the third current mirror is used to provide a working current for the third amplifier tube NM2.

[0055] For example, the undershoot detection circuit also includes a fifth amplifier tube NM3 and a fifth current mirror (for example, a current mirror composed of a current source and MP0 and MP3), wherein the fifth amplifier tube NM3 is used to amplify the trigger signal output by the third amplifier tube NM2, and the fifth current mirror is used to provide a working current for the fifth amplifier tube NM3.

[0056] In some implementations, the overshoot detection circuit may take a form similar to the undershoot detection circuit.

[0057] For example, the overshoot detection circuit of FB is as follows Figure 5 As shown in the lower half of the figure: the overshoot detection circuit includes a second coupling capacitor C2, a second bootstrap resistor R2, a second current mirror (for example, a current mirror composed of a current source and NM0 and NM4), and a second amplifier tube MP4; wherein the second coupling capacitor C2 is used to couple the feedback voltage of the feedback voltage terminal to the gate of the second amplifier tube MP4, the drain of the second amplifier tube MP4 is provided with an operating current by the second current mirror, the source of the second amplifier tube MP4 is connected to the power supply terminal, and the second bootstrap resistor R2 is connected across the drain and the gate of the second amplifier tube MP4.

[0058] Correspondingly, the overshoot detection circuit may also be in the form of a multi-stage transistor amplifier circuit.

[0059] For example, the overshoot detection circuit includes a fourth amplifier tube MP5 and a fourth current mirror (for example, a current mirror composed of a current source and NM0 and NM5), wherein the fourth amplifier tube MP5 is used to amplify the trigger signal output by the second amplifier tube MP4 of the previous stage, and the fourth current mirror is used to provide a working current for the fourth amplifier tube MP5.

[0060] For example, the overshoot detection circuit includes a sixth amplifier tube MP6 and a sixth current mirror (for example, a current mirror composed of a current source and NM0 and NM6), wherein the sixth amplifier tube MP6 is used to amplify the trigger signal output by the fourth amplifier tube MP5 of the previous stage, and the sixth current mirror is used to provide a working current for the sixth amplifier tube MP6.

[0061] In some embodiments, when the multi-stage amplifier is implemented in a semiconductor, it can be designed in proportion.

[0062] For example, the currents between the current mirrors are designed to be proportional. For example, the third current mirror is proportional to the first current mirror, and / or the fifth current mirror is proportional to the third current mirror and / or the first current mirror. For example, the fourth current mirror is proportional to the second current mirror, and / or the sixth current mirror is proportional to the fourth current mirror and / or the second current mirror.

[0063] Through current proportional design, the parameter design between the amplifier stages can be simplified, which is also beneficial to improving the amplification performance.

[0064] For example, the sizes of the amplifier tubes are designed to be proportional. For example, the size of the third amplifier tube NM2 is proportional to the size of the first amplifier tube NM1; the size of the fifth amplifier tube NM3 is proportional to the size of the first amplifier tube NM1 and / or the third amplifier tube NM2; for example, the size of the fourth amplifier tube MP5 is proportional to the size of the second amplifier tube MP4; for example, the size of the sixth amplifier tube MP6 is proportional to the size of the fourth amplifier tube MP5 and / or the second amplifier tube MP4.

[0065] For example, in the proportional design of the amplifier tubes, the size of the fifth amplifier tube NM3 is proportional to the size of the third amplifier tube NM2, the size of the third amplifier tube NM2 is proportional to the size of the first amplifier tube NM1, and the size of MN3 is set to be relatively large, and the pull-down capability is stronger. During normal operation, VO3 can still be a low-level signal with a lower amplitude, and the undershoot detection signal output will not be triggered due to noise, thereby ensuring the reliability and accuracy of the detection.

[0066] Similarly, a similar size design can also be used in the overshoot detection circuit. For example, the size of MP6 is proportional to the size of MP5, and MP5 is proportional to MP4. The size of MP6 is set larger (for example, larger than the preset size), thereby increasing the pull-up current capability of MP6, so that the high level of the trigger signal is maintained above the preset high level signal, and the overshoot detection signal output will not be triggered due to noise, thereby ensuring the reliability and accuracy of the detection.

[0067] In some implementations, the current source may also be designed with reference to the size ratio between the amplifier tubes. In particular, multiple current sources may also form a proportional design relationship with the same reference source.

[0068] For example, the first current mirror, the third current mirror and the fifth current mirror share the same first reference current source to form a first current source bias circuit.

[0069] For example, the second current mirror, the fourth current mirror and the sixth current mirror share the same second reference current source to form a second current source bias circuit.

[0070] Continue to refer Figure 5 Schematic diagram: The first current source bias circuit includes: a first reference current source, MP0, MP1, MP2 and MP3; wherein MP0 and the reference current source provide a reference current, MP1 proportionally copies the current to provide a working current for NM1, MP2 proportionally copies the current to provide a working current for NM2, and MP3 proportionally copies the current to provide a working current for NM3.

[0071] Similarly, the second current source bias circuit includes: a second reference current source, NM0, NM4, NM5 and NM6; wherein NM0 and the reference current source provide a reference current, NM4 proportionally copies the current to provide a working current for MP4, NM5 proportionally copies the current to provide a working current for MP5, and NM6 proportionally copies the current to provide a working current for MP6.

[0072] In some implementations, a waveform shaping circuit may be used to form a pulse signal with a steep edge for a signal detected by a detection circuit from a feedback voltage.

[0073] For example, the shaping circuit can be in the form of a Schmitt trigger, an inverter, or a combination of the two. Figure 4 and Figure 5 Illustration: Add circuits such as a mitre trigger and an inverter to the detection circuit.

[0074] For example, a first Schmitt trigger circuit and a first inverter circuit are provided in the undershoot detection circuit, so that the detection result forms a trigger pulse signal with a steep edge as the trigger signal, so that the edge of the trigger signal is steep, and the high level and the low level are more stable, so as to better trigger the delay timer to work. Similarly, a second Schmitt trigger circuit and a second inverter circuit are provided in the overshoot detection circuit.

[0075] In implementation, the Schmitt trigger circuit is used to perform shaping on the detection signal, and the inverter circuit further performs inversion processing on the shaped signal output by the Schmitt trigger circuit to generate the trigger signal in the pulse form (such as a positive pulse waveform) required by the delay timer. In addition, the detection signal is a signal obtained by the amplifier circuit based on threshold detection of the overshoot / undershoot existing on the feedback voltage of the feedback voltage terminal.

[0076] In some embodiments, since the signal width of overshoot / undershoot occurring during load switching may be relatively narrow (e.g., microsecond level or even nanosecond level) or relatively wide (e.g., hundreds of micrometers or even millisecond level), a delay timer may be used to form a pulse model with a relatively uniform width. Specifically, the delay timer generates the pulse control signal with a pulse width of 50-200 μs, preferably 100 μs, based on timing when triggered by the trigger signal, so that a compromise can be made between conversion efficiency and response speed to obtain better overall performance.

[0077] In some implementations, the variable gain amplifying unit may be in the form of a circuit of an amplifying unit and a gain variable unit, or may be in the form of an amplifying unit with adjustable gain.

[0078] The present application provides a variable gain amplifying unit, which comprises: an amplifying unit and a gain variable unit; wherein the gain variable unit comprises a plurality of gain resistors and a plurality of switches, wherein the gain resistors are used to set the gain of the amplifying unit, and the switches are connected in parallel or in series with the gain resistors, so that the gain resistors are connected to the amplifying unit or disconnected from the amplifying unit or the gain resistors are short-circuited by turning the switches on and off under the control of the pulse control signal, so that the amplifying unit operates at the first gain during the working period of the pulse control signal, and operates at the second gain during the non-working period of the pulse control signal.

[0079] In one example, the gain resistor is used as a bias and / or load of a transistor amplifier circuit, so that the gain resistor is connected, disconnected or short-circuited in the bias branch and / or load branch by a switch to achieve a change in the transistor operating point to achieve transistor gain switching.

[0080] In implementation, the amplification unit includes a differential amplifier circuit, wherein one input end of the differential amplifier circuit is connected to the feedback voltage end, and the other input end is connected to the reference reference, the switch is connected in parallel with the gain resistor, and the gain resistor is used as a bias and / or load of the differential amplifier circuit, so that the switch is turned on during the operation of the pulse control signal, thereby reducing the size of the resistance connected to the differential amplifier circuit, so that the gain of the differential amplifier circuit is increased to the preset first gain, and the switch is turned off during the non-operating period of the pulse control signal, thereby restoring the size of the resistance connected to the differential amplifier circuit, so that the gain of the differential amplifier circuit is restored to the preset second gain.

[0081] It should be noted that the size of the connected resistor is used to change the operating point of the transistor. The connection, disconnection or short circuit of the resistor can be achieved through switch control. Therefore, when the switch changes the connection, disconnection or short circuit of the resistor, the switch and the resistor can be in parallel (for example, refer to Figure 6 Schematic diagram of the SPL switch and R PLThe parallel connection relationship of resistors) is realized, so that the resistor is short-circuited by the switch. At this time, after the resistor is short-circuited by the switch, the resistance value of the connected circuit is reduced to zero (equivalent to the on-resistance of the switch close to zero), the switch is turned on as a current path, and the resistor is connected to the circuit by disconnecting the switch; the switch and the resistor can also be in a series relationship (not shown in the figure), such as using multiple switches to realize the series or parallel connection between multiple resistors to form the connection or disconnection of the equivalent resistor in the circuit. Therefore, in the implementation example of the switch controlling the resistor, the switch can connect the resistor to the circuit, or the switch can disconnect the resistor from the circuit, or the switch can short-circuit the resistor (that is, after the resistor is short-circuited by the switch, the turned-on switch serves as a path). The specific method can be set according to the circuit form in which the resistor affects the gain in the circuit.

[0082] The present application provides a variable gain amplifier unit for implementing differential amplification based on transistors: Figure 6 Schematically, the differential amplifier circuit includes a first transistor M1L, a second transistor M1R, a third transistor M2L, a fourth transistor M2R, a fifth transistor M3L, a sixth transistor M3R, a seventh transistor M4L, an eighth transistor M4R, a ninth transistor M5L, a tenth transistor M5R, an eleventh transistor M6L, a twelfth transistor M6R, a first bias resistor R L0 and the second bias resistor R R0 , the plurality of gain resistors include a first gain resistor R NL , the second gain resistor R NR , the third gain resistor R PL and the fourth gain resistor R PR The plurality of switches include a first switch SNL, a second switch SNR, a third switch SPL and a fourth switch SPR.

[0083] The connection relationship between the components is as follows: the gate of M1L is connected to the feedback voltage V FB , the gate of M1R is connected to the reference voltage V REF ; The source of M1L and the source of M1R are biased by a current source; the drain of M1L is connected to the drain of M2L and the gate of M3L, the drain of M1R is connected to the drain of M2R and the gate of M3R, the gate of M2L is connected to the gate of M2R, and R is connected between the gate and drain of M2L 0L , R is connected between the gate and drain of M2R 0R , the source of M2L and the source of M2R are grounded; SNL and R NL After being connected in parallel, it is connected in series between the source and ground of M3L, SNR and R NRAfter being connected in parallel, they are connected in series between the source of M3R and the ground; the drain of M3L is connected to the source of M4L, the drain of M3R is connected to the source of M4R, and the gate of M4L and the gate of M4R are connected to the first bias voltage V B1 The drain and gate of M5L are connected to the drain of M4L, the drain of M5R is connected to the drain of M4R and serves as the error amplifier output terminal Vc, the gate of M5L is connected to the gate of M5R; the gate and drain of M6L are connected to the source of M5L, the drain of M6R is connected to the source of M5R, and the gate of M6L is connected to the gate of M6R; SPL and R PL After being connected in parallel, they are connected in series between the power supply terminal and the source of M6L. SPR and R PR After being connected in parallel, they are connected in series between the power supply end and the source of M6R; the first switch SNL, the second switch SNR, the third switch SPL, and the fourth switch SPR are all controlled by the pulse control signal (for example Figure 6 UO MODE signal shown).

[0084] In summary, based on the circuit connection relationship and circuit device characteristics, the circuit working principles in each example are briefly illustrated as follows:

[0085] When the output is working normally, the FB node voltage is stable at the set V REF Nearby, it can be approximately regarded as a sine wave. For the first stage detection circuit, the gate G end of MN1 is connected by R1 to form a diode, and MN1 and MP1 form the first stage detection circuit to amplify the higher frequency signal of FB. MN2 and MP2 form the second stage of the detection circuit, and their size is proportional to the size of the first stage to enhance the amplification gain. The last stage of the MN3 and MP3-shaped detection circuit is set to a relatively large size of MN3, with strong pull-down capability. During normal operation, VO3 is still a low-level signal and does not trigger the undershoot signal.

[0086] When the output is switching from a lower load to a higher load, the FB undershoot detection circuit works as follows: Figure 4 The arrow in the middle indicates that the voltage at the FB node senses the drop in the output quickly due to the presence of the feed-forward capacitor CFF. The G terminal of MN1 drops rapidly due to the presence of the C1 capacitor, and the pull-down current of MN1 decreases. Part of the current flowing through MP1 charges the G terminal of MN1 through R1, and part of it charges the D terminal of MN1 (the G terminal of MN2). As the pull-down current of MN1 decreases, the voltage at the VO1 node rises, the voltage at the VO2 node drops, and the voltage at the VO3 node rises. Finally, at the output end of the detection circuit, for example, when the inverter is the final stage circuit, the inverter outputs a trigger signal (Undershoot mode signal).

[0087] Similarly, the Overshoot detection circuit and Undershoot detection circuit of FB form a symmetrical structure (refer to Figure 5 Schematic circuit), so the working principle is the same (or similar). Figure 5 The example circuit shown in the figure can detect whether the output voltage is in the overshoot and undershoot states respectively. Figure 5 The upper middle box shows the undershoot circuit. Figure 5 The block diagram in the middle and lower part shows the overshoot circuit. Therefore, based on the Undershoot detection circuit and the Overshoot detection circuit, the Undershoot mode signal and the Overshoot mode signal are output respectively, which are input to the U / O analog counting delay module, and finally the UO MODE logic signal is output for switching the control mode.

[0088] When the circuit is working normally, the output UO mode of the FB detection circuit is low, and the amplifier works at a relatively reasonable second gain during this period, providing appropriate charge and discharge currents to ensure that the loop has a certain response and the conversion efficiency is maintained at a high efficiency level.

[0089] When the circuit is in load switching, the circuit is in the Undershoot / Overshoot state. At this time, the Undershoot mode signal or the Overshoot mode signal is triggered, the U / O COUNT module is entered for timing, and the output UOmode is high. The high level of the pulse signal is maintained within the preset range (for example, about 100μs), so that the amplifier works at a higher first gain during this period to provide a larger charge and discharge current, thereby achieving a fast loop response.

[0090] In summary, by introducing the load switching detection mechanism and the amplification gain switching working mechanism into the error amplifier, a good compromise can be achieved in terms of response speed and conversion efficiency (for details, please refer to the aforementioned Figure 2 , Figure 3 ).

[0091] Based on the same inventive concept, on the basis of the above-mentioned improved error amplifier structure, the present application also provides a new structure of a BUCK converter: that is, in the traditional BUCK converter structure, the variable gain error amplifier structure of the present application is introduced.

[0092] Refer to the above Figure 1As shown, in the BUCK converter structure, the error amplifier in the traditional structure is improved into a variable gain error amplifier circuit as described in any of the aforementioned examples of the present application; the error amplifier is used to operate in a first mode (i.e., UO MODE in the aforementioned example) within a preset first time when overshoot / undershoot is detected in the feedback voltage, so as to provide a larger first charge and discharge current to the RC loop, and to restore to a second mode (such as the normal working mode in the aforementioned example) after the first mode ends, so as to provide a second charge and discharge current with high-efficiency conversion and good loop response speed to the RC loop, wherein the first mode is an operating mode for error amplification with a first gain, and the second mode is an operating mode for error amplification with a second gain, and the first gain is greater than the second gain, so that the first charge and discharge current is greater than the second charge and discharge current.

[0093] In practice, the RC loop can be designed as a circuit integrated in the improved structure in the error amplifier, or it can be set outside the error amplifier, where the RC loop has a resistor R VC and capacitor C VC They are connected in series and then in parallel between the error amplifier output terminal Vc of the error amplifier and the ground.

[0094] Compared with the existing methods for improving the response speed of the BUCK system loop in China and abroad, this application adopts an innovative transient gain enhancement path structure. When in load change switching, the system loop responds quickly and quickly increases the transient bias current to obtain a smaller transient voltage. And when working normally, it has the advantage of high efficiency. Therefore, after the BUCK converter adopts the new structure, it can meet more application scenarios, especially in smart terminal applications with frequent load switching, ensuring the reliability of use in these occasions.

[0095] It should be noted that the above examples of the present application are illustrations of related improved examples of the error amplifier in a BUCK converter structure based on current mode control, but the error amplifiers in other BUCK converter structures, if the error amplifier of the present application is applicable, then the error amplifier of the present application can be applied to these BUCK converter structures without specific limitation here.

[0096] In this specification, the same or similar parts between the various embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the embodiments described later, the description is relatively simple, and the relevant parts can be referred to the partial description of the previous embodiments.

[0097] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A variable gain error amplifier circuit, characterized in that: In a BUCK converter for current mode control, the error amplifier circuit includes: a feedforward capacitor, a variable gain amplifier unit, a feedback detection circuit, and a delay timer; The two ends of the feedforward capacitor are connected to the output end and the feedback voltage end of the BUCK converter, wherein the feedback voltage end provides a feedback voltage V for the resistor sampling branch at the output end of the BUCK converter. FB The resistance sampling branch is composed of a first resistor and a second resistor, one end of the first resistor is connected to the output end of the BUCK converter, one end of the second resistor is grounded, and the other end of the first resistor and the other end of the second resistor are connected to serve as the feedback voltage end; The feedback detection circuit and the delay timer are connected in series between the feedback voltage terminal and the variable gain amplifier unit in sequence, wherein the feedback detection circuit is used to detect whether the change of the feedback voltage at the feedback voltage terminal exceeds a preset threshold value, and if so, output a trigger signal to the delay timer, so that the delay timer outputs a pulse control signal to the variable gain amplifier unit under the action of the trigger signal, and the pulse control signal is a pulse signal generated by the delay timer according to preset parameters after being triggered by the trigger signal; The variable gain amplifier unit serves as an error amplifier of the BUCK converter, and is used to perform error amplification on the feedback voltage at the feedback voltage end and the reference reference with a first gain during the period when the pulse control signal is on, and to perform error amplification on the feedback voltage at the feedback voltage end and the reference reference with a second gain during the period when the pulse control signal is not on, wherein the first gain is greater than the second gain.

2. The variable gain error amplifier circuit according to claim 1, characterized in that: The feedback detection circuit includes an overshoot detection circuit and an undershoot detection circuit, wherein the overshoot detection circuit is used to detect whether the feedback voltage at the feedback voltage end overshoots to a first preset threshold value, and if so, outputs the trigger signal; the undershoot detection circuit is used to detect whether the feedback voltage at the feedback voltage end undershoots to a second preset threshold value, and if so, outputs the trigger signal.

3. The variable gain error amplifier circuit according to claim 2, characterized in that: The undershoot detection circuit comprises a first coupling capacitor, a first bootstrap resistor, a first current mirror, and a first amplifier tube; wherein the first coupling capacitor is used to couple the feedback voltage of the feedback voltage terminal to the gate of the first amplifier tube, the drain of the first amplifier tube is provided with a working current by the first current mirror, the source of the first amplifier tube is grounded, and the first bootstrap resistor is connected between the drain and the gate of the first amplifier tube; And / or, the overshoot detection circuit includes a second coupling capacitor, a second bootstrap resistor, a second current mirror, and a second amplifier tube; wherein the second coupling capacitor is used to couple the feedback voltage of the feedback voltage terminal to the gate of the second amplifier tube, the drain of the second amplifier tube is provided with an operating current by the second current mirror, the source of the second amplifier tube is connected to the power supply terminal, and the second bootstrap resistor is connected between the drain and the gate of the second amplifier tube.

4. The variable gain error amplifier circuit according to claim 3, characterized in that: The undershoot detection circuit further includes a third amplifier tube and a third current mirror, wherein the third amplifier tube is used to amplify the trigger signal output by the first amplifier tube, and the third current mirror is used to provide a working current for the third amplifier tube; And / or, the overshoot detection circuit includes a fourth amplifier tube and a fourth current mirror, wherein the fourth amplifier tube is used to amplify the trigger signal output by the second amplifier tube, and the fourth current mirror is used to provide an operating current for the fourth amplifier tube.

5. The variable gain error amplifier circuit according to claim 4, characterized in that: The third current mirror is proportional to the first current mirror, and the size of the third amplifier tube is proportional to the size of the first amplifier tube; And / or, the fourth current mirror is proportional to the second current mirror, and the size of the fourth amplifier tube is proportional to the size of the second amplifier tube; And / or, the undershoot detection circuit further includes a fifth amplifier tube and a fifth current mirror, wherein the fifth amplifier tube is used to amplify the trigger signal output by the third amplifier tube, and the fifth current mirror is used to provide a working current for the fifth amplifier tube; And / or, the overshoot detection circuit includes a sixth amplifier tube and a sixth current mirror, wherein the sixth amplifier tube is used to amplify the trigger signal output by the fourth amplifier tube, and the sixth current mirror is used to provide a working current for the sixth amplifier tube.

6. The variable gain error amplifier circuit according to claim 5, characterized in that: The size of the fifth amplifier tube is proportional to the size of the third amplifier tube, and the size of the fifth amplifier tube is larger than that of the third amplifier tube, and is designed to be a preset first size to increase the pull-down current capability of the fifth amplifier tube, so that the low level of the trigger signal is maintained below the preset low level signal; And / or, the size of the sixth amplifier tube is proportional to the size of the fourth amplifier tube, and the size of the sixth amplifier tube is larger than a preset size to increase the pull-up current capability of the sixth amplifier tube, so that the high level of the trigger signal is maintained above the preset high level signal; And / or, the fifth current mirror is proportional to the third current mirror and / or the first current mirror; And / or, the sixth current mirror is proportional to the fourth current mirror and / or the second current mirror; And / or, the first current mirror, the third current mirror and the fifth current mirror share the same first reference current source to form a first current source bias circuit, wherein the first current source bias circuit comprises: a first reference current source, a first PMOS tube, a second PMOS tube, a third PMOS tube and a fourth PMOS tube; wherein the gate of the first PMOS tube is connected to the drain of the first PMOS tube, the gate of the second PMOS tube, the gate of the third PMOS tube and the gate of the fourth PMOS tube; the source of the first PMOS tube, the source of the second PMOS tube, the source of the third PMOS tube and the source of the fourth PMOS tube are connected to the power supply terminal; the first reference current source is connected in series to the first PMOS tube. The drain of the first PMOS tube is connected to the drain of the first amplifier tube, so that the first reference current source, the first PMOS tube and the second PMOS tube form a first current mirror to provide a working current for the first amplifier tube; the drain of the third PMOS tube is connected to the drain of the third amplifier tube, so that the first reference current source, the first PMOS tube and the third PMOS tube form a third current mirror to provide a working current for the third amplifier tube; the drain of the fourth PMOS tube is connected to the drain of the fifth amplifier tube, so that the first reference current source, the first PMOS tube and the fourth PMOS tube form a fifth current mirror to provide a working current for the fifth amplifier tube; And / or, the second current mirror, the fourth current mirror and the sixth current mirror share the same second reference current source to form a second current source bias circuit, wherein the second current source bias circuit comprises: a second reference current source, a first NMOS tube, a second NMOS tube, a third NMOS tube and a fourth NMOS tube; wherein the gate of the first NMOS tube is connected to the drain of the first NMOS tube, the gate of the second NMOS tube, the gate of the third NMOS tube and the gate of the fourth NMOS tube; the source of the first NMOS tube, the source of the second NMOS tube, the source of the third NMOS tube and the source of the fourth NMOS tube are connected to ground; the second reference current source is connected in series to the first NMOS The drain of the second NMOS tube is connected to the drain of the second amplifier tube, so that the second reference current source, the first NMOS tube and the second NMOS tube form a second current mirror to provide a working current for the second amplifier tube; the drain of the third NMOS tube is connected to the drain of the fourth amplifier tube, so that the second reference current source, the first NMOS tube and the third NMOS tube form a fourth current mirror to provide a working current for the fourth amplifier tube; the drain of the fourth NMOS tube is connected to the drain of the sixth amplifier tube, so that the second reference current source, the first NMOS tube and the fourth NMOS tube form a sixth current mirror to provide a working current for the sixth amplifier tube.

7. The variable gain error amplifier circuit according to claim 1, characterized in that: The variable gain error amplifier circuit further includes a first Schmitt trigger circuit and a first inverter circuit, wherein the first Schmitt trigger circuit is used to perform shaping on the detection signal, and the first inverter circuit is used to perform inversion processing on the shaped signal output by the first Schmitt trigger circuit to generate the trigger signal of a positive pulse waveform, and the detection signal is a signal obtained when it is detected that the feedback voltage at the feedback voltage terminal overshoots to a first preset threshold value; And / or, the variable gain error amplifier circuit further includes a second Schmitt trigger circuit and a second inverter circuit, wherein the second Schmitt trigger circuit is used to perform shaping on the detection signal, and the second inverter circuit is used to perform inversion processing on the shaped signal output by the second Schmitt trigger circuit to generate the trigger signal of the positive pulse waveform, and the detection signal is a signal obtained when the feedback voltage at the feedback voltage terminal is detected to undershoot to a second preset threshold value; And / or, the delay timer, under the triggering of the trigger signal, generates the pulse control signal with a pulse width of 50-200 μs; And / or, the variable gain amplification unit comprises: an amplification unit and a gain variable unit; The gain variable unit includes a plurality of gain resistors and a plurality of switches, wherein the gain resistors are used to set the gain of the amplifying unit, and the switches are connected in parallel or in series with the gain resistors, so that the gain resistors are connected to or disconnected from the amplifying unit or the gain resistors are short-circuited by turning the switches on and off under the control of the pulse control signal, so that the amplifying unit operates at the first gain during the working period of the pulse control signal, and operates at the second gain during the non-working period of the pulse control signal.

8. The variable gain error amplifier circuit according to claim 7, characterized in that: The amplification unit includes a differential amplifier circuit, wherein one input end of the differential amplifier circuit is connected to the feedback voltage end, and the other input end is connected to the reference reference, the switch is connected in parallel with the gain resistor, and the gain resistor is used as a bias and / or load of the differential amplifier circuit, so that the switch is turned on during the operation of the pulse control signal, thereby reducing the size of the resistance connected to the differential amplifier circuit, so that the gain of the differential amplifier circuit is increased to the preset first gain, and the switch is turned off during the non-operation period of the pulse control signal, thereby restoring the size of the resistance connected to the differential amplifier circuit, so that the gain of the differential amplifier circuit is restored to the preset second gain.

9. The variable gain error amplifier circuit according to claim 8, characterized in that: The differential amplifier circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a first bias resistor, and a second bias resistor; the plurality of gain resistors include a first gain resistor, a second gain resistor, a third gain resistor, and a fourth gain resistor; the plurality of switches include a first switch, a second switch, a third switch, and a fourth switch; the gate of the first transistor is connected to the feedback voltage, and the gate of the second transistor is connected to the reference reference; the source of the first transistor and the source of the second transistor are biased by a current source; the drain of the first transistor and the drain of the third transistor, the drain of the fifth transistor, and the drain of the fifth transistor are connected to the feedback voltage; the gate of the first transistor and the source of the second transistor are biased by a current source; the drain of the first transistor and the drain of the third transistor, the drain of the fifth transistor, and the drain of the fifth transistor are connected to the feedback voltage; the gate of the first transistor and the drain of the fifth transistor are connected to the feedback voltage; the gate of the second transistor and the reference ... The gate of the transistor is connected to the drain of the fourth transistor and the gate of the sixth transistor, the gate of the third transistor is connected to the gate of the fourth transistor, the first bias resistor is connected between the gate and the drain of the third transistor, the second bias resistor is connected between the gate and the drain of the fourth transistor, and the source of the third transistor and the source of the fourth transistor are grounded; the first switch and the first gain resistor are connected in parallel and then connected in series between the source of the fifth transistor and the ground, the second switch and the second gain resistor are connected in parallel and then connected in series between the source of the sixth transistor and the ground; the drain of the fifth transistor is connected to the source of the seventh transistor, the drain of the sixth transistor is connected to the source of the eighth transistor, and the gate of the seventh transistor and the gate of the eighth transistor are connected to the first bias voltage; The drain and gate of the ninth transistor are connected to the drain of the seventh transistor, the drain of the tenth transistor is connected to the drain of the eighth transistor and serves as an error amplification output terminal, and the gate of the ninth transistor is connected to the gate of the tenth transistor; the gate and drain of the eleventh transistor are connected to the source of the ninth transistor, the drain of the twelfth transistor is connected to the source of the tenth transistor, and the gate of the eleventh transistor is connected to the gate of the twelfth transistor; the third switch and the third gain resistor are connected in parallel and then connected in series between the power supply terminal and the source of the eleventh transistor, and the fourth switch and the fourth gain resistor are connected in parallel and then connected in series between the power supply terminal and the source of the twelfth transistor; the first switch, the second switch, the third switch, and the fourth switch are all controlled by the pulse control signal.

10. A BUCK converter, characterized in that: It comprises an error amplifier and an RC loop, wherein the error amplifier is a variable gain error amplifier circuit as described in any one of claims 1 to 9; the RC loop is connected in parallel between the error amplifier output terminal of the error amplifier and ground, and the RC loop comprises a loop resistor and a loop capacitor connected in series; the error amplifier is used to operate in a first mode within a preset first time when overshoot / undershoot is detected in the feedback voltage to provide a first charge and discharge current to the RC loop, and to restore to a second mode after the first mode ends to provide a second charge and discharge current to the RC loop, wherein the first mode is an operating mode for error amplification with a first gain, and the second mode is an operating mode for error amplification with a second gain, and the first gain is greater than the second gain, so that the first charge and discharge current is greater than the second charge and discharge current.

Images