CXL unit time delay test method, device, system, equipment and medium

Abstract

The invention relates to the technical field of CXL, and particularly discloses a time delay test method, device, system, equipment and medium for a CXL unit, and the method comprises the steps: directly receiving and transmitting a message to a to-be-tested computer fast interconnection unit through a computer fast interconnection interface module corresponding to the to-be-tested computer fast interconnection unit through an application message manager, and recording a receiving and transmitting timestamp; the computer fast interconnection interface module comprises a computer fast interconnection root port module and / or a computer fast interconnection terminal interface module, so that the message receiving and transmitting timestamps of the computer fast interconnection unit can be directly obtained based on hardware, and link errors introduced in a system-level test are avoided; direct measurement of the time delay performance of the computer fast interconnection unit is achieved, and therefore accurate testing of the time delay performance of the computer fast interconnection unit is achieved.

Description

Technical Field

[0001] The present invention relates to the field of CXL technology, and in particular to a method, device, system, equipment and medium for testing the time delay of a CXL unit. Background Art

[0002] Compute Express Link (CXL) is a new open interconnect standard for memory access and coherent caching between hosts and devices that need to share memory resources. A complete CXL system may consist of one or more CXL-enabled hosts (CXL hosts) and one or more CXL devices (CXL devices). The performance of each of these CXL units directly impacts overall system performance. Therefore, a thorough understanding of the performance metrics of each CXL unit is crucial during early system design.

[0003] The current method for testing the latency performance of computer interconnect units (CXLs) is to use software tools (such as Intel MLC) in the system to test the latency of the computer interconnect device (CXL device). Specifically, the CXL device is connected to a test host. The software tool running on the test host operating system reads and writes to the CXL device multiple times, and then the average value is taken as the final performance indicator.

[0004] However, this system testing method is limited by the performance of the test host itself, such as motherboard wiring parameters, central processing unit (CPU) performance, and the physical path from the CPU socket to the Computer Express Root (CXL RP) port (when multiple CPU sockets are used). This results in significant differences in the latency performance test results of the Computer Express Root (CXL) device measured by different test hosts. This does not strictly reflect the performance of the Computer Express Root (CXL) device itself, making it of little reference value for the design of Computer Express Root (CXL) systems. Furthermore, this system testing method cannot fully test the performance of the Computer Express Root (CXL) device.

[0005] Providing a more accurate delay performance testing solution for computer rapid interconnection units is a technical problem that needs to be solved by those skilled in the art. Summary of the Invention

[0006] The object of the present invention is to provide a method, apparatus, system, device and medium for testing the time delay of a CXL unit, so as to improve the accuracy of the test results of the time delay performance of a computer rapid interconnection unit.

[0007] To solve the above technical problems, the present invention provides a CXL unit latency testing method, which is applied to a message manager and includes:

[0008] Sending a test message to the computer rapid interconnection unit to be tested through a computer rapid interconnection interface module corresponding to the computer rapid interconnection unit to be tested, and recording a sending timestamp of the test message;

[0009] receiving, through a computer rapid interconnection interface module corresponding to the computer rapid interconnection unit under test, a feedback message from the computer rapid interconnection unit under test to the test message, and recording a reception timestamp of the feedback message;

[0010] Among them, the computer rapid interconnection interface module corresponding to the computer rapid interconnection unit to be tested includes a computer rapid interconnection root port module and / or a computer rapid interconnection terminal interface module; the sending timestamp and the receiving timestamp are used to calculate the delay test result of the computer rapid interconnection unit to be tested.

[0011] In some implementations, the computer-to-be-tested rapid interconnection unit is a computer-to-be-tested rapid interconnection terminal interface device;

[0012] The method of sending a test message to the computer rapid interconnection unit to be tested through the computer rapid interconnection interface module corresponding to the computer rapid interconnection unit to be tested comprises: sending the test message to the computer rapid interconnection terminal interface device to be tested through the computer rapid interconnection root port module;

[0013] The receiving, through the computer rapid interconnection interface module corresponding to the computer rapid interconnection unit under test, a feedback message from the computer rapid interconnection unit under test to the test message, includes: receiving, through the computer rapid interconnection root port module, the feedback message from the computer rapid interconnection terminal interface device under test to the test message.

[0014] In some implementations, the computer fast interconnection unit under test is a computer fast interconnection root port device under test;

[0015] The sending of the test message to the computer rapid interconnection unit to be tested through the computer rapid interconnection interface module corresponding to the computer rapid interconnection unit to be tested comprises: sending the test message to the computer rapid interconnection root port device to be tested through the computer rapid interconnection terminal interface module;

[0016] The receiving, through the computer rapid interconnection interface module corresponding to the computer rapid interconnection unit under test, a feedback message from the computer rapid interconnection unit under test to the test message, includes: receiving, through the computer rapid interconnection terminal interface module, the feedback message from the computer rapid interconnection root port device under test to the test message.

[0017] In some implementations, the computer-to-be-tested fast interconnection unit is a computer-to-be-tested fast interconnection switch;

[0018] The sending of a test message to the computer rapid interconnection unit to be tested through the computer rapid interconnection interface module corresponding to the computer rapid interconnection unit to be tested comprises: sending the test message to the uplink port of the computer rapid interconnection switch to be tested through the computer rapid interconnection root port module, and sending the test message to the downlink port of the computer rapid interconnection switch to be tested through the computer rapid interconnection terminal interface module;

[0019] The receiving, through the computer rapid interconnection interface module corresponding to the computer rapid interconnection unit under test, a feedback message from the computer rapid interconnection unit under test to the test message, includes: receiving, through the computer rapid interconnection root port module, the feedback message from the uplink port of the computer rapid interconnection switch under test, and receiving, through the computer rapid interconnection terminal interface module, the feedback message from the downlink port of the computer rapid interconnection switch under test.

[0020] In some implementations, the method further includes:

[0021] The delay test result of the computer fast interconnection unit to be tested is obtained by calculating the time difference between the sending timestamp and the receiving timestamp.

[0022] In some implementations, calculating the latency test result of the computer fast interconnect unit under test based on the time difference between the sending timestamp and the receiving timestamp includes:

[0023] The average value of the time difference between the multiple groups of sending timestamps and receiving timestamps is calculated to obtain the delay test result of the computer fast interconnection unit to be tested.

[0024] In some implementations, the method further includes:

[0025] The sending timestamp and the receiving timestamp are sent to a test host via a communication module so that the test host can calculate a delay test result of the fast interconnection unit of the computer to be tested.

[0026] In some implementations, sending a test message to the computer rapid interconnection unit to be tested through a computer rapid interconnection interface module corresponding to the computer rapid interconnection unit to be tested includes:

[0027] Determine the message type and the number of times each message type is sent according to the delay test parameters sent by the test host;

[0028] Determining configuration information of the test message to the computer fast interconnection unit to be tested according to the message type and the number of times each message type is sent;

[0029] According to the configuration information of the message to be tested, the test message is sent to the computer rapid interconnection unit to be tested through a computer rapid interconnection interface module corresponding to the computer rapid interconnection unit to be tested.

[0030] In some implementations, sending a test message to the computer rapid interconnection unit to be tested through a computer rapid interconnection interface module corresponding to the computer rapid interconnection unit to be tested includes:

[0031] Generate a message in a computer rapid interconnection protocol format according to the message parameter data stream sent by the test host to obtain the test message;

[0032] The test message is sent to the computer rapid interconnection unit to be tested through a computer rapid interconnection interface module corresponding to the computer rapid interconnection unit to be tested.

[0033] In some implementations, at least one of the CIRCUIT root port module, the CIRCUIT terminal interface module, and the message manager are built based on a programmable controller.

[0034] In some implementations, the programmable controller includes a field programmable gate array, a complex programmable logic device, a system-on-chip, a digital signal processor, or an application-specific integrated circuit.

[0035] To solve the above technical problems, the present invention further provides a CXL unit latency testing method, which is applied to a test host and includes:

[0036] Using a communication module connected to a message manager, reading a sending timestamp of a test message sent by the message manager to the computer rapid interconnection unit under test via a computer rapid interconnection interface module corresponding to the computer rapid interconnection unit under test, and a receiving timestamp of a feedback message received by the message manager via the computer rapid interconnection interface module corresponding to the computer rapid interconnection unit under test in response to the test message;

[0037] Calculate the delay test result of the computer fast interconnection unit to be tested according to the sending timestamp and the receiving timestamp;

[0038] Wherein, the computer rapid interconnection interface module corresponding to the computer rapid interconnection unit to be tested includes a computer rapid interconnection root port module and / or a computer rapid interconnection terminal interface module.

[0039] In some implementations, the method further includes:

[0040] Sending the latency test parameters to the message manager using a memory-mapped bus in the communication module to complete register configuration of the message manager;

[0041] The delay test parameters include at least: message type and the number of times each message type is sent.

[0042] In some implementations, the method further includes:

[0043] A message parameter data stream is sent to the message manager, so that the message manager generates a message in a computer rapid interconnection protocol format from the message parameter data stream to obtain the test message.

[0044] In order to solve the above technical problems, the present invention also provides a CXL unit latency test device, comprising: a message manager, a computer rapid interconnection root port module and a computer rapid interconnection terminal interface module;

[0045] The message manager is configured to send a test message to the computer rapid interconnection unit under test through a computer rapid interconnection interface module corresponding to the computer rapid interconnection unit under test, and record a timestamp of when the test message was sent; receive a feedback message from the computer rapid interconnection unit under test to the test message through a computer rapid interconnection interface module corresponding to the computer rapid interconnection unit under test, and record a timestamp of when the feedback message was received;

[0046] Among them, the computer rapid interconnection interface module corresponding to the computer rapid interconnection unit to be tested includes the computer rapid interconnection root port module and / or the computer rapid interconnection terminal interface module; the sending timestamp and the receiving timestamp are used to calculate the delay test result of the computer rapid interconnection unit to be tested.

[0047] In some implementations, the message manager includes: a message generator, a log buffer, a time module, a sending module, and a receiving module;

[0048] Wherein, the first end of the message generator is connected to the first end of the sending module, the second end of the sending module is connected to the first end of the log buffer, the third end of the sending module is the message output interface of the message manager, the first end of the receiving module is connected to the second end of the log buffer, the second end of the receiving module is the message input interface of the message manager, and the output end of the time module is connected to the fourth end of the sending module and the third end of the receiving module respectively;

[0049] The message generator is used to send the test message to the fast interconnection unit of the computer to be tested through the sending module;

[0050] The sending module is used to cache the sending timestamp obtained from the time module when sending the test message to the log buffer;

[0051] The receiving module is configured to cache the receiving timestamp obtained from the time module when the feedback message is received in the log buffer.

[0052] In some implementations, further comprising a communication module;

[0053] The first end of the communication module is used to connect to the test host, and the second end of the communication module is connected to the register configuration interface of the message manager so that the test host can send delay test parameters to the message manager to complete the register configuration of the message manager; the third end of the communication module is connected to the log transmission interface of the message manager so that the test host can read the test message, the feedback message, the sending timestamp and the receiving timestamp recorded in the message register.

[0054] In some implementations, the number of the computer rapid interconnection root port modules and the number of the computer rapid interconnection terminal interface modules are both multiple, each of the computer rapid interconnection root port modules is connected to a different interface of the message manager, and each of the computer rapid interconnection terminal interface modules is connected to a different interface of the message manager.

[0055] To solve the above technical problems, the present invention further provides a time delay test system for a CXL unit, comprising: a time delay test device for a computer rapid interconnection unit and a test host connected to the time delay test device;

[0056] The delay test device includes a message manager, a computer rapid interconnection root port module, a computer rapid interconnection terminal interface module, and a communication module; the message manager is used to send a test message to the computer rapid interconnection unit under test through the computer rapid interconnection interface module corresponding to the computer rapid interconnection unit under test, and record the sending timestamp of the test message; receive a feedback message from the computer rapid interconnection unit under test to the test message through the computer rapid interconnection interface module corresponding to the computer rapid interconnection unit under test, and record the receiving timestamp of the feedback message;

[0057] The test host is used to read the sending timestamp and the receiving timestamp through the communication module, and calculate the delay test result of the fast interconnection unit of the computer to be tested according to the sending timestamp and the receiving timestamp;

[0058] Wherein, the computer rapid interconnection interface module corresponding to the computer rapid interconnection unit to be tested includes the computer rapid interconnection root port module and / or the computer rapid interconnection terminal interface module.

[0059] To solve the above technical problems, the present invention further provides a CXL unit latency test device, which is applied to a message manager and includes:

[0060] a sending unit, configured to send a test message to the computer rapid interconnection unit to be tested through a computer rapid interconnection interface module corresponding to the computer rapid interconnection unit to be tested, and record a sending timestamp of the test message;

[0061] a receiving unit, configured to receive a feedback message from the computer rapid interconnection unit under test to the test message through a computer rapid interconnection interface module corresponding to the computer rapid interconnection unit under test, and record a reception timestamp of the feedback message;

[0062] Among them, the computer rapid interconnection interface module corresponding to the computer rapid interconnection unit to be tested includes a computer rapid interconnection root port module and / or a computer rapid interconnection terminal interface module; the sending timestamp and the receiving timestamp are used to calculate the delay test result of the computer rapid interconnection unit to be tested.

[0063] To solve the above technical problems, the present invention further provides a CXL unit latency testing device, which, in some implementations, is applied to a test host and includes:

[0064] a data reading unit configured to read, by means of a communication module connected to a message manager, a sending timestamp of a test message sent by the message manager to the computer rapid interconnection unit under test via a computer rapid interconnection interface module corresponding to the computer rapid interconnection unit under test, and a receiving timestamp of a feedback message received by the message manager via the computer rapid interconnection interface module corresponding to the computer rapid interconnection unit under test in response to the test message;

[0065] A second calculation unit is used to calculate the delay test result of the computer fast interconnection unit to be tested according to the sending timestamp and the receiving timestamp;

[0066] Wherein, the computer rapid interconnection interface module corresponding to the computer rapid interconnection unit to be tested includes a computer rapid interconnection root port module and / or a computer rapid interconnection terminal interface module.

[0067] To solve the above technical problems, the present invention further provides a CXL unit latency test device, comprising:

[0068] Memory for storing computer programs;

[0069] The processor is configured to execute the computer program, wherein when the computer program is executed by the processor, the steps of any one of the above methods for testing the latency of a CXL unit are implemented.

[0070] To solve the above technical problems, the present invention further provides a medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of any one of the above methods for testing the delay of a CXL unit.

[0071] The present invention provides a method for testing a CXL unit latency. The method uses a message manager to directly send a test message to the computer rapid interconnection unit under test via a computer rapid interconnection interface module corresponding to the computer rapid interconnection unit under test, and records the sending timestamp of the test message. The method then receives a feedback message from the computer rapid interconnection unit under test to the test message via the computer rapid interconnection interface module corresponding to the computer rapid interconnection unit under test, and records the receiving timestamp of the feedback message. The computer rapid interconnection interface module corresponding to the computer rapid interconnection unit under test includes a computer rapid interconnection root port module and / or a computer rapid interconnection terminal interface module. This method achieves direct hardware-based acquisition of message sending and receiving timestamps of the computer rapid interconnection unit under test. The method is built directly on hardware without going through a test host operating system, thereby avoiding link errors introduced in system-level testing, and achieving direct measurement of the latency performance of the computer rapid interconnection unit, thereby accurately testing the latency performance of the computer rapid interconnection unit.

[0072] The present invention also provides a method, device, system, equipment and medium for testing the time delay of a CXL unit, which have the above-mentioned beneficial effects and will not be described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS

[0073] In order to more clearly illustrate the embodiments of the present invention or the technical solutions of the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0074] Figure 1 A schematic diagram of the connection of a time delay test device for a CXL unit provided in an embodiment of the present invention;

[0075] Figure 2 A connection diagram of another CXL unit delay test device provided by an embodiment of the present invention;

[0076] Figure 3 A flowchart of a delay testing method for a CXL unit provided in an embodiment of the present invention;

[0077] Figure 4 A connection diagram of a terminal interface device for testing a computer to be tested for rapid interconnection provided by an embodiment of the present invention;

[0078] Figure 5 A schematic diagram of a connection for testing a root port device for fast interconnection of a computer under test provided by an embodiment of the present invention;

[0079] Figure 6 A schematic diagram of a connection for testing a switch for fast interconnection of computers under test provided by an embodiment of the present invention;

[0080] Figure 7 A flowchart of another method for testing the time delay of a CXL unit provided by an embodiment of the present invention;

[0081] Figure 8 A schematic structural diagram of a time delay test device for a CXL unit provided in an embodiment of the present invention;

[0082] Figure 9 A schematic structural diagram of another CXL unit delay test device provided in an embodiment of the present invention;

[0083] Figure 10 A schematic structural diagram of a CXL unit delay test device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0084] The core of the present invention is to provide a method, device, system, equipment and medium for testing the time delay of a CXL unit, so as to improve the accuracy of the test results of the time delay performance of a computer rapid interconnection unit.

[0085] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0086] The following describes the first embodiment of the present invention.

[0087] Figure 1 A schematic diagram of the connection of a time delay test device for a CXL unit provided in an embodiment of the present invention; Figure 2 A connection diagram of another CXL unit delay test device provided by an embodiment of the present invention.

[0088] To facilitate understanding, the time delay test device for the CXL unit provided by the present invention is first introduced.

[0089] like Figure 1 As shown, the latency test device of the CXL unit provided by the present invention includes: a message manager 101 , a Computer Interconnect Express Root Port (CXL RP) module 102 and a Computer Interconnect Express Terminal Port (CXL EP) module 103 .

[0090] like Figure 2 As shown, in the latency testing device for the CXL unit provided by the present invention, the message output interface of the message manager 101 is connected to the message input interface of the CIE-R root port module 102 and the message input interface of the CIE-R terminal interface module 103, respectively; and the message input interface of the message manager 101 is connected to the message output interface of the CIE-R root port module 102 and the message output interface of the CIE-R terminal interface module 103, respectively.

[0091] The message manager 101 is used to send a test message to the computer rapid interconnection unit under test through the computer rapid interconnection interface module corresponding to the computer rapid interconnection unit under test, and record the sending timestamp of the test message; receive a feedback message from the computer rapid interconnection unit under test to the test message through the computer rapid interconnection interface module corresponding to the computer rapid interconnection unit under test, and record the receiving timestamp of the feedback message.

[0092] The computer rapid interconnection interface module corresponding to the computer rapid interconnection unit under test includes a computer rapid interconnection root port module 102 and / or a computer rapid interconnection terminal interface module 103; the sending timestamp and the receiving timestamp are used to calculate the delay test result of the computer rapid interconnection unit under test.

[0093] In practical applications, the CXL unit latency testing device provided by the present invention may target CXL units to be tested, including CXL root port devices, CXL terminal interface devices, and CXL switches.

[0094] Among them, a Computer Express Root Port Device is a device with a Computer Express Root Port (CXL EP) that, in application, needs to connect to the Computer Express Terminal Port (CXL RP) of another device to achieve rapid computer interconnection. A Computer Express Terminal Interface Device is a device with a Computer Express Terminal Port (CXL EP) that, in application, needs to connect to the Computer Express Root Port (CXL RP) of another device to achieve rapid computer interconnection. A Computer Express Switch (CXL Switch) is a device with an uplink interface and a downlink interface. The uplink interface is connected to the Computer Express Root Port (CXL RP) of another device, and the downlink interface is connected to the Computer Express Root Port (CXL EP) of another device to achieve rapid computer interconnection.

[0095] In practical applications, a CXL root port device can be either a CXL host or a CXL device. A CXL terminal interface device can be either a CXL host or a CXL device. By configuring the CXL interface type, the role of the CXL root port device can be changed to that of a CXL terminal interface device.

[0096] The Computer Express Cross-Connect Host (CXL host) may be a server that supports the Computer Express Cross-Connect protocol.

[0097] A Computer Express (CXL) device may be a card that supports the Computer Express (CXL) protocol. CXL devices may include, but are not limited to, CXL Type 1 devices, CXL Type 2 devices, and CXL Type 3 devices. A CXL Type 1 device refers to a CXL device that supports the Computer Express (CXL) I / O protocol (CXL.io) and the Computer Express (CXL) Cache protocol (CXL.cache). A CXL Type 2 device refers to a CXL device that supports the Computer Express (CXL) I / O protocol (CXL.io), the Computer Express (CXL) Cache protocol (CXL.cache), and the Computer Express (CXL) Memory protocol (CXL.mem). A CXL Type 3 device refers to a CXL device that supports the Computer Express (CXL) I / O protocol (CXL.io) and the Computer Express (CXL) Memory protocol (CXL.mem).

[0098] The delay test device of the CXL unit provided by the present invention can be implemented based on a programmable controller, and may include but is not limited to a field programmable gate array (FPGA), a complex programmable logic device (CPLD), a system on chip (SoC), a digital signal processor (DSP), and an application specific integrated circuit (ASIC). By pre-programming and burning the programmable controller, the hardware functions of each part including the message manager 101, the computer rapid interconnection root port module 102 and the computer rapid interconnection terminal interface module 103 are realized. In addition, the hardware devices of each part of the delay test device of the CXL unit provided by the present invention can also be built separately, which is not limited here. By configuring the register parameters of each part of the hardware, the configuration of the delay test parameters such as the message type required for the computer rapid interconnection unit delay test and the number of times each message type is sent can be realized. The configuration process can be performed before the test, or it can be executed during the test by an external test host.

[0099] The time delay test device of the CXL unit provided by the present invention can be designed with a power supply interface that adopts 220V mains electricity.

[0100] The CRI Express root port module 102 implements the CRI Express protocol and provides a CRI Express root port-type interface for communicating with an external CRI Express terminal interface device. During latency testing, it connects to the CRI Express terminal interface device under test or the uplink port of the CRI Express switch under test. The logic circuitry of CRI Express root port module 102 includes a CRI Express transport layer, a CRI Express link layer, a CRI Express arbitration multiplexing layer, a resilient bus physical layer, and a CRI Express root port. The CRI Express root port is used to connect to the CRI Express unit under test.

[0101] The CRI terminal interface module 103 implements the CRI protocol and provides a CRI terminal interface type interface for communicating with an external CRI root port device. During latency testing, it connects to the CRI root port device under test or the downlink port of the CRI switch under test. The logic circuitry of CRI terminal interface module 103 includes a CRI transport layer, a CRI link layer, a CRI arbitration multiplexing layer, a resilient bus physical layer, and a CRI terminal interface. The CRI terminal interface is used to connect to the CRI unit under test.

[0102] The computer rapid interconnection root port module 102 and the computer rapid interconnection terminal interface module 103 can be designed to be compatible with 68B-Flit / 256B-Flit (>32GT / s) protocols, and are compatible with the fourth generation interface (Gen 4: x16, x8, x4, 16GT / s, 8GT / s), the fifth generation interface (Gen 5: x16, x8, x4, 32GT / s, 16GT / s, 8GT / s), the sixth generation interface (Gen 6: x16, x8, x4, 64GT / s, 32GT / s, 16GT / s, 8GT / s), etc. By being designed as a high version of the interface protocol, it can be downwardly compatible with the computer rapid interconnection units under test of various interface versions.

[0103] The external interface of the computer rapid interconnection root port module 102 and the external interface of the computer rapid interconnection terminal interface module 103 can both be configured as a gold finger, slot, or cable interface. Specifically, a delay test device can be provided with a variety of computer rapid interconnection root port modules 102 with different interface forms and a variety of computer rapid interconnection terminal interface modules 103 with different interface forms, so that they can be directly connected to the computer rapid interconnection unit under test during testing. Shortening the link length of the test loop helps reduce the delay caused by link components other than the computer rapid interconnection unit under test, thereby improving the accuracy of the delay test results of the computer rapid interconnection unit under test. Therefore, the external interface of the computer rapid interconnection root port module 102 and the external interface of the computer rapid interconnection terminal interface module 103 are preferably configured as a gold finger or slot form.

[0104] The number of CXL root port modules 102 can be one or more, and the number of CXL terminal interface modules 103 can be one or more. If both the number of CXL root port modules 102 and the number of CXL terminal interface modules 103 are multiple, each CXL root port module 102 is connected to a different interface of the message manager 101, and each CXL terminal interface module 103 is connected to a different interface of the message manager 101. Based on this, the latency testing device for a CXL unit provided by the present invention can simultaneously test multiple CXL units under test, thereby improving testing efficiency.

[0105] The message manager 101 is used to send a test message, record a sending timestamp, receive a feedback message, and record a feedback timestamp. Figure 2 As shown, the message manager 101 may include: a message generator, a log buffer, a time module, a sending module and a receiving module;

[0106] Among them, the first end of the message generator is connected to the first end (B) of the sending module, the second end (C) of the sending module is connected to the first end of the log buffer, the third end (E) of the sending module is the message output interface of the message manager 101, the first end (B) of the receiving module is connected to the second end of the log buffer, the second end (D) of the receiving module is the message input interface of the message manager 101, and the output end of the time module is connected to the fourth end (D) of the sending module and the third end (C) of the receiving module respectively.

[0107] The message generator is used to send the test message to the computer rapid interconnection unit under test through the sending module. Specifically, the message generator is used to generate a test message in accordance with the computer rapid interconnection protocol format according to the delay test parameters and send the test message to the sending module.

[0108] The sending module is used to cache the sending timestamp obtained from the time module when sending the test message in the log buffer. Specifically, the sending module is connected to the transport layer sending channel of one or more CRI root port modules 102. The sending module can also be connected to the transport layer sending channel of one or more CRI terminal interface modules 103. The sending module receives the test message from the message generator and sends the test message to the corresponding CRI unit under test based on the specified port information (CRI root port module 102 or CRI terminal interface module 103). After the test message is sent, the sending module caches the test message and the corresponding sending timestamp in the log buffer.

[0109] The receiving module is configured to cache the reception timestamp obtained from the time module upon receiving the feedback message in a log buffer. Specifically, the receiving module may also be connected to the transport layer transmission channels of one or more CRI root port modules 102. The receiving module may also be connected to the transport layer transmission channels of one or more CRI terminal interface modules 103. The receiving module receives feedback messages from the CRI root port module 102 and / or CRI terminal interface module 103, which are received from the CRI unit under test. After receiving the feedback messages, the receiving module caches the feedback messages and the corresponding reception timestamp in the log buffer.

[0110] The time module is used to provide high-precision timestamps for the sending and receiving modules. The time module can use a precise time module, such as a clock module, to provide clock signals for various components, allowing the sending module to determine the sending timestamp and the receiving module to record the receiving timestamp.

[0111] The log buffer is used to receive message transmission logs from the sending module and the receiving module. The message transmission log of the sending module may include the identification information and sending timestamp of the test message. The message transmission log of the receiving module may include the identification information and receiving timestamp of the feedback message.

[0112] To facilitate the configuration of the delay test parameters and the display of the delay test results, Figure 1 As shown, the delay testing device for the CXL unit provided by the present invention may further include a communication module 104 .

[0113] The first end of the communication module 104 is used to connect to the test host, and the second end of the communication module 104 is connected to the register configuration interface of the message manager 101 so that the test host can send delay test parameters to the message manager 101 to complete the register configuration of the message manager 101; the third end of the communication module 104 is connected to the log transmission interface of the message manager 101 so that the test host can read the test message, feedback message, sending timestamp and receiving timestamp recorded in the message register.

[0114] In practical applications, as described above, the configuration process of the register parameters of the various hardware components of the CXL unit delay test device provided by the present invention can be performed before the test, or can be flexibly adjusted during the test through an external test host.

[0115] In addition, the function of calculating the delay test result of the computer rapid interconnection unit under test based on the sending timestamp and the receiving timestamp can be realized by configuring the register of the delay test device of the CXL unit. Alternatively, the delay test device of the CXL unit can only record the sending timestamp and the receiving timestamp, and the test host can read the sending timestamp and the receiving timestamp to calculate the delay test result of the computer rapid interconnection unit under test. The latter can also be realized by the communication module 104.

[0116] The communication module 104 can be an Ethernet communication module 104, which can realize the communication function between the delay test device and the external computer. The test host communicates with the delay test device according to the specified message format. Two application scenarios are distinguished, such as Figure 2 As shown, in the latency test device for a CXL unit provided by the present invention, the communication module 104 may include a memory-mapped bus, a data stream bus receiver (RX), and a data stream bus transmitter (TX). The communication module 104 maps received messages, based on the message headers, to an internal memory-mapped bus for data request messages and an internal data stream bus for data stream messages. Data passing through the data stream bus transmitter (TX) within the latency test device is also generated into messages in a specified format and sent to the test host. The latency test device uses three internal buses for data stream transmission and register reads within the internal modules.

[0117] Based on the memory-mapped bus, when the delay test device receives a control and status register (CSR) read request or a control and status register (CSR) write request message sent by the test host, the communication module 104 uses the memory-mapped bus to access the control and status register (CSR) of the internal module, where the communication module 104 acts as the host of the memory-mapped bus, and other modules inside the delay test device act as slave devices, responding to the control and status register (CSR) read request or the control and status register (CSR) write request of the communication module 104 by using different address segments.

[0118] When the latency test device receives a unidirectional data stream from the test host via the data stream bus receiving end (RX), the communication module 104 uses the data stream bus receiving end (RX) to send a standard data stream to the internal module, which then flows to the message generator within the message manager 101. The message generator then generates a test message in the Computer Rapid Interconnection Protocol format based on the latency test parameters recorded in the standard data stream. The latency test parameters can include various parameters such as the message type encapsulated in a specific format, the number of times each message type is sent, and the address generation method. Optionally, the message generator can also generate test messages based on pre-configured latency test parameters without requiring configuration from the test host.

[0119] like Figure 2 As shown, in conjunction with the data stream bus transmitter (TX), the latency testing device for the CXL unit provided by the present invention can also include a log transmission module located between the data stream bus transmitter (TX) and the log buffer. Based on the data stream bus transmitter (TX), the latency testing device transmits latency test-related data from the log transmission module within the message manager 101 to the test host.

[0120] Different latency test parameters are used depending on the type or even model of the computer rapid interconnection unit under test. By configuring the latency test device, after the tester connects the computer rapid interconnection unit under test to the corresponding interface of the latency test device, the latency test device can send a device attribute query message to the computer rapid interconnection unit under test via the computer rapid interconnection root port module 102 or the computer rapid interconnection terminal interface module 103 based on the message manager 101, receive the message fed back by the computer rapid interconnection unit under test, and parse it to obtain the type and model of the computer rapid interconnection unit under test, so as to switch to the corresponding latency test parameters or carry the type and model of the computer rapid interconnection unit under test when caching the test log message.

[0121] The second embodiment of the present invention is described below.

[0122] like Figure 2 As shown, an embodiment of the present invention provides a CXL unit latency test system, which may include: a computer rapid interconnect unit latency test device (such as the CXL latency test device introduced in the first embodiment of the present invention) and a test host connected to the latency test device.

[0123] The latency testing device includes a message manager 101, a computer rapid interconnection root port module 102, a computer rapid interconnection terminal interface module 103, and a communication module 104. The message manager 101 sends a test message to the computer rapid interconnection unit under test via the computer rapid interconnection interface module corresponding to the computer rapid interconnection unit under test and records the test message sending timestamp. The computer rapid interconnection interface module corresponding to the computer rapid interconnection unit under test receives a feedback message from the computer rapid interconnection unit under test in response to the test message and records the feedback message reception timestamp. The computer rapid interconnection interface module corresponding to the computer rapid interconnection unit under test includes the computer rapid interconnection root port module 102 and / or the computer rapid interconnection terminal interface module 103.

[0124] The test host is used to read the sending timestamp and receiving timestamp recorded by the delay test device, and calculate the delay test result of the computer fast interconnection unit to be tested based on the sending timestamp and receiving timestamp.

[0125] The test host can also be used to visualize the delay test results of the fast interconnection unit of the computer under test using a graphic display template.

[0126] The specific implementation of the delay test device can be referred to the first embodiment of the present invention, which will not be described in detail here. The test host can be any computer device.

[0127] Based on the above-mentioned CXL unit latency testing device, a CXL unit latency testing method provided by an embodiment of the present invention will be described below with reference to the accompanying drawings.

[0128] The third embodiment of the present invention is described below.

[0129] Figure 3 The present invention provides a flowchart of a method for testing the latency of a CXL unit.

[0130] like Figure 3 As shown, the latency testing method of the CXL unit provided in the embodiment of the present invention, applied to the message manager, includes:

[0131] S301: Sending a test message to the computer rapid interconnection unit to be tested via a computer rapid interconnection interface module corresponding to the computer rapid interconnection unit to be tested, and recording a sending timestamp of the test message.

[0132] S302: Receive a feedback message from the computer rapid interconnection unit under test to the test message through the computer rapid interconnection interface module corresponding to the computer rapid interconnection unit under test, and record a reception timestamp of the feedback message.

[0133] Among them, the computer rapid interconnection interface module corresponding to the computer rapid interconnection unit to be tested includes a computer rapid interconnection root port module and / or a computer rapid interconnection terminal interface module; the sending timestamp and the receiving timestamp are used to calculate the delay test result of the computer rapid interconnection unit to be tested.

[0134] To address the problem in related technologies that system-level testing solutions are affected by the performance of the test host itself, resulting in inaccurate latency test results for computer express interconnect units under test and an inability to test computer express interconnect hosts (CXL hosts) and computer express interconnect switches (CXL switches), embodiments of the present invention provide a solution that is applicable to various types of computer express interconnect units under test and significantly reduces the impact of other components in the test loop on latency test results.

[0135] In a specific implementation, a test loop for the computer rapid interconnection unit under test is established based on at least one of a computer rapid interconnection root port module, a computer rapid interconnection terminal interface module, a message manager, and the computer rapid interconnection unit under test. Specifically, the message manager directly transmits and receives messages to the computer rapid interconnection unit under test through the computer rapid interconnection interface module corresponding to the computer rapid interconnection unit under test and records the transmission and reception timestamps. The computer rapid interconnection interface module includes a computer rapid interconnection root port module and / or a computer rapid interconnection terminal interface module. This allows for direct hardware-based acquisition of the computer rapid interconnection unit's message transmission and reception timestamps. Based on the transmission timestamp and the reception timestamp, the processing delay of the test message by the computer rapid interconnection unit under test can be calculated. Because the message transmission and reception and timestamp recording in this test loop are all implemented by the message manager hardware, it does not pass through a complex transmission link like a test host, nor does it introduce errors caused by the operating system running test software to read the test results. This significantly reduces the impact of other components in the test loop on the delay test results, thereby improving the accuracy of the delay performance test results of the computer rapid interconnection unit.

[0136] It should be noted that, since some of the rapid interconnection units of the computer under test will also actively send messages, in order to ensure the accuracy of the test results, S302: receiving the feedback message of the rapid interconnection unit of the computer under test to the test message through the computer rapid interconnection interface module corresponding to the rapid interconnection unit of the computer under test, and recording the reception timestamp of the feedback message, may include: when receiving the message sent by the rapid interconnection unit of the computer under test through the computer rapid interconnection interface module corresponding to the rapid interconnection unit of the computer under test, parsing the message and determining whether it is the feedback message of the rapid interconnection unit of the computer under test to the test message, if so, recording the reception timestamp of the feedback message; if not, waiting for the rapid interconnection unit of the computer under test to send a message.

[0137] At least one of the computer rapid interconnect root port module, the computer rapid interconnect terminal interface module, and the message manager can be built based on a programmable controller. The programmable controller can be a field programmable gate array (FPGA), a complex programmable logic device (CPLD), a system on chip (SoC), a digital signal processor (DSP), an application specific integrated circuit (ASIC), etc. Alternatively, at least one of the computer rapid interconnect root port module, the computer rapid interconnect terminal interface module, and the message manager can be assembled separately.

[0138] In the CXL unit latency test method provided by the embodiment of the present invention, the sending timestamp and receiving timestamp recorded by the message manager can be sent to an external test host to calculate the latency test result of the CXL unit under test, or can be calculated by the message manager itself.

[0139] The CXL unit latency testing method provided in an embodiment of the present invention may further include calculating a latency test result for the computer rapid interconnect unit under test based on the time difference between the transmit timestamp and the receive timestamp. To improve the accuracy of the latency test results, multiple tests are performed on the same item and the average is taken. Calculating a latency test result for the computer rapid interconnect unit under test based on the time difference between the transmit timestamp and the receive timestamp may include calculating the average of multiple sets of time differences between transmit and receive timestamps to obtain the latency test result for the computer rapid interconnect unit under test.

[0140] Alternatively, the latency testing method for a CXL unit provided by the embodiment of the present invention may further include: sending the sending timestamp and the receiving timestamp to a test host via the communication module so that the test host calculates the latency test result of the CXL unit under test.

[0141] When the message manager is externally connected to the test host via a communication module, the test host can also configure the parameters of the message manager during testing. S301: Sending a test message to the computer rapid interconnection unit under test via the computer rapid interconnection interface module corresponding to the computer rapid interconnection unit under test can include: determining the message type and the number of transmissions corresponding to each message type based on the delay test parameters sent by the test host; determining configuration information for the test message to the computer rapid interconnection unit under test based on the message type and the number of transmissions corresponding to each message type; and sending the test message to the computer rapid interconnection unit under test via the computer rapid interconnection interface module corresponding to the computer rapid interconnection unit under test based on the configuration information of the test message. Furthermore, the delay test parameters can also include address generation methods, etc. Determining the configuration information for the test message to the computer rapid interconnection unit under test based on the message type and the number of transmissions corresponding to each message type, configuring the registers of the message manager, and completing the delay test configuration for the message manager.

[0142] Based on these delay test parameters, the message manager can generate a test message. S301: Sending a test message to the computer rapid interconnection unit under test via the computer rapid interconnection interface module corresponding to the computer rapid interconnection unit under test can include: generating a message in a computer rapid interconnection protocol format based on a message parameter data stream sent by the test host to obtain the test message; and sending the test message to the computer rapid interconnection unit under test via the computer rapid interconnection interface module corresponding to the computer rapid interconnection unit under test.

[0143] An embodiment of the present invention provides a method for testing a CXL unit latency. A message manager is used to directly send a test message to the computer rapid interconnection unit under test via a computer rapid interconnection interface module corresponding to the computer rapid interconnection unit under test, and the test message sending timestamp is recorded. A feedback message from the computer rapid interconnection unit under test to the test message is then received via the computer rapid interconnection interface module corresponding to the computer rapid interconnection unit under test, and the feedback message receiving timestamp is recorded. The computer rapid interconnection interface module corresponding to the computer rapid interconnection unit under test includes a computer rapid interconnection root port module and / or a computer rapid interconnection terminal interface module. This method achieves direct hardware-based acquisition of message sending and receiving timestamps of the computer rapid interconnection unit under test, without going through a test host operating system and directly based on hardware. This avoids link errors introduced in system-level testing, achieves direct measurement of the latency performance of the computer rapid interconnection unit, and thus accurately tests the latency performance of the computer rapid interconnection unit.

[0144] The fourth embodiment of the present invention is described below.

[0145] Figure 4A connection diagram of a terminal interface device for rapidly interconnecting a computer to be tested provided by an embodiment of the present invention.

[0146] Based on the above embodiment, when the computer rapid interconnection unit to be tested is a computer rapid interconnection terminal interface device to be tested, S301: sending a test message to the computer rapid interconnection unit to be tested through the computer rapid interconnection interface module corresponding to the computer rapid interconnection unit to be tested, including: sending a test message to the computer rapid interconnection terminal interface device to be tested through the computer rapid interconnection root port module.

[0147] S302: receiving a feedback message from the computer rapid interconnection unit to the test message through the computer rapid interconnection interface module corresponding to the computer rapid interconnection unit to the test message, including: receiving a feedback message from the computer rapid interconnection terminal interface device to the test message through the computer rapid interconnection root port module.

[0148] The types of test messages sent by the computer fast interconnection terminal interface device under test may include but are not limited to: a cache snoop request message sent by the host to the device when the cache misses, a cache write pull request message sent by the host to the device, a memory read request message sent by the host to the device, and a memory write request message sent by the host to the device. The corresponding feedback messages include: a cache snoop response message sent by the device to the host, a cache data message sent by the device to the host, a memory data message sent by the device to the host, and a no data response message sent by the device to the host.

[0149] like Figure 4 As shown, by connecting the computer rapid interconnection terminal interface of the computer rapid interconnection terminal interface device under test to the external interface of the computer rapid interconnection root port module, a first test loop for the computer rapid interconnection terminal interface device under test is formed, and messages related to the computer rapid interconnection terminal interface device under test are sent and received based on the first test loop.

[0150] The following combination Figure 2 The single test process of the latency of a computer fast interconnection terminal interface device to be tested in responding to a cache snoop message is described.

[0151] The test host sends a request message for testing the cache snoop latency. After the communication module parses the message, it configures the control and status registers of the message generator through the memory-mapped bus.

[0152] A message generator generates a cache snoop request (H2D Req Snoop) message that a host with a single randomly specified address sends to a device when a cache miss occurs, and sends it to the transport layer of the computer rapid interconnection root port module through a sending module. Finally, the message is sent to the computer rapid interconnection terminal interface device under test through the external interface of the computer rapid interconnection root port module. When the sending is completed, the sending module queries the current timestamp Ts1 as the sending timestamp, and sends the H2D ReqSnoop message and the sending timestamp Ts1 together to the log buffer for caching.

[0153] Both the message generator and the sending module enter the idle state.

[0154] When the receiving module receives a message sent by the fast interconnection terminal interface device of the computer under test, it queries the current timestamp Ts2 and parses the received message. If it is not a cache snoop response (D2HResp Snoop Response) message sent by the device to the host, the current timestamp Ts2 is discarded; if it is a D2H Resp Snoop Response message, the D2H Resp Snoop Response message and the corresponding receiving timestamp Ts2 are sent to the log buffer for caching.

[0155] When the log transmission module detects that the data valid signal of the log buffer is true, it reads the data and sends it to the communication module, and finally uploads it to the external test host.

[0156] The test host calculates Ts2-Ts1 to obtain the time delay of the fast interconnection terminal interface device of the computer under test in responding to the cache snoop message.

[0157] The following combination Figure 2 The single test process of the latency of the computer fast interconnection terminal interface device responding to the cache write and pull messages is described.

[0158] The test host sends a request message to test the cache write pull latency. After the communication module parses the message, it configures the control and status registers of the message generator through the memory-mapped bus.

[0159] A message generator generates a cache write pull request (H2D Resp WritePull) message sent by a host with a single randomly specified address to a device and sends it to the transport layer of the computer rapid interconnection root port module through a message sending module. Finally, it is sent to the computer rapid interconnection terminal interface device under test through the external interface of the computer rapid interconnection root port module. When the sending is completed, the sending module queries the current timestamp Ts1 as the sending timestamp, and sends the H2D RespWritePull message and the Ts1 sending timestamp to the log buffer.

[0160] Both the message generator and the sending module enter the idle state.

[0161] The receiving module receives the message returned by the computer's fast interconnection terminal interface device and queries the current timestamp Ts2. The receiving module parses the received message. If it is not a cached data (D2HData) message sent by the device to the host, the current timestamp Ts2 is discarded. If it is a D2H Data message, the message D2H Data and the corresponding reception timestamp Ts2 are sent to the log buffer.

[0162] When the log transmission module detects that the data valid signal of the log buffer is true, it reads the data and sends it to the communication module, and finally uploads it to the test host.

[0163] The test host calculates Ts2-Ts1 to obtain the delay of the fast interconnection terminal interface device of the computer under test responding to the cache write pull message.

[0164] The following combination Figure 2 The single test process of the delay of the computer fast interconnection terminal interface device under test responding to the host's memory reading message is described.

[0165] The test host sends a request message for testing the memory read latency. After the communication module parses the message, it configures the message generator control and status registers through the memory-mapped bus.

[0166] A message generator generates a memory read request (M2S Req MemRd) message sent by a host with a single randomly specified address to a device and sends it to the transport layer of the computer rapid interconnection root port module through a message sending module. Finally, it is sent to the computer rapid interconnection terminal interface device under test through the external interface of the computer rapid interconnection root port module. When the sending is completed, the sending module queries the current timestamp Ts1 as the sending timestamp, and sends the M2S Req MemRd message and the sending timestamp Ts1 to the log buffer.

[0167] Both the message generator and the sending module enter the idle state.

[0168] The receiving module receives messages from the computer's fast interconnection terminal interface device and queries the current timestamp Ts2. The receiving module parses the received message. If it is not a memory data (S2M DRSMemData) message sent by the device to the host, the current timestamp Ts2 is discarded. If it is an S2MDRS MemData message, the message S2M DRSMemData and the corresponding reception timestamp Ts2 are sent to the log buffer.

[0169] When the log transmission module detects that the data valid signal of the log buffer is true, it reads the data and sends it to the communication module, and finally uploads it to the test host.

[0170] The test host calculates Ts2-Ts1 to obtain the time delay of the fast interconnection terminal interface device of the computer under test in responding to the memory reading message.

[0171] The following combination Figure 2 The single test process of the delay of the computer fast interconnection terminal interface device under test responding to the host's memory write message is described.

[0172] The test host sends a request message for testing the memory write latency. After the communication module parses the message, it configures the message generator control and status registers through the memory-mapped bus.

[0173] A message generator generates a memory write request (M2S RwD MemWr) message sent by a host to a device with a single randomly specified address and sends it to the transport layer of the computer rapid interconnection root port module through a message sending module. Finally, it is sent to the computer rapid interconnection terminal interface device under test through the external interface of the computer rapid interconnection root port module. When the sending is completed, the sending module queries the current timestamp Ts1 as the sending timestamp and sends the M2S RwD MemWr message and the sending timestamp Ts1 to the log buffer.

[0174] Both the message generator and the sending module enter the idle state.

[0175] The receiving module receives the message returned by the computer rapid interconnection terminal interface device under test and queries the current timestamp Ts2. The receiving module parses the received message. If it is not a no data response (S2MNDR Cmp) message sent by the device to the host, the current timestamp Ts2 is discarded. If it is an S2M NDR Cmp message, the message message S2M NDRCmp and the corresponding reception timestamp Ts2 are sent to the log buffer.

[0176] When the log transmission module detects that the data valid signal of the log buffer is true, it reads the data and sends it to the communication module, and finally uploads it to the test host.

[0177] The test host calculates Ts2-Ts1 to obtain the time delay of the fast interconnection terminal interface device of the computer under test in responding to the memory write message.

[0178] The fifth embodiment of the present invention is described below.

[0179] Figure 5 A connection diagram of a root port device for testing a computer for rapid interconnection provided by an embodiment of the present invention.

[0180] Based on the above embodiment, when the computer rapid interconnection unit to be tested is a computer rapid interconnection root port device to be tested, S301: sending a test message to the computer rapid interconnection unit to be tested through the computer rapid interconnection interface module corresponding to the computer rapid interconnection unit to be tested, including: sending a test message to the computer rapid interconnection root port device to be tested through the computer rapid interconnection terminal interface module.

[0181] S302: receiving a feedback message from the computer rapid interconnection unit to the test message through the computer rapid interconnection interface module corresponding to the computer rapid interconnection unit to the test message, including: receiving a feedback message from the computer rapid interconnection root port device to the test message through the computer rapid interconnection terminal interface module.

[0182] The types of test messages sent by the CEE root port device under test may include but are not limited to: a reverse failure snoop request message sent by the device to the host, and the corresponding feedback message includes: a reverse failure response message sent by the host to the device.

[0183] like Figure 5 As shown, by connecting the CRI root port of the CRI root port device under test to the external interface of the CRI terminal interface module of the latency testing device, a second test loop for the CRI root port device under test is formed, and messages related to the CRI root port device under test are sent and received based on the second test loop.

[0184] The following combination Figure 2 The single test process of the latency of a computer fast interconnection root port device under test responding to a reverse failure snoop message is described.

[0185] The test host sends a request message for testing the reverse failure snoop delay. After the communication module parses the message, it configures the message generator control and status registers through the memory-mapped bus.

[0186] A message generator generates a (memory) reverse failure snoop request (S2M BISnp) message sent by a device with a single randomly specified address to the host and sends it to the transmission layer of the computer rapid interconnection terminal interface module through the message sending module. Finally, the computer rapid interconnection root port device to be tested is sent through the external interface of the computer rapid interconnection terminal interface module. When the sending is completed, the sending module queries the current timestamp Ts1 as the sending timestamp, and sends the S2M BISnp message and the sending timestamp Ts1 to the log buffer.

[0187] Both the message generator and the sending module enter the idle state.

[0188] The receiving module receives the message returned by the computer fast interconnect root port device under test and queries the current timestamp Ts2. It parses the received message and discards the current timestamp Ts2 if it is not a (Memory) Inverse Failure Response (M2SBIRsp) message sent by the host to the device. If it is an M2S BIRsp message, it sends the message message M2S BIRsp and the corresponding reception timestamp Ts2 to the log buffer.

[0189] When the log transmission module detects that the data valid signal of the log buffer is true, it reads the data and sends it to the communication module, and finally uploads it to the test host.

[0190] The test host calculates Ts2-Ts1 to obtain the time delay of the tested computer's fast interconnection root port device in responding to the reverse failure snoop message.

[0191] The sixth embodiment of the present invention is described below.

[0192] Figure 6 A connection diagram of a switch for rapidly interconnecting computers under test provided by an embodiment of the present invention.

[0193] Based on the above embodiment, when the computer rapid interconnection unit to be tested is a computer rapid interconnection switch to be tested, S301: sending a test message to the computer rapid interconnection unit to be tested through the computer rapid interconnection interface module corresponding to the computer rapid interconnection unit to be tested, including: sending the test message to the uplink port of the computer rapid interconnection switch to be tested through the computer rapid interconnection root port module, and sending the test message to the downlink port of the computer rapid interconnection switch to be tested through the computer rapid interconnection terminal interface module.

[0194] S302: receiving a feedback message from the computer rapid interconnection unit to be tested to a test message through a computer rapid interconnection interface module corresponding to the computer rapid interconnection unit to be tested, including: receiving a feedback message from an uplink port of the computer rapid interconnection switch to be tested through a computer rapid interconnection root port module, and receiving a feedback message from a downlink port of the computer rapid interconnection switch to be tested through a computer rapid interconnection terminal interface module.

[0195] The types of test messages sent to the CEE switch to be tested may include, but are not limited to: CEE root port device messages and CEE terminal interface device messages.

[0196] like Figure 4As shown, by connecting the uplink interface of the computer rapid interconnection switch under test to the external interface of the computer rapid interconnection root port module of the latency test device, and connecting the downlink interface of the computer rapid interconnection switch under test to the external interface of the computer rapid interconnection terminal interface module of the latency test device, a third test loop for the computer rapid interconnection switch under test is formed. Messages related to the computer rapid interconnection switch under test are sent and received based on the third test loop.

[0197] The delay performance test of the computer rapid interconnection switch under test is mainly divided into testing the delay of the computer rapid interconnection switch under test forwarding the computer rapid interconnection root port device message and testing the delay of the computer rapid interconnection switch under test forwarding the computer rapid interconnection terminal interface device message.

[0198] The following combination Figure 2 A single process of measuring the delay of a computer rapid interconnection switch forwarding a computer rapid interconnection root port device message is described.

[0199] The test host sends a request message to enumerate the ports of the computer fast interconnect switch. After the communication module parses the message, it controls the message generator control and status register through the memory mapped bus.

[0200] The message generator generates a message for reading the extended DVSEC register of the computer rapid interconnection switch, and sends the message to the uplink port of the computer rapid interconnection switch to be tested through the external interface of the computer rapid interconnection root port module via the message sending module.

[0201] The receiving module listens to the message returned by the computer rapid interconnection root port module.

[0202] The test host sends a request message to read the port information of the Computer Express Interconnect switch. After the communication module parses the message, it reads the control and status registers of the message receiving module through the memory-mapped bus. The reading process is blocked until the receiving module detects the message returned by the Computer Express Interconnect root port module.

[0203] The test host sends a message about the forwarding delay from the uplink port to the downlink port of the computer rapid interconnection switch. The message contains the downlink port information of the computer rapid interconnection switch corresponding to the interface of the computer rapid interconnection terminal interface module of the delay test device. After parsing the message, the communication module controls the message generator control and status register through the memory-mapped bus.

[0204] The message generator generates a memory read request (M2S Req MemRd) message from the host to the device based on the specified port information and other parameters. The sending module then transmits the M2S Req MemRd message via the external interface of the CRI root port module to the uplink port of the CRI switch under test. Simultaneously, the M2S Req MemRd message is sent to the log buffer along with the current timestamp, Ts1. Because the message contains port information, it is forwarded by the CRI switch under test to the corresponding downlink port of the CRI terminal interface module of the latency test device.

[0205] The receiving module listens to the computer rapid interconnection terminal interface module. When it hears the M2S Req MemRd message, it obtains the current timestamp Ts2 and transmits it along with the message to the log buffer. It should be noted that the computer rapid interconnection terminal interface module randomly generates test data and returns the memory data (abbreviated as S2M DRS MemData) message sent by the device to the host.

[0206] When the log transmission module detects that the data valid signal of the log buffer is true, it reads the data and sends it to the communication module, and finally uploads it to the test host.

[0207] The test host calculates Ts2-Ts1 to obtain the time delay of forwarding the computer fast interconnection root port device message from the uplink port to the downlink port of the computer fast interconnection switch under test.

[0208] The following combination Figure 2 A single process of measuring the delay of a computer rapid interconnection switch forwarding a computer rapid interconnection terminal interface device message is described.

[0209] The delay test device sends a computer rapid interconnection message to the downlink port of the computer rapid interconnection switch to be tested through the computer rapid interconnection terminal interface module. The message specifies the external interface of the computer rapid interconnection root port module of the delay test device corresponding to the uplink port.

[0210] The seventh embodiment of the present invention is described below.

[0211] Figure 7 This is a flowchart of another method for delay testing of a CXL unit provided by an embodiment of the present invention.

[0212] like Figure 7 As shown, the latency testing method of the CXL unit provided by the embodiment of the present invention, applied to a test host, may include:

[0213] S701: Using a communication module connected to a message manager, read the sending timestamp of a test message sent by the message manager to the computer rapid interconnection unit under test through a computer rapid interconnection interface module corresponding to the computer rapid interconnection unit under test, and the receiving timestamp of a feedback message received by the message manager from the computer rapid interconnection unit under test through the computer rapid interconnection interface module corresponding to the computer rapid interconnection unit under test in response to the test message.

[0214] S702: Calculate the delay test result of the computer fast interconnection unit to be tested according to the sending timestamp and the receiving timestamp.

[0215] The computer rapid interconnection interface module corresponding to the computer rapid interconnection unit to be tested includes a computer rapid interconnection root port module and / or a computer rapid interconnection terminal interface module.

[0216] In a specific implementation, the latency testing method for a CXL unit provided in an embodiment of the present invention may further include: using a memory-mapped bus in the communication module to send latency test parameters to the message manager to complete register configuration of the message manager. The latency test parameters include at least a message type and a corresponding number of transmissions for each message type.

[0217] The latency testing method for a CXL unit provided by an embodiment of the present invention may further include: sending a message parameter data stream to a message manager, so that the message manager generates a message in a Computer Interconnect Express protocol format from the message parameter data stream to obtain a test message.

[0218] The method for testing the time delay of a CXL unit provided by an embodiment of the present invention may further include: visually displaying the time delay test result of the computer rapid interconnect unit to be tested using a graphic display template.

[0219] For the time delay test method of the CXL unit applied to the test host, please refer to the method description when the test host is included in the above embodiment, which will not be repeated here.

[0220] The above describes in detail various embodiments corresponding to the method for testing the latency of a CXL unit. Based on this, the present invention further discloses a device, apparatus, and medium for testing the latency of a CXL unit corresponding to the above method.

[0221] The eighth embodiment of the present invention is described below.

[0222] Figure 8 A schematic structural diagram of a delay testing device for a CXL unit provided by an embodiment of the present invention.

[0223] like Figure 8 As shown, the delay test device of the CXL unit provided by the embodiment of the present invention, applied to the message manager, includes:

[0224] The sending unit 801 is used to send a test message to the computer rapid interconnection unit under test through the computer rapid interconnection interface module corresponding to the computer rapid interconnection unit under test, and record the sending timestamp of the test message;

[0225] The receiving unit 802 is configured to receive a feedback message from the computer rapid interconnection unit under test to the test message through the computer rapid interconnection interface module corresponding to the computer rapid interconnection unit under test, and record a reception timestamp of the feedback message;

[0226] Among them, the computer rapid interconnection interface module corresponding to the computer rapid interconnection unit to be tested includes a computer rapid interconnection root port module and / or a computer rapid interconnection terminal interface module; the sending timestamp and the receiving timestamp are used to calculate the delay test result of the computer rapid interconnection unit to be tested.

[0227] In some implementations, the computer rapid interconnection unit to be tested is a computer rapid interconnection terminal interface device to be tested; the sending unit 801 sends a test message to the computer rapid interconnection unit to be tested through a computer rapid interconnection interface module corresponding to the computer rapid interconnection unit to be tested, including: sending a test message to the computer rapid interconnection terminal interface device to be tested through a computer rapid interconnection root port module;

[0228] The receiving unit 802 receives the feedback message of the computer rapid interconnection unit under test to the test message through the computer rapid interconnection interface module corresponding to the computer rapid interconnection unit under test, including: receiving the feedback message of the computer rapid interconnection terminal interface device under test to the test message through the computer rapid interconnection root port module.

[0229] In some implementations, the computer rapid interconnection unit to be tested is a computer rapid interconnection root port device to be tested; the sending unit 801 sends a test message to the computer rapid interconnection unit to be tested through a computer rapid interconnection interface module corresponding to the computer rapid interconnection unit to be tested, including: sending a test message to the computer rapid interconnection root port device to be tested through a computer rapid interconnection terminal interface module;

[0230] The receiving unit 802 receives the feedback message of the computer rapid interconnection unit under test to the test message through the computer rapid interconnection interface module corresponding to the computer rapid interconnection unit under test, including: receiving the feedback message of the computer rapid interconnection root port device under test to the test message through the computer rapid interconnection terminal interface module.

[0231] In some implementations, the computer rapid interconnection unit to be tested is a computer rapid interconnection switch to be tested; the sending unit 801 sends a test message to the computer rapid interconnection unit to be tested through a computer rapid interconnection interface module corresponding to the computer rapid interconnection unit to be tested, including: sending the test message to the uplink port of the computer rapid interconnection switch to be tested through the computer rapid interconnection root port module, and sending the test message to the downlink port of the computer rapid interconnection switch to be tested through the computer rapid interconnection terminal interface module;

[0232] The receiving unit 802 receives a feedback message from the computer rapid interconnection unit under test to the test message through the computer rapid interconnection interface module corresponding to the computer rapid interconnection unit under test, including: receiving a feedback message from the uplink port of the computer rapid interconnection switch under test through the computer rapid interconnection root port module, and receiving a feedback message from the downlink port of the computer rapid interconnection switch under test through the computer rapid interconnection terminal interface module.

[0233] In some implementations, the latency testing apparatus for a CXL unit provided by an embodiment of the present invention may further include:

[0234] The first calculation unit is used to calculate the delay test result of the computer fast interconnection unit to be tested according to the time difference between the sending timestamp and the receiving timestamp.

[0235] In some implementations, the calculation unit calculates the delay test result of the computer rapid interconnection unit under test based on the time difference between the sending timestamp and the receiving timestamp, including: calculating the average value of the time difference between multiple groups of sending timestamps and receiving timestamps to obtain the delay test result of the computer rapid interconnection unit under test.

[0236] Alternatively, the latency testing device for a CXL unit provided in an embodiment of the present invention may further include:

[0237] The output unit is used to send the sending timestamp and the receiving timestamp to the test host via the communication module so that the test host can calculate the delay test result of the fast interconnection unit of the computer to be tested.

[0238] In some implementations, the sending unit 801 sends a test message to the computer rapid interconnection unit under test through the computer rapid interconnection interface module corresponding to the computer rapid interconnection unit under test, which may include: determining the message type and the number of times each message type is sent according to the delay test parameters sent by the test host; determining the configuration information of the test message to the computer rapid interconnection unit under test according to the message type and the number of times each message type is sent; and sending the test message to the computer rapid interconnection unit under test through the computer rapid interconnection interface module corresponding to the computer rapid interconnection unit under test according to the configuration information of the message under test.

[0239] In some implementations, the sending unit 801 sends a test message to the computer rapid interconnection unit to be tested through the computer rapid interconnection interface module corresponding to the computer rapid interconnection unit to be tested, which may include: generating a message in the computer rapid interconnection protocol format according to the message parameter data stream sent by the test host to obtain the test message; and sending the test message to the computer rapid interconnection unit to be tested through the computer rapid interconnection interface module corresponding to the computer rapid interconnection unit to be tested.

[0240] In some implementations, at least one of the CIE Express root port module, the CIE Express terminal interface module, and the message manager are built based on a programmable controller, a complex programmable logic device, a system-on-chip, a digital signal processor, or an application-specific integrated circuit.

[0241] In some implementations, the programmable controller includes a field programmable gate array.

[0242] Since the embodiments of the apparatus part correspond to the embodiments of the method part, please refer to the description of the embodiments of the method part for the embodiments of the apparatus part, and they will not be repeated here.

[0243] The ninth embodiment of the present invention is described below.

[0244] Figure 9 A schematic structural diagram of another CXL unit delay test device provided by an embodiment of the present invention.

[0245] like Figure 9 As shown, the delay test device of the CXL unit provided by the embodiment of the present invention is applied to the test host and includes:

[0246] The data reading unit 901 is configured to use a communication module connected to the message manager to read a sending timestamp of a test message sent by the message manager to the computer rapid interconnection unit under test via a computer rapid interconnection interface module corresponding to the computer rapid interconnection unit under test, and a receiving timestamp of a feedback message received by the message manager via the computer rapid interconnection interface module corresponding to the computer rapid interconnection unit under test in response to the test message.

[0247] A second calculation unit 902 is configured to calculate a delay test result of the computer fast interconnection unit under test according to the sending timestamp and the receiving timestamp;

[0248] Wherein, the computer rapid interconnection interface module corresponding to the computer rapid interconnection unit to be tested includes a computer rapid interconnection root port module and / or a computer rapid interconnection terminal interface module.

[0249] In some implementations, the latency testing apparatus for a CXL unit provided by an embodiment of the present invention may further include:

[0250] The first configuration unit is configured to send the delay test parameters to the message manager using the memory mapping bus in the communication module to complete the register configuration of the message manager. The delay test parameters include at least: message type and the number of transmissions corresponding to each message type.

[0251] In some implementations, the latency testing apparatus for a CXL unit provided by an embodiment of the present invention may further include:

[0252] The second configuration unit is used to send a message parameter data stream to the message manager, so that the message manager generates a message in a computer rapid interconnection protocol format from the message parameter data stream to obtain a test message.

[0253] Since the embodiments of the apparatus part correspond to the embodiments of the method part, please refer to the description of the embodiments of the method part for the embodiments of the apparatus part, and they will not be repeated here.

[0254] The following describes the tenth embodiment of the present invention.

[0255] Figure 10 A schematic structural diagram of a CXL unit delay test device provided by an embodiment of the present invention.

[0256] like Figure 10 As shown, the latency testing device of the CXL unit provided in the embodiment of the present invention includes:

[0257] Memory 1010, for storing computer programs 1011;

[0258] The processor 1020 is configured to execute the computer program 1011 . When the computer program 1011 is executed by the processor 1020 , the steps of the method for delay testing of a CXL unit as described in any one of the above embodiments are implemented.

[0259] Among them, the processor 1020 may include one or more processing cores, such as a 3-core processor, an 8-core processor, etc. The processor 1020 can be implemented in at least one hardware form of digital signal processing DSP (Digital Signal Processing), field programmable gate array FPGA (Field-Programmable Gate Array), and programmable logic array PLA (Programmable Logic Array). The processor 1020 may also include a main processor and a coprocessor. The main processor is a processor for processing data in the awake state, also known as the central processing unit CPU (Central Processing Unit); the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, the processor 1020 may be integrated with a graphics processing unit GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor 1020 may also include an artificial intelligence AI (Artificial Intelligence) processor, which is used to process computing operations related to machine learning.

[0260] The memory 1010 may include one or more media, which may be non-transitory. The memory 1010 may also include a high-speed random access memory, and a non-volatile memory, such as one or more disk storage devices, flash memory storage devices. In this embodiment, the memory 1010 is used to store at least the following computer program 1011, wherein, after the computer program 1011 is loaded and executed by the processor 1020, it can implement the relevant steps in the delay test method of the CXL unit disclosed in any of the aforementioned embodiments. In addition, the resources stored in the memory 1010 may also include an operating system 1012 and data 1013, etc., and the storage method may be temporary storage or permanent storage. Among them, the operating system 1012 may be Windows. The data 1013 may include but is not limited to the data involved in the above method.

[0261] In some embodiments, the latency testing device of the CXL unit may further include a display screen 1030 , a power supply 1040 , a communication interface 1050 , an input / output interface 1060 , a sensor 1070 , and a communication bus 1080 .

[0262] Those skilled in the art will understand that Figure 10 The structure shown in the figure does not constitute a limitation on the delay test equipment of the CXL unit, and may include more or less components than shown in the figure.

[0263] The latency testing device for a CXL unit provided by an embodiment of the present invention includes a memory and a processor. When the processor executes a program stored in the memory, it can implement the latency testing method for the CXL unit described above, achieving the same effect as above.

[0264] The following describes the eleventh embodiment of the present invention.

[0265] It should be noted that the above-described embodiments of the apparatus and equipment are merely illustrative. For example, the division of modules is merely a logical function division. In actual implementation, there may be other division methods, such as multiple modules or components may be combined or integrated into another system, or some features may be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces, indirect coupling or communication connection of the apparatus or module, which may be electrical, mechanical or other forms. The modules described as separate components may or may not be physically separated, and the components shown as modules may or may not be physical modules, that is, they may be located in one place, or they may be distributed on multiple network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment.

[0266] In addition, the functional modules in various embodiments of the present invention may be integrated into a single processing module, or each module may exist physically separately, or two or more modules may be integrated into a single module. The aforementioned integrated modules may be implemented in the form of hardware or software functional modules.

[0267] If the integrated modules are implemented as software functional modules and sold or used as independent products, they can be stored on a single medium. Based on this understanding, the technical solution of the present invention, or the portion that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored on a storage medium and executes all or part of the steps of the methods described in various embodiments of the present invention.

[0268] To this end, an embodiment of the present invention further provides a medium having a computer program stored thereon. When the computer program is executed by a processor, the steps of the delay testing method of the CXL unit are implemented.

[0269] The medium may include: a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, and other media that can store program codes.

[0270] The computer program contained in the medium provided in this embodiment can implement the steps of the delay testing method of the CXL unit described above when executed by a processor, and the effects are the same as above.

[0271] The above is a detailed introduction to the delay test method, device, system, equipment and medium of a CXL unit provided by the present invention. The various embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same and similar parts between the various embodiments can be referred to each other. For the devices, equipment and media disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple, and the relevant parts can be referred to the method part description. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present invention, the present invention can also be improved and modified in several ways, and these improvements and modifications also fall within the scope of protection of the claims of the present invention.

[0272] It should also be noted that, in this specification, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus comprising the element.

Claims

1. A delay test method for a CXL unit, characterized in that: Applies to message managers, including: Sending a test message to the computer rapid interconnection unit to be tested through a computer rapid interconnection interface module corresponding to the computer rapid interconnection unit to be tested, and recording a sending timestamp of the test message; Receiving a feedback message of the test message from the test computer fast interconnection unit through a computer fast interconnection interface module corresponding to the test computer fast interconnection unit, and recording a receiving timestamp of the feedback message; Among them, the computer rapid interconnection interface module corresponding to the computer rapid interconnection unit to be tested includes a computer rapid interconnection root port module and / or a computer rapid interconnection terminal interface module; the sending timestamp and the receiving timestamp are used to calculate the delay test result of the computer rapid interconnection unit to be tested.

2. The delay test method of the CXL unit according to claim 1, characterized in that: The computer rapid interconnection unit to be tested is a terminal interface device for rapid interconnection of the computer to be tested; The method of sending a test message to the computer rapid interconnection unit to be tested through a computer rapid interconnection interface module corresponding to the computer rapid interconnection unit to be tested comprises: sending the test message to the computer rapid interconnection terminal interface device to be tested through the computer rapid interconnection root port module; The step of receiving the feedback message of the computer rapid interconnection unit under test to the test message through the computer rapid interconnection interface module corresponding to the computer rapid interconnection unit under test comprises: receiving the feedback message of the computer rapid interconnection terminal interface device under test to the test message through the computer rapid interconnection root port module.

3. The delay test method of the CXL unit according to claim 1, characterized in that: The computer fast interconnection unit to be tested is a computer fast interconnection root port device to be tested; The method of sending a test message to the computer rapid interconnection unit to be tested through a computer rapid interconnection interface module corresponding to the computer rapid interconnection unit to be tested comprises: sending the test message to the computer rapid interconnection root port device to be tested through the computer rapid interconnection terminal interface module; The step of receiving the feedback message of the computer rapid interconnection unit under test to the test message through the computer rapid interconnection interface module corresponding to the computer rapid interconnection unit under test comprises: receiving the feedback message of the computer rapid interconnection root port device under test to the test message through the computer rapid interconnection terminal interface module.

4. The delay test method of the CXL unit according to claim 1, characterized in that: The computer fast interconnection unit to be tested is a computer fast interconnection switch to be tested; The sending of the test message to the computer rapid interconnection unit to be tested through the computer rapid interconnection interface module corresponding to the computer rapid interconnection unit to be tested comprises: sending the test message to the uplink port of the computer rapid interconnection switch to be tested through the computer rapid interconnection root port module, and sending the test message to the downlink port of the computer rapid interconnection switch to be tested through the computer rapid interconnection terminal interface module; The step of receiving a feedback message of the computer rapid interconnection unit to the test message through a computer rapid interconnection interface module corresponding to the computer rapid interconnection unit to be tested comprises: receiving the feedback message of the uplink port of the computer rapid interconnection switch to be tested through the computer rapid interconnection root port module, and receiving the feedback message of the downlink port of the computer rapid interconnection switch to be tested through the computer rapid interconnection terminal interface module.

5. The delay test method of the CXL unit according to claim 1, characterized in that: Also includes: The delay test result of the computer fast interconnection unit to be tested is obtained by calculating the time difference between the sending timestamp and the receiving timestamp.

6. The delay test method of the CXL unit according to claim 5, characterized in that: The step of calculating the delay test result of the computer fast interconnection unit to be tested according to the time difference between the sending timestamp and the receiving timestamp comprises: The average value of the time difference between the multiple groups of the sending timestamps and the receiving timestamps is calculated to obtain the delay test result of the fast interconnection unit of the computer to be tested.

7. The delay test method of the CXL unit according to claim 1, characterized in that: Also includes: The sending timestamp and the receiving timestamp are sent to a test host via a communication module so that the test host can calculate the delay test result of the fast interconnection unit of the computer to be tested.

8. The delay test method of the CXL unit according to claim 1, characterized in that: The method of sending a test message to the computer rapid interconnection unit to be tested through a computer rapid interconnection interface module corresponding to the computer rapid interconnection unit to be tested comprises: Determine the message type and the number of times each message type is sent according to the delay test parameters sent by the test host; Determining configuration information of the test message to the fast interconnection unit of the computer to be tested according to the message type and the number of times each message type is sent; According to the configuration information of the message to be tested, the test message is sent to the computer rapid interconnection unit to be tested through a computer rapid interconnection interface module corresponding to the computer rapid interconnection unit to be tested.

9. The delay test method of the CXL unit according to claim 1, characterized in that: The method of sending a test message to the computer rapid interconnection unit to be tested through a computer rapid interconnection interface module corresponding to the computer rapid interconnection unit to be tested comprises: Generate a message in a computer rapid interconnection protocol format according to a message parameter data stream sent by the test host to obtain the test message; The test message is sent to the computer rapid interconnection unit to be tested through a computer rapid interconnection interface module corresponding to the computer rapid interconnection unit to be tested.

10. The delay test method of the CXL unit according to claim 1, characterized in that: The computer rapid interconnection root port module, at least one of the computer rapid interconnection terminal interface modules, and the message manager are constructed based on a programmable controller.

11. The time delay test method of the CXL unit according to claim 10, characterized in that: The programmable controller includes a field programmable logic gate array, a complex programmable logic device, a system-on-chip, a digital signal processor or an application-specific integrated circuit.

12. A method for testing the delay of a CXL unit, characterized in that: Applicable to test hosts, including: Using a communication module connected to a message manager, read a sending timestamp of a test message sent by the message manager to the computer rapid interconnection unit under test through a computer rapid interconnection interface module corresponding to the computer rapid interconnection unit under test, and a receiving timestamp of a feedback message of the computer rapid interconnection unit under test to the test message received by the message manager through the computer rapid interconnection interface module corresponding to the computer rapid interconnection unit under test; Calculate the delay test result of the fast interconnection unit of the computer to be tested according to the sending timestamp and the receiving timestamp; Wherein, the computer rapid interconnection interface module corresponding to the computer rapid interconnection unit to be tested includes a computer rapid interconnection root port module and / or a computer rapid interconnection terminal interface module.

13. The delay test method of the CXL unit according to claim 12, characterized in that: Also includes: Sending the delay test parameters to the message manager using a memory-mapped bus in the communication module to complete register configuration of the message manager; The delay test parameters include at least: message type and the number of times each message type is sent.

14. The delay test method of the CXL unit according to claim 12, characterized in that: Also includes: A message parameter data stream is sent to the message manager, so that the message manager generates a message in a computer rapid interconnection protocol format from the message parameter data stream to obtain the test message.

15. A time delay test device for a CXL unit, characterized in that: include: A message manager, a computer rapid interconnection root port module and a computer rapid interconnection terminal interface module; The message manager is used to send a test message to the computer rapid interconnection unit under test through a computer rapid interconnection interface module corresponding to the computer rapid interconnection unit under test, and record the sending timestamp of the test message; receive a feedback message from the computer rapid interconnection unit under test to the test message through a computer rapid interconnection interface module corresponding to the computer rapid interconnection unit under test, and record the receiving timestamp of the feedback message; Among them, the computer rapid interconnection interface module corresponding to the computer rapid interconnection unit to be tested includes the computer rapid interconnection root port module and / or the computer rapid interconnection terminal interface module; the sending timestamp and the receiving timestamp are used to calculate the delay test result of the computer rapid interconnection unit to be tested.

16. The delay test device of the CXL unit according to claim 15, characterized in that: The message manager includes: a message generator, a log buffer, a time module, a sending module and a receiving module; Wherein, the first end of the message generator is connected to the first end of the sending module, the second end of the sending module is connected to the first end of the log buffer, the third end of the sending module is the message output interface of the message manager, the first end of the receiving module is connected to the second end of the log buffer, the second end of the receiving module is the message input interface of the message manager, and the output end of the time module is respectively connected to the fourth end of the sending module and the third end of the receiving module; The message generator is used to send the test message to the fast interconnection unit of the computer to be tested through the sending module; The sending module is used to cache the sending timestamp obtained from the time module when sending the test message to the log buffer; The receiving module is used to cache the receiving timestamp obtained from the time module when the feedback message is received into the log buffer.

17. The delay test device of the CXL unit according to claim 15, characterized in that: Also includes a communication module; The first end of the communication module is used to connect to the test host, and the second end of the communication module is connected to the register configuration interface of the message manager so that the test host sends delay test parameters to the message manager to complete the register configuration of the message manager; the third end of the communication module is connected to the log transmission interface of the message manager so that the test host can read the test message, the feedback message, the sending timestamp and the receiving timestamp recorded in the message register.

18. The delay test device of the CXL unit according to claim 15, characterized in that: The number of the computer rapid interconnection root port modules and the number of the computer rapid interconnection terminal interface modules are both multiple, each of the computer rapid interconnection root port modules is respectively connected to a different interface of the message manager, and each of the computer rapid interconnection terminal interface modules is respectively connected to a different interface of the message manager.

19. A time delay test system for a CXL unit, characterized in that: include: A time delay test device for a computer fast interconnect unit and a test host connected to the time delay test device; The delay test device includes a message manager, a computer rapid interconnection root port module, a computer rapid interconnection terminal interface module and a communication module; the message manager is used to send a test message to the computer rapid interconnection unit to be tested through the computer rapid interconnection interface module corresponding to the computer rapid interconnection unit to be tested, and record the sending timestamp of the test message; receive the feedback message of the computer rapid interconnection unit to be tested to the test message through the computer rapid interconnection interface module corresponding to the computer rapid interconnection unit to be tested, and record the receiving timestamp of the feedback message; The test host is used to read the sending timestamp and the receiving timestamp through the communication module, and calculate the delay test result of the fast interconnection unit of the computer to be tested according to the sending timestamp and the receiving timestamp; Wherein, the computer rapid interconnection interface module corresponding to the computer rapid interconnection unit to be tested includes the computer rapid interconnection root port module and / or the computer rapid interconnection terminal interface module.

20. A time delay test device for a CXL unit, characterized in that: Applies to message managers, including: A sending unit, used for sending a test message to the computer rapid interconnection unit to be tested through a computer rapid interconnection interface module corresponding to the computer rapid interconnection unit to be tested, and recording a sending timestamp of the test message; A receiving unit, configured to receive a feedback message from the computer rapid interconnection unit to the test message through a computer rapid interconnection interface module corresponding to the computer rapid interconnection unit to be tested, and record a receiving timestamp of the feedback message; Among them, the computer rapid interconnection interface module corresponding to the computer rapid interconnection unit to be tested includes a computer rapid interconnection root port module and / or a computer rapid interconnection terminal interface module; the sending timestamp and the receiving timestamp are used to calculate the delay test result of the computer rapid interconnection unit to be tested.

21. A time delay test device for a CXL unit, characterized in that: Applicable to test hosts, including: A data reading unit is used to read, by means of a communication module connected to a message manager, a sending timestamp of a test message sent by the message manager to the computer rapid interconnection unit under test through a computer rapid interconnection interface module corresponding to the computer rapid interconnection unit under test, and a receiving timestamp of a feedback message of the computer rapid interconnection unit under test to the test message received by the message manager through the computer rapid interconnection interface module corresponding to the computer rapid interconnection unit under test; A second calculation unit, used for calculating the delay test result of the fast interconnection unit of the computer to be tested according to the sending timestamp and the receiving timestamp; Wherein, the computer rapid interconnection interface module corresponding to the computer rapid interconnection unit to be tested includes a computer rapid interconnection root port module and / or a computer rapid interconnection terminal interface module.

22. A time delay test device for a CXL unit, characterized in that: include: Memory for storing computer programs; A processor is used to execute the computer program, and when the computer program is executed by the processor, the steps of the delay testing method of the CXL unit according to any one of claims 1 to 14 are implemented.

23. A medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the delay testing method of the CXL unit according to any one of claims 1 to 14 are implemented.

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