Multi-bus compatible aircraft online anomaly detection system

Abstract

The invention relates to a multi-bus compatible aircraft online anomaly detection system, and belongs to the technical field of state monitoring and bus communication. Comprising a first monitoring module used for monitoring data of a communication board card transmission line; the second monitoring module is used for monitoring data of the bus transmission line; the acquisition module is used for converting the analog signal into a digital signal; the core board module is responsible for operating a logic program to decode monitored data and deploying a subsequent fault prediction algorithm; and the voltage conversion module is used for converting the voltage supplied by the power supply and outputting the required voltage to be used by other modules. According to the invention, the monitoring and acquisition of various data types (RS485 bus data, 1553B bus data and analog quantity) are highly comprehensive; according to the method, self-adaptive algorithm design is carried out for multiple transmission protocols, the anomaly detection quality is improved, and the method is suitable for complex environments, faces multiple data types and realizes effective system monitoring.

Description

Technical Field

[0001] The invention relates to a multi-bus compatible aircraft online anomaly detection system, belonging to the technical field of state monitoring and bus communication. Background Art

[0002] At this stage, condition monitoring technology has become one of the core technologies for realizing equipment maintenance and intelligent management. Specifically, for aircraft in flight, as the complexity of the aircraft itself and the complexity of the flight environment continue to increase, the demand for real-time monitoring of its overall system status is also increasing. For example: The publication number is CN116243085A, and the name of the invention is a wearable electrical and electronic system diagnostic device. Its technical solution realizes the support of fixed protocols and the completion of protocol parsing, that is, the monitoring and decoding process under a single protocol. Therefore, the existing monitoring system has the following problems:

[0003] (1) The existing real-time status monitoring system embedded in the aircraft is unable to effectively monitor the complex environment of the aircraft in flight and various data types;

[0004] (2) At present, multiple communication protocols are often used to transmit data between the key components of aircraft to be monitored and the embedded non-intrusive monitoring system. The purpose is to ensure that the communication protocol is switched to another protocol when one protocol fails, and to improve the compatibility, flexibility and reliability of the whole system in different network environments and devices. However, the existing monitoring system can only identify and decode one communication protocol for a specific data type, and it needs to be manually reconfigured to deal with multiple protocols, which is seriously insufficient in flexibility.

[0005] (3) Current fault monitoring systems that use a single channel data source for processing often face the problem of single features. For example, some faults may not be obvious in the data of a certain protocol, but may be significant in the data of another protocol.

[0006] Therefore, it is urgent to propose a multi-bus compatible aircraft online anomaly detection system to solve the above technical problems. Summary of the invention

[0007] In order to solve the above problems, a non-intrusive monitoring system for aircraft fault diagnosis based on protocol adaptation is provided, which can be embedded in an aircraft in flight to monitor the status of many components of the aircraft in flight. A brief overview of the present invention is given below to provide a basic understanding of certain aspects of the present invention. It should be understood that this overview is not an exhaustive overview of the present invention. It is not intended to identify the key or important parts of the present invention, nor is it intended to limit the scope of the present invention.

[0008] The technical solution of the present invention:

[0009] Multi-bus compatible aircraft online anomaly detection system, including:

[0010] The first monitoring module: used to monitor the data of the communication board transmission line;

[0011] The second monitoring module: used to monitor the data of the bus transmission line;

[0012] Acquisition module: used to convert analog signals into digital signals with high sampling rate and resolution;

[0013] Core board module: responsible for running the logic program to decode the monitored data and deploy subsequent fault prediction algorithms;

[0014] Voltage conversion module: converts the voltage supplied by the power supply and outputs the required voltage for use by other modules;

[0015] It can be used for satellite or UAV status monitoring and data processing.

[0016] Preferably: the first monitoring module is a 1553B monitoring module, including a dual transceiver, all output and input pins of the dual transceiver are connected to the core board module, and are used to monitor the data of the communication board transmission line; it complies with the MIL-STD-1553B standard and supports multiple interfaces such as synchronous or asynchronous parallel bus, serial port and SPI interface;

[0017] The second monitoring module is an RS485 monitoring module, which includes a four-channel integrated circuit, the four-channel integrated circuit has a dual driver and a receiver, the differential signal receiving end of each channel is connected to the transmitting end, and the four-channel integrated circuit is connected to the core board module for monitoring the data of the bus transmission line;

[0018] The acquisition module is an AD acquisition module, including an operational amplifier part (four pieces of eight-channel voltage-stabilized operational amplifiers) and an analog-to-digital conversion part (a highly integrated 8-input analog-to-digital converter ADC). The operational amplifier part is connected to the input end of the analog-to-digital conversion part, and the output end of the analog-to-digital conversion part is connected to the core board module through the DOUT pin;

[0019] Core board module: The core board is connected to the CPU through the JTAG terminal. The CPU uses the PDS development software of Unigroup Tongchuang to burn the logic program to the PG2L100H chip of the core board through the connector. The host computer can be a display with a user interface program. The host computer is connected to the CPU and configures the system parameters through the host computer program. The core board module is connected to the storage module (SD card);

[0020] Voltage conversion module: The power supply is connected to the 1553B monitoring module, RS485 monitoring module, AD acquisition module, and core board module through the voltage conversion module and supplies power. The voltage conversion module converts the 27V voltage supplied by the power supply into 5V, and then converts the 5V voltage into 3.3V for use by other modules; this DC-DC voltage conversion module uses components such as inductors and capacitors to transform and filter the input DC voltage, and finally outputs the required voltage.

[0021] Preferably: the 1553B monitoring module includes a low-power CMOS dual transceiver and two transformers, the transformer adopts a PM-DB2725EX transformer, and the dual transceiver is a HI-1573 chip; the output ends of the two transformers are connected to the input ends of the HI-1573 chip, and the output end of the HI-1573 chip is connected to the core board module; the transformer is used to step down the received 1553B signal and convert it into a signal with a suitable voltage value that can be subsequently input into the HI-1573 chip so that it can be received by the HI-1573 chip).

[0022] Preferably: the operational amplifier part of the AD acquisition module includes four chips of model AD8552AR; the analog-to-digital conversion part of the AD acquisition module includes an analog-to-digital conversion chip, and the analog-to-digital conversion chip adopts a highly integrated chip of model AD7856ARZ.

[0023] Preferred: The core board module is the core of the entire system, and the domestic PANGO series Logos2 FPGA core board produced by Ziguang Tongchuang is adopted. For the RS485 bus data transmitted above, protocol judgment and decoding processing must be performed first, and different protocols will use different decoding methods later.

[0024] Preferably: the voltage conversion module converts the voltage provided by the external power supply into a voltage suitable for other modules to complete the energy supply operation, including a voltage conversion chip and a low-dropout voltage regulator, the power supply is connected to the core board module, the second monitoring module, and the acquisition module through the voltage conversion chip, and the power supply is connected to the SD card of the first monitoring module through the voltage conversion chip and the low-dropout voltage regulator in sequence;

[0025] The voltage conversion chip adopts the voltage conversion chip of model VRB_S-10WR3; the low voltage dropout regulator adopts the low voltage dropout regulator of model TPS73801-SEP.

[0026] Preferably: the storage module includes a Micro SD connector (Micro_SuD_Connector) and a Micro SD card, and the SD card is connected to the core board module via the connector.

[0027] Preferably: for RS485 bus data under various protocol transmission modes, an adaptive protocol recognition algorithm is designed, and different protocol types are identified before subsequent decoding processes are performed, and the obtained data is time-aligned and spliced ​​and input into the LSSVM model for joint status monitoring, including the following steps:

[0028] The first byte of the Modbus RTU protocol data string is the address. When the value is 0, it means that the broadcast communication method is adopted. When the value is 1-247, it represents a specific slave address device. The common values ​​of the 1-byte function code following it are shown in Table 1 below;

[0029] Table 1 ModbusRTU protocol function codes and functions

[0030]

[0031] The HDLC protocol has fixed start and end flags, namely 0×7E, so the HDLC protocol judgment based on this feature is highly accurate.

[0032] The different start delimiters (first byte) of the Profibus DP protocol can be distinguished into four different communication modes. The values ​​and meanings are shown in Table 2 below. The transmission protocol and communication mode used in the transmission process are determined according to the start delimiter, tail frame and frame structure of different communication modes.

[0033] Table 2 Characteristics of the four transmission modes of Profibus DP protocol

[0034]

[0035] Therefore, combining the characteristics of the four protocols, the adaptive protocol processing design is as follows Figure 7 As shown;

[0036] Among them, the interpretation of the DMX512 protocol is relatively easy. It only needs to detect whether the data contains a low level (Break) lasting at least 88μs and followed by a high level (MAB) lasting at least 8μs. This method can be used to determine whether the DMX512 protocol is used.

[0037] The main method for interpreting the HDLC protocol is to determine its start frame and end frame. If both are 0×7E, it can be determined that the HDLC protocol is used for 485 communication. If only the start frame is 0×7E and the end frame is not 0×7E, it is determined that the Modbus RTU unicast mode is used to communicate with the device with address 126 (0×7E).

[0038] As described in Table 2 above, for the four Profibus DP protocol transmission modes, when the start frame is 0×10, the SD1 communication mode of the Profibus DP protocol may be used, or the Modbus RTU protocol may be used to transmit data to the device with address 16 (0×10) in a single-end manner, which requires further judgment later; since the SD1 mode of the Profibus DP protocol is a short frame transmission mode, its frame length is significantly shorter than that of the Modbus RTU protocol, only 5-6 bytes, so when the frame length is 5-6 bytes, it is judged that the protocol used at this time is Profibus DP and the communication mode used is SD1; if the frame length is longer, it is judged that the Modbus RTU protocol is used to transmit data to the device with address 16;

[0039] As described in Table 2 above, for the four Profibus DP protocol transmission modes, when the start frames are 0×2A, 0×68, and 0×DC respectively, if the end frame is fixed to 0×16, it can be judged that the three transmission modes SD2, SD3, and SD4 of the Profibus DP protocol are adopted respectively. Otherwise, it is judged that the Modbus RTU protocol is used for unicast transmission to the devices with addresses 42 (0×2A), 104 (0×68), and 220 (0×DC) respectively.

[0040] If the start frame is 0×00, it can be determined that the broadcast transmission mode of the Modbus RTU protocol is used. When the start frame is not the above-mentioned situation, it can be determined that the Modbus RTU protocol is used for unicast transmission to the device with address X (Note: X is the number of frames not mentioned above);

[0041] After the protocol determination is completed, the bus data under different protocols are imported into the corresponding decoding module for decoding. The obtained RS485 bus data is called the first state data, the 1553B bus data is called the second state data, and the data obtained by AD sampling is the third state data;

[0042] A 0.1s time window is used for time alignment, and the missing time points of the two protocols contained in the small window are filled in by Hermite interpolation. The principle of Hermite interpolation is as follows: Let the interpolation function be H, then H(x i )=y i ,H'(x i )=y i '(x),(i=0,1,…,n); There are 2n+2 conditions here, which uniquely determine a polynomial with a degree not exceeding 2n+1, as shown in formula (1):

[0043] H 2n+1(x) = a0+a1x+…+a 2n+1 x 2n+1 (1)

[0044] According to the solution method of Lagrange interpolation polynomial, the function value and the first-order derivative value at the interpolation node are used as the polynomial coefficients, and the zero point and sampling delta properties are used to solve the appropriate basis function; denoted by m i =y i '(x), then the Lagrange polynomial of H can be expressed as formula (2):

[0045]

[0046] The interpolation remainder R(x) can be expressed as formula (3):

[0047]

[0048] The first state data after interpolation is recorded as α1, α2, ..., and the second state data after interpolation is recorded as β1, β2, .... The two sets of state data are completely corresponding in time. They are horizontally spliced ​​according to the timestamp to form a new data set [(α1, β1), (α2, β2), ...]. The data in the data set are sequentially input into an array of size 10×2, which is recorded as C. The first C is:

[0049]

[0050] Put these ten spliced ​​data points into the trained LSSVM model for inference calculation and obtain (α' 11 ,β' 11 ), the predicted value (α' 11 ,β' 11 ) and the true value (α 11 ,β 11 ) is compared, if it is less than the threshold, it is judged to be fault-free, if it is greater than the threshold, the aircraft has a fault; it should be noted that when the data is judged to be fault-free at this point, the next inference calculation needs to be (α 11 ,β 11 ) is put into the last row of matrix C and (α1,β1) is removed to make (α' 12 ,β' 12 ) prediction work, and so on; when the point is judged to be faulty, the next reasoning calculation needs to be (α' 11 ,β' 11 ) is put into the last row of matrix C and (α1,β1) is removed to make (α' 12 ,β' 12 ) and so on;

[0051] For the third state data, which is marked as γ1, γ2, ..., there is no need to perform protocol data fusion processing as described above. The data can be directly spliced ​​into a matrix of size 10×1, and the same as above, ten points are used to splice into an array (γ1, γ2, ..., γ 10 ) to predict the next point γ' 11 Fault situation; when the predicted value γ' 11 and the true value γ 11 When the difference is greater than the set threshold, the data at this point is judged to be faulty and γ' 11 Spliced ​​to the previous nine points γ2,γ3,…,γ 10 Finally, the array (γ2,γ3,…,γ 10 ,γ' 11 ) to the twelfth point γ' 12 prediction, and so on; when the predicted value γ' 11 and the true value γ 11 When the difference is less than the set threshold, it is judged that there is no fault at this point, and γ 11 Spliced ​​to the previous nine points γ2,γ3,…,γ 10 Finally, the array (γ2,γ3,…,γ 10 ,γ 11 ) to the twelfth point γ' 12 predictions, and so on;

[0052] The obtained raw data and fault handling results are stored in the SD card for easy reading.

[0053] The present invention has the following beneficial effects:

[0054] The present invention proposes an acquisition system integrating 4-channel RS485 monitoring channels, 2-channel 1553B monitoring channels and 8-channel AD based on a core board module, and has strong comprehensiveness in monitoring and acquisition of various data types (RS485 bus data, 1553B bus data, analog quantity); the present invention designs an adaptive algorithm for various transmission protocols of RS485, and sends the identified different protocol data to subsequent modules for decoding and other processing; the decoded RS485 bus data and 1553B bus data are aligned and spliced, and subsequently sent to an LSSVM model for training and reasoning, the trained model integrates the data transmitted by the two protocols, and has more comprehensive performance for fault monitoring of equipment; the AD acquisition module also inputs the analog quantities of each channel into the LSSVM model used by the present invention for reasoning calculation, which generally improves the quality of fault monitoring, is suitable for complex environments and facing various data types, and realizes efficient system monitoring. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] Figure 1 It is a schematic diagram of the structure of a multi-bus compatible aircraft online anomaly detection system;

[0056] Figure 2 It is a monitoring system voltage conversion module (27V to 5V, 5V to 3.3V);

[0057] Figure 3 This is the RS485 monitoring module circuit connection diagram (channel 1);

[0058] Figure 4 This is the circuit connection diagram of the 1553B monitoring module (channels A and B);

[0059] Figure 5 This is the circuit connection diagram of the AD acquisition module;

[0060] Figure 6 It is the SD card connector;

[0061] Figure 7 It is a flow chart of a non-intrusive monitoring and identification method for aircraft fault diagnosis based on protocol adaptation and data fusion;

[0062] Figure 8 It is the LSSVM data processing flow chart. DETAILED DESCRIPTION

[0063] In order to make the purpose, technical scheme and advantages of the present invention clearer, the present invention is described below by the specific embodiments shown in the accompanying drawings. However, it should be understood that these descriptions are only exemplary and are not intended to limit the scope of the present invention. In addition, in the following description, the description of well-known structures and technologies is omitted to avoid unnecessary confusion of the concept of the present invention.

[0064] Specific implementation method 1: Combination Figure 1-6 The present embodiment is described. The multi-bus compatible aircraft online anomaly detection system of the present embodiment includes:

[0065] The first monitoring module: used to monitor the data of the communication board transmission line;

[0066] The second monitoring module: used to monitor the data of the bus transmission line;

[0067] Acquisition module: used to convert analog signals into digital signals with high sampling rate and resolution;

[0068] Core board module: responsible for running the logic program to decode the monitored data and deploy subsequent fault prediction algorithms;

[0069] Voltage conversion module: converts the voltage supplied by the power supply and outputs the required voltage for use by other modules;

[0070] It can be used for status monitoring and data processing of satellites or unmanned aerial vehicles; based on the domestic core board module, the present invention proposes an integrated 4-channel RS485 monitoring channel, 2-channel 1553B monitoring channel and 8-channel AD acquisition system, which has strong comprehensiveness in monitoring and acquisition of various data types (RS485 bus data, 1553B bus data, analog quantity). Since most 1553B bus transmissions use the MIL-STD-1553B transmission standard for communication, and RS485 bus communication often uses multiple protocols, the present invention is aimed at multiple transmission protocols of RS485. An adaptive algorithm is designed, and the identified different protocol data are sent to subsequent modules for decoding and other processing; thereafter, the decoded RS485 bus data and the 1553B bus data are aligned and spliced, and then sent to the LSSVM model for training and reasoning. The trained model integrates the data transmitted by the two protocols and has a more comprehensive performance for equipment fault monitoring; the AD acquisition module also inputs the analog quantities of each channel into the LSSVM model used in the present invention for reasoning operations, which generally improves the quality of fault monitoring and is suitable for complex environments and facing a variety of data types to achieve efficient system monitoring.

[0071] Specific implementation method 2: Combination Figure 1-6 The present embodiment is described. The multi-bus compatible aircraft online anomaly detection system of the present embodiment, the first monitoring module is a 1553B monitoring module, including a dual transceiver, all output and input pins of the dual transceiver are connected to the core board module, and are used to monitor the data of the communication board transmission line; it complies with the MIL-STD-1553B standard, and supports multiple interfaces such as synchronous or asynchronous parallel bus, serial port and SPI interface;

[0072] The second monitoring module is an RS485 monitoring module, which includes a four-channel integrated circuit, the four-channel integrated circuit has a dual driver and a receiver, the differential signal receiving end of each channel is connected to the transmitting end, and the four-channel integrated circuit is connected to the core board module for monitoring the data of the bus transmission line;

[0073] The acquisition module is an AD acquisition module, including an operational amplifier part (four pieces of eight-channel voltage-stabilized operational amplifiers) and an analog-to-digital conversion part (a highly integrated 8-input analog-to-digital converter ADC). The operational amplifier part is connected to the input end of the analog-to-digital conversion part, and the output end of the analog-to-digital conversion part is connected to the core board module through the DOUT pin;

[0074] Core board module: The core board is connected to the CPU through the JTAG terminal. The CPU uses the PDS development software of Unigroup Tongchuang to burn the logic program to the PG2L100H chip of the core board through the connector. The core board module is connected to the storage module (SD card);

[0075] Voltage conversion module: The power supply is connected to the 1553B monitoring module, RS485 monitoring module, AD acquisition module, and core board module through the voltage conversion module and supplies power. The voltage conversion module converts the 27V voltage supplied by the power supply into 5V, and then converts the 5V voltage into 3.3V for use by other modules; this DC-DC voltage conversion module uses components such as inductors and capacitors to transform and filter the input DC voltage, and finally outputs the required voltage.

[0076] Specific implementation method three: Combination Figure 1-6 The present embodiment is described. The multi-bus compatible aircraft online anomaly detection system of the present embodiment, the 1553B monitoring module includes a low-power CMOS dual transceiver and two transformers, the transformer adopts a PM-DB2725EX transformer, and the dual transceiver is a HI-1573 chip; the two transformers are connected to the HI-1573 chip, and the HI-1573 chip is connected to the core board module; the transformer is used to step down the received 1553B signal so that it can be received by the HI-1573 chip.

[0077] Specific implementation method four: Combination Figure 1-6 The present embodiment is described. The multi-bus compatible aircraft online anomaly detection system of the present embodiment, the RS485 monitoring module includes four chips of model SN65C1167ENSR, which convert the received RS485 clock and data into single-ended signals.

[0078] Specific implementation method five: Combination Figure 1-6 To illustrate this embodiment, the multi-bus compatible aircraft online anomaly detection system of this embodiment, the operational amplifier part of the AD acquisition module includes four chips of model AD8552AR, and the analog-to-digital conversion part of the AD acquisition module includes an analog-to-digital conversion chip, and the analog-to-digital conversion chip adopts the highly integrated chip of model AD7856ARZ.

[0079] Specific implementation method six: Combination Figure 1-6 To illustrate this embodiment, the multi-bus compatible aircraft online anomaly detection system of this embodiment, the core board module is the core of the entire system, and the domestic PANGO series Logos2 FPGA core board produced by Tsinghua Tongchuang is adopted for the RS485 bus data transmitted above.

[0080] Specific implementation method seven: Combination Figure 1-6The present embodiment is described. In the multi-bus compatible aircraft online abnormality detection system of the present embodiment, the voltage conversion module converts the voltage provided by the external power supply into a voltage suitable for other modules to complete the energy supply operation, including a voltage conversion chip and a low voltage dropout regulator. The power supply is connected to the core board module, the second monitoring module, and the acquisition module through the voltage conversion chip. The power supply is connected to the SD card of the first monitoring module through the voltage conversion chip and the low voltage dropout regulator in sequence.

[0081] The voltage conversion chip adopts the voltage conversion chip of model VRB_S-10WR3; the low voltage dropout regulator adopts the low voltage dropout regulator of model TPS73801-SEP.

[0082] Specific implementation method eight: Combination Figure 1-6 To illustrate this embodiment, the multi-bus compatible aircraft online anomaly detection system of this embodiment, the storage module includes a Micro SD connector (Micro_SuD_Connector) and a Micro SD card, and the SD card is connected to the core board module through the connector.

[0083] Specific implementation method nine: Combination Figure 1-8 The embodiment of the present invention is described. The multi-bus compatible aircraft online anomaly detection system of the present embodiment designs an adaptive protocol identification algorithm for RS485 bus data under various protocol transmission modes. After different protocol types are identified, subsequent decoding processes are performed separately. The obtained data is time-aligned and spliced ​​and input into the LSSVM model for joint status monitoring, including the following steps:

[0084] The first byte of the Modbus RTU protocol data string is the address. When the value is 0, it means that the broadcast communication method is adopted. When the value is 1-247, it represents a specific slave address device. The common values ​​of the 1-byte function code following it are shown in Table 1 below;

[0085] Table 1 ModbusRTU protocol function codes and functions

[0086]

[0087] The HDLC protocol has a fixed start mark bit and end mark bit, namely 0×7E. Therefore, the HDLC protocol judgment based on this feature has a strong accuracy. 0X7E is converted into binary 01111110. In the actual operation process, the design realizes the identification of the HDLC protocol by monitoring 01111110.

[0088] The different start delimiters (first byte) of the Profibus DP protocol can be distinguished into four different communication modes. The values ​​and meanings are shown in Table 2 below. The transmission protocol and communication mode used in the transmission process are determined according to the start delimiter, tail frame and frame structure of different communication modes.

[0089] Table 2 Characteristics of the four transmission modes of the Profibus DP protocol

[0090]

[0091]

[0092] Therefore, combining the characteristics of the four protocols, the adaptive protocol processing design is as follows Figure 7 As shown;

[0093] Among them, the interpretation of the DMX512 protocol is relatively easy. It only needs to detect whether the data contains a low level (Break) lasting at least 88μs and followed by a high level (MAB) lasting at least 8μs. This method can be used to determine whether the DMX512 protocol is used.

[0094] The main method for interpreting the HDLC protocol is to determine its start frame and end frame. If both are 0×7E, it can be determined that the HDLC protocol is used for 485 communication. If only the start frame is 0×7E and the end frame is not 0×7E, it is determined that the Modbus RTU unicast mode is used to communicate with the device with address 126 (0×7E).

[0095] As described in Table 2 above, for the four Profibus DP protocol transmission modes, when the start frame is 0×10, the SD1 communication mode of the Profibus DP protocol may be used, or the Modbus RTU protocol may be used to transmit data to the device with address 16 (0×10) in a single-end manner, which requires further judgment later; since the SD1 mode of the Profibus DP protocol is a short frame transmission mode, its frame length is significantly shorter than that of the Modbus RTU protocol, only 5-6 bytes, so when the frame length is 5-6 bytes, it is judged that the protocol used at this time is Profibus DP and the communication mode used is SD1; if the frame length is longer, it is judged that the Modbus RTU protocol is used to transmit data to the device with address 16;

[0096] As described in Table 2 above, for the four Profibus DP protocol transmission modes, when the start frames are 0×2A, 0×68, and 0×DC, respectively, if the end frame is fixed at 0×16, it can be judged that the three transmission modes SD2, SD3, and SD4 of the Profibus DP protocol are adopted respectively. Otherwise, it is judged that the Modbus RTU protocol is used for unicast transmission to the devices with addresses 42 (0×2A), 104 (0×68), and 220 (0×DC) respectively; this is because 0×2A, 0×68, and 0×DC are converted to decimal 42, 104, and 220 respectively. When the monitoring device detects the above three frame data, it may be the three transmission formats SD2-SD4 of the Profibus DP protocol, or it may be the sign of the Modbus RTU protocol transmitting from the device with addresses 42, 104, and 220, so it is necessary to judge the end frame;

[0097] If the start frame is 0×00, it can be determined that the broadcast transmission mode of the Modbus RTU protocol is used. When the start frame is not the above-mentioned situation, it can be determined that the Modbus RTU protocol is used for unicast transmission to the device with address X (Note: X is the number of frames not mentioned above);

[0098] After the protocol determination is completed, the bus data under different protocols are imported into the corresponding decoding module for decoding. The obtained RS485 bus data is called the first state data, the 1553B bus data is called the second state data, and the data obtained by AD sampling is the third state data;

[0099] The decoded data needs to be further processed to facilitate the subsequent splicing process; for the first state data and the second state data, first of all, it should be ensured that the two have consistent timestamps. Here, the small window + linear interpolation method is used for processing; this patent uses a 0.1s time window for time alignment processing, and Hermite interpolation is performed on the missing time points corresponding to the two protocols contained in the small window to fill in the time. The principle of Hermite interpolation is as follows: Let the interpolation function be H, then H(x i )=y i (x i ),H'(x i )=y i '(x i ), (i=0,1,…,n); there are 2n+2 conditions in total, which can uniquely determine a polynomial with a degree not exceeding 2n+1, as shown in formula (1):

[0100] H 2n+1 (x) = a0+a1x+…+a 2n+1 x 2n+1 (1)

[0101] Where n represents all existing time points of the data to be spliced, a total of n, each point is recorded as 1, 2, 3, ... n; x i is the corresponding time of the i-th time point (value ranges from 1 to n), y i (x i ) is x i Decoded data corresponding to the time point, y i '(x i ) is x i The derivative of the decoded data corresponding to the time point can be obtained by using the difference method; H(x i ) is the constructed Hermitian polynomial, H'(x i ) is its derivative; a in the polynomial is the unknown coefficient of the polynomial not exceeding 2n+1, and its specific value is given by H(x i )=y i (x i ),H'(x i )=y i '(x i ),(i=0,1,…,n) to solve.

[0102] According to the solution method of Lagrange interpolation polynomial, the function value and the first-order derivative value at the interpolation node are used as the polynomial coefficients, and the zero point and sampling delta properties are used to solve the appropriate basis function; denoted by m i =y i '(x), then the Lagrange polynomial of H can be expressed as formula (2):

[0103]

[0104] Among them, α j (x) and β j (x) is the basis function, l j (x j ) is the Lagrange interpolation basis function, x k and x j is a time point, the values ​​of k and j are 0, 1, ..., n, y j is time point x j The value of the Hermitian polynomial corresponding to m j is x j The derivative value corresponding to the point; that is, H(x j )=y j ,H'(x j )=m j ,(j=0,1,…,n);

[0105] The interpolation remainder R(x) can be expressed as formula (3):

[0106]

[0107] Among them, f (2n+2) represents the (2n+2)th order derivative of the function f, ξ is in [x0,x n ] a point in the interval;

[0108] Afterwards, the first state data after interpolation is recorded as α1, α2, ..., and the second state data after interpolation is recorded as β1, β2, .... The two sets of state data completely correspond in time. They are horizontally spliced ​​according to the timestamp to form a new data set [(α1, β1), (α2, β2), ...]. The data in the data set are sequentially input into an array of size 10×2, which is recorded as C. The first C is:

[0109]

[0110] Put these ten spliced ​​data points into the trained LSSVM model for inference calculation and obtain (α' 11 ,β' 11 ), the predicted value (α' 11 ,β' 11 ) and the true value (α 11 ,β 11 ) is compared, if it is less than the threshold, it is judged to be fault-free, if it is greater than the threshold, the aircraft has a fault; it should be noted that when the data is judged to be fault-free at this point, the next inference calculation needs to be (α 11 ,β 11 ) is put into the last row of matrix C and (α1,β1) is removed to make (α' 12 ,β' 12 ) prediction work, and so on; when the point is judged to be faulty, the next reasoning calculation needs to be (α' 11 ,β' 11 ) is put into the last row of matrix C and (α1,β1) is removed to make (α' 12 ,β' 12 ) prediction work, and so on. Figure 7 As shown;

[0111] For the third state data, which is marked as γ1, γ2, ..., there is no need to perform protocol data fusion processing as described above. The data can be directly spliced ​​into a matrix of size 10×1, and the same as above, ten points are used to splice into an array (γ1, γ2, ..., γ 10 ) to predict the next point γ' 11 Fault situation; when the predicted value γ' 11 and the true value γ 11When the difference is greater than the set threshold, the data at this point is judged to be faulty and γ' 11 Spliced ​​to the previous nine points γ2,γ3,…,γ 10 Finally, the array (γ2,γ3,…,γ 10 ,γ' 11 ) to the twelfth point γ' 12 prediction, and so on; when the predicted value γ' 11 and the true value γ 11 When the difference is less than the set threshold, it is judged that there is no fault at this point, and γ 11 Spliced ​​to the previous nine points γ2,γ3,…,γ 10 Finally, the array (γ2,γ3,…,γ 10 ,γ 11 ) to the twelfth point γ' 12 prediction, and so on; the process is as follows Figure 7 As shown;

[0112] Finally, the obtained raw data and fault handling results are stored in the SD card for easy reading.

[0113] Embodiment 1:

[0114] Multi-bus compatible aircraft online anomaly detection system, including:

[0115] The first monitoring module: used to monitor the data of the communication board transmission line;

[0116] The first monitoring module is a 1553B monitoring module, which includes a dual transceiver. All output and input pins of the dual transceiver are connected to the core board module and are used to monitor the data of the communication board transmission line; it complies with the MIL-STD-1553B standard and supports multiple interfaces such as synchronous or asynchronous parallel bus, serial port and SPI interface;

[0117] The 1553B monitoring module includes a low-power CMOS dual transceiver and two transformers. The transformer adopts a PM-DB2725EX transformer, and the dual transceiver is a HI-1573 chip. The output ends of the two transformers are connected to the input ends of the HI-1573 chip, and the output end of the HI-1573 chip is connected to the core board module. The transformer is used to step down the received 1553B signal and convert it into a signal with a suitable voltage value that can be subsequently input into the HI-1573 chip so that it can be received by the HI-1573 chip. The turns ratio between the 1-3 pins and the 2-8 pins of the first transformer and the second transformer is 1:2.5, and the turns ratio between the 1-3 pins and the 5-7 pins is 1:1.79, that is, the transformer has two transformation ratios of 1:2.5 and 1:1.79, which are used to convert the signal RT_BUS_A- The voltage of RT_BUS_A+ is reduced to RT_A- and RT_A+; in the actual transmission test process, the peak-to-peak value of the differential signal on the transmission line is between 12 and 15Vp-p, which exceeds the maximum peak-to-peak value (9Vp-p) of the input differential signal that the HI-1573CMOS dual transceiver can receive. Therefore, the signal needs to be reduced in voltage before being connected to HI-1573; in order to achieve this goal, a transformer model PM-DB2725EX is used for voltage reduction, and RT_BUS_A+, RT_BUS_A-, RT_BUS_B+, and RT_BUS_B- are converted into RT_A+, RT_A-, RT_B+, and RT_B-. The peak-to-peak value of the signal is converted from 12 to 15Vp-p to 6.70 to 8.38Vp-p, which is within the range that the HI-1573 chip can receive;

[0118] During the connection, leave pins 4, 6, and 8 floating, pins 5 and 7 connected to the 1553B bus differential signal pair RT_BUS_A+ (RT_BUS_B+) and RT_BUS_A- (RT_BUS_B-), respectively, and pins 1 and 3 connected to the signals RT_A+ (RT_B+) and RT_A- (RT_B-) converted by the transformer, respectively. The converted signals are connected to HI-1573 for subsequent processing;

[0119] The HI-1573 chip meets the specification requirements of MIL-STD-1553. The transmitter part of each bus obtains complementary CMOS / TTL Manchester II bi-phase data and converts it into a differential voltage suitable for driving the bus isolation transformer. At the same time, the receiver part of each bus converts the bi-phase differential data of the 1553 bus into complementary CMOS / TTL data suitable for input to the Manchester decoder.

[0120] In the connection, the RT_A+, RT_B+, RT_A- and RT_B- obtained by the transformer are connected to the BUSA end (pin 2), BUSB end (pin 7) of the HI-1573 chip. Terminal (3 pins), The monitored bus signal after voltage reduction is processed by the HI-1573 chip and the differential output is sent to the RXA terminal (17 pin) and end (16 pins), RXB end (12 pins) and The TXA terminal (pin 19) is connected to the FPGA core board for subsequent decoding processing; at the same time, the TXA terminal (pin 19) and TXB (20 pins), TXB (14 pins) and The pin (15) is also connected to the PG2L100H chip; VDDA (1) and VDDB (6) are connected to the 3.3V voltage output by the power conversion module. The RXENA (4) and RXENB (9) are enable terminals. When they are low, the output ports RXA, RXB and When the TXINHA pin (18 pin) and TXINHB pin (13 pin) are low level, they are also enable pins. When they are high, data transmission to the bus is blocked. All the above enable pins are connected to the PG2L100H chip for assignment configuration. All other pins of the chip are grounded.

[0121] For example, if the monitoring channel selects channel B, the differential signals RT_BUS_B+ and RT_BUS_B- from the bus are first transformed by the PM-DB2725EX transformer to generate differential signals RT_B+ and RT_B-, which meet the input peak-to-peak conditions of the HI-1573 chip; after supplying 3.3V voltage to the HI-1573 chip, the enable is assigned through the chip PG2L100H, the RXENA end is assigned a low level to block, and the RXENB is assigned a high level to ensure the smooth conversion. At the same time, TXINHB and TXINHA are assigned a high level to block; the above input differential signals are transmitted through the HI-1573 through the RXB end and The two ends are converted into complementary CMOS / TTL data signals F_RT_RXB+ and F_RT_RXB- suitable for input to the Manchester decoder, and the differential signal pair is directly connected to the FPGA core board for subsequent decoding operation and storage processing.

[0122] The second monitoring module: used to monitor the data of the bus transmission line;

[0123] The second monitoring module is an RS485 monitoring module. The RS485 module mainly includes a four-channel integrated circuit with dual drivers and receivers. The differential signal receiving end of any channel is connected to the differential signal transmitting end. The four-channel integrated circuit is connected to the core board module and is used to monitor the data of the bus transmission line.

[0124] The RS485 monitoring module includes four chips of model SN65C1167ENSR, each of which contains two pairs of differential input channels. The SN65C1167ENSR chip is the core of the RS485 monitoring module. Its main function is to convert the received RS485 clock and data into single-ended signals. The common-mode input voltage range of the SN65C1167ENSR chip is -7V to +7V. When the transmission enable DE is high, the data D is converted to Y and Z and sent out. When the enable DE is low, the channel is blocked; similarly, when the receiving data enable is low, the received data A and B are converted into single-ended output R; because the receiver input sensitivity is ±200mV, when the signal voltage difference received by the receiving end is less than 200mV, the output will be unstable;

[0125] In the connection, the VCC terminal (pin 16) of the SN65C1167ENSR chip is connected to the 5.0V voltage generated by the voltage conversion module, the GND terminal (pin 8) is grounded, and the differential signal receiving end of the path is directly connected to the differential signal sending end. The specific connection method is: the 1A terminal (pin 2) is connected to the 1Y terminal (pin 14), the 1B terminal (pin 1) is connected to the 1Z terminal (pin 13), the 2A terminal (pin 6) is connected to the 2Y terminal (pin 11), and the 2B terminal (pin 7) is connected to the 2Z terminal (pin 11); a 120-ohm resistor is connected between the same pair of differential signals to solve the RS485 level mismatch. The communication failure caused by the single-ended output 1R (pin 3) and the single-ended output 2R (pin 5) are first divided by the resistor to obtain 3V and then connected to the FPGA core board for subsequent data decoding operations. The low level of the read enable end is valid, so a 0 ohm resistor is directly connected in series to ground; in addition, if data needs to be sent externally, the PG2L100H chip is required to assign a value to the enable DE end (pin 12) of the SN65C1167ENSR chip, and a high level turns on the enable, and the PG2L100H chip transmits the data to be transmitted to the 1D end (pin 15) or the 2D end (pin 9);

[0126] For example, taking the first channel as an example, the data and clock differential signals RS485_DATA_-1, RS485_DATA_+1, RS485_CLK_-1, RS485_CLK_+1 generated by the HDLC protocol are connected to the 1B end (pin 1), the 1A end (pin 2), the 2A end (pin 6), and the 2B end (pin 7) respectively. At the same time, the DE end (pin 12) is enabled to be blocked at a low level through the PG2L100H assignment, thus ensuring the interference-free monitoring process. The two pairs of differential signals are converted into single-ended signals through the SN65C1167ENSR, and the data single-ended signal RS485_DATA_1 and the clock single-ended signal RS485_CLK_1 are generated at the 1R end (pin 3) and the 2R end (pin 5) respectively. After the above-mentioned step-down process, the two are connected to the FPGA core board pins for subsequent processing.

[0127] Acquisition module: used to convert analog signals into digital signals with high sampling rate and resolution;

[0128] The acquisition module is an AD acquisition module, including an operational amplifier part (four pieces of eight-channel voltage-stabilized operational amplifiers) and an analog-to-digital conversion part (a highly integrated 8-input analog-to-digital converter ADC). The operational amplifier part is connected to the input end of the analog-to-digital conversion part, and the output end of the analog-to-digital conversion part is connected to the core board module through the DOUT pin;

[0129] The operational amplifier part of the AD acquisition module includes four chips of model number AD8552AR, which mainly play the role of signal amplification, filtering processing and impedance matching; the AD8552AR chip has two channels, and the operational amplifier enables this system to achieve high precision, low noise and zero drift, which is suitable for high-precision signal conditioning and amplification scenarios; its functions are as follows: signal amplification, because the signal amplitude output by many sensors and signal sources is small, direct input to the ADC may not achieve effective resolution, so the AD8552AR chip plays the role of amplifying the signal and improving the resolution; the filtering function of the AD8552AR chip needs to be rectified with external capacitors and diode circuits; impedance matching, that is, the operational amplifier chip has a high input impedance, which can prevent the load effect on the signal source and ensure the integrity of the signal output from the signal source, while the low output impedance helps drive the input of the ADC to avoid attenuation;

[0130] In the connection, the output OUTA (pin 1) and OUT B (pin 7) of the op amp are connected to the negative input terminal -INA (pin 2) and -IN B (pin 6). The output signal is the signal processed as above and used for subsequent analog-to-digital conversion; the V+ terminal (pin 8) is connected to the power supply, and the V- terminal (pin 4) is grounded; for the input of the sensor or signal source, it must first be filtered out by the external circuit to remove high-frequency noise and rectified. Here, the external input signal is connected in series with a 49.9 ohm resistor and a 0.1μF capacitor is connected to the bypass and grounded. The purpose of this is to remove high-frequency noise and AC components to achieve a stable effect. After that, four 1N4148 diode +66 bridge rectifier circuits are connected to further filter out the AC components; the input differential signals ADCIN1+ and ADCIN1- after conditioning and filtering are connected to the +INA terminal (pin 3) and +IN B terminal (pin 5) of the AD8552 chip respectively;

[0131] The analog-to-digital conversion part of the AD acquisition module includes an analog-to-digital conversion chip. The analog-to-digital conversion chip uses a highly integrated AD7856ARZ model chip. It is a high-speed, low-power 14-bit ADC powered by a single 5V power supply; it has eight single-ended or four pseudo-differential inputs, uses self-calibration and system calibration with automatic calibration, and has a flexible serial interface that automatically powers off after conversion; the chip The BUSY terminal (pin 2) is a logic input terminal. After the conversion starts, the transition from low to high on this input will maintain a certain pattern for conversion. When the conversion starts, the BUSY terminal (pin 2) is The falling edge or The rising edge triggers the high level and keeps the high level until the conversion is completed. A logic 0 at the REF pin (pin 3) starts sleep mode and all circuits are powered off, including the internal reference voltage. A logic 1 allows normal operation. IN / REF OUT The 4-pin terminal is the reference source for analog-to-digital conversion. REF1 and C REF2 The pins 7 and 8 are reference capacitors, and pins 9-16 are analog inputs, i.e. the output signals after the op amp processing. The terminal (pin 17) is the automatic calibration terminal with an internal pull-up current of 0.15μA. The DOUT terminal (pin 20) outputs the converted 16-bit serial data. The DIN terminal (pin 21) is used to receive the data written to the AD7856ARZ configuration register to configure the ADC's working modulus and operating parameters. The CLKIN terminal (pin 22) is the main clock input terminal, and the SCLK terminal (pin 23) is the serial port clock.

[0132] In connection, end, BUSY end, The DIN, SCLK and DIN terminals are connected to the FPGA core board for configuration; pins 9-16 are connected in sequence to the analog signals processed by the op amp; The terminal is directly connected to an analog voltage source to ensure that it does not enter a dormant state; The REF terminal is connected to ground through a 0.01μF capacitor to achieve self-calibration at power-on to provide excellent DC accuracy. IN / REF OUT The analog power supply terminal is directly connected to AVDD, and a bypass capacitor is connected to filter out high-frequency interference; the DOUT terminal outputs the converted result and is connected to the PG2L100H chip pin;

[0133] For example, when the AD acquisition channel 1-8 is working, the ADCINx+ and ADCINx- terminals are processed by the op amp to obtain the VOPx and VONx signals as pseudo differential pairs to input AD7856ARZ for analog-to-digital conversion. The inputs are connected to the AIN1-AIN8 terminals respectively. After the power supply is completed, the PG2L100H chip will BUSY is set to high level, Assign low level, configure the conversion mode through DIN terminal and provide SCLK master clock, the conversion result is transmitted to PG2L100H chip through DOUT terminal to complete monitoring. (Note: x value is 1-8).

[0134] Core board module: responsible for running the logic program to decode the monitored data and deploy subsequent fault prediction algorithms;

[0135] Core board module: The core board is connected to the CPU through the JTAG terminal. The CPU uses the PDS development software of Unigroup Tongchuang to burn the logic program to the PG2L100H chip of the core board through the connector. The host computer can be a display with a user interface program. The host computer is connected to the CPU and configures the system parameters through the host computer program. The core board module is connected to the storage module (SD card);

[0136] The core board module is the core of the whole system. It adopts the domestic PANGO series Logos2 FPGA core board produced by Ziguang Tongchuang. For the RS485 bus data transmitted above, protocol judgment and decoding processing must be performed first. Different protocols will use different decoding methods later.

[0137] The types of RS485 bus data communication protocols considered in this patent include Modbus RTU protocol, Profibus DP protocol, DMX512 protocol and HDLC protocol; among them, Modbus RTU protocol is used for real-time status monitoring of parameters of some non-critical equipment in the flight state of the aircraft, such as the temperature and pressure inside the aircraft, etc. It is simple, mature and highly compatible, and is easy to deploy in the aircraft monitoring system in the flight state. The Modbus RTU protocol contains a 1-byte address, a 1-byte function code, 0-252 bytes of data and a CRC16-bit cyclic redundancy check in sequence; the Profibus DP protocol is suitable for real-time status monitoring and processing of various key components such as the braking system, power system and flight control system of the aircraft in the flight state, and it has high reliability and real-time performance. The Profibbus DP protocol frame contains a start delimiter SD, a 1- or 2-byte length field LE, a 1-byte address field DA (indicating the target address) and a 1-byte SA (indicating the source address), a 1-byte control field (FC), a byte variable data field (Data), and a 1- or 2-byte frame check sequence (FCS); the DMX512 protocol is mainly used for status monitoring of the lighting system of an aircraft in flight. Its frame structure is relatively special. It does not have a separate length field. Instead, the length of the entire frame is determined by the fixed start code and the length of the data field. It contains a Break signal (a low-level signal of more than 88μs, indicating the beginning of the frame), a MarkAfter Break signal (a high-level signal of 8μs), and a 1-byte start code Start. Code and a data field of up to 512 bytes; the HDLC protocol with a wider range of applications is used to monitor the status of key components such as the power system, flight control system, and hydraulic device of the aircraft in flight. The reliable data link makes it highly resistant to interference and has the characteristics of real-time performance. The HDLC protocol layer contains a 1-byte flag field (Flag), a 1-byte or more address field, a 1-byte or 2-byte control field, a variable-length data field, a 2-byte or 4-byte frame check sequence, and a 1-byte end frame; the applicable conditions under the flight state corresponding to the four protocols are improved;

[0138] For RS485 bus data under various protocol transmission modes, an adaptive protocol identification algorithm is designed. After identifying different protocol types, the subsequent decoding process is carried out separately, and the obtained data is time-aligned and spliced ​​and input into the LSSVM model for joint status monitoring, including the following steps:

[0139] The first byte of the Modbus RTU protocol data string is the address. When the value is 0, it means that the broadcast communication method is adopted. When the value is 1-247, it represents a specific slave address device. The common values ​​of the 1-byte function code following it are shown in Table 1 below;

[0140] Table 1 ModbusRTU protocol function codes and functions

[0141]

[0142]

[0143] The HDLC protocol has fixed start and end flags, namely 0×7E, so the HDLC protocol judgment based on this feature is highly accurate.

[0144] The different start delimiters (first byte) of the Profibus DP protocol can be distinguished into four different communication modes. The values ​​and meanings are shown in Table 2 below. The transmission protocol and communication mode used in the transmission process are determined according to the start delimiter, tail frame and frame structure of different communication modes.

[0145] Table 2 Characteristics of the four transmission modes of the Profibus DP protocol

[0146]

[0147] Therefore, combining the characteristics of the four protocols, the adaptive protocol processing design is as follows Figure 7 As shown;

[0148] Among them, the interpretation of the DMX512 protocol is relatively easy. It only needs to detect whether the received bus voltage signal contains a low level (Break) lasting at least 88μs and followed by a high level (MAB) lasting at least 8μs. This method can be used to determine whether the DMX512 protocol is adopted.

[0149] The interpretation of the protocol first requires converting the bus voltage signal received by the link layer into a bit stream signal, specifically using the Non-Return-to-Zero Inverted (NRZI) encoding method. NRZI encoding triggers a signal level change through a bit "1", while a bit "0" keeps the level unchanged. This encoding method can avoid a long-term fixed level and help maintain clock synchronization.

[0150] Then, the start frame and end frame of the converted bit stream signal are judged. If both are 0×7E, it can be judged that the HDLC protocol is used for 485 communication. If only the start frame is 0×7E and the end frame is not 0×7E, it is judged that the Modbus RTU unicast mode is used to communicate with the device with the address 126 (0×7E); (For the 485 communication protocol, the judgment should be made from the signal level change: the actual RS485 HDLC decoding uses the non-return-to-zero encoding method to convert the received link layer bus signal level into the form of a bit stream, and then perform subsequent frame judgment, and then directly read the bit stream data, and no longer perform direct level judgment);

[0151] As described in Table 2 above, for the four Profibus DP protocol transmission modes, when the starting frame of the encoded bit stream signal is 0×10, the SD1 communication mode of the Profibus DP protocol may be used, or the Modbus RTU protocol may be used to transmit data to the device with address 16 (0×10) in a single end, which requires further judgment later; since the SD1 mode of the Profibus DP protocol is a short frame transmission mode, its frame length is significantly shorter than that of the Modbus RTU protocol, only 5-6 bytes, so when the frame length is 5-6 bytes, it is judged that the protocol used at this time is Profibus DP and the communication mode used is SD1; if the frame length is longer, it is judged that the Modbus RTU protocol is used to transmit data to the device with address 16;

[0152] As described in Table 2 above, for the four Profibus DP protocol transmission modes, when the start frames are 0×2A, 0×68, and 0×DC respectively, if the end frame is fixed to 0×16, it can be judged that the three transmission modes SD2, SD3, and SD4 of the Profibus DP protocol are adopted respectively. Otherwise, it is judged that the Modbus RTU protocol is used for unicast transmission to the devices with addresses 42 (0×2A), 104 (0×68), and 220 (0×DC) respectively.

[0153] If the start frame is 0×00, it can be determined that the broadcast transmission mode of the Modbus RTU protocol is used. When the start frame is not the above-mentioned situation, it can be determined that the Modbus RTU protocol is used for unicast transmission to the device with address X (Note: X is the number of frames not mentioned above);

[0154] After the protocol determination is completed, the bus data under different protocols are imported into the corresponding decoding module for decoding. The obtained RS485 bus data is called the first state data, the 1553B bus data is called the second state data, and the data obtained by AD sampling is the third state data;

[0155] Description of the relationship between protocol analysis and LSSVM: The design at that time was to first perform protocol determination, followed by protocol analysis. Analysis is similar to a redundancy removal process, extracting key data information from the channel signal, and the result of the analysis is the obtained bus data; RS485-first state data; 1553B-second state data; AD acquisition-third state data, and then the first and second state data are aligned and spliced. After processing, the formed data group is injected into the subsequent LSSVM for fault prediction, and the third state data is also injected into the LSSVM separately; this is the process between protocol analysis and LSSVM;

[0156] The decoded data needs to be further processed to facilitate the subsequent splicing process; for the first state data and the second state data, first of all, it should be ensured that the two have consistent timestamps. Here, the small window + linear interpolation method is used for processing; this patent uses a 0.1s time window for time alignment processing, and Hermite interpolation is performed on the missing time points corresponding to the two protocols contained in the small window to fill in the time. The principle of Hermite interpolation is as follows: Let the interpolation function be H, then H(x i )=y i ,H'(x i )=y i '(x),(i=0,1,…,n); There are 2n+2 conditions here, which can uniquely determine a polynomial with a degree not exceeding 2n+1, as shown in formula (1):

[0157] H 2n+1 (x) = a0+a1x+…+a 2n+1 x 2n+1 (1)

[0158] According to the solution method of Lagrange interpolation polynomial, the function value and the first-order derivative value at the interpolation node are used as the polynomial coefficients, and the zero point and sampling delta properties are used to solve the appropriate basis function; denoted by m i =y i '(x), then the Lagrange polynomial of H can be expressed as formula (2):

[0159]

[0160] The interpolation remainder can be expressed as formula (3):

[0161]

[0162] Afterwards, the first state data after interpolation is recorded as α1, α2, ..., and the second state data after interpolation is recorded as β1, β2, .... The two sets of state data completely correspond in time. They are horizontally spliced ​​according to the timestamp to form a new data set [(α1, β1), (α2, β2), ...]. The data in the data set are sequentially input into an array of size 10×2, which is recorded as C. The first C is:

[0163]

[0164] Put these ten spliced ​​data points into the trained LSSVM (least squares support vector machine) model for inference calculation, and get (α' 11 ,β' 11 ), the predicted value (α' 11 ,β' 11 ) and the true value (α 11 ,β 11 ) is compared, if it is less than the threshold, it is judged to be fault-free, if it is greater than the threshold, the aircraft has a fault; it should be noted that when the data is judged to be fault-free at this point, the next inference calculation needs to be (α 11 ,β 11 ) is put into the last row of matrix C and (α1,β1) is removed to make (α' 12 ,β' 12 ) prediction work, and so on; when the point is judged to be faulty, the next reasoning calculation needs to be (α' 11 ,β' 11 ) is put into the last row of matrix C and (α1,β1) is removed to make (α' 12 ,β' 12 ) prediction work, and so on. Figure 8 As shown;

[0165] For the third state data, which is marked as γ1, γ2, ..., there is no need to perform protocol data fusion processing as described above. The data can be directly spliced ​​into a matrix of size 10×1, and the same as above, ten points are used to splice into an array (γ1, γ2, ..., γ 10 ) to predict the next point γ' 11 Fault situation; when the predicted value γ' 11 and the true value γ 11 When the difference is greater than the set threshold, the data at this point is judged to be faulty and γ' 11 Spliced ​​to the previous nine points γ2,γ3,…,γ 10 Finally, the array (γ2,γ3,…,γ 10 ,γ' 11 ) to the twelfth point γ' 12prediction, and so on; when the predicted value γ' 11 and the true value γ 11 When the difference is less than the set threshold, it is judged that there is no fault at this point, and γ 11 Spliced ​​to the previous nine points γ2,γ3,…,γ 10 Finally, the array (γ2,γ3,…,γ 10 ,γ 11 ) to the twelfth point γ' 12 prediction, and so on; the process is as follows Figure 8 As shown;

[0166] Finally, the obtained raw data and fault handling results are stored in the SD card for easy reading.

[0167] Voltage conversion module: converts the voltage supplied by the power supply and outputs the required voltage for use by other modules;

[0168] Voltage conversion module: The power supply is connected to the 1553B monitoring module, RS485 monitoring module, AD acquisition module, and core board module through the voltage conversion module and supplies power. The voltage conversion module converts the 27V voltage supplied by the power supply into 5V, and then converts the 5V voltage into 3.3V for use by other modules; this DC-DC voltage conversion module uses components such as inductors and capacitors to transform and filter the input DC voltage, and finally outputs the required voltage;

[0169] The voltage conversion module converts the voltage provided by the external power supply into a voltage suitable for other modules to complete the energy supply operation, including a voltage conversion chip and a low-dropout voltage regulator. The power supply is connected to the core board module, the second monitoring module, and the acquisition module through the voltage conversion chip. The power supply is connected to the SD card of the first monitoring module through the voltage conversion chip and the low-dropout voltage regulator in sequence;

[0170] The voltage conversion chip adopts the model VRB_S-10WR3 voltage conversion chip to convert 27V voltage into 5V voltage. The output power of this series of chips is 10W, the efficiency is as high as 88%, and it has the functions of undervoltage protection, output short circuit, and overcurrent protection. The operating temperature range is -40℃—+85℃; the chip Vin pin (pin 2) is connected to the positive end 27V of the external power supply, the chip GND pin (pin 1) is connected to the negative end of the external power supply, and a 47μF capacitor is connected between the positive and negative inputs to ensure stability. The -VO pin (pin 7) is grounded, and the +VO pin (pin 6) is connected to the output 5V voltage. The generated 5V voltage end needs to be connected to the ground through a 22μF capacitor to filter out the high-frequency noise in the power supply;

[0171] The low-dropout voltage regulator uses the TPS73801-SEP low-dropout voltage regulator to convert the voltage from 5V to 3.3V. The chip can increase the output current of 1A (voltage drop of 300mV) and the working quiescent current is 1mA. Compared with many other regulators, the quiescent current is better controlled and has lower output noise; the output 3.3V voltage and the connected resistance meet the following formula:

[0172] V OUT =V FB ×(1+R 48 / R 49 )(V FB =1.21V) (4)

[0173] R 48 =(V OUT / V FB -1)×R 49 (5)

[0174] In order to obtain an output voltage of 3.3V, R 48 =3.5kΩ, R 49 =2kΩ, according to formula 4, we can calculate V OUT =V FB ×(1+R 48 / R 49 )=3.3275kΩ, which is close to the required 3.3V;

[0175] The storage module includes a Micro SD connector (Micro_SuD_Connector) and a Micro SD card. The SD card is connected to the core board module through the connector. The Micro SD connector is an interface element used to connect a Micro SD card (also known as a TF card or MicroSecure Digital card). Micro SD cards are widely used in storage devices such as smartphones, tablets, cameras, and embedded systems. They are very small and suitable for systems with limited space. The main function of the connector is to provide stable electrical connections and physical support.

[0176] Micro_SD_Connector contains 13 pins. The PG2L100H chip communicates with the Micro SD card by connecting the DAT0 terminal (pin 7), DAT1 terminal (pin 8), DAT2 terminal (pin 1) and CD / DAT3 (pin 3). It issues commands and provides clocks by connecting the CMD terminal (pin 3) and the CLK terminal (pin 5). The DET terminal (pin 9) is used to monitor whether the Micro SD card is mounted in the connector. The power supply voltage of the connector is 3.3V and is connected to the VDD terminal (pin 4). Pins 10-13 are directly grounded.

[0177] The present invention can be used for status monitoring and data processing of satellites or drones;

[0178] Protocol processing part:

[0179] Protocol Adaptation: This patent comprehensively interprets the four protocols and multiple working modes of the RS485 bus, and flexibly selects the monitoring decoding method according to the different protocols of the bus, which greatly improves the flexibility and autonomy of the system;

[0180] Protocol adaptive result fusion: When faced with timing data obtained from multiple different protocols, this patent uses Hermite interpolation to align the data and uses the timestamp method to splice the data, which are then sent to the fault diagnosis module for processing. The advantage of this is that it overcomes the defect that "some faults may not be obvious in the data of a certain protocol". The results of fault diagnosis will combine the monitoring / collection data of different protocols for diagnosis, which is more comprehensive and reliable.

[0181] It should be noted that in the above embodiments, as long as the technical solutions are not contradictory, they can be arranged and combined, and those skilled in the art can exhaust all possibilities based on the mathematical knowledge of arrangement and combination. Therefore, the present invention will no longer describe the technical solutions after arrangement and combination one by one, but it should be understood that the technical solutions after arrangement and combination have been disclosed by the present invention.

[0182] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A multi-bus compatible aircraft online anomaly detection system, characterized by: include: The first monitoring module: used to monitor the data of the communication board transmission line; The second monitoring module: used to monitor the data of the bus transmission line; Acquisition module: used to convert analog signals into digital signals; Core board module: responsible for running the logic program to decode the monitored data and deploy subsequent fault prediction algorithms; Voltage conversion module: converts the voltage supplied by the power supply and outputs the required voltage for use by other modules.

2. The multi-bus compatible aircraft online anomaly detection system according to claim 1, characterized in that: The first monitoring module is a 1553B monitoring module, including a dual transceiver, and the dual transceiver is connected to the core board module; The second monitoring module is an RS485 monitoring module, including a four-channel integrated circuit, the four-channel integrated circuit has a dual driver and a receiver, the differential signal receiving end of each channel is connected to the transmitting end, and the four-channel integrated circuit is connected to the core board module; The acquisition module is an AD acquisition module, including an operational amplifier part and an analog-to-digital conversion part, the operational amplifier part is connected to the analog-to-digital conversion part, and the analog-to-digital conversion part is connected to the core board module; Core board module: The core board is connected to the CPU, the logic program is burned into the core board, and the system parameters are configured through the host computer program; Voltage conversion module: The voltage conversion module converts the 27V voltage of the power supply into 5V, and then converts the 5V voltage into 3.3V for use by other modules.

3. The multi-bus compatible aircraft online anomaly detection system according to claim 1 or 2, characterized in that: The 1553B monitoring module includes dual transceivers and two transformers. The transformer uses PM-DB2725EX transformer, and the dual transceiver is HI-1573 chip; the two transformers are connected to the HI-1573 chip, and the HI-1573 chip is connected to the core board module; the transformer is used to step down the received 1553B signal so that it can be received by the HI-1573 chip.

4. The multi-bus compatible aircraft online anomaly detection system according to claim 1 or 2, characterized in that: The RS485 monitoring module includes four chips of model SN65C1167ENSR, which convert the received RS485 clock and data into single-ended signals.

5. The multi-bus compatible aircraft online anomaly detection system according to claim 4, characterized in that: The operational amplifier part of the AD acquisition module includes four chips of model AD8552AR; the analog-to-digital conversion part of the AD acquisition module includes an analog-to-digital conversion chip, and the analog-to-digital conversion chip adopts a highly integrated chip of model AD7856ARZ.

6. The multi-bus compatible aircraft online anomaly detection system according to claim 5, characterized in that: The core board module adopts Logos2 FPGA core board for the RS485 bus data transmitted above.

7. The multi-bus compatible aircraft online anomaly detection system according to claim 6, characterized in that: The voltage conversion module includes a voltage conversion chip and a low-voltage dropout regulator. The power supply is connected to the core board module, the second monitoring module, and the acquisition module through the voltage conversion chip. The power supply is connected to the SD card of the first monitoring module through the voltage conversion chip and the low-voltage dropout regulator in sequence. The voltage conversion chip uses a voltage conversion chip of model VRB_S-10WR3, and the low-dropout voltage regulator uses a low-dropout voltage regulator of model TPS73801-SEP.

8. The multi-bus compatible aircraft online anomaly detection system according to claim 7, characterized in that: The storage module includes a connector and an SD card, and the SD card is connected to the core board module through the connector.

9. The multi-bus compatible aircraft online anomaly detection system according to claim 8, characterized in that: The first byte of the ModbusRTU protocol data string is the address. When the value is 0, it means that the broadcast communication method is adopted. When the value is 1-247, it represents a specific slave address device; The HDLC protocol has fixed start and end flags, namely 0×7E, so the HDLC protocol judgment based on this feature is highly accurate. The different start delimiters of the Profibus DP protocol can be divided into four different communication modes. The transmission protocol and communication mode used in the transmission process are determined according to the start delimiter, tail frame and frame structure of different communication modes. The interpretation of the DMX512 protocol requires detecting whether the data contains a low level (Break) lasting at least 88μs and followed by a high level (MAB) lasting at least 8μs; The main method for interpreting the HDLC protocol is to determine its start frame and end frame. If both are 0×7E, it can be determined that the HDLC protocol is used for 485 communication. If only the start frame is 0×7E and the end frame is not 0×7E, it is determined that the Modbus RTU unicast mode is used to communicate with the device with address 126 (0×7E). When the start frame is 0×10, since the SD1 mode of the Profibus DP protocol is a short frame transmission mode, its frame length is significantly shorter than that of the Modbus RTU protocol, only 5-6 bytes. Therefore, when the frame length is 5-6 bytes, it is judged that the protocol used at this time is Profibus DP and the communication mode used is SD1; if the frame length is longer, it is judged that the Modbus RTU protocol is used to transmit data to the device with address 16; When the start frames are 0×2A, 0×68, and 0×DC respectively, if the end frame is fixed to 0×16, it can be judged that the three transmission modes of Profibus DP protocol SD2, SD3, and SD4 are adopted respectively. Otherwise, it is judged that Modbus RTU protocol is adopted to perform unicast transmission to the devices with addresses 42 (0×2A), 104 (0×68), and 220 (0×DC) respectively; If the start frame is 0×00, it can be determined that the broadcast transmission mode of the Modbus RTU protocol is used. When the start frame is not the above-mentioned situation, it can be determined that the Modbus RTU protocol is used for unicast transmission to the device with address X; After the protocol determination is completed, the bus data under different protocols are imported into the corresponding decoding module for decoding. The obtained RS485 bus data is called the first state data, the 1553B bus data is called the second state data, and the data obtained by AD sampling is the third state data; A 0.1s time window is used for time alignment, and the missing time points of the two protocols contained in the small window are filled in by Hermite interpolation. The principle of Hermite interpolation is as follows: Let the interpolation function be H, then H(x i )=y i ,H'(x i )=y i '(x),(i=0,1,…,n); There are 2n+2 conditions here, which uniquely determine a polynomial with a degree not exceeding 2n+1, as shown in formula (1): H 2n+1 (x)=a0+a1x+…+a 2n+1 x 2n+1 (1) According to the solution method of Lagrange interpolation polynomial, the function value and the first-order derivative value at the interpolation node are used as the polynomial coefficients, and the zero point and sampling delta properties are used to solve the appropriate basis function; denoted by m i =y i '(x), then the Lagrange polynomial of H can be expressed as formula (2): The interpolation remainder R(x) can be expressed as formula (3): The first state data after interpolation is recorded as α1, α2, ..., and the second state data after interpolation is recorded as β1, β2, .... The two sets of state data are completely corresponding in time. They are horizontally spliced ​​according to the timestamp to form a new data set [(α1, β1), (α2, β2), ...]. The data in the data set are sequentially input into an array of size 10×2, which is recorded as C. The first C is: Put these ten spliced ​​data points into the trained LSSVM model for inference calculation and obtain (α1'1, β1'1). Compare the predicted value (α1'1, β1'1) with the true value (α 11 ,β 11 ) is compared, if it is less than the threshold, it is judged to be fault-free, if it is greater than the threshold, the aircraft has a fault; it should be noted that when the data is judged to be fault-free at this point, the next inference calculation needs to be (α 11 ,β 11 ) is put into the last row of matrix C and (α1, β1) is removed to perform the prediction work of (α1'2, β1'2), and so on; when the point is judged to be faulty, the next reasoning calculation needs to put (α1'1, β1'1) into the last row of matrix C and (α1, β1) is removed to perform the prediction work of (α1'2, β1'2); For the third state data, which is marked as γ1, γ2, ..., there is no need to perform protocol data fusion processing as described above. The data can be directly spliced ​​into a matrix of size 10×1, and the same as above, ten points are used to splice into an array (γ1, γ2, ..., γ 10 ) to predict the failure of the next point γ1'1; when the predicted value γ1'1 is equal to the true value γ 11 When the difference is greater than the set threshold, the data of this point is judged to be faulty, and γ1'1 is spliced ​​to the previous nine points γ2, γ3, ..., γ 10 Finally, the array (γ2,γ3,…,γ 10 ,γ1'1) predicts the twelfth point γ1'2, and so on; when the predicted value γ1'1 is equal to the true value γ 11 When the difference is less than the set threshold, it is judged that there is no fault at this point, and γ 11 Spliced ​​to the previous nine points γ2,γ3,…,γ 10 Finally, the array (γ2,γ3,…,γ 10 ,γ 11 ) predicts the twelfth point γ1'2; The obtained raw data and fault handling results are stored in the SD card.

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