Semiconductor package with memory devices stacked in steps

Abstract

The invention relates to a semiconductor package with memory devices stacked in steps. A semiconductor package includes: a substrate having bonding fingers; a main memory chip mounted on the substrate; and a slave memory chip stacked over the master memory chip. The main memory chip includes: a main external pad and a main internal pad disposed adjacent to a first side edge of the main memory chip; and a main power pad disposed adjacent to the second side edge of the main memory chip. The slave memory chip includes: a slave external pad and a slave internal pad disposed adjacent to a first side edge of the slave memory chip; and a slave power pad disposed adjacent to the second side edge of the slave memory chip. A portion of the bonding finger is electrically connected to the main external pad through an external bonding wire. The master internal pads are electrically connected to the slave internal pads through the internal bonding wires, respectively, and the slave external pads are floated.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2023-0086942, filed on Jul. 5, 2023, which is hereby incorporated by reference in its entirety. Technical Field

[0003] An embodiment of the present disclosure relates to a semiconductor package including memory chips stacked in a stair shape, the memory chips including pads and bonding wires separately disposed according to functions and channels. Background Art

[0004] A semiconductor package including a plurality of memory chips stacked in a stair shape for high capacity and high-speed operation is proposed. Summary of the invention

[0005] Embodiments of the present disclosure provide a semiconductor package including a plurality of memory chips stacked in a three-dimensional (3D) offset.

[0006] An embodiment of the present disclosure provides a semiconductor package including a plurality of memory chips stacked in a 3D offset using bonding wires.

[0007] Embodiments of the present disclosure provide a semiconductor package including a plurality of memory chips stacked in a 3D offset, the plurality of memory chips having pads and bonding wires separately disposed according to functions.

[0008] According to one embodiment of the present disclosure, a semiconductor package includes: a substrate having a plurality of bond fingers; a main memory chip mounted on the substrate; and a slave memory chip stacked above the main memory chip. The main memory chip includes: a main external pad and a main internal pad disposed adjacent to a first side edge of the main memory chip; and a main power pad disposed adjacent to a second side edge of the main memory chip. The slave memory chip includes: a slave external pad and a slave internal pad disposed adjacent to a first side edge of the slave memory chip; and a slave power pad disposed adjacent to a second side edge of the slave memory chip. A portion of the bond fingers is electrically connected to the main external pads through external bonding wiring, and the main internal pads are electrically connected to the slave internal pads through internal bonding wiring, respectively, and the slave external pads are floated.

[0009] According to one embodiment of the present disclosure, a semiconductor package includes: a substrate including a signal bonding finger disposed adjacent to a first side and a first power bonding finger and a second power bonding finger disposed adjacent to a second side; a main memory chip stacked above the substrate; and a lower slave memory chip stacked above the main memory chip. The main memory chip includes: a main external pad; a main internal pad; and a main power pad electrically connected to the first power bonding finger. The lower slave memory chip includes: a lower slave external pad; a lower slave internal pad; and a lower slave power pad electrically connected to the second power bonding finger. The signal bonding fingers are electrically connected to the main external pads, respectively, through external bonding wiring. The main internal pads are electrically connected to the lower slave internal pads, respectively, through lower internal bonding wiring. The main external pads and the lower slave external pads are not connected through bonding wiring.

[0010] According to one embodiment of the present disclosure, a semiconductor package includes: a substrate having a signal bonding finger, a main power bonding finger, and a slave power bonding finger; a main memory chip mounted on the substrate and including a main external pad, a main internal pad, and a main power pad; a slave memory chip stacked above the main memory chip and including a slave external pad, a slave internal pad, and a slave power pad; external bonding wires electrically connecting the signal bonding finger and the main external pad, respectively; internal bonding wires electrically connecting the main internal pad and the slave internal pad, respectively; main power bonding wires electrically connecting the main power bonding finger and the main power pad, respectively; and slave power bonding wires electrically connecting the slave power bonding finger and the slave power pad, respectively. The main external pads are arranged in a column adjacent to the first side edge of the main chip. The main internal pads are arranged in a column adjacent to the main external pads. The slave external pads are arranged in a column adjacent to the first side edge of the slave chip. The slave internal pads are arranged in a column adjacent to the slave external pads. The slave external pads of the slave memory chip are floated. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1A is a schematic block diagram illustrating an electronic system according to one embodiment of the present disclosure.

[0012] Figure 1B is a schematic block diagram illustrating a semiconductor package according to one embodiment of the present disclosure.

[0013] Figure 2A is a top view illustrating a main memory chip according to one embodiment of the present disclosure.

[0014] Figure 2B is a top view illustrating a lower slave memory chip according to one embodiment of the present disclosure.

[0015] Figure 2C is a top view illustrating an intermediate slave memory chip according to one embodiment of the present disclosure.

[0016] Figure 2D is a top view illustrating a memory chip from above according to one embodiment of the present disclosure.

[0017] Figure 3A is a top view of a semiconductor package according to one embodiment of the present disclosure, and Figure 3B It is along Figure 3A The side view is obtained by line I-I', and Figure 3C It is along Figure 3A A side view taken along line II-II'.

[0018] Figure 4A and Figure 4B is a view illustrating the arrangement of internal circuit blocks and internal electrical signal paths of a main memory chip according to one embodiment of the present disclosure.

[0019] Figure 5A and Figure 5B is a view illustrating the arrangement of internal circuit blocks and internal electrical signal paths of a slave memory chip according to one embodiment of the present disclosure.

[0020] Figure 6 is a top view schematically illustrating a substrate according to one embodiment of the present disclosure.

[0021] Fig. 7A is a top view illustrating a main memory chip according to one embodiment of the present disclosure.

[0022] FIG. 7B to FIG. 7D is a top view illustrating a lower slave memory chip, a middle slave memory chip, and an upper slave memory chip according to an embodiment of the present disclosure.

[0023] Fig. 8A and Figure 8B are top and side views of a semiconductor package according to one embodiment of the present disclosure.

[0024] Fig. 9 is a longitudinal cross-sectional view illustrating a redistribution structure of a memory chip according to one embodiment of the present disclosure. DETAILED DESCRIPTION

[0025] Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. However, the present disclosure may be embodied in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure will be thorough and complete, and the scope of the present disclosure will be fully conveyed to those skilled in the art. Throughout the present disclosure, throughout the various drawings and embodiments of the present disclosure, similar reference numerals refer to similar parts.

[0026] The drawings are not necessarily to scale, and in some instances, the proportions may have been exaggerated in order to clearly illustrate features of the embodiments. When a first layer is referred to as being "on" a second layer or "on" a substrate, this refers not only to the case where the first layer is directly formed on the second layer or substrate, but also to the case where a third layer exists between the first layer and the second layer or substrate.

[0027] Figure 1A is a schematic block diagram illustrating an electronic system 600 according to an embodiment of the present disclosure. Figure 1A , the electronic system 600 may include a host 700 and a memory system 800 .

[0028] The host 700 may include one of a server, a processor, and a computing system. The processor may include at least one of a processing unit such as a central processing unit (CPU), an application processor (AP), and a micro control unit (MCU). The electronic system 600 may further include a bus line BUS electrically connecting the host 700 to the memory system 800. The host 700 and the memory system 800 may communicate with each other through the bus line BUS.

[0029] The memory system 800 may include a memory controller 900 and a memory unit 1000. The memory controller 900 may receive various signals from the host 700 and transmit the signals to the memory unit 1000, and may receive data from the memory unit 1000 and transmit the data to the host 700. The memory unit 1000 may store data. The memory system 800 may further include a first external channel Ech1 and a second external channel Ech2. The first external channel Ech1 and the second external channel Ech2 may electrically connect the memory controller 900 to the memory unit 1000. The memory controller 900 and the memory unit 1000 may communicate with each other through the first external channel Ech1 and the second external channel Ech2. For example, the first external channel Ech1 may transmit a data signal and a data strobe signal. The second external channel Ech2 may transmit an external clock signal, an external chip select signal, an external command signal, and an external address signal. According to one embodiment of the present disclosure, "communication" may be interpreted as meaning that an electrical signal is transmitted from one element to another element and an electrical signal is received from another element. That is, “not in communication” may be interpreted to mean that electric signals are not transmitted to and received from different elements.

[0030] Figure 1B is a schematic block diagram illustrating a memory cell 1000 according to one embodiment of the present disclosure. Figure 1B, the memory unit 1000 may include one master memory chip 100 and a plurality of slave memory chips 200 to 400. Although three slave memory chips 200 to 400 are illustrated in the drawings, the memory unit 1000 may include one or more slave memory chips. For example, the memory unit 1000 may include seven or more slave memory chips.

[0031] The master memory chip 100 may communicate with the memory controller 900 through the first and second external channels Ech1 and Ech2. The master memory chip 100 may communicate with the slave memory chips 200 to 400 through the first and second internal channels Ich1 and Ich2.

[0032] The slave memory chips 200 to 400 may communicate with the memory controller 900 through the first and second internal channels Ich1 and Ich2 , the master memory chip 100 , and the first and second external channels Ech1 and Ech2 .

[0033] The memory unit 1000 may be provided in a module form (eg, package form). The first external channel Ech1 and the first internal channel Ich1 may transmit data signals and data strobe signals. The second external channel Ech2 and the second internal channel Ich2 may transmit clock signals, chip select signals, command signals, address signals, and control signals.

[0034] Figure 2A is a top view illustrating a main memory chip 100 according to one embodiment of the present disclosure. Figure 2A , the main memory chip 100 may include a first main outer pad region 111R, a second main outer pad region 112R, and a first main inner pad region 121R, a second main inner pad region 122R, and a main power pad region 130R.

[0035] The first main external pad area 111R, the second main external pad area 112R, the first main internal pad area 121R, and the second main internal pad area 122R may be arranged adjacent to the first side edge E1 of the main memory chip 100. The first main external pad area 111R, the second main external pad area 112R, the first main internal pad area 121R, and the second main internal pad area 122R may be arranged side by side to form a column. According to one embodiment of the present disclosure, the first main external pad area 111R and the second main external pad area 112R may be arranged side by side to be close to the middle portion of the first side edge E1. The first main internal pad area 121R and the second main internal pad area 122R may be arranged to be separated to be close to the two side portions of the first side edge E1. According to another embodiment of the present disclosure, the first main external pad area 111R and the second main external pad area 112R may be separately arranged on the two side portions, and the first main internal pad area 121R and the second main internal pad area 122R may be arranged in the middle portion. The main power pad region 130R may be disposed adjacent to the second side edge E2 of the main memory chip 100 to form one column. The first side edge E1 and the second side edge E2 may be disposed opposite to each other.

[0036] The first main outer pad 111P may be disposed in the first main outer pad region 111R. The second main outer pad 112P may be disposed in the second main outer pad region 112R. The first main inner pad 121P may be disposed in the first main inner pad region 121R. The second main inner pad 122P may be disposed in the second main inner pad region 122R. The main power pad 130P may be disposed in the main power pad region 130R.

[0037] The first main external pads 111P may be electrically connected to the first external bonding wires 111W, respectively. The first external bonding wires 111W may be electrically connected to the first external channels Ech1, respectively. According to one embodiment of the present disclosure, the first external bonding wires 111W may correspond to portions of the first external channels Ech1, respectively.

[0038] The second main external pads 112P may be electrically connected to the second external bonding wires 112W, respectively. The second external bonding wires 112W may be electrically connected to the second external channels Ech2, respectively. According to one embodiment of the present disclosure, the second external bonding wires 112W may correspond to portions of the second external channels Ech2, respectively.

[0039] The first main internal pads 121P may be electrically connected to the first lower internal bonding wires 121W, respectively. The second main internal pads 122P may be electrically connected to the second lower internal bonding wires 122W, respectively. The main power pads 130P may be electrically connected to the main power bonding wires 130W.

[0040] Figure 2B is a top view illustrating a lower portion of a memory chip according to one embodiment of the present disclosure. Figure 2B , the lower slave memory chip 200 may include a first lower slave external pad region 211R, a second lower slave external pad region 212R, a first lower slave internal pad region 221R, a second lower slave internal pad region 222R, and a lower slave power pad region 230R. The arrangement of the first lower slave external pad region 211R, the second lower slave external pad region 212R, the first lower slave internal pad region 221R, the second lower slave internal pad region 222R, and the lower slave power pad region 230R of the lower slave memory chip 200 may be the same as the arrangement of the first main external pad region 111R, the second main external pad region 112R, the first main internal pad region 121R, the second main internal pad region 122R, and the main power pad region 130R of the main memory chip 100.

[0041] The first lower slave external pad 211P may be disposed in the first lower slave external pad region 211R. The second lower slave external pad 212P may be disposed in the second lower slave external pad region 212R. The first lower slave internal pad 221P may be disposed in the first lower slave internal pad region 221R. The second lower slave internal pad 222P may be disposed in the second lower slave internal pad region 222R. The lower slave power pad 230P may be disposed in the lower slave power pad region 230R. The arrangement of the first lower slave external pad 211P, the second lower slave external pad 212P, the first lower slave internal pad 221P, the second lower slave internal pad 222P and the lower slave power pad 230P of the lower slave memory chip 200 can be the same as the arrangement of the first main external pad 111P, the second main external pad 112P, the first main internal pad 121P, the second main internal pad 122P and the main power pad 130P of the main memory chip 100.

[0042] The first and second lower slave external pads 211P and 212P of the lower slave memory chip 200 may not be connected to the first and second external channels Ech1 and Ech2. Each of the first and second lower slave external pads 211P and 212P of the lower slave memory chip 200 may be floated.

[0043] The first lower slave internal pads 221P may be electrically connected to the first intermediate internal bonding wires 221W, respectively. The first lower slave internal pads 221P of the lower slave memory chip 200 may be electrically connected to the first lower internal bonding wires 121W of the main memory chip 100, respectively. Therefore, the first lower slave internal pads 221P of the lower slave memory chip 200 may be commonly connected to the first lower internal bonding wires 121W of the main memory chip 100 and the first intermediate internal bonding wires 221W of the lower slave memory chip 200.

[0044] The second lower slave internal pads 222P may be electrically connected to the second middle internal bonding wires 222W, respectively. The second lower slave internal pads 222P of the lower slave memory chip 200 may be electrically connected to the second lower internal bonding wires 122W of the main memory chip 100, respectively. Therefore, the second lower slave internal pads 222P of the lower slave memory chip 200 may be commonly connected to the second lower internal bonding wires 122W of the main memory chip 100 and the second middle internal bonding wires 222W of the lower slave memory chip 200.

[0045] The lower slave power pads 230P may be electrically connected to the lower slave power bonding wires 230W, respectively.

[0046] Figure 2C is a top view illustrating an intermediate slave memory chip 300 according to one embodiment of the present disclosure. Figure 2C , the intermediate slave memory chip 300 may include a first intermediate slave external pad region 311R, a second intermediate slave external pad region 312R, a first intermediate slave internal pad region 321R, a second intermediate slave internal pad region 322R, and an intermediate slave power pad region 330R. The arrangement of the first intermediate slave external pad region 311R, the second intermediate slave external pad region 312R, the first intermediate slave internal pad region 321R, the second intermediate slave internal pad region 322R, and the intermediate slave power pad region 330R of the intermediate slave memory chip 300 may be the same as the arrangement of the first master external pad region 111R, the second master external pad region 112R, the first master internal pad region 121R, the second master internal pad region 122R, and the master power pad region 130R.

[0047] The first middle slave external pad 311P may be disposed in the first middle slave external pad region 311R. The second middle slave external pad 312P may be disposed in the second middle slave external pad region 312R. The first middle slave internal pad 321P may be disposed in the first middle slave internal pad region 321R. The second middle slave internal pad 322P may be disposed in the second middle slave internal pad region 322R. The middle slave power pad 330P may be disposed in the middle slave power pad region 330R. The arrangement of the first intermediate slave external pad 311P, the second intermediate slave external pad 312P, the first intermediate slave internal pad 321P, the second intermediate slave internal pad 322P and the intermediate slave power pad 330P of the intermediate slave memory chip 300 can be the same as the arrangement of the first main external pad 111P, the second main external pad 112P, the first main internal pad 121P, the second main internal pad 122P and the main power pad 130P of the main memory chip 100.

[0048] The first and second intermediate slave external pads 311P and 312P of the intermediate slave memory chip 300 may not be connected to the first and second external channels Ech1 and Ech2. Each of the first and second intermediate slave external pads 311P and 312P of the intermediate slave memory chip 300 may be floated.

[0049] The first middle slave internal pads 321P may be electrically connected to the first upper internal bonding wires 321W, respectively. The first middle slave internal pads 321P of the middle slave memory chip 300 may be electrically connected to the first middle internal bonding wires 221W of the lower slave memory chip 200, respectively. Therefore, the first middle slave internal pads 321P of the middle slave memory chip 300 may be commonly connected to the first middle internal bonding wires 221W of the lower slave memory chip 200 and the first upper internal bonding wires 321W of the middle slave memory chip 300.

[0050] The second middle slave internal pads 322P may be electrically connected to the second upper internal bonding wires 322W, respectively. The second middle slave internal pads 322P of the middle slave memory chip 300 may be electrically connected to the second middle internal bonding wires 222W of the lower slave memory chip 200, respectively. Therefore, the second middle slave internal pads 322P of the middle slave memory chip 300 may be commonly connected to the second middle internal bonding wires 222W of the lower slave memory chip 200 and the second upper internal bonding wires 322W of the middle slave memory chip 300.

[0051] The intermediate slave power pads 330P may be electrically connected to the intermediate slave power bonding wires 330W, respectively.

[0052] Figure 2D4 is a top view illustrating an upper portion of a memory chip 400 according to one embodiment of the present disclosure. Figure 2D , the upper slave memory chip 400 may include a first upper slave external pad region 411R, a second upper slave external pad region 412R, a first upper slave internal pad region 421R, a second upper slave internal pad region 422R, and an upper slave power pad region 430R. The arrangement of the first upper slave external pad region 411R, the second upper slave external pad region 412R, the first upper slave internal pad region 421R, the second upper slave internal pad region 422R, and the upper slave power pad region 430R of the upper slave memory chip 400 may be the same as the arrangement of the first main external pad region 111R, the second main external pad region 112R, the first main internal pad region 121R, the second main internal pad region 122R, and the main power pad region 130R of the main memory chip 100.

[0053] The first upper slave external pad 411P may be disposed in the first upper slave external pad region 411R. The second upper slave external pad 412P may be disposed in the second upper slave external pad region 412R. The first upper slave internal pad 421P may be disposed in the first upper slave internal pad region 421R. The second upper slave internal pad 422P may be disposed in the second upper slave internal pad region 422R. The upper slave power pad 430P may be disposed in the upper slave power pad region 430R.

[0054] The arrangement of the first upper slave external pad 411P, the second upper slave external pad 412P, the first upper slave internal pad 421P, the second upper slave internal pad 422P and the upper slave power pad 430P of the upper slave memory chip 400 can be the same as the arrangement of the first main external pad 111P, the second main external pad 112P, the first main internal pad 121P, the second main internal pad 122P and the main power pad 130P of the main memory chip 100.

[0055] The first and second upper slave external pads 411P and 412P of the upper slave memory chip 400 may not be connected to the first and second external channels Ech1 and Ech2. Each of the first and second upper slave external pads 411P and 412P of the upper slave memory chip 400 may be floated.

[0056] The first upper slave internal pads 421P of the upper slave memory chip 400 may be electrically connected to the first upper internal bonding wires 321W of the middle slave memory chip 300 , respectively.

[0057] The second upper slave internal pads 422P of the upper slave memory chip 400 may be electrically connected to the second upper internal bonding wires 322W of the middle slave memory chip 300 , respectively.

[0058] The upper slave power pads 430P may be electrically connected to the upper slave power bonding wires 430W, respectively.

[0059] Figure 3A is a top view of a semiconductor package 1000 according to one embodiment of the present disclosure, and Figure 3B It is along Figure 3A The side view is obtained by line I-I', and Figure 3C It is along Figure 3A The side view is obtained by the line II-II'. FIG. 3A to FIG. 3C, the semiconductor package 1000 may include: a main memory chip 100 mounted on a substrate 50, and slave memory chips 200, 300 and 400 stacked above the main memory chip 100. The main memory chip 100 and the slave memory chips 200 to 400 may be offset and stacked in a stepped shape. The slave memory chips 200 to 400 may include a lower slave memory chip 200, a middle slave memory chip 300 and an upper slave memory chip 400. The substrate 50 may include a package substrate, such as a printed circuit board (PCB). The substrate 50 may include a first external channel Ech1 and a second external channel Ech2 disposed therein. The first signal binding finger 11, the second signal binding finger 12 and the first power binding finger 31 to the fourth power binding finger 34 may be disposed on the top surface of the substrate 50. The first external channel Ech1 and the second external channel Ech2 and the first signal binding finger 11 and the second signal binding finger 12 may be disposed adjacent to the first side S1 of the substrate 50. For example, the first external channel Ech1 and the second external channel Ech2 and the first signal bonding finger 11 and the second signal bonding finger 12 may be disposed adjacent to the first side edge E1 of each of the memory chips 100 to 400. The power pads 130P, 230P, 330P, and 430P and the first power bonding finger 31 to the fourth power bonding finger 34 may be disposed adjacent to the second side S2 of the substrate 50. For example, the power pads 130P, 230P, 330P, and 430P and the first power bonding finger 31 to the fourth power bonding finger 34 may be disposed adjacent to the second side edge E2 of the corresponding memory chips 100 to 400. For example, the memory chips 100 to 400 may be mounted and stacked in the following manner: the first side edge E1 of the main memory chip 100 is adjacent to the first external channel Ech1 and the second external channel Ech2 and the first signal bonding finger 11 and the second signal bonding finger 12 of the substrate 50. Although the semiconductor package 1000 is illustrated as including four memory chips 100 to 400 in this embodiment of the present disclosure, according to other embodiments of the present disclosure, the semiconductor package 1000 may include two or more memory chips. For example, according to one embodiment of the present disclosure, the semiconductor package 1000 may include a master memory chip 100 and an upper slave memory chip 400. According to another embodiment of the present disclosure, the semiconductor package 1000 may include a master memory chip 100, a plurality of lower slave memory chips 200 or a plurality of middle slave memory chips 300, and an upper slave memory chip 400.

[0060] Further references Figure 2A, the first main external pads 111P of the main memory chip 100 may be respectively connected to the first signal bonding finger 11 above the substrate 50 through the first external bonding wire 111W. The first signal bonding finger 11 of the substrate 50 and the first main external pad 111P of the main memory chip 100 may be arranged adjacent to each other. The first signal bonding finger 11 may be connected to the first external channel Ech1 in the substrate 50. The second main external pads 112P of the main memory chip 100 may be respectively connected to the second signal bonding finger 12 above the substrate 50 through the second external bonding wire 112W. The second signal bonding finger 12 of the substrate 50 and the second main external pad 112P of the main memory chip 100 may be arranged adjacent to each other. The second signal bonding finger 12 may be connected to the second external channel Ech2 in the substrate 50. The first signal bonding finger 11 and the second signal bonding finger 12 may not be connected to the first main internal pad 121P and the second main internal pad 122P.

[0061] Further references FIG. 2B to FIG. 2D , the first lower from external pad 211P, the first middle from external pad 311P, and the first upper from external pad 411P, and the second lower from external pad 212P, the second middle from external pad 312P, and the second upper from external pad 412P from the memory chips 200 to 400 may be floated. That is, the first lower from external pad 211P, the first middle from external pad 311P, and the first upper from external pad 411P, and the second lower from external pad 212P, the second middle from external pad 312P, and the second upper from external pad 412P from the memory chips 200 to 400 may not be connected to any bonding wire.

[0062] Further references FIG. 2A to FIG. 2D, the first main internal pad 121P of the master memory chip 100, the first lower slave internal pad 221P of the lower slave memory chip 200, the first middle slave internal pad 321P of the middle slave memory chip 300, and the first upper slave internal pad 421P of the upper slave memory chip 400 may be electrically connected to each other through the first lower internal bonding wire 121W, the first middle internal bonding wire 221W, and the first upper internal bonding wire 321W. The second main internal pad 122P of the master memory chip 100, the second lower slave internal pad 222P of the lower slave memory chip 200, the second middle slave internal pad 322P of the middle slave memory chip 300, and the second upper slave internal pad 422P of the upper slave memory chip 400 may be electrically connected to each other through the second lower internal bonding wire 122W, the second middle internal bonding wire 222W, and the second upper internal bonding wire 322W. The first lower internal bonding wire 121W, the first middle internal bonding wire 221W, and the first upper internal bonding wire 321W may form a first internal channel Ich1, and the second lower internal bonding wire 122W, the second middle internal bonding wire 222W, and the second upper internal bonding wire 322W may form a second internal channel Ich2.

[0063] The power pads 130P, 230P, 330P, and 430P of the master memory chip 100, the lower slave memory chip 200, the middle slave memory chip 300, and the upper slave memory chip 400 may be electrically connected to the power bonding fingers 31 to 34 of the substrate 50 independently and respectively through the power bonding wires 130W, 230W, 330W, and 430W. For example, the main power pad 130P of the master memory chip 100 may be electrically connected to the first power bonding finger 31 of the substrate 50 through the main power bonding wire 130W. The lower slave power pad 230P of the slave memory chip 200 may be electrically connected to the second power bonding finger 32 of the substrate, and the middle slave power pad 330P of the middle slave memory chip 300 may be electrically connected to the third power bonding finger 33 of the substrate. The upper slave power pad 430P of the upper slave memory chip 400 may be electrically connected to the fourth power bonding finger 34 of the substrate. In the substrate 50, the first power combining finger 31 to the fourth power combining finger 34 can be selectively electrically connected to each other. For example, among the first power combining finger 31 to the fourth power combining finger 34, the power combining fingers that transmit and provide the same power can be selectively electrically connected to each other. The power may include a drain voltage VDD, a source voltage VSS, a boost voltage VPP or other commonly used voltages. The first power combining finger 31 may be a main power combining finger for providing a voltage to the main memory chip 100. The second power combining finger 32 may be a lower slave power combining finger for providing a voltage to the lower slave memory chip 200. The third power combining finger 33 may be an intermediate slave power combining finger for providing a voltage to the intermediate slave memory chip 300. The fourth power combining finger 34 may be an upper slave power combining finger for providing a voltage to the upper slave memory chip 400.

[0064] According to the inventive concept of the present disclosure, the signal bonding fingers 11 and 12 of the substrate 50 may be electrically connected to the external pads 111P and 112P of the main memory chip 100 through the external bonding wires 111W and 112W. The signal bonding fingers 11 and 12 of the substrate 50 may not be connected to the external pads 211P, 212P, 311P, 312P, 411P and 412P of the slave memory chips 200 to 400. The first internal pads 121P, 221P, 321P and 421P of the memory chips 100 to 400 may be electrically connected to each other through the first internal bonding wires 121W, 221W and 321W. The second internal pads 122P, 222P, 322P and 422P of the memory chips 100 to 400 may be electrically connected to each other through the second internal bonding wires 122W, 222W and 322W.

[0065] According to one embodiment of the present disclosure, in the inventive concept of the present disclosure, the power pads 130P, 230P, 330P and 430P of the memory chips 100 to 400 can be electrically connected to the first to fourth power bonding fingers 31, 32, 33 and 34 in a one-to-one manner through power bonding wires 130W, 320W, 330W and 430W, respectively.

[0066] Spacer elements for adhering and supporting the memory chips 100 to 400 to each other may be provided between the memory chips 100 to 400. The spacer elements may include dummy elements and / or adhesive films.

[0067] Figure 4A and Figure 4B The arrangement of the internal circuit blocks and internal electrical signal paths of the main memory chip 100 according to one embodiment of the present disclosure is illustrated. The internal electrical signal paths are indicated using arrows. Double-headed arrows may mean internal interconnects.

[0068] refer to Figure 4A and Figure 4B , the main memory chip 100 according to an embodiment of the present disclosure may include a main cell bank area CBm and a main peripheral circuit area PCm. The main peripheral circuit area PCm may be disposed adjacent to the first side edge E1. The main cell bank area CBm may be disposed adjacent to the second side edge E2. According to an embodiment of the present disclosure, the main peripheral circuit area PCm may overlap or be adjacent to the main pad areas 111R, 112R, 121R, and 122R. The main cell bank area CBm may overlap or be adjacent to the power pad area (refer to Figure 2A 130R) overlaps or is adjacent to the main cell library area CBm. The main cell library area CBm may include a main memory cell block and a main core block. The main peripheral circuit area PCm may include a first main external circuit block 151, a second main external circuit block 152, a first main internal circuit block 161, and a second main internal circuit block 162. According to one embodiment of the present disclosure, the first main external circuit block 151 may include a main data buffer. The second main external circuit block 152 may include a main signal buffer. The first main internal circuit block 161 may include a main data serialization / deserialization circuit. The second main internal circuit block 162 may include a main signal decoding circuit.

[0069] The first main external circuit block 151 may be disposed adjacent to the first main external pad 111P in the first main external pad region 111R. The first main external circuit block 151 may be electrically connected to the first main external pad 111P in the first main external pad region 111R, and communicate with the memory controller 900 through the first external channel Ech1. The first main external circuit block 151 may be electrically connected to the first main internal circuit block 161 through the internal interconnection and communicate with the first main internal circuit block 161. Therefore, the first main external circuit block 151 may receive a data signal and a data strobe signal from the memory controller 900 through the first external channel Ech1, and transmit them to the first main internal circuit block 161. The first main external circuit block 151 may receive a data signal from the first main internal circuit block 161, and provide the received data signal to the memory controller 900 through the first external channel Ech1.

[0070] The first main internal circuit block 161 may be disposed adjacent to the first main internal pad 121P in the first main internal pad region 121R. The first main internal circuit block 161 may be electrically connected to the first main internal pad 121P in the first main internal pad region 121R, and communicate with the slave memory chips 200 to 400 through the first internal channel Ich1. The first main internal circuit block 161 may transmit an electrical signal received from the first main external circuit block 151 to the first internal channel Ich1. According to one embodiment of the present disclosure, the electrical signal provided from the first main external circuit block 151 may be directly provided to the first internal channel Ich1 without electrically passing through the first main internal circuit block 161. The first main internal circuit block 161 may transmit an electrical signal received from the first internal channel Ich1 to the first main external circuit block 151. According to one embodiment of the present disclosure, the electrical signal provided from the first internal channel Ich1 may be directly provided to the first main external circuit block 151 without electrically passing through the first main internal circuit block 161. The first master internal circuit block 161 may be electrically connected to the main memory cells and the main memory core circuit in the main cell bank area CBm through internal interconnects. For example, the first master internal circuit block 161 may be electrically connected to the bit lines and sense amplifiers in the main memory cells and the main memory core circuit through internal interconnects. The first master internal circuit block 161 may transmit the electrical signal provided from the first master external circuit block 151 to the main cell bank area CBm. The first master internal circuit block 161 may transmit the electrical signal provided from the main cell bank area CBm to the first master external circuit block 151.

[0071] Therefore, the first master external pad 111P may communicate with the main cell bank region CBm through the first master external circuit block 151 and the first master internal circuit block 161. The first master external pad 111P, the first master external circuit block 151, the first master internal circuit block 161, and the bit lines or sense amplifiers of the main cell bank region CBm may be connected in series.

[0072] The second main external circuit block 152 may be disposed adjacent to the second main external pad 112P in the second main external pad region 112R. The second main external circuit block 152 may be electrically connected to the second main external pad 112P in the second main external pad region 112R, and communicate with the memory controller 900 through the second external channel Ech2. The second main external circuit block 152 may be electrically connected to the second main internal circuit block 162 through an internal interconnect and communicate with the second main internal circuit block 162. For example, the second main external circuit block 152 may receive a clock signal, a chip select signal, a command signal, and an address signal through the second external channel Ech2, and transmit them to the second main internal circuit block 162. The second main external circuit block 152 may transmit the electrical signal received from the second main internal circuit block 162 to the second external channel Ech2.

[0073] The second main internal circuit block 162 may be disposed adjacent to the second main internal pad 122P in the second main internal pad region 122R. The second main internal circuit block 162 may be electrically connected to the second main internal pad 122P in the second main internal pad region 122R, and communicate with the slave memory chips 200 to 400 through the second internal channel Ich2. The second main internal circuit block 162 may transmit the electrical signal received from the second main external circuit block 152 to the second internal channel Ich2. The second main internal circuit block 162 may transmit the electrical signal received from the second internal channel Ich2 to the second main external circuit block 152. According to one embodiment of the present disclosure, the electrical signal provided from the second main external circuit block 152 may be directly provided to the second internal channel Ich2 without electrically passing through the second main internal circuit block 162. The second main internal circuit block 162 may transmit the electrical signal received from the second internal channel Ich2 to the second main external circuit block 152. According to one embodiment of the present disclosure, the electrical signal provided from the second internal channel Ich2 can be provided to the second main external circuit block 152 without electrically passing through the second main internal circuit block 162. The second main internal circuit block 162 can be electrically connected to the main memory cell and the main memory core circuit in the main cell bank area CBm through the internal interconnection. For example, the second main internal circuit block 162 can be electrically connected to the main memory cell and the word line in the main memory core circuit through the internal interconnection. The second main internal circuit block 162 can transmit the electrical signal provided from the second main external circuit block 152 to the main cell bank area CBm. The second main internal circuit block 162 can transmit the electrical signal provided from the main cell bank area CBm to the second main external circuit block 152.

[0074] Therefore, the second master external pad 112P may communicate with the main cell bank area CBm through the second master external circuit block 152 and the second master internal circuit block 162. The second master external pad 112P, the second master external circuit block 152, the second master internal circuit block 162, and the word lines of the main cell bank area CBm may be connected in series.

[0075] Figure 5A and Figure 5B The arrangement of the internal circuit blocks and internal electrical signal paths of the slave memory chip 500 according to one embodiment of the present disclosure is illustrated. Double-headed arrows indicate electrical connections and communication paths of the elements, and dashed lines indicate that the components are electrically connected but not communicating. The slave memory chip 500 may be one of the lower slave memory chip, the middle slave memory chip, and the upper slave memory chips 200 to 400. Reference Figure 5A and Figure 5B, the slave memory chip 500 may include a slave cell bank region CBs and a slave peripheral circuit region PCs. The slave peripheral circuit region PCs may be disposed adjacent to the first side edge E1. The slave cell bank region CBs may be disposed adjacent to the second side edge E2. According to one embodiment of the present disclosure, the slave peripheral circuit region PCs may overlap or be adjacent to the slave pad regions 511R, 512R, 521R, and 522R. The slave cell bank region CBs may overlap or be adjacent to the power pad region (refer to FIG. 2B to FIG. 2D The slave cell library area CBs may include a slave memory cell block and a slave core block. The slave peripheral circuit area PCs may include a first slave external circuit block 551, a second slave external circuit block 552, a first slave internal circuit block 561, and a second slave internal circuit block 562. The first slave external circuit block 551 may include a slave data buffer. The second slave external circuit block 552 may include a slave signal buffer. The first slave internal circuit block 561 may include a slave data serialization / deserialization circuit. The second slave internal circuit block 562 may include a slave signal decoding circuit.

[0076] The first slave data buffer 551 may be disposed adjacent to the first slave external pad 511P in the first slave external pad region 511R. The first slave external circuit block 551 may be electrically connected to the first slave external pad 511P in the first slave external pad region 511R. However, the first slave external circuit block 551 may not be connected to the first external channel Ech1 and may not communicate with the memory controller 900. The first slave external circuit block 551 may be electrically connected to the first slave internal circuit block 561 through an internal interconnect. However, the first slave external circuit block 551 may not communicate with the first slave internal circuit block 561. For example, the first slave external circuit block 551 may be dummy.

[0077] The first slave internal circuit block 561 may be disposed adjacent to the first slave internal pad 521P. The first slave internal circuit block 561 may be electrically connected to the first slave internal pad 521P in the first slave internal pad region 521R through an internal interconnect. Therefore, the first slave internal circuit block 561 may receive a data signal and a data strobe signal from the first master external circuit block 151 of the master memory chip 100 through the first internal channel Ich1 and the first slave internal pad 521P. The first slave internal circuit block 561 may be electrically connected to the slave memory cells and the slave memory core circuit in the slave cell bank area CBs through an internal interconnect. The first slave internal circuit block 561 may transmit an electrical signal received from the first internal channel Ich1 to the slave cell bank area CBs, and transmit an electrical signal received from the slave cell bank area CBs to the first internal channel Ich1.

[0078] Therefore, the first master external pad 111P can communicate with the slave cell bank area CBs through the first master external circuit block 151 and the first slave internal circuit block 561. The first master external pad 111P, the first master external circuit block 151, the first slave internal circuit block 561, and the bit lines or sense amplifiers of the slave cell bank area CBs can be connected in series.

[0079] The second slave external circuit block 552 may be disposed adjacent to the second slave external pad 512P in the second slave external pad region 512R. The second slave external circuit block 552 may be electrically connected to the second slave external pad 512P in the second slave external pad region 512R. However, the second slave external circuit block 552 may not be connected to the second external channel Ech2 and may not communicate with the memory controller 900. The second slave external circuit block 552 may be electrically connected to the second slave internal circuit block 562 through an internal interconnect. However, the second slave external circuit block 552 may not communicate with the second slave internal circuit block 562. For example, the second slave external circuit block 552 may be dummy.

[0080] The second slave internal circuit block 562 can be disposed adjacent to the second slave internal pad 522P. The second slave internal circuit block 562 can be electrically connected to the second slave internal pad 522P in the second slave internal pad region 522R through an internal interconnect. Therefore, the second slave internal circuit block 562 can receive a clock signal, a chip select signal, a command signal, and an address signal from the second main external circuit block 152 of the main memory chip 100 through the second internal channel Ich2 and the second slave internal pad 522P. The second slave internal circuit block 562 can be electrically connected to the slave memory cell and the slave memory core circuit in the slave cell bank area CBs through an internal interconnect. The second slave internal circuit block 562 can transmit the electrical signal received from the second internal channel Ich2 to the slave cell bank area CBs, and transmit the electrical signal received from the slave cell bank area CBs to the second internal channel Ich2.

[0081] Therefore, the second master external pad 112P can communicate with the slave cell bank area CBs through the second master external circuit block 152 and the second slave internal circuit block 562. The second master external pad 112P, the second master external circuit block 152, the second slave internal circuit block 562, and the word lines of the slave cell bank area CBs can be connected in series.

[0082] According to the inventive concept of the present disclosure, the first master external circuit block 151 of the master memory chip 100 may control the first master internal circuit block 161 and the first slave internal circuit block 561. For example, the first master external circuit block 151 of the master memory chip 100 may transmit a data signal and a data strobe signal to the first master internal circuit block 161 and the first slave internal circuit block 561, and receive a data signal from the first master internal circuit block 161 and the first slave internal circuit block 561. The first slave external circuit block 551 of the slave memory chip 500 may be bypassed.

[0083] According to the inventive concept of the present disclosure, the second master external circuit block 152 of the main memory chip 100 may control the second master internal circuit block 162 and the second slave internal circuit block 562. For example, the second master external circuit block 152 of the main memory chip 100 may provide a clock signal, a chip selection signal, a command signal, and an address signal to the second master internal circuit block 162 and the second slave internal circuit block 562. The second slave external circuit block 552 may be bypassed or skipped.

[0084] Figure 6 is a schematic top view illustrating a substrate 50 according to an embodiment of the present disclosure. Figure 6 , the substrate 50 may include a first external channel Ech1 and a second external channel Ech2, and a first signal combining finger 11 and a second signal combining finger 12 disposed on the upper surface. The first external channel Ech1 and the second external channel Ech2 and the first signal combining finger 11 and the second signal combining finger 12 may be disposed in the left half of the substrate 50 to be adjacent to the first side S1 of the substrate 50. The first power combining finger 31 to the fourth power combining finger 34 may be disposed in the right half of the substrate 50 to be close to the second side S2 of the substrate 50. The first power combining finger 31 to the fourth power combining finger 34 may be respectively disposed to form columns. These columns may extend parallel to the second side S2 of the substrate 50. The first power combining finger 31 may be disposed farthest from the second side S2 of the substrate 50. The fourth power combining finger 34 may be disposed closest to the second side S2 of the substrate 50. Further reference Figure 3A, in the top view, the first power combining finger 31 may be disposed at a position covered by at least one of the lower slave memory chip, the middle slave memory chip, and the upper slave memory chips 200 to 400. The second power combining finger 32 may be disposed at a position covered by at least one of the middle slave memory chip 300 and the upper slave memory chip 400. The third power combining finger 33 may be disposed at a position covered by the upper slave memory chip 400. The fourth power combining finger 34 may be exposed without being covered by the memory chips 100 to 400. The accompanying drawings illustrate that only the first power combining finger 31 to the fourth power combining finger 34 form four columns, but since the memory chips can be stacked into two or more layers according to the inventive concept of the present disclosure, the power combining fingers may be disposed to form two or more columns.

[0085] Fig. 7A is a top view illustrating a main memory chip 100A according to another embodiment of the present disclosure. Fig. 7A , according to an embodiment of the present disclosure, the main memory chip 100A may include a main external pad area 110R, a main internal pad area 120R, and a main power pad area 130R. The main external pad area 110R and the main internal pad area 120R may be arranged adjacent to the first side edge E1 of the main memory chip 100A and form two columns. For example, the main external pad area 110R may be arranged closer to the first side edge E1 of the main memory chip 100A to form a column. The main internal pad area 120R may be arranged adjacent to the external pad area 110R to form a column. The main power pad area 130R may be arranged adjacent to the second side edge E2 of the main memory chip 100A to form a column. The main external pads 110P may be arranged in the main external pad area 110R. The main external pads 110P may include Figure 2A The main external pads 111P and the second main external pads 112P are shown in FIG. The main external pads 110P may be electrically connected to the external bonding wires 110W. The main internal pads 120P may be disposed in the main internal pad region 120R. The main internal pads 120P may include Figure 2A 1 and 2. The main inner pads 121P and 122P are shown in FIG. The main inner pads 120P may be electrically connected to the lower inner bonding wire 120W.

[0086] FIG. 7B to FIG. 7D is a top view illustrating a lower slave memory chip 200A, a middle slave memory chip 300A, and an upper slave memory chip 400A according to an embodiment of the present disclosure. FIG. 7B to FIG. 7D, from memory chips 200A, 300A and 400A, respectively, external pad regions 210R, 310R and 410R may be included, and internal pad regions 220R, 320R and 420R may be included, and power pad regions 230R, 330R and 430R may be included. External pad regions 210R, 310R and 410R and internal pad regions 220R, 320R and 420R may be disposed adjacent to first side edges E1 of memory chips 200A, 300A and 400A, and form two columns. For example, external pad regions 210R, 310R and 410R may be disposed to form a column to be closer to first side edges E1 of memory chips 200A, 300A and 400A. The slave inner pad regions 220R, 320R and 420R may be arranged to form a column respectively, to be adjacent to the slave outer pad regions 210R, 310R and 410R. For example, the slave outer pad regions 210R, 310R and 410R may be arranged between the first side edge E1 and the corresponding slave inner pad regions 220R, 320R and 420R. The slave power pad regions 230R, 330R and 430R may be arranged to form a column, to be adjacent to the second side edge E2 of the corresponding slave memory chips 200A, 300A and 400A.

[0087] The slave external pads 210P, 310P, and 410P may be disposed in the slave external pad regions 210R, 310R, and 410R, respectively. The slave external pads 210P, 310P, and 410P may include FIG. 2B to FIG. 2D 100A, 100A, 100B, 100C ...

[0088] The slave inner pads 220P, 320P, and 420P may be disposed in the slave inner pad regions 220R, 320R, and 420R, respectively. The slave inner pads 220P, 320P, and 420P may include FIG. 2B to FIG. 2D 1 and 2. The first slave inner pads 221P, 321P and 421P and the second slave inner pads 222P, 322P and 422P are shown in FIG.

[0089] The lower slave internal pad 220P may be electrically connected to both the lower internal bonding wire 120W of the master memory chip 100A and the middle internal bonding wire 220W of the lower slave memory chip 200A.

[0090] The middle slave internal pads 320P may be commonly electrically connected to the middle internal bonding wires 220W of the lower slave memory chip 200A and the upper internal bonding wires 320W of the middle slave memory chip 300A.

[0091] The upper slave internal pad 420P may be electrically connected to the upper internal bonding wire 320W of the middle slave memory chip 300A.

[0092] The lower internal bonding wire 120W of the master memory chip 100A, the middle internal bonding wire 220W of the lower slave memory chip 200A, and the upper internal bonding wire 320W of the middle slave memory chip 300A may form an internal channel.

[0093] Fig. 8A and Figure 8B 1 is a top view and a side view of a semiconductor package 1000A according to another embodiment of the present disclosure. Fig. 8A and Figure 8B , the semiconductor package 1000A may include a master memory chip 100A, a lower slave memory chip 200A, a middle slave memory chip 300A, and an upper slave memory chip 400A offset-stacked above a substrate 50. The substrate 50 may include an external channel Ech, a signal bonding finger 10, and first to fourth power bonding fingers 31 to 34.

[0094] refer to Fig. 7A , Fig. 8A , Figure 8B , the main external pads 110P of the main memory chip 100A may be connected to the signal bonding fingers 10 above the substrate 50 through the external bonding wires 110W. The signal bonding fingers 10 may be connected to the external channels Ech in the substrate 50.

[0095] refer to FIG. 7B to FIG. 7D , Fig. 8A and Figure 8B , the slave external pads 210P, 310P, and 410P of the slave memory chips 200A to 400A may be floated. The slave external pads 210P, 310P, and 410P of the slave memory chips 200A to 400A may not be connected to any bonding wire.

[0096] refer to 7A to 7D , Fig. 8A and Figure 8B, the main internal pad 120P of the master memory chip 100A, the lower slave internal pad 220P of the lower slave memory chip 200A, the middle slave internal pad 320P of the middle slave memory chip 300A, and the upper slave internal pad 420P of the upper slave memory chip 400A may be electrically connected to each other through the internal bonding wires 120W, 220W, and 320W. The internal bonding wires 120W, 220W, and 320W may form an internal channel Ich.

[0097] The power pads 130P, 230P, 330P and 430P of the main memory chip 100A, the lower slave memory chip 200A, the middle slave memory chip 300A and the upper slave memory chip 400A can be independently and respectively electrically connected to the power bonding fingers 31 to 34 of the substrate 50 through power bonding wires 130W, 230W, 330W and 430W.

[0098] Fig. 9 is a longitudinal cross-sectional view illustrating a redistribution structure of a memory chip according to one embodiment of the present disclosure. Fig. 9 , the memory chips 100 to 500 may include a semiconductor substrate Sub, an interlayer dielectric layer ILD, top metal pads 91S and 91P, redistribution vias 92S, 92Pa and 92Pb, redistribution wiring 93, a redistribution dielectric layer RDLD, and redistribution pads 95 and 96.

[0099] The semiconductor substrate Sub may include a silicon wafer. A circuit element may be formed over the semiconductor substrate Sub. The interlayer dielectric layer ILD may cover the circuit element. The interlayer dielectric layer ILD may include a silicon oxide-based dielectric layer and a silicon nitride-based dielectric layer.

[0100] The top metal pads 91S and 91P may be formed above the interlayer dielectric layer ILD. The top metal pads 91S and 91P may include a signal top metal pad 91S and a power top metal pad 91P. The signal top metal pad 91S and the power top metal pad 91P may include a metal such as aluminum (Al). Both the signal top metal pad 91S and the power top metal pad 91P may be disposed adjacent to the first side edge E1 of the semiconductor substrate Sub.

[0101] Redistribution pads 95 and 96 may be disposed above the redistribution dielectric layer RDLD. The redistribution pads 95 and 96 may include a signal redistribution pad 95 and a power redistribution pad 96. The signal redistribution pad 95 may be formed adjacent to a first side edge E1 of the semiconductor substrate Sub, and the power redistribution pad 96 may be formed adjacent to a second side edge E2 of the semiconductor substrate Sub. The first side edge E1 of the semiconductor substrate Sub may correspond to the first side edge E1 of the main memory chip 100 and the slave memory chips 200 to 400, and the second side edge E2 of the semiconductor substrate Sub may correspond to the second side edge E2 of the main memory chip 100 and the slave memory chips 200 to 400.

[0102] The signal redistribution via 92S may vertically penetrate the redistribution dielectric layer RDLD to electrically connect the signal top metal pad 91S and the signal redistribution pad 95 .

[0103] The lower power redistribution via 92Pa may be disposed above the power top metal pad 91P, and the upper power redistribution via 92Pb may be disposed below the power redistribution pad 96. The lower power redistribution via 92Pa and the upper power redistribution via 92Pb may vertically penetrate a portion of the redistribution dielectric layer RDLD.

[0104] The redistribution wiring 93 may electrically connect the lower power redistribution via 92Pa and the upper power redistribution via 92Pb. The redistribution wiring 93 may extend horizontally within the redistribution dielectric layer RDLD.

[0105] According to the technical concept of the present disclosure, the power top metal pad 91P disposed adjacent to the first side edge E1 and the power redistribution pad 96 disposed adjacent to the second side edge E2 may be electrically connected to each other through the lower power redistribution via 92Pa, the redistribution wiring 93, and the upper power redistribution via 92Pb. Therefore, the power supplied to the power redistribution pad 96 close to the second edge E2 may be transmitted and supplied to the power top metal pad 91P disposed adjacent to the first side edge E1. According to the technical concept of the present disclosure, the peripheral circuit regions PCm and PCs may be disposed close to the first side edge E1, but may be supplied with power through the power pads 130P to 530P disposed close to the second side edge E2.

[0106] According to an embodiment of the present disclosure, a three-dimensional stacked (3DS) memory device having an electrical connection structure formed using a relatively inexpensive wire bonding structure instead of using an expensive through silicon via (TSV) may be provided.

[0107] According to the embodiments of the present disclosure, pads and bonding wires can be separately arranged according to functions and channels, thereby simplifying interconnection wiring, reducing parasitic capacitance between interconnections, reducing signal loss, and suppressing signal interference and noise generation.

[0108] Although the present disclosure has been described with respect to specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the present disclosure as defined in the appended claims. Furthermore, the embodiments may be combined to form additional embodiments.

Claims

1. A semiconductor package, comprising: a substrate having a plurality of binding fingers; a main memory chip mounted on the substrate; as well as a slave memory chip stacked above the master memory chip, The main memory chip comprises: a main external pad and a main internal pad disposed adjacent to a first side edge of the main memory chip; and a main power pad disposed adjacent to a second side edge of the main memory chip, and The slave memory chip comprises: a slave external pad and a slave internal pad disposed adjacent to a first side edge of the slave memory chip; and a slave power pad disposed adjacent to a second side edge of the slave memory chip, wherein: Some of the bonding fingers are electrically connected to the main external pad through external bonding wires, The master internal pads are electrically connected to the slave internal pads through internal bonding wires, respectively, and The slave external pad is floated.

2. The semiconductor package according to claim 1, The combination refers to: a signal combining finger disposed adjacent to the first side edge of the main memory chip; as well as A master power combining finger and a slave power combining finger are disposed adjacent to the second side edge of the main memory chip. 3 . The semiconductor package according to claim 2 , wherein the signal bonding finger and the main internal pad are not electrically connected to each other.

4. The semiconductor package according to claim 2, wherein: The main power combining fingers are respectively connected to the main power pads through main power combining wires, and The slave power combining fingers are respectively connected to the slave power pads through slave power combining wires.

5. The semiconductor package according to claim 2, wherein: The main external pads include a first main external pad and a second main external pad disposed adjacent to a middle portion of the first side edge of the main memory chip, The main internal pads include a first main internal pad and a second main internal pad respectively disposed adjacent to both ends of the first side edge of the main memory chip. The slave external pads include a first slave external pad and a second slave external pad disposed adjacent to a middle portion of the first side edge of the slave memory chip, and The slave inner pads include a first slave inner pad and a second slave inner pad respectively disposed adjacent to both ends of the first side edge of the slave memory chip and separated from each other.

6. The semiconductor package according to claim 5, wherein: The signal binding finger comprises a first signal binding finger and a second signal binding finger, The first signal combining finger is disposed on the substrate adjacent to the first main external pad, and The second signal combining finger is disposed on the substrate adjacent to the second main external pad.

7. The semiconductor package according to claim 6, wherein: The external bonding wiring comprises: a first external bonding wire connecting the first signal bonding finger to the first main external pad; and connecting the second signal bonding finger to a second external bonding wire of the second main external pad, and The internal bonding wiring comprises: a first internal bonding wire connecting the first master internal pad to the first slave internal pad; and connecting the second master internal pad to a second internal bonding wire of the second slave internal pad, and The first slave external pad and the second slave external pad are not connected to any bonding wire.

8. The semiconductor package according to claim 6, The main memory chip includes a main cell library and a main peripheral circuit, and The main peripheral circuit comprises: a first main external circuit block adjacent to and electrically connected to the first main external pad; a first main internal circuit block adjacent to and electrically connected to the first main internal pad; a second main external circuit block adjacent to and electrically connected to the second main external pad; and A second main internal circuit block is adjacent to and electrically connected to the second main internal pad.

9. The semiconductor package according to claim 8, wherein: The first master external circuit block includes a master data buffer, The first master internal circuit block includes a master data serialization / deserialization circuit, The second master external circuit block includes a master signal buffer, and The second main internal circuit block includes a main signal decoding circuit.

10. The semiconductor package according to claim 9, wherein: The first master external circuit block and the first master internal circuit block transmit a data signal and a data strobe signal, and The second master external circuit block and the second master internal circuit block transmit a clock signal, a chip selection signal, a command signal, and an address signal.

11. The semiconductor package according to claim 8, wherein: The first main external circuit block and the first main internal circuit block are disposed adjacent to each other and electrically connected to each other; and The second main external circuit block and the second main internal circuit block are disposed adjacent to each other and are electrically connected to each other.

12. The semiconductor package according to claim 11, wherein: The first main external circuit block, the first main internal circuit block, and the bit lines of the main cell bank are connected in series, and The second main external circuit block, the second main internal circuit block, and word lines of the main cell bank are connected in series.

13. The semiconductor package according to claim 8, The slave memory chip includes a slave cell library and a slave peripheral circuit, and The slave peripheral circuit comprises: a first slave external circuit block adjacent to and electrically connected to the first slave external pad; a first slave inner circuit block adjacent to and electrically connected to the first slave inner pad; a second slave external circuit block adjacent to and electrically connected to the second slave external pad; and A second slave inner circuit block is adjacent to and electrically connected to the second slave inner pad.

14. The semiconductor package according to claim 13, wherein: The first master external circuit block, the first slave internal circuit block, and the bit lines of the slave cell library are connected in series, and The second master external circuit block, the second slave internal circuit block, and word lines of the slave cell library are connected in series.

15. A semiconductor package, comprising: a substrate including a signal bonding finger disposed adjacent to the first side and a first power bonding finger and a second power bonding finger disposed adjacent to the second side; a main memory chip stacked above the substrate; as well as a lower slave memory chip stacked above the master memory chip, The main memory chip comprises: Main external pads; main internal pads; and A main power pad electrically connected to the first power combining finger, and The lower slave memory chip comprises: The lower part is soldered from the outside; The lower part is soldered from the inner pad; and electrically connected to a lower portion of the second power bonding finger from a power pad, and wherein: The signal bonding fingers are electrically connected to the main external pads through external bonding wires, the main internal pads are electrically connected to the lower slave internal pads through lower internal bonding wires, and The main external pad and the lower slave external pad are not connected by a bonding wire.

16. The semiconductor package according to claim 15, wherein: The signal binding finger comprises a first signal binding finger and a second signal binding finger, The main external pads include a first main external pad and a second main external pad, The main internal pads include a first main internal pad and a second main internal pad, The lower external pads include a first lower external pad and a second lower external pad, The lower inner pads include a first lower inner pad and a second lower inner pad, The external bonding wires include a first external bonding wire and a second external bonding wire, The lower internal connection wire comprises a first lower internal connection wire and a second lower internal connection wire, The first signal bonding finger, the first external bonding wire, the first main external pad, the first main internal pad, the first lower internal bonding wire and the first lower slave internal pad are electrically connected to form a first channel, and The second signal bonding finger, the second external bonding wire, the second main external pad, the second main internal pad, the second lower internal bonding wire and the second lower slave internal pad are electrically connected to form a second channel.

17. The semiconductor package according to claim 16, The main memory chip comprises: a first main external circuit block electrically connected to the first main external pad; a second main external circuit block electrically connected to the second main external pad; a first main internal circuit block electrically connected to the first main internal pad; as well as a second main internal circuit block electrically connected to the second main internal pad, in: The first main external circuit block is electrically connected to the first main internal circuit block, and The second main external circuit block is electrically connected to the second main internal circuit block, The lower slave memory chip comprises: A first lower external circuit block electrically connected to the first lower external pad; The second lower portion of the external circuit block is electrically connected to the second lower portion of the external pad; A first lower slave internal circuit block electrically connected to the first lower slave internal pad; and electrically connected to the second lower portion of the internal pad from the second lower portion of the internal circuit block, wherein the first lower portion from the external circuit block and the first lower portion from the internal circuit block are electrically connected, and Wherein the second lower portion from the external circuit block and the second lower portion from the internal circuit block are electrically connected.

18. The semiconductor package according to claim 15, further comprising: stacking the upper slave memory chip above the lower slave memory chip, The upper slave memory chip comprises: The upper part is soldered from the external pad; The upper part is soldered from the inner pad; and From the upper power pad, in: The lower slave internal pads are electrically connected to the upper slave internal pads through upper internal bonding wires, respectively, and The main external pad, the lower slave external pad, and the upper slave external pad are not connected.

19. The semiconductor package according to claim 15, wherein: The main external pad is electrically connected to the main internal pad through an internal interconnect in the main memory chip, and The lower slave external pad is electrically connected to the lower slave internal pad through an internal interconnection in the lower slave memory chip.

20. A semiconductor package, comprising: a substrate having signal binding fingers, master power binding fingers, and slave power binding fingers; a main memory chip mounted on the substrate and comprising a main external pad, a main internal pad, and a main power pad; as well as a slave memory chip stacked above the master memory chip and comprising a slave external pad, a slave internal pad, and a slave power pad; external bonding wires electrically connecting the signal bonding fingers and the main external pads respectively; internal bonding wires electrically connecting the main internal pad and the slave internal pad, respectively; Main power combining wires electrically connecting the main power combining fingers and the main power pads respectively; as well as a slave power combining wire that electrically connects the slave power combining fingers and the slave power pads, respectively; in: The main external pads are arranged in a column to be adjacent to a first side edge of the main memory chip, and The main inner pads are arranged in a column to be adjacent to the main outer pads, The slave external pads are arranged in a column to be adjacent to a first side edge of the slave memory chip, The inner pads are arranged in a column to be adjacent to the outer pads, and The slave external pad of the slave memory chip is floated. 21 . The semiconductor package of claim 20 , wherein the signal bonding finger and the main internal pad are not connected.

22. The semiconductor package according to claim 21, wherein: The main external pads include a first main external pad and a second main external pad, The main internal pads include a first main internal pad and a second main internal pad, The slave external pads include a first slave external pad and a second slave external pad, and The slave inner pads include a first slave inner pad and a second slave inner pad.

23. The semiconductor package according to claim 22, wherein: The signal binding finger comprises a first signal binding finger and a second signal binding finger, The first signal combining finger is disposed adjacent to the first main external pad, and The second signal combining finger is disposed adjacent to the second main external pad.

24. The semiconductor package according to claim 23, The external bonding wiring comprises: a first external bonding wire adapted to connect the first signal bonding finger to the first main external pad; as well as a second external bonding wire adapted to connect the second signal bonding finger to the second main external pad, The internal bonding wiring comprises: a first internal bonding wire adapted to connect the first main internal pad and the first slave internal pad; as well as a second internal bonding wire adapted to connect the second main internal pad and the second slave internal pad, The first slave external pad and the second slave external pad are not connected to any bonding wire.

25. The semiconductor package according to claim 23, The main memory chip includes a main cell library and a main peripheral circuit. The main peripheral circuit comprises: a first main external circuit block electrically connected to the first main external pad; a first main internal circuit block electrically connected to the first main internal pad; a second main external circuit block electrically connected to the second main external pad; as well as A second main internal circuit block is electrically connected to the second main internal pad.

26. The semiconductor package according to claim 25, wherein the first master external circuit block comprises a master data buffer, in: The first master internal circuit block includes a master data serialization / deserialization circuit, The second master external circuit block includes a master signal buffer, and The second main internal circuit block includes a main signal decoding circuit.

27. The semiconductor package according to claim 26, wherein: The first master external circuit block and the first master internal circuit block transmit a data signal and a data strobe signal, and The second master external circuit block and the second master internal circuit block transmit a clock signal, a chip selection signal, a command signal, and an address signal.

28. The semiconductor package according to claim 25, wherein: The first main external circuit block and the first main internal circuit block are disposed adjacent to each other and electrically connected to each other; and The second main external circuit block and the second main internal circuit block are disposed adjacent to each other and are electrically connected to each other.

29. The semiconductor package according to claim 28, wherein: The first main external circuit block, the first main internal circuit block, and the bit lines of the main cell bank are connected in series, and The second main external circuit block, the second main internal circuit block, and word lines of the main cell bank are connected in series.

30. The semiconductor package according to claim 25, The slave memory chip includes a slave cell library and a slave peripheral circuit, and The slave peripheral circuit comprises: a first slave external circuit block electrically connected to the first slave external pad; a first slave internal circuit block electrically connected to the first slave internal pad; a second slave external circuit block electrically connected to the second slave external pad; as well as A second slave internal circuit block is electrically connected to the second slave internal pad.

31. The semiconductor package according to claim 30, wherein: The first master external circuit block, the first slave internal circuit block, and the bit lines of the slave cell library are connected in series; and The second master external circuit block, the second slave internal circuit block, and word lines of the slave cell library are connected in series.

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