Solar cell, preparation method thereof and photovoltaic module

Abstract

The invention provides a solar cell, a preparation method thereof and a photovoltaic module. The solar cell includes: a substrate; the first tunneling oxide layer is located on the surface of one side of the substrate; the first phosphorus doped layer is located on the surface of one side, far away from the substrate, of the first tunneling oxide layer; the second tunneling oxide layer is located on the surface of the side, away from the first tunneling oxide layer, of the first phosphorus-doped layer; the second phosphorus-doped layer is located on the surface of one side, far away from the first phosphorus-doped layer, of the second tunneling oxide layer; the third tunneling oxide layer is located on the surface of the side, away from the second tunneling oxide layer, of the second phosphorus-doped layer. The third phosphorus-doped layer is located on the surface of one side, far away from the second phosphorus-doped layer, of the third tunneling oxide layer; wherein the doping concentration of phosphorus in the first phosphorus-doped layer is smaller than the doping concentration of phosphorus in the second phosphorus-doped layer, and the doping concentration of phosphorus in the second phosphorus-doped layer is smaller than the doping concentration of phosphorus in the third phosphorus-doped layer. The solar cell has a good passivation effect.

Description

Technical Field

[0001] The present application relates to the technical field of solar cells, and in particular to a solar cell and a preparation method thereof, and a photovoltaic module. Background Art

[0002] As society continues to develop, people's demand for energy has increased significantly, and the deepening of ecological and green environmental protection concepts has led to the rapid development of clean energy applications. Photovoltaic solar cells have been widely recognized and developed rapidly in this context.

[0003] Metal contact recombination of solar cells and losses caused by current transmission are two important conditions that limit the improvement of solar cell efficiency. TOPCon (tunneling oxide contact) cells were born under such conditions. They have a tunneling oxide layer and a phosphorus-doped polysilicon layer on the back, which can greatly reduce the contact recombination between the back surface and the metal paste. Among them, the phosphorus-doped polysilicon layer needs to be annealed after deposition. Through high-temperature annealing, the transformation from amorphous silicon to polysilicon is completed, and the phosphorus atoms are redistributed. However, current cells still have problems such as poor passivation effect and poor contact between the phosphorus-doped layer and the metal electrode.

[0004] It should be noted that the above content is not necessarily prior art, nor is it intended to limit the scope of patent protection of this application. Summary of the invention

[0005] The embodiments of the present application provide a solar cell and a method for preparing the same, and a photovoltaic module to solve or alleviate one or more of the technical problems mentioned above.

[0006] According to a first aspect of an embodiment of the present application, a solar cell is provided, comprising: a substrate; a first tunneling oxide layer, the first tunneling oxide layer being located on one side surface of the substrate; a first phosphorus-doped layer, the first phosphorus-doped layer being located on one side surface of the first tunneling oxide layer away from the substrate; a second tunneling oxide layer, the second tunneling oxide layer being located on one side surface of the first phosphorus-doped layer away from the first tunneling oxide layer; a second phosphorus-doped layer, the second phosphorus-doped layer being located on one side surface of the second tunneling oxide layer away from the first phosphorus-doped layer; a third tunneling oxide layer, the third tunneling oxide layer being located on one side surface of the second phosphorus-doped layer away from the second tunneling oxide layer; a third phosphorus-doped layer, the third phosphorus-doped layer being located on one side surface of the third tunneling oxide layer away from the second phosphorus-doped layer; wherein the doping concentration of phosphorus in the first phosphorus-doped layer is less than the doping concentration of phosphorus in the second phosphorus-doped layer, and the doping concentration of phosphorus in the second phosphorus-doped layer is less than the doping concentration of phosphorus in the third phosphorus-doped layer.

[0007] The solar cell of the embodiment of the present application can improve the contact between the phosphorus-doped layer and the electrode, reduce the tunneling resistance and enhance the passivation effect. Specifically, a stacked structure of three tunneling oxide layers and three phosphorus-doped layers is adopted, and such a structure can enhance the carrier concentration of each phosphorus-doped layer. The doping concentration of phosphorus in the third phosphorus-doped layer in the stacked structure can be further improved, so that the third phosphorus-doped layer with a larger surface concentration improves its contact with the metal electrode. This improved contact can also increase the selection window of the metal slurry (the slurry formula can be selected in a wider range, such as electrode slurry with less corrosiveness), and the process window of the sintering of the electrode slurry is also reduced simultaneously (sintering peak temperature 660-770°C). The design of the stacked structure also establishes a good barrier difference to form an additional field passivation effect. The second tunneling oxide layer and the third tunneling oxide layer can also block the diffusion of phosphorus, so that the doping level of phosphorus in the first phosphorus-doped layer is uniform and controllable, further enhancing the passivation effect of the solar cell.

[0008] According to an embodiment of the present application, the phosphorus doping concentration ρ1 in the first phosphorus doped layer is 1.1E 19 -8.0E 19 cm -3 .

[0009] According to an embodiment of the present application, the phosphorus doping concentration ρ2 in the second phosphorus doped layer is 8.0E 19 -6.0E 20 cm -3 .

[0010] According to an embodiment of the present application, the phosphorus doping concentration ρ3 in the third phosphorus doped layer is 6.0E 20 -1.2E 21 cm -3 .

[0011] According to an embodiment of the present application, the thickness of the first phosphorus-doped layer is 20-40 nm.

[0012] According to an embodiment of the present application, the thickness of the second phosphorus-doped layer is 25-50 nm.

[0013] According to an embodiment of the present application, the thickness of the third phosphorus-doped layer is 40-60 nm.

[0014] According to an embodiment of the present application, the thickness of the first tunneling oxide layer is 0.8-2 nm.

[0015] According to an embodiment of the present application, the thickness of the second tunneling oxide layer is 0.5-1.6 nm.

[0016] According to an embodiment of the present application, the thickness of the third tunnel oxide layer is 0.5-1.6 nm.

[0017] According to a second aspect of an embodiment of the present application, a method for preparing a solar cell is provided, comprising the following steps: providing a substrate; performing a first oxidation treatment on a surface of one side of the substrate to obtain a first tunneling oxide layer; performing a first deposition treatment on a surface of the first tunneling oxide layer away from the substrate to obtain a first phosphorus-doped amorphous silicon layer; performing a second oxidation treatment on a surface of the first phosphorus-doped amorphous silicon layer away from the first tunneling oxide layer to obtain a second tunneling oxide layer; performing a second deposition treatment on a surface of the second tunneling oxide layer away from the first phosphorus-doped amorphous silicon layer to obtain a second phosphorus-doped amorphous silicon layer; performing a deposition treatment on a surface of the second phosphorus-doped amorphous silicon layer away from the second tunneling oxide layer; A third oxidation treatment is performed to obtain a third tunneling oxide layer; a third deposition treatment is performed on the surface of the third tunneling oxide layer away from the second phosphorus-doped amorphous silicon layer to obtain a third phosphorus-doped amorphous silicon layer; a fourth deposition treatment is performed on the surface of the third phosphorus-doped amorphous silicon layer away from the third tunneling oxide layer to obtain a protective layer; the resultant with the protective layer is annealed to obtain a first phosphorus-doped layer, a second phosphorus-doped layer, and a third phosphorus-doped layer; wherein the phosphorus doping concentration in the first phosphorus-doped amorphous silicon layer is less than the phosphorus doping concentration in the second phosphorus-doped amorphous silicon layer, and the phosphorus doping concentration in the second phosphorus-doped amorphous silicon layer is less than the phosphorus doping concentration in the third phosphorus-doped amorphous silicon layer. The method of the embodiment of the present application forms a first phosphorus-doped layer, a second phosphorus-doped layer, and a third phosphorus-doped layer with a concentration gradient by layer-by-layer preparation, and the stacked structure forms a gradient potential barrier difference, and the potential barrier difference forms an additional field passivation effect to improve the passivation effect. The obtained solar cell has a lower tunneling resistance and a better passivation effect. And the phosphorus doping concentration in the third phosphorus doping is made higher, so that the selection window of electrode slurry becomes wider (the slurry formula can be selected in a wider range, such as electrode slurry with less corrosiveness), and the sintering process window of electrode slurry is also reduced simultaneously (sintering peak temperature 660-770℃).

[0018] According to an embodiment of the present application, the time of the first oxidation treatment is 50-80s.

[0019] According to an embodiment of the present application, the time of the second oxidation treatment is 20-50s.

[0020] According to an embodiment of the present application, the duration of the third oxidation treatment is 20-40 seconds.

[0021] According to an embodiment of the present application, the thickness of the protective layer is 10-70 nm.

[0022] According to an embodiment of the present application, the annealing treatment is performed at 800°C-920°C.

[0023] According to an embodiment of the present application, the annealing time is 1500s-2600s.

[0024] According to an embodiment of the present application, the method further comprises a removal treatment, wherein the removal treatment is performed using an HF solution having a concentration of 8-10 wt %.

[0025] According to an embodiment of the present application, the method further includes: forming an electrode on a surface of a side of the third phosphorus-doped layer away from the third tunneling oxide layer to obtain the solar cell.

[0026] According to a third aspect of the embodiments of the present application, a photovoltaic module is provided, wherein the photovoltaic module comprises the solar cell according to the first aspect or the solar cell prepared by the method according to the second aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the multiple drawings represent the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings only depict some embodiments disclosed in the present application and should not be regarded as limiting the scope of the present application.

[0028] Figure 1 Schematic diagram of the structure of solar cells in some embodiments.

[0029] Reference numerals: 1: substrate; 2: first tunneling oxide layer; 3: first phosphorus-doped layer; 4: second tunneling oxide layer; 5: second phosphorus-doped layer; 6: third tunneling oxide layer; 7: third phosphorus-doped layer; 8: anti-reflection layer; 9: boron-doped layer; 10: passivation layer; 11: second electrode; 12: first electrode. DETAILED DESCRIPTION

[0030] Embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings. In the accompanying drawings, for clarity, the sizes of layers, regions, elements and their relative sizes may be exaggerated. Wherein the same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limitations on the present application. It should be noted that, in the absence of conflict, the embodiments in the present application and the features in the embodiments can be combined with each other.

[0031] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. When the second element, component, region, layer or part is discussed, it does not indicate that the present application necessarily has the first element, component, region, layer or part.

[0032] In this application, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0033] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein, for example. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0034] In the present application, when it comes to a numerical interval (i.e., a numerical range), unless otherwise specified, the distribution of the optional numerical values ​​in the numerical interval is considered to be continuous, and includes the two numerical endpoints (i.e., the minimum and maximum values) of the numerical interval, and each numerical value between the two numerical endpoints. Unless otherwise specified, when the numerical interval only refers to an integer in the numerical interval, it includes the two endpoint integers of the numerical range, and each integer between the two endpoints, which is equivalent to directly listing each integer. When multiple numerical ranges are provided to describe features or characteristics, these numerical ranges can be merged. In other words, unless otherwise specified, the numerical range disclosed in the present application should be understood to include any and all sub-ranges included therein. The "numerical value" in the numerical interval can be any quantitative value, such as a number, a percentage, a ratio, etc. "Numerical interval" allows for broadly including quantitative intervals such as percentage intervals, ratio intervals, and ratio intervals.

[0035] At present, amorphous silicon stacking technology is mostly used to solve the passivation problem of batteries. The first layer of amorphous silicon uses a lower concentration of P atoms to prevent its inward expansion. The second layer of amorphous silicon uses a higher concentration of P atoms to enable better ohmic contact with the metal electrode. However, there are still some problems. For example, in the subsequent annealing and crystallization process, the P atoms in the second amorphous silicon will gradually be added to the first amorphous silicon layer, and the concentrations of the last two layers will tend to be consistent, thus failing to achieve the original purpose. In addition, for the control of P atom concentration, too high a concentration will cause P atoms to break through the tunneling oxide layer, destroying the interface passivation effect of the silicon substrate and the tunneling oxide layer; too low a concentration will increase the back tunneling resistance and worsen the contact with the metal electrode.

[0036] According to a first aspect of the embodiments of the present application, a solar cell is provided. Figure 1 The solar cell comprises a substrate 1; a first tunneling oxide layer 2, the first tunneling oxide layer 2 is located on one side surface of the substrate 1; a first phosphorus-doped layer 3, the first phosphorus-doped layer 3 is located on one side surface of the first tunneling oxide layer 2 away from the substrate 1; a second tunneling oxide layer 4, the second tunneling oxide layer 4 is located on one side surface of the first phosphorus-doped layer 3 away from the first tunneling oxide layer 2; a second phosphorus-doped layer 5, the second phosphorus-doped layer 5 is located on one side surface of the second tunneling oxide layer 4 away from the first phosphorus-doped layer 3; a third tunneling oxide layer 6, the third tunneling oxide layer 6 is located on one side surface of the second phosphorus-doped layer 5 away from the second tunneling oxide layer 4; a third phosphorus-doped layer 7, the third phosphorus-doped layer 7 is located on one side surface of the third tunneling oxide layer 6 away from the second phosphorus-doped layer 5; wherein the phosphorus doping concentration in the first phosphorus-doped layer is less than the phosphorus doping concentration in the second phosphorus-doped layer, and the phosphorus doping concentration in the second phosphorus-doped layer is less than the phosphorus doping concentration in the third phosphorus-doped layer.

[0037] The solar cell of the embodiment of the present application can improve the contact between the phosphorus-doped layer and the electrode, reduce the tunneling resistance and enhance the passivation effect. Specifically, a stacked structure of three tunneling oxide layers and three phosphorus-doped layers is adopted, and such a structure can enhance the carrier concentration of each phosphorus-doped layer. The doping concentration of phosphorus in the third phosphorus-doped layer in the stacked structure can be further improved, so that the third phosphorus-doped layer with a larger surface concentration improves its contact with the metal electrode. This improved contact can also increase the selection window of the metal slurry (the slurry formula can be selected in a wider range, such as electrode slurry with less corrosiveness), and the process window of the sintering of the electrode slurry is also reduced simultaneously (sintering peak temperature 660-770°C). The design of the stacked structure also establishes a good barrier difference to form an additional field passivation effect. The second tunneling oxide layer and the third tunneling oxide layer can also block the diffusion of phosphorus, so that the doping level of phosphorus in the first phosphorus-doped layer is uniform and controllable, further enhancing the passivation effect of the solar cell.

[0038] In some embodiments, the solar cell is a TOPcon cell.

[0039] In some embodiments, the substrate includes a silicon wafer, and the substrate has a velvet structure.

[0040] Optionally, the thickness of the substrate is 130-150 nm.

[0041] In some embodiments, the first tunnel oxide layer, the second tunnel oxide layer, and the third tunnel oxide layer each independently comprise silicon dioxide.

[0042] In some embodiments, the thickness of the first tunneling oxide layer is 0.8-2 nm, which is beneficial to the tunneling of electrons and blocks the diffusion of phosphorus into the substrate.

[0043] In some embodiments, the thickness of the second tunneling oxide layer is 0.5-1.6 nm, which is beneficial to the secondary tunneling of electrons.

[0044] In some embodiments, the thickness of the third tunnel oxide layer is 0.5-1.6 nm, which is helpful to block the inward diffusion of phosphorus in the third phosphorus-doped layer, so that more phosphorus is retained in the surface layer, improves contact, and increases the selection window of the metal paste.

[0045] According to an embodiment of the present application, the first phosphorus-doped layer, the second phosphorus-doped layer and the third phosphorus-doped layer are stacked, and the phosphorus doping concentration in the first phosphorus-doped layer is less than the phosphorus doping concentration in the second phosphorus-doped layer, and the phosphorus doping concentration in the second phosphorus-doped layer is less than the phosphorus doping concentration in the third phosphorus-doped layer. Such a stacked structure design also establishes a good potential barrier difference, forming an additional field passivation effect.

[0046] Optionally, the phosphorus doping concentration ρ1 in the first phosphorus doped layer is 1.1E 19 -8.0E 19 cm -3 This is beneficial to control the concentration of phosphorus diffusion into the silicon substrate, preventing the diffusion through to form a dark film.

[0047] Optionally, the phosphorus doping concentration ρ2 in the second phosphorus doped layer is 8.0E 19 -6.0E 20 cm -3 This is conducive to establishing a good potential barrier difference and forming an additional field passivation effect.

[0048] Optionally, the phosphorus doping concentration ρ3 in the third phosphorus doped layer is 6.0E 20 -1.2E 21 cm -3 This helps to increase the phosphorus concentration on the cell surface, improve the contact with the metal electrode, and increase the selection window of the metal paste.

[0049] In some embodiments, the total thickness of the first phosphorus-doped layer, the second phosphorus-doped layer, and the phosphorus-doped layer is 80-150 nm.

[0050] Optionally, the thickness of the first phosphorus-doped layer is 20-40 nm.

[0051] Optionally, the thickness of the second phosphorus-doped layer is 25-50 nm.

[0052] Optionally, the thickness of the third phosphorus-doped layer is 40-60 nm. A thicker third phosphorus-doped layer is beneficial to the formation of phosphorus doping, which is beneficial to increasing the phosphorus concentration on the surface of the cell, improving the contact with the metal electrode, increasing the selection window of the metal paste, and forming a good potential barrier with the first phosphorus-doped layer and the second phosphorus-doped layer.

[0053] In some embodiments, reference Figure 1 , further comprising a first electrode 12, wherein the first electrode 12 is in contact with the third phosphorus-doped layer 7. The third phosphorus-doped layer has a higher phosphorus doping concentration. As the concentration is high, the phosphorus element contains more charges, and the charges can be in contact with the metal electrode to conduct and form a current.

[0054] In some embodiments, reference Figure 1 , further comprising: a boron-doped layer 9 and a passivation layer 10, wherein the boron-doped layer 9 is located on the front surface of the substrate 1, and the passivation layer 10 is located on the side surface of the boron-doped layer 9 away from the substrate 1. The thickness of the boron-doped layer is 70-1200 nm. The boron-doped layer within the aforementioned thickness range can reduce the risk of electrode burn-through and reduce the current loss caused by free carrier absorption.

[0055] In some embodiments, a second electrode 11 is further included, and the second electrode 11 is in contact with the boron-doped layer 9 .

[0056] In some embodiments, the first electrode and the second electrode each independently include a silver electrode or an aluminum electrode.

[0057] In some embodiments, an anti-reflection layer 8 is further included, and the anti-reflection layer 8 is located on the surface of the third phosphorus-doped layer 7 away from the substrate 1, and on the surface of the passivation layer 10 away from the boron-doped layer 9. The design of the passivation layer is conducive to improving the photoelectric efficiency of the battery.

[0058] Optionally, the thickness of the passivation layer is 10-70 nm.

[0059] Optionally, the material of the passivation layer includes TMA (aluminum oxide), silicon nitride, silicon oxynitride, silicon dioxide, or a combination thereof.

[0060] In some embodiments, the FF (fill factor) of the solar cell is improved by 0.1%-0.15%.

[0061] In some embodiments, the Voc (open circuit voltage) of the solar cell is increased by 0.5-1 mv.

[0062] According to a second aspect of an embodiment of the present application, a method for preparing a solar cell is provided, comprising the following steps: (1) providing a substrate; (2) performing a first oxidation treatment on a surface of one side of the substrate to obtain a first tunneling oxide layer; (3) performing a first deposition treatment on a surface of the first tunneling oxide layer away from the substrate to obtain a first phosphorus-doped amorphous silicon layer; (4) performing a second oxidation treatment on a surface of the first phosphorus-doped amorphous silicon layer away from the first tunneling oxide layer to obtain a second tunneling oxide layer; (5) performing a second deposition treatment on a surface of the second tunneling oxide layer away from the first phosphorus-doped amorphous silicon layer to obtain a second phosphorus-doped amorphous silicon layer; and (6) performing a first deposition treatment on a surface of the second phosphorus-doped amorphous silicon layer away from the second tunneling oxide layer. (7) performing a third oxidation treatment on the surface to obtain a third tunneling oxide layer; (8) performing a fourth deposition treatment on the surface of the third phosphorus-doped amorphous silicon layer away from the third tunneling oxide layer to obtain a protective layer; (9) performing an annealing treatment on the resultant with the protective layer to obtain a first phosphorus-doped layer, a second phosphorus-doped layer, and a third phosphorus-doped layer; wherein the phosphorus doping concentration in the first phosphorus-doped amorphous silicon layer is less than the phosphorus doping concentration in the second phosphorus-doped amorphous silicon layer, and the phosphorus doping concentration in the second phosphorus-doped amorphous silicon layer is less than the phosphorus doping concentration in the third phosphorus-doped amorphous silicon layer.

[0063] The method of the embodiment of the present application forms a first phosphorus-doped layer, a second phosphorus-doped layer, and a third phosphorus-doped layer with a concentration gradient by layer-by-layer preparation. The laminated structure forms a gradient barrier difference, and the barrier difference forms an additional field passivation effect to enhance the passivation effect. The obtained solar cell has a lower tunneling resistance and a better passivation effect. And the phosphorus doping concentration in the third phosphorus doping is made higher, so that the selection window of the electrode slurry becomes wider (the slurry formula can be selected in a wider range, such as electrode slurry with less corrosiveness), and the process window of the sintering of the electrode slurry is also reduced synchronously (sintering peak temperature 660-770°C).

[0064] According to an embodiment of the present application, step (1) provides a substrate.

[0065] In some embodiments, step (1) also includes texturing and cleaning the substrate to remove dirt and metal impurities on the surface of the substrate, and to remove the mechanical damage layer of the substrate generated during the cutting process, thereby reducing the recombination center and forming an uneven velvet surface to enhance the silicon wafer's absorption of sunlight and reduce reflectivity.

[0066] Optionally, a uniform “positive pyramid” velvet surface is formed on two opposite surfaces of the substrate, and the velvet surface height is 0.5-3 μm.

[0067] In some embodiments, after step (1) and before step (2), the process further includes: performing boron doping on the front side of the substrate to form a boron doped layer and a borosilicate glass layer on the surface of the substrate, wherein the borosilicate glass layer includes a boron-rich layer, and performing a fourth oxidation treatment on the boron doped layer. P-type impurities are diffused on the substrate to achieve a suitable doping concentration and square resistance, and to obtain a depth suitable for the PN junction of the solar cell. A phosphosilicate glass layer is also generated on the surface of the front doped layer, and the phosphosilicate glass layer is composed of a stacked boron-rich layer and an oxide layer, and the oxide layer is close to the doped layer.

[0068] In some embodiments, the temperature during the boron doping diffusion is 600-1000° C. and the time is 60-120 seconds. After the boron is diffused, P-type impurities are diffused on the N-type substrate to form a PN junction, reaching a suitable doping concentration ρ / square resistance R.

[0069] In some embodiments, the boron source in the boron doping diffusion process includes at least one of BCl 3 and BBr 3 .

[0070] In some embodiments, the substrate includes an N-type silicon wafer.

[0071] In some embodiments, the boron doped layer has a thickness of 70-1200 nm, for example, 70 nm, 160 nm, 260 nm, 380 nm, 500 nm, 600 nm, 800 nm, 900 nm, 1100 nm, 1200 nm, etc.

[0072] In some embodiments, the back side and the side of the substrate after the boron doping layer is formed are respectively etched at a first degree to remove the borosilicate glass layer on the back side and the side and etch and polish the back side to increase the back side reflectivity, thereby improving the long-wave absorption of the silicon wafer and making the back side more solid to reduce the recombination of surface dangling bonds.

[0073] In some embodiments, the removal of the borosilicate glass layer on the back and sides is performed by chain pickling the substrate after the first winding etching using an HF solution.

[0074] Optionally, the concentration of HF is 0.5-10wt%, for example, 0.5wt%, 1wt%, 2wt%, 5wt%, 10wt%, etc.

[0075] In some embodiments, the backside etching further includes a polishing process, and the polishing process is performed in an alkaline solution, and the alkaline solution includes a sodium hydroxide solution or a potassium hydroxide solution.

[0076] Optionally, the concentration of the sodium hydroxide solution is 0.5-5wt%, for example, 0.5wt%, 1wt%, 2wt%, 3wt%, 4wt%, 5wt%, etc.

[0077] In some embodiments, the fourth oxidation treatment may reduce the surface concentration of the boron doped layer.

[0078] Optionally, the conditions of the fourth oxidation treatment include an oxidation temperature of 1000-1050° C. and an oxidation time of 2000-3000 s.

[0079] According to an embodiment of the present application, in step (2), a first oxidation treatment is performed on one side surface of the substrate to obtain a first tunneling oxide layer. The first tunneling oxide layer can provide a tunneling channel, selectively pass electrons, and form an interface chemical passivation to prevent excessive phosphorus in the N-type doped layer from entering the silicon wafer.

[0080] It can be understood that the first tunnel oxide layer is formed on the back side of the substrate.

[0081] In some embodiments, the conditions of the first oxidation treatment include growing a first tunnel oxide layer on the back side of the silicon wafer using a PECVD device at a temperature of 400-450° C. and a protective gas.

[0082] Optionally, the protective gas includes at least one of N2O and N2.

[0083] Optionally, the power of the PECVD device is 10000-15000 W. This is conducive to the full ionization of the reaction gas to obtain a uniform and dense first tunnel oxide layer.

[0084] Optionally, a protective gas is introduced into the furnace tube with a flow volume of 9000-20000 sccm.

[0085] Optionally, the duty ratio (NO:OFF) is 20:2000. In this way, a uniform and dense first tunnel oxide layer can be obtained.

[0086] Optionally, the first oxidation treatment time is 80-120 seconds, so that a first tunneling oxide layer with a target thickness can be obtained.

[0087] Optionally, the thickness of the first tunnel oxide layer is 0.8-2 nm.

[0088] According to an embodiment of the present application, in step (3), a first deposition process is performed on a surface of the first tunnel oxide layer away from the substrate to obtain a first phosphorus-doped amorphous silicon layer. + layer, forming lightly doped polysilicon and forming a good passivation contact structure.

[0089] In some embodiments, the process gas for the first deposition process is SiH4, PH4 and H 2。

[0090] In some embodiments, the temperature of the first deposition process is 400-450°C.

[0091] In some embodiments, the first deposition treatment uses PEVCD (Plasma Enhanced Deposition) to introduce process gas and in-situ doping to obtain a first phosphorus-doped amorphous silicon layer.

[0092] Optionally, the power of the PEVCD device is 10000-15000 W. This is conducive to the full ionization of the reaction gas to obtain a uniformly doped first phosphorus-doped amorphous silicon layer.

[0093] Optionally, the first deposition process lasts for 160-260 seconds, which is conducive to obtaining the first phosphorus-doped amorphous silicon layer with a target thickness.

[0094] Optionally, the flow volume of SiH4 is 2000-5000 sccm, the flow volume of PH4 is 300-500 sccm, and the flow volume of H2 is 8000-12000 sccm. This is conducive to the diffusion of surface atoms, making the surface of the first phosphorus-doped amorphous silicon layer more flat and uniform.

[0095] Optionally, the thickness of the first phosphorus-doped amorphous silicon layer is 20-40 nm.

[0096] According to an embodiment of the present application, in step (4), a second oxidation treatment is performed on a surface of the first phosphorus-doped amorphous silicon layer away from the first tunneling oxide layer to obtain a second tunneling oxide layer. The second tunneling oxide layer can provide a tunneling channel, selectively pass electrons, and form an interface chemical passivation to prevent phosphorus in the second phosphorus-doped layer from diffusing toward the substrate side.

[0097] In some embodiments, the second oxidation treatment conditions include using a PECVD device at a temperature of 400° C. to 450° C. and a protective gas to grow a second tunnel oxide layer.

[0098] Optionally, the protective gas includes at least one of N2O and N2.

[0099] Optionally, the power of the PECVD device is 10000-15000 W. This is conducive to the full ionization of the reaction gas to obtain a uniform and dense second tunnel oxide layer.

[0100] Optionally, a protective gas is introduced into the furnace tube with a flow volume of 9000-20000 sccm.

[0101] Optionally, the second oxidation treatment time is 20-50 seconds, which is conducive to obtaining a second tunnel oxide layer with a target thickness.

[0102] Optionally, the thickness of the second tunnel oxide layer is 0.5-1.6 nm.

[0103] According to an embodiment of the present application, in step (5), a second deposition process is performed on a surface of the second tunnel oxide layer away from the first phosphorus-doped amorphous silicon layer to obtain a second phosphorus-doped amorphous silicon layer. + layer, forming heavily doped polysilicon and forming a good passivation contact structure.

[0104] In some embodiments, the process gases for the second deposition process are SiH4, PH4, and H2.

[0105] In some embodiments, the temperature of the second deposition process is 400-450°C.

[0106] In some embodiments, the second deposition process uses PEVCD (Plasma Enhanced Deposition) to introduce process gas to in-situ dope the second phosphorus-doped amorphous silicon layer.

[0107] Optionally, the power of the PEVCD device is 10000-15000 W. This is conducive to the full ionization of the reaction gas to obtain a uniformly doped second phosphorus-doped amorphous silicon layer.

[0108] Optionally, the second deposition process lasts for 160-260 seconds, which is conducive to obtaining a second phosphorus-doped amorphous silicon layer with a target thickness.

[0109] Optionally, the flow volume of SiH4 is 2000-5000 sccm, the flow volume of PH4 is 300-500 sccm, and the flow volume of H2 is 8000-12000 sccm. This is conducive to the diffusion of surface atoms, making the surface of the second phosphorus-doped amorphous silicon layer more flat and uniform.

[0110] Optionally, the thickness of the second phosphorus-doped amorphous silicon layer is 25-50 nm.

[0111] According to an embodiment of the present application, in step (6), a second oxidation treatment is performed on a surface of the second phosphorus-doped amorphous silicon layer away from the second tunnel oxide layer to obtain a third tunnel oxide layer. The third tunnel oxide layer can provide a tunnel channel, selectively pass electrons, and form an interface chemical passivation to prevent phosphorus in the third phosphorus-doped layer from diffusing toward the substrate side.

[0112] In some embodiments, the conditions of the third oxidation treatment include using a PECVD device at a temperature of 400° C. to 450° C. and a protective gas to grow a third tunnel oxide layer.

[0113] Optionally, the protective gas includes at least one of N2O and N2.

[0114] Optionally, the power of the PECVD device is 10000-15000 W. This is conducive to the full ionization of the reaction gas to obtain a dense and uniform third tunnel oxide layer.

[0115] Optionally, a protective gas is introduced into the furnace tube with a flow volume of 9000-20000 sccm.

[0116] Optionally, the third oxidation treatment lasts for 20-40 seconds, which is conducive to obtaining a third tunnel oxide layer with a target thickness.

[0117] Optionally, the thickness of the third tunnel oxide layer is 0.5-1.6 nm.

[0118] According to an embodiment of the present application, in step (7), a third deposition process is performed on a surface of the third tunnel oxide layer away from the second phosphorus-doped amorphous silicon layer to obtain a third phosphorus-doped amorphous silicon layer. + layer, forming heavily doped polysilicon and forming a good passivation contact structure.

[0119] In some embodiments, the process gases of the third deposition process are SiH 4 , PH 4 , and H 2 .

[0120] In some embodiments, the temperature of the third deposition process is 400-450°C.

[0121] In some embodiments, the third deposition process uses a PEVCD (Plasma Enhanced Deposition) method to introduce process gas to in-situ dope the third phosphorus-doped amorphous silicon layer.

[0122] Optionally, the power of the PEVCD device is 10000-15000 W. This is conducive to the full ionization of the reaction gas to obtain a uniformly doped third phosphorus-doped amorphous silicon layer.

[0123] Optionally, the third deposition process lasts for 260-400 seconds, which is conducive to obtaining the third phosphorus-doped amorphous silicon layer with a target thickness.

[0124] Optionally, the flow volume of SiH4 is 2000-5000 sccm, the flow volume of PH4 is 300-500 sccm, and the flow volume of H2 is 8000-12000 sccm. This is conducive to the diffusion of surface atoms, making the surface of the third phosphorus-doped amorphous silicon layer more flat and uniform.

[0125] Optionally, the thickness of the third phosphorus-doped amorphous silicon layer is 40-60 nm.

[0126] In some embodiments, the first oxidation treatment time is 80-120s; the second oxidation treatment time is 20-50s; the third oxidation treatment time is 20-40s, and the first oxidation treatment time is controlled to be greater than the second oxidation treatment time and greater than the third oxidation treatment time. In this way, tunnel oxide layers with different thicknesses can be obtained, and the thickness of the first tunnel oxide layer is greater than the thickness of the second tunnel oxide layer and greater than the thickness of the third tunnel oxide layer, so as to protect the silicon substrate and prevent it from being penetrated by phosphorus.

[0127] In some embodiments, the thickness of the first phosphorus-doped amorphous silicon layer is 20-40 nm; the thickness of the second phosphorus-doped amorphous silicon layer is 20-50 nm; the thickness of the third phosphorus-doped amorphous silicon layer is 40-60 nm, and the thicknesses of the first phosphorus-doped amorphous silicon layer, the second phosphorus-doped amorphous silicon layer, and the third phosphorus-doped amorphous silicon layer are controlled to increase in sequence. In this way, the first phosphorus-doped layer, the second phosphorus-doped layer, and the third phosphorus-doped layer with increasing phosphorus doping concentrations can be obtained.

[0128] According to an embodiment of the present application, in step (8), a fourth deposition process is performed on the surface of the third phosphorus-doped layer away from the third tunnel oxide layer to obtain a protective layer. The protective layer is used to block impurities in the air from entering the amorphous silicon layer and to reduce corrosion of the internal phosphorus-doped amorphous silicon layer (the first phosphorus-doped amorphous silicon layer, the second phosphorus-doped amorphous silicon layer, and the third phosphorus-doped amorphous silicon layer) during cleaning.

[0129] In some embodiments, the process gases of the fourth deposition process are SiH 4 and N 2 O.

[0130] In some embodiments, the temperature of the fourth deposition process is 400-450°C.

[0131] In some embodiments, the fourth deposition process uses PEVCD (Plasma Enhanced Deposition) to introduce process gas to form a silicon oxide protective layer.

[0132] Optionally, the power of the PEVCD device is 10000-15000w.

[0133] Optionally, the fourth deposition process lasts for 30-70 seconds, which is conducive to obtaining a protective layer with a target thickness.

[0134] Optionally, the SiH4 flow volume is 1000-2000sccm, and the N2O flow volume is 7000-9000sccm.

[0135] Optionally, the thickness of the protective layer is 10-70 nm, which is helpful to prevent impurities in the air from entering the amorphous silicon layer and reduce the corrosion of the internal phosphorus-doped amorphous silicon layer (the first phosphorus-doped amorphous silicon layer, the second phosphorus-doped amorphous silicon layer, and the third phosphorus-doped amorphous silicon layer) during cleaning.

[0136] According to an embodiment of the present application, in step (9), the resultant having the protective layer is annealed to obtain a first phosphorus-doped layer, a second phosphorus-doped layer, and a third phosphorus-doped layer. In this step, the amorphous silicon in the first phosphorus-doped amorphous silicon, the second phosphorus-doped amorphous silicon, and the third phosphorus-doped amorphous silicon is converted into polycrystalline silicon by annealing to obtain the first phosphorus-doped layer, the second phosphorus-doped layer, and the third phosphorus-doped layer.

[0137] Optionally, the annealing temperature is 800°C-920°C.

[0138] Optionally, the annealing time is 1500s-2600s.

[0139] In some embodiments, the method further includes step (10): removing treatment, so as to remove the oxide layer on the surface.

[0140] Optionally, the removal treatment is performed using an HF solution with a concentration of 8-10wt%.

[0141] In some embodiments, the step further includes (11): forming an electrode on a surface of the third phosphorus-doped layer away from the third tunnel oxide layer.

[0142] Optionally, the printing and drying of the electrode slurry is performed by screen printing.

[0143] In some embodiments, before forming the electrode, the method further includes: depositing an anti-reflection layer on a surface of the third phosphorus-doped layer away from the third tunnel oxide layer, and depositing a passivation layer on a surface of the anti-reflection layer away from the third phosphorus-doped layer and a surface of the boron-doped layer away from the substrate.

[0144] Optionally, the anti-reflection layer is deposited using a PEVCD device.

[0145] In some embodiments, the method further comprises step (13): injecting light into the resultant having the electrode to obtain a solar cell.

[0146] Optionally, the light injection temperature is 200-300°C.

[0147] In some embodiments, the method further comprises step (14): performing laser-assisted sintering on the product obtained after light injection. Laser-assisted sintering is used to improve the contact effect between the solar cell electrode and the doping layer (such as the boron-doping layer or the phosphorus-doping layer).

[0148] Optionally, the conditions for laser irradiation sintering are: using high-intensity laser irradiation and applying a deflection voltage of 10-15V at the same time.

[0149] Optionally, the photoelectric conversion efficiency of the solar cell can be improved by 0.2-0.5%.

[0150] According to a third aspect of the embodiments of the present application, a photovoltaic module is provided, wherein the photovoltaic module comprises the solar cell according to the first aspect or the solar cell prepared by the method according to the second aspect.

[0151] In some embodiments, the photovoltaic module includes a plurality of solar cells connected in series and / or in parallel; wherein at least one of the solar cells of the first aspect or the solar cell prepared by the method of the second aspect. A plurality of solar cells in series form a cell string, and adjacent solar cells can be connected together by string welding.

[0152] In the fourth aspect of the embodiments of the present application, a photovoltaic system can be provided, including the photovoltaic components in any of the above embodiments. The advantages of the above photovoltaic components are also possessed by the photovoltaic system, which will not be repeated here. The above photovoltaic system has a wide range of applications, not only limited to photovoltaic power stations, such as ground power stations, rooftop power stations and water power stations, but also includes various equipment and devices that use solar energy to generate electricity, such as user solar power supplies, solar street lights, solar cars and solar buildings. Of course, it can be understood that the application scenarios of the photovoltaic system are not limited to this, that is to say, the photovoltaic system can be used in all fields where solar energy is required for power generation. Taking the photovoltaic power generation system network as an example, the photovoltaic system may include a photovoltaic array, a junction box and an inverter. The photovoltaic array may be an array combination of multiple photovoltaic components. For example, multiple photovoltaic components may form multiple photovoltaic arrays. The photovoltaic array is connected to the junction box, and the junction box can converge the current generated by the photovoltaic array. The converged current flows through the inverter and is converted into the alternating current required by the mains power grid, and then connected to the mains network to realize solar power supply.

[0153] Hereinafter, exemplary embodiments according to the present application will be described in more detail with reference to the accompanying drawings. It should be noted that these exemplary embodiments can be implemented in many different forms and should not be construed as being limited to the embodiments described herein.

[0154] Example 1 S1: Texturing and cleaning The N-type silicon wafer with a thickness of 120 μm was textured and cleaned to form a uniform "positive pyramid" texture surface on the two opposite surfaces of the silicon wafer, and the texture surface height was 3 μm.

[0155] S2: performing boron doping and fourth oxidation treatment on the front side of the N-type silicon wafer.

[0156] A 10nm thick boron-doped layer is diffused on the front side of the silicon wafer after texturing and cleaning.

[0157] S3: First winding etching The boron-doped substrate was chain-picked using a 5wt% HF solution.

[0158] The back side of the substrate is etched using a sodium hydroxide solution with a concentration of 5 wt %.

[0159] S4: Removal of Boron-Rich Layer The removal treatment uses a tank pickling method with a concentration of 3wt% HF.

[0160] S5: using plasma enhanced chemical vapor deposition equipment (PECVD), at a furnace temperature range of 400°C, N2 purging with a flow volume of 10,000 sccm to fully remove the air in the furnace tube; S6: At a furnace temperature of 400°C and a power of 11000w, N2O was introduced into the furnace tube with a flow volume of 10000sccm and a duty ratio (NO:OFF=20:2000) to prepare a first tunneling oxide layer for 60s. The back side of the silicon substrate was oxidized to form a first tunneling oxide layer with a thickness of 1.5nm. S7: At a temperature of 400° C. and a power of 11000 W, SiH4, PH4 and H2 are introduced into the furnace tube for deposition for 150 seconds, with a flow volume of 3000 sccm for SiH4, a flow volume of 400 sccm for PH4 and a flow volume of 10000 sccm for H2, to form a first phosphorus-doped amorphous silicon layer with a thickness of 30 nm on the first tunneling oxide layer; S8: At a furnace temperature of 400°C and a power of 11000w, N2O was introduced into the furnace tube with a flow volume of 10000sccm and a duty ratio (NO:OFF=20:2000) to prepare a first tunneling oxide layer for 35s to form a second tunneling oxide layer with a thickness of 0.7nm; S9: at a temperature of 4000° C. and a power of 11000 W, SiH4, PH4 and H2 are introduced into the furnace tube for deposition for 160 seconds, with a flow volume of 3000 sccm for SiH4, a flow volume of 400 sccm for PH4 and a flow volume of 10000 sccm for H2, to form a second phosphorus-doped amorphous silicon layer with a thickness of 35 nm on the second tunneling oxide layer; S10: at a furnace temperature of 400°C and a power of 11000w, N2O is introduced into the furnace tube with a flow volume of 10000sccm and a duty ratio (NO:OFF=20:2000) to prepare a first tunneling oxide layer for 30s to form a third tunneling oxide layer with a thickness of 0.45nm; S11: at a temperature of 4000° C. and a power of 11000 W, SiH4, PH4 and H2 are introduced into the furnace tube for deposition for 200 seconds, with a flow volume of 3000 sccm for SiH4, a flow volume of 400 sccm for PH4 and a flow volume of 10000 sccm for H2, to form a third phosphorus-doped amorphous silicon layer with a thickness of 50 nm on the third tunneling oxide layer; S12: At a temperature of 400°C and a power of 11000W, SiH4 and N2O were introduced into the furnace tube for reaction for 65s, with a flow volume range of 1500sccm for SiH4 and a flow volume range of 8000sccm for N2O, to form a protective layer with a thickness of 40nm; S13: Perform high temperature annealing at 900° C. for 1800 s and remove the protective layer to obtain a phosphorus doping concentration ρ1 of 4E in the first phosphorus doped layer. 19 cm -3 The phosphorus doping concentration ρ2 in the second phosphorus doped layer is 3E20 cm -3 The phosphorus doping concentration ρ3 in the third phosphorus doped layer is 1E 21 cm -3 ; S14: depositing a silicon nitride anti-reflection layer by a PECVD method; S15: printing silver paste on the silicon nitride anti-reflection layer, drying and sintering, and then performing light injection treatment; S16: Using laser-assisted sintering to complete the production of solar cells. The laser-assisted sintering conditions are to irradiate the cell with a high-intensity laser and apply a 12V deflection voltage at the same time.

[0161] Example 2 A solar cell was prepared in the manner of Example 1, except that, in step S7: at a temperature of 400° C. and a power of 11000 W, SiH4, PH4 and H2 were introduced into the furnace tube for deposition for 100 s, with a SiH4 flow volume of 3000 sccm, a PH4 flow volume of 400 sccm, and a H2 flow volume of 10000 sccm, to form a first phosphorus-doped amorphous silicon layer with a thickness of 12 nm on the first tunneling oxide layer; In S13: a high temperature annealing treatment is performed at a temperature of 900° C. for 1800 seconds, and the protective layer is removed to obtain a phosphorus doping concentration ρ1 of 1.1E in the first phosphorus doped layer. 19 cm -3 The phosphorus doping concentration ρ2 in the second phosphorus doped layer is 3E 20 cm -3 The phosphorus doping concentration ρ3 in the third phosphorus doped layer is 1.0E 21 cm -3 .

[0162] Example 3 A solar cell was prepared in the manner of Example 1, except that, in step S7: at a temperature of 4000° C. and a power of 11000 W, SiH4, PH4 and H2 were introduced into the furnace tube for deposition for 240 s, with a SiH4 flow volume of 3000 sccm, a PH4 flow volume of 400 sccm, and a H2 flow volume of 10000 sccm, to form a first phosphorus-doped amorphous silicon layer with a thickness of 35 nm on the first tunneling oxide layer; In S13: a high temperature annealing treatment is performed at a temperature of 900° C. for 1800 seconds, and the protective layer is removed to obtain a phosphorus doping concentration ρ1 of 8E in the first phosphorus doped layer. 19 cm -3 The phosphorus doping concentration ρ2 in the second phosphorus doped layer is 3E 20 cm -3 The phosphorus doping concentration ρ3 in the third phosphorus doped layer is 0.9E 21 cm-3 .

[0163] Example 4 A solar cell was prepared in the manner of Example 1, except that, in step S9: at a temperature of 4000° C. and a power of 11000 W, SiH4, PH4 and H2 were introduced into the furnace tube for deposition for 160 s, with a SiH4 flow volume of 3000 sccm, a PH4 flow volume of 400 sccm, and a H2 flow volume of 10000 sccm, to form a second phosphorus-doped amorphous silicon layer with a thickness of 22 nm on the second tunneling oxide layer; In S13: a high temperature annealing treatment is performed at a temperature of 900° C. for 1800 seconds, and the protective layer is removed to obtain a phosphorus doping concentration ρ1 of 4E in the first phosphorus doped layer. 19 cm -3 The phosphorus doping concentration ρ2 in the second phosphorus doped layer is 8E 19 cm -3 The phosphorus doping concentration ρ3 in the third phosphorus doped layer is 0.9E 21 cm -3 .

[0164] Example 5 A solar cell was prepared in the manner of Example 1, except that, in step S9: at a temperature of 4000° C. and a power of 11000 W, SiH4, PH4 and H2 were introduced into the furnace tube for deposition for 260 s, with a SiH4 flow volume of 3000 sccm, a PH4 flow volume of 400 sccm, and a H2 flow volume of 10000 sccm, to form a second phosphorus-doped amorphous silicon layer with a thickness of 38 nm on the second tunneling oxide layer; In S13: a high temperature annealing treatment is performed at a temperature of 900° C. for 1800 seconds, and the protective layer is removed to obtain a phosphorus doping concentration ρ1 of 4E in the first phosphorus doped layer. 19 cm -3 The phosphorus doping concentration ρ2 in the second phosphorus doped layer is 6E 20 cm -3 The phosphorus doping concentration ρ3 in the third phosphorus doped layer is 0.9E 21 cm -3 .

[0165] Example 6 A solar cell was prepared in the manner of Example 1, except that, in step S11: at a temperature of 4000° C. and a power of 11000 W, SiH4, PH4 and H2 were introduced into the furnace tube for deposition for 260 s, with a SiH4 flow volume of 3000 sccm, a PH4 flow volume of 400 sccm, and a H2 flow volume of 10000 sccm, to form a third phosphorus-doped amorphous silicon layer with a thickness of 38 nm on the third tunneling oxide layer; S13: Perform high temperature annealing at 900° C. for 1800 s and remove the protective layer to obtain a phosphorus doping concentration ρ1 of 4E in the first phosphorus doped layer. 19 cm -3 The phosphorus doping concentration ρ2 in the second phosphorus doped layer is 3E 20 cm -3 The phosphorus doping concentration ρ3 in the third phosphorus doped layer is 0.6E 21 cm -3 .

[0166] Example 7 A solar cell was prepared in the manner of Example 1, except that, in step S11: at a temperature of 4000° C. and a power of 11000 W, SiH4, PH4 and H2 were introduced into the furnace tube for deposition for 400 s, with a SiH4 flow volume of 3000 sccm, a PH4 flow volume of 400 sccm, and a H2 flow volume of 10000 sccm, to form a third phosphorus-doped amorphous silicon layer with a thickness of 55 nm on the third tunneling oxide layer; S13: Perform high temperature annealing at 900° C. for 1800 s and remove the protective layer to obtain a phosphorus doping concentration ρ1 of 4E in the first phosphorus doped layer. 19 cm -3 The phosphorus doping concentration ρ2 in the second phosphorus doped layer is 3E 20 cm -3 The phosphorus doping concentration ρ3 in the third phosphorus doped layer is 1.2E 21 cm -3 .

[0167] Comparative Example 1 A solar cell is prepared in the manner of Example 1, except that, in step S7: at a temperature of 4000° C. and a power of 11000 W, SiH4, PH4 and H2 are introduced into the furnace tube for deposition for 290 s, with a flow volume of 3000 sccm of SiH4, a flow volume of 400 sccm of PH4 and a flow volume of 10000 sccm of H2, to form a first phosphorus-doped amorphous silicon layer with a thickness of 45 nm on the first tunneling oxide layer; In S13: a high temperature annealing treatment is performed at a temperature of 900° C. for 1800 s, and the protective layer is removed to obtain a phosphorus doping concentration ρ1 of 5E in the first phosphorus doped layer. 20 cm -3 The phosphorus doping concentration ρ2 in the second phosphorus doped layer is 3E 20 cm -3 The phosphorus doping concentration ρ3 in the third phosphorus doped layer is 0.9E 21 cm -3 .

[0168] Comparative Example 2 A solar cell was prepared in the manner of Example 1, except that, in step S9: at a temperature of 4000° C. and a power of 11000 W, SiH4, PH4 and H2 were introduced into the furnace tube for deposition for 380 s, with a SiH4 flow volume of 3000 sccm, a PH4 flow volume of 400 sccm, and a H2 flow volume of 10000 sccm, to form a second phosphorus-doped amorphous silicon layer with a thickness of 45 nm on the second tunneling oxide layer; In S13: a high temperature annealing treatment is performed at a temperature of 900° C. for 1800 s, and the protective layer is removed, so that the phosphorus doping concentration ρ1 in the first phosphorus doped layer is 4×E 19 cm -3 The phosphorus doping concentration ρ2 in the second phosphorus doped layer is 1×E 21 cm -3 The phosphorus doping concentration ρ3 in the third phosphorus doped layer is 0.9×E 21 cm -3 .

[0169] Comparative Example 3 A solar cell was prepared in the manner of Example 1, except that, in step S11: at a temperature of 4000° C. and a power of 11000 W, SiH4, PH4 and H2 were introduced into the furnace tube for deposition for 220 s, with a SiH4 flow volume of 3000 sccm, a PH4 flow volume of 400 sccm, and a H2 flow volume of 10000 sccm, to form a third phosphorus-doped amorphous silicon layer with a thickness of 27 nm on the third tunneling oxide layer; S13: Perform high temperature annealing at 900° C. for 1800 s and remove the protective layer to obtain a phosphorus doping concentration ρ1 of 4×E in the first phosphorus doped layer. 19 cm -3 The phosphorus doping concentration ρ2 in the second phosphorus doped layer is 3×E 20 cm -3 The phosphorus doping concentration ρ3 in the third phosphorus doped layer is 2×E 19 cm -3 .

[0170] Comparative Example 4 A solar cell is prepared in the manner of Example 1, except that steps S11 and S12 are not performed, that is, only a double tunneling structure is provided.

[0171] The above examples and comparative examples were tested as follows, and the test results are shown in Table 1.

[0172] Photoelectric conversion efficiency, short-circuit current, open-circuit voltage, and fill factor testing: The specific testing method is to place the battery under a light source of 100 mW / cm 2The results are obtained by connecting the source meter using the four-wire method under AM 1.5G simulated sunlight at 25°C.

[0173] Table 1

[0174] It can be seen from the above table that, compared with comparative examples 1-4, the photoelectric conversion efficiency of solar cells through embodiments 1-7 is significantly superior, indicating that the best effect is achieved when the phosphorus element increases successively from the first phosphorus-doped amorphous silicon layer to the third phosphorus-doped amorphous silicon layer. If the concentration of the first phosphorus-doped amorphous silicon layer is too high or the concentration of the second phosphorus-doped amorphous silicon layer and the third phosphorus-doped amorphous silicon layer is too low, the solar cell will be damaged to a certain extent, affecting performance improvement.

[0175] It should also be noted that the "some embodiments", "other embodiments", "embodiments", etc. mentioned in this application refer to the specific features, structures or characteristics described in conjunction with the embodiment included in at least one embodiment generally described in this application. The same expression appearing in multiple places in the specification does not necessarily refer to the same embodiment. Furthermore, when a specific feature, structure or characteristic is described in conjunction with any embodiment, it is claimed that the realization of such feature, structure or characteristic in conjunction with other embodiments also falls within the scope of this application.

[0176] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0177] It should also be noted that the above are only preferred embodiments of the present application, and the patent protection scope of the present application is not limited thereto. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly used in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A solar cell, characterized in that: include: substrate; A first tunneling oxide layer, wherein the first tunneling oxide layer is located on a side surface of the substrate; a first phosphorus-doped layer, wherein the first phosphorus-doped layer is located on a surface of the first tunnel oxide layer that is away from the substrate; a second tunneling oxide layer, wherein the second tunneling oxide layer is located on a surface of the first phosphorus-doped layer away from the first tunneling oxide layer; a second phosphorus-doped layer, wherein the second phosphorus-doped layer is located on a surface of the second tunneling oxide layer away from the first phosphorus-doped layer; a third tunneling oxide layer, wherein the third tunneling oxide layer is located on a surface of the second phosphorus-doped layer away from the second tunneling oxide layer; a third phosphorus-doped layer, the third phosphorus-doped layer being located on a surface of the third tunnel oxide layer away from the second phosphorus-doped layer; The phosphorus doping concentration in the first phosphorus doping layer is lower than the phosphorus doping concentration in the second phosphorus doping layer, and the phosphorus doping concentration in the second phosphorus doping layer is lower than the phosphorus doping concentration in the third phosphorus doping layer.

2. The solar cell according to claim 1, characterized in that The phosphorus doping concentration ρ1 in the first phosphorus doped layer is 1.1E 19 -8.0E 19 cm -3 ; The phosphorus doping concentration ρ2 in the second phosphorus doped layer is 8.0E 19 -6.0E 20 cm -3 ; The phosphorus doping concentration ρ3 in the third phosphorus doped layer is 6.0E 20 -1.2E 21 cm -3 .

3. The solar cell according to claim 1, characterized in that The thickness of the first phosphorus-doped layer is 20-40 nm; and / or, the thickness of the second phosphorus-doped layer is 25-50 nm; And / or, the thickness of the third phosphorus-doped layer is 40-60 nm.

4. The solar cell according to claim 1, characterized in that The thickness of the first tunneling oxide layer is 0.8-2nm; And / or, the thickness of the second tunneling oxide layer is 0.5-1.6 nm; And / or, the thickness of the third tunnel oxide layer is 0.5-1.6 nm.

5. A method for preparing a solar cell, characterized in that: The following steps are involved: providing a substrate; Performing a first oxidation treatment on a surface of one side of the substrate to obtain a first tunneling oxide layer; Performing a first deposition process on a surface of the first tunneling oxide layer away from the substrate to obtain a first phosphorus-doped amorphous silicon layer; Performing a second oxidation treatment on a surface of the first phosphorus-doped amorphous silicon layer away from the first tunneling oxide layer to obtain a second tunneling oxide layer; Performing a second deposition process on a surface of the second tunneling oxide layer on a side away from the first phosphorus-doped amorphous silicon layer to obtain a second phosphorus-doped amorphous silicon layer; Performing a third oxidation treatment on a surface of the second phosphorus-doped amorphous silicon layer away from the second tunneling oxide layer to obtain a third tunneling oxide layer; Performing a third deposition process on a surface of the third tunnel oxide layer on a side away from the second phosphorus-doped amorphous silicon layer to obtain a third phosphorus-doped amorphous silicon layer; Performing a fourth deposition process on a surface of the third phosphorus-doped amorphous silicon layer away from the third tunnel oxide layer to obtain a protective layer; After annealing the obtained product with the protective layer, a first phosphorus-doped layer, a second phosphorus-doped layer, and a third phosphorus-doped layer are obtained; The phosphorus doping concentration in the first phosphorus-doped amorphous silicon layer is lower than the phosphorus doping concentration in the second phosphorus-doped amorphous silicon layer, and the phosphorus doping concentration in the second phosphorus-doped amorphous silicon layer is lower than the phosphorus doping concentration in the third phosphorus-doped amorphous silicon layer.

6. The preparation method according to claim 5, characterized in that: The first oxidation treatment time is 50-80s; And / or, the second oxidation treatment time is 20-50s; And / or, the third oxidation treatment time is 20-40s.

7. The preparation method according to claim 5, characterized in that: The thickness of the protective layer is 10-70 nm.

8. The preparation method according to claim 5, characterized in that: The annealing treatment satisfies at least one of the following conditions: annealing temperature is 800° C.-920° C.; annealing time is 1500s-2600s.

9. The preparation method according to claim 5, characterized in that: The method further comprises removing the The removal treatment is carried out using a HF solution with a concentration of 8-10wt%.

10. The preparation method according to claim 9, characterized in that: Also includes: An electrode is formed on a surface of the third phosphorus-doped layer that is away from the third tunnel oxide layer to obtain the solar cell.

11. A photovoltaic module, characterized in that: The invention comprises the solar cell according to any one of claims 1 to 4 or the solar cell obtained by the preparation method according to any one of claims 5 to 10.

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