Display device and method for manufacturing display device

Abstract

The invention provides a display device and a manufacturing method of the display device. A display device according to an embodiment includes: a substrate; a lower electrode disposed on the substrate; a rib having an opening overlapping the lower electrode; a partition wall disposed on the rib; an organic layer in contact with the lower electrode through the opening; and an upper electrode disposed on the organic layer. The lower electrodes include: a plurality of first lower electrodes disposed in the first region; and a plurality of second lower electrodes disposed in the second region. The openings include: a plurality of first openings overlapping the plurality of first lower electrodes; and a plurality of second openings overlapping the plurality of second lower electrodes. The partition walls include: a first partition wall that partitions the plurality of first openings; and a plurality of second partition walls that partition each of the plurality of second openings. The second opening is smaller than the first opening. The second partition walls are connected to each other by a transparent conductive layer disposed on the ribs.

Description

[0001] This application is based on Japanese Patent Application No. 2023-111655 (filing date: July 6, 2023) and claims the benefit of priority from that application, and the present application incorporates the entire contents of that application by reference. Technical Field

[0002] Embodiments of the present invention relate to a display device and a method for manufacturing the display device. Background Art

[0003] In recent years, display devices using organic light emitting diodes (OLEDs) as display elements have been put to practical use, and electronic devices such as smartphones are known to include such display devices.

[0004] In such an electronic device, by adopting a structure in which a camera is arranged on the back side of a display device (display area), it is possible to expand the display area to a region overlapping with the camera.

[0005] However, in the case of such a structure, light needs to be incident on the camera (the imaging element included therein) via the display device, and therefore, sufficient light transmittance needs to be ensured in the display device (the area in the display area that overlaps with the camera). Summary of the invention

[0006] An object of the present invention is to provide a display device and a method for manufacturing the display device capable of improving light transmittance.

[0007] The display device of the embodiment comprises: a substrate; a lower electrode arranged on the substrate; a rib having an opening overlapping with the lower electrode; a partition wall having a lower portion arranged on the rib and an upper portion protruding from a side surface of the lower portion; an organic layer in contact with the lower electrode through the opening; and an upper electrode arranged on the organic layer. The lower electrode includes: a plurality of first lower electrodes arranged in a first region on the substrate; and a plurality of second lower electrodes arranged in a second region different from the first region. The opening includes: a plurality of first openings overlapping with the plurality of first lower electrodes; and a plurality of second openings overlapping with the plurality of second lower electrodes. The partition wall includes: a first partition wall dividing the plurality of first openings; and a plurality of second partition walls dividing each of the plurality of second openings. The area of ​​each of the plurality of second openings is smaller than the area of ​​each of the plurality of first openings. The plurality of second partition walls are arranged in a manner with a gap between each of the plurality of second partition walls and are connected to the other second partition walls through a transparent conductive layer arranged on the rib. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 It is a diagram showing a configuration example of a display device according to an embodiment.

[0009] Figure 2 This is a diagram showing an example of a sub-pixel layout.

[0010] Figure 3 It is along Figure 2 A schematic cross-sectional view of the display device taken along line AA in FIG.

[0011] Figure 4 It is a schematic cross-sectional view of the partition wall.

[0012] Figure 5 This is a schematic cross-sectional view for explaining a display element formed using partition walls.

[0013] Figure 6 This is a schematic cross-sectional view for explaining a display element formed using partition walls.

[0014] Figure 7 This is a schematic cross-sectional view for explaining a display element formed using partition walls.

[0015] Figure 8 It is a plan view showing a part of an electronic device in which a display device is incorporated.

[0016] Fig. 9 This is a diagram schematically showing an example of the arrangement of openings included in the ribs formed in the first display region.

[0017] Fig.10 This is a diagram schematically showing an example of an opening included in a rib formed in the second display region.

[0018] Fig.11 It is along Fig.10 A schematic cross-sectional view of the display device taken along line BB in FIG.

[0019] Fig.12 This is a diagram for explaining an example of a process for forming ribs, partition walls, and a transparent conductive layer in the second display area.

[0020] Fig.13 This is a diagram for explaining an example of a process for forming ribs, partition walls, and a transparent conductive layer in the second display area.

[0021] Fig.14 This is a diagram for explaining an example of a process for forming ribs, partition walls, and a transparent conductive layer in the second display area.

[0022] Fig.15 This is a diagram schematically showing another example of the openings included in the ribs formed in the second display region.

[0023] Fig.16This is a diagram schematically showing still another example of the openings included in the ribs formed in the second display region.

[0024] Fig.17 This is a diagram schematically showing still another example of the openings included in the ribs formed in the second display region.

[0025] Description of Reference Numerals

[0026] DSP: display device, DA: display area, DA1: first display area, DA2: second display area, NDA: non-display area, PX: pixel, SP, SP1, SP2, SP3: sub-pixel, AP, AP1, AP2, AP3: opening, LE, LE1, LE2, LE3: lower electrode, UE, UE1, UE2, UE3: upper electrode, OR, OR1, OR2, OR3: organic layer, SE, SE1, SE2, SE3: sealing layer, 1: pixel circuit, 2: pixel switch, 3: driving transistor, 4: capacitor, 5: rib, 6: partition wall, 7: transparent conductive layer, 10: substrate, 11: insulating layer, 12: circuit layer, 13: insulating layer, 14: resin layer, 15: sealing layer, 16: resin layer, 20: display element, 61: lower part, 62: upper part. DETAILED DESCRIPTION

[0027] One embodiment is described with reference to the drawings.

[0028] The disclosed content is only an example, and solutions that can be easily thought of by those skilled in the art for appropriate changes with the main purpose of the invention are of course included in the scope of the present invention. In addition, in order to make the description clearer, the drawings show schematically the width, thickness, shape, etc. of each part compared with the actual form, but this is only an example and does not limit the interpretation of the present invention. In addition, in this specification and each figure, the same reference figure number is sometimes marked for the constituent elements that have the same or similar functions as the constituent elements that have been described in the accompanying figures, and repeated detailed descriptions are appropriately omitted.

[0029] It should be noted that in the drawings, in order to facilitate understanding as needed, mutually orthogonal X-axis, Y-axis and Z-axis are recorded. The direction along the X-axis is called the first direction X, the direction along the Y-axis is called the second direction Y, and the direction along the Z-axis is called the third direction Z. Observing various elements parallel to the third direction Z is called a top view.

[0030] The display device of this embodiment is an organic electroluminescent display device having an organic light emitting diode (OLED) as a display element, and can be mounted on an electronic device such as a smartphone. It should be noted that the electronic device mounted on the display device of this embodiment may also be a device other than a smartphone (such as a tablet terminal, etc.).

[0031] Figure 1 1 is a diagram showing a configuration example of a display device DSP according to the present embodiment. The display device DSP includes a display area DA for displaying an image and a non-display area NDA around the display area DA on an insulating substrate 10. The substrate 10 may be glass or a flexible resin film.

[0032] In the present embodiment, the shape of the substrate 10 in a plan view is a rectangle. However, the shape of the substrate 10 in a plan view is not limited to a rectangle, and may be other shapes such as a square, a circle, or an ellipse.

[0033] The display area DA includes a plurality of pixels PX arranged (configured) in a matrix in the first direction X and the second direction Y. The pixel PX includes a plurality of sub-pixels SP. In one example, the pixel PX includes a red sub-pixel SP1, a green sub-pixel SP2, and a blue sub-pixel SP3. In addition, the pixel PX may include sub-pixels SP of other colors such as white in addition to the sub-pixels SP1, SP2, and SP3. In addition, the pixel PX may include sub-pixels SP of other colors instead of any one of the sub-pixels SP1, SP2, and SP3.

[0034] The sub-pixel SP includes a pixel circuit 1 and a display element 20 driven by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a driving transistor 3, and a capacitor 4. The pixel switch 2 and the driving transistor 3 are switching elements composed of, for example, thin film transistors.

[0035] The gate electrode of the pixel switch 2 is connected to the scanning line GL. One of the source electrode and the drain electrode of the pixel switch 2 is connected to the signal line SL, and the other is connected to the gate electrode of the driving transistor 3 and the capacitor 4. In the driving transistor 3, one of the source electrode and the drain electrode is connected to the power line PL and the capacitor 4, and the other is connected to the display element 20.

[0036] It should be noted that the structure of the pixel circuit 1 is not limited to Figure 1 The pixel circuit 1 may include, for example, more thin film transistors and capacitors.

[0037] The display element 20 is an organic light emitting diode (OLED) as a light emitting element. For example, the sub-pixel SP1 includes a display element 20 that emits light in a red wavelength range, the sub-pixel SP2 includes a display element 20 that emits light in a green wavelength range, and the sub-pixel SP3 includes a display element 20 that emits light in a blue wavelength range.

[0038] Figure 2 FIG. 4 shows an example of the layout of sub-pixels SP1, SP2, and SP3. Figure 2In the example shown, the sub-pixel SP1 and the sub-pixel SP2 are arranged in the second direction Y. In addition, the sub-pixels SP1 and SP2 are arranged in the first direction X with the sub-pixel SP3 , respectively.

[0039] In sub-pixels SP1, SP2 and SP3 Figure 2 In the case of the layout shown, in the display area DA, there are formed columns in which sub-pixels SP1 and SP2 are alternately arranged in the second direction Y, and columns in which a plurality of sub-pixels SP3 are repeatedly arranged in the second direction Y. These columns are alternately arranged in the first direction X.

[0040] It should be noted that the layout of the sub-pixels SP1, SP2 and SP3 is not limited to Figure 2 As another example, the sub-pixels SP1 , SP2 , and SP3 in each pixel PX may be arranged in the first direction X in sequence.

[0041] The rib 5 and the partition wall 6 are arranged in the display area DA. The rib 5 has openings AP1, AP2, and AP3 in the sub-pixels SP1, SP2, and SP3, respectively. Figure 2 In the example shown, the area of ​​the opening AP2 is larger than that of the opening AP1, and the area of ​​the opening AP3 is larger than that of the opening AP2. The partition wall 6 is arranged at the boundary between adjacent sub-pixels SP and overlaps with the rib 5 in a plan view.

[0042] The partition wall 6 includes a partition wall 6x extending in the first direction X and a partition wall 6y extending in the second direction Y. The partition wall 6x is disposed between the opening AP1 and the opening AP2 adjacent to each other in the second direction Y, and between two openings AP3 adjacent to each other in the second direction Y. The partition wall 6y is disposed between the opening AP1 and the opening AP3 adjacent to each other in the first direction X, and between the opening AP2 and the opening AP3 adjacent to each other in the first direction X.

[0043] exist Figure 2 In the example shown, the partition walls 6x and the partition walls 6y are connected to each other. Thus, the partition walls 6 as a whole are in a lattice shape surrounding the openings AP1, AP2, and AP3. It can be said that the partition walls 6 also have openings in the sub-pixels SP1, SP2, and SP3, similarly to the ribs 5.

[0044] That is, in the present embodiment, the ribs 5 and the partition walls 6 are arranged so as to partition the sub-pixels SP1 , SP2 , and SP3 (the openings AP1 , AP2 , and AP3 ).

[0045] The sub-pixel SP1 includes a lower electrode LE1, an upper electrode UE1, and an organic layer OR1 respectively overlapping the opening AP1. The sub-pixel SP2 includes a lower electrode LE2, an upper electrode UE2, and an organic layer OR2 respectively overlapping the opening AP2. The sub-pixel SP3 includes a lower electrode LE3, an upper electrode UE3, and an organic layer OR3 respectively overlapping the opening AP3. Figure 2 In the example shown, the upper electrode UE1 and the organic layer OR1 have the same outer shape, the upper electrode UE2 and the organic layer OR2 have the same outer shape, and the upper electrode UE3 and the organic layer OR3 have the same outer shape.

[0046] The lower electrode LE1, the upper electrode UE1 and the organic layer OR1 constitute the display element 20 of the subpixel SP1. The lower electrode LE2, the upper electrode UE2 and the organic layer OR2 constitute the display element 20 of the subpixel SP2. The lower electrode LE3, the upper electrode UE3 and the organic layer OR3 constitute the display element 20 of the subpixel SP3.

[0047] The lower electrode LE1 is connected to the pixel circuit 1 of the driving sub-pixel SP1 (the display element 20) through the contact hole CH1. The lower electrode LE2 is connected to the pixel circuit 1 of the driving sub-pixel SP2 (the display element 20) through the contact hole CH2. The lower electrode LE3 is connected to the pixel circuit 1 of the driving sub-pixel SP3 (the display element 20) through the contact hole CH3.

[0048] exist Figure 2 In the example shown, the contact holes CH1 and CH2 entirely overlap with the partition wall 6x between the opening AP1 and the opening AP2 adjacent to each other in the second direction Y. The contact hole CH3 entirely overlaps with the partition wall 6x between two openings AP3 adjacent to each other in the second direction Y. As another example, at least a portion of the contact holes CH1, CH2, and CH3 may not overlap with the partition wall 6x.

[0049] exist Figure 2 In the example shown, the lower electrodes LE1 and LE2 have protrusions PR1 and PR2, respectively. The protrusion PR1 protrudes from the body of the lower electrode LE1 (the portion overlapping the opening AP1) toward the contact hole CH1. The protrusion PR2 protrudes from the body of the lower electrode LE2 (the portion overlapping the opening AP2) toward the contact hole CH2. The contact holes CH1 and CH2 overlap with the protrusions PR1 and PR2, respectively.

[0050] Figure 3 It is along Figure 2 Schematic cross-sectional view of the display device DSP taken along line AA in FIG. In the display device DSP, an insulating layer 11 called a primer layer is disposed on a light-transmitting substrate 10 such as glass (the surface on which the display element 20 and the like are disposed).

[0051] The insulating layer 11 has, for example, a three-layer stacked structure including a silicon oxide film (SiO), a silicon nitride film (SiN), and a silicon oxide film (SiO). In addition, the insulating layer 11 is not limited to a three-layer stacked structure. The insulating layer 11 may also have a stacked structure with more than three layers, and may also have a single-layer structure or a two-layer stacked structure.

[0052] A circuit layer 12 is disposed on the insulating layer 11. The circuit layer 12 has Figure 1 The pixel circuit 1 , scanning lines GL, signal lines SL, power lines PL, and other circuits and wirings shown are used to drive the sub-pixels SP ( SP1 , SP2 , and SP3 ). The circuit layer 12 is covered with an insulating layer 13 .

[0053] The insulating layer 13 functions as a planarizing film that planarizes the unevenness generated by the circuit layer 12. Figure 3 Although not shown in the figure, the contact holes CH1 , CH2 , and CH3 are provided in the insulating layer 13 .

[0054] The lower electrodes LE (LE1, LE2, and LE3) are arranged on the insulating layer 13. The ribs 5 are arranged on the insulating layer 13 and the lower electrodes LE. The end portions (parts) of the lower electrodes LE are covered by the ribs 5.

[0055] The partition wall 6 includes a lower portion 61 disposed on the rib 5 and an upper portion 62 covering the upper surface of the lower portion 61. The upper portion 62 has a greater width than the lower portion 61 in the first direction X and the second direction Y. Thus, the partition wall 6 has a shape in which both ends of the upper portion 62 protrude from the side surface of the lower portion 61. Such a shape of the partition wall 6 can be called an overhang shape.

[0056] The organic layer OR (OR1, OR2 and OR3) and the upper electrode UE (UE1, UE2 and UE3) together with the lower electrode LE (LE1, LE2 and LE3) constitute the display element 20. Figure 3 As shown, the organic layer OR1 includes a first organic layer OR1a and a second organic layer OR1b separated from each other. The upper electrode UE1 includes a first upper electrode UE1a and a second upper electrode UE1b separated from each other. The first organic layer OR1a contacts the lower electrode LE1 through the opening AP1 and covers a portion of the rib 5. The second organic layer OR1b is located above the upper portion 62. The first upper electrode UE1a is opposite to the lower electrode LE1 and covers the first organic layer OR1a. In addition, the first upper electrode UE1a contacts the side surface of the lower portion 61. The second upper electrode UE1b is located above the partition wall 6 and covers the second organic layer OR1b.

[0057] In addition, if Figure 3As shown, the organic layer OR2 includes a first organic layer OR2a and a second organic layer OR2b separated from each other. The upper electrode UE2 includes a first upper electrode UE2a and a second upper electrode UE2b separated from each other. The first organic layer OR2a contacts the lower electrode LE2 through the opening AP2 and covers a portion of the rib 5. The second organic layer OR2b is located above the upper portion 62. The first upper electrode UE2a is opposite to the lower electrode LE2 and covers the first organic layer OR2a. In addition, the first upper electrode UE2a contacts the side surface of the lower portion 61. The second upper electrode UE2b is located above the partition wall 6 and covers the second organic layer OR2b.

[0058] In addition, if Figure 3 As shown, the organic layer OR3 includes a first organic layer OR3a and a second organic layer OR3b separated from each other. The upper electrode UE3 includes a first upper electrode UE3a and a second upper electrode UE3b separated from each other. The first organic layer OR3a contacts the lower electrode LE3 through the opening AP3 and covers a portion of the rib 5. The second organic layer OR3b is located above the upper portion 62. The first upper electrode UE3a is opposite to the lower electrode LE3 and covers the first organic layer OR3a. In addition, the first upper electrode UE3a contacts the side surface of the lower portion 61. The second upper electrode UE3b is located above the partition wall 6 and covers the third organic layer OR3b.

[0059] exist Figure 3 In the example shown, the sub-pixels SP1, SP2, and SP3 include cover layers CP1, CP2, and CP3 (optical path adjustment layers) for adjusting the optical characteristics of light emitted from the light-emitting layers of the organic layers OR1, OR2, and OR3.

[0060] The cover layer CP1 includes a first cover layer CP1a and a second cover layer CP1b which are separated from each other. The first cover layer CP1a is located in the opening AP1 and is disposed on the first upper electrode UE1a. The second cover layer CP1b is located above the partition wall 6 and is disposed on the second upper electrode UE1b.

[0061] The cover layer CP2 includes a first cover layer CP2a and a second cover layer CP2b which are separated from each other. The first cover layer CP2a is located in the opening AP2 and is disposed on the first upper electrode UE2a. The second cover layer CP2b is located above the partition wall 6 and is disposed on the second upper electrode UE2b.

[0062] The cover layer CP3 includes a first cover layer CP3a and a second cover layer CP3b which are separated from each other. The first cover layer CP3a is located at the opening AP3 and is arranged on the first upper electrode UE3a. The second cover layer CP3b is located above the partition wall 6 and is arranged on the second upper electrode UE3b.

[0063] Sealing layers SE1, SE2 and SE3 are respectively arranged in sub-pixels SP1, SP2 and SP3. Sealing layer SE1 continuously covers the components of sub-pixel SP1 including the first covering layer CP1a, partition wall 6 and second covering layer CP1b. Sealing layer SE2 continuously covers the components of sub-pixel SP2 including the first covering layer CP2a, partition wall 6 and second covering layer CP2b. Sealing layer SE3 continuously covers the components of sub-pixel SP3 including the first covering layer CP3a, partition wall 6 and second covering layer CP3b.

[0064] exist Figure 3 In the example shown, the second organic layer OR1b, the second upper electrode UE1b, the second covering layer CP1b, and the sealing layer SE1 on the partition wall 6 between the sub-pixel SP1 and the sub-pixel SP3 are separated from the second organic layer OR3b, the second upper electrode UE3b, the second covering layer CP3b, and the sealing layer SE3 on the partition wall 6. In addition, the second organic layer OR2b, the second upper electrode UE2b, the second covering layer CP2b, and the sealing layer SE2 on the partition wall 6 between the sub-pixel SP2 and the sub-pixel SP3 are separated from the second organic layer OR3b, the second upper electrode UE3b, the second covering layer CP3b, and the sealing layer SE3 on the partition wall 6.

[0065] The sealing layers SE1 , SE2 , and SE3 are covered with a resin layer 14 (planarization film). The resin layer 14 is covered with a sealing layer 15 . In addition, the sealing layer 15 is covered with a resin layer 16 .

[0066] The insulating layer 13 and the resin layers 14 and 16 are formed of an organic material. The rib 5, the sealing layer 15, and the SE (SE1, SE2, and SE3) are formed of an inorganic material such as silicon nitride (SiNx).

[0067] The lower portion 61 of the partition wall 6 is conductive. The upper portion 62 of the partition wall 6 may also be conductive. The lower electrode LE may be formed of a transparent conductive oxide such as ITO (Indium Tin Oxide), or may have a laminated structure of a metal material such as silver (Ag) and a conductive oxide. The upper electrode UE may also be formed of a conductive oxide such as ITO.

[0068] When the potential of the lower electrode LE is relatively higher than that of the upper electrode UE, the lower electrode LE is equivalent to an anode and the upper electrode UE is equivalent to a cathode. In addition, when the potential of the upper electrode UE is relatively higher than that of the lower electrode LE, the upper electrode UE is equivalent to an anode and the lower electrode LE is equivalent to a cathode.

[0069] The organic layer OR includes a pair of functional layers and a light-emitting layer disposed between the functional layers. As an example, the organic layer OR has a structure in which a hole injection layer, a hole transport layer, an electron blocking layer, a light-emitting layer, a hole blocking layer, an electron transport layer, and an electron injection layer are stacked in this order.

[0070] The covering layer CP (CP1, CP2 and CP3) is formed by a multilayer body of multiple transparent thin films, for example. The multilayer body as multiple thin films may include a thin film formed of an inorganic material and a thin film formed of an organic material. In addition, these multiple thin films have different refractive indices from each other. The material of the thin film constituting the multilayer body is different from the material of the upper electrode UE and also different from the material of the sealing layer SE. In addition, the covering layer CP may also be omitted.

[0071] A common voltage is supplied to the partition wall 6. The common voltage is supplied to the upper electrodes UE (first upper electrodes UE1a, UE2a, and UE3a) in contact with the side surfaces of the lower portion 61. The pixel voltage is supplied to the lower electrodes LE (LE1, LE2, and LE3) through the pixel circuits 1 included in the sub-pixels SP (SP1, SP2, and SP3).

[0072] When a potential difference is formed between the lower electrode LE1 and the upper electrode UE1, the light-emitting layer of the first organic layer OR1a emits light in a red wavelength range. When a potential difference is formed between the lower electrode LE2 and the upper electrode UE2, the light-emitting layer of the first organic layer OR2a emits light in a green wavelength range. When a potential difference is formed between the lower electrode LE3 and the upper electrode UE3, the light-emitting layer of the first organic layer OR3a emits light in a blue wavelength range.

[0073] As another example, the light-emitting layers of the organic layers OR1, OR2, and OR3 may also emit light of the same color (e.g., white). In this case, the display device DSP may also include a color filter that converts the light emitted by the light-emitting layer into light of a color corresponding to the sub-pixels SP1, SP2, and SP3. In addition, the display device DSP may also include a layer including quantum dots that are excited by the light emitted by the light-emitting layer to generate light of a color corresponding to the sub-pixels SP1, SP2, and SP3.

[0074] Figure 4 6 is a schematic enlarged cross-sectional view of the partition wall 6. Figure 4 In the figure, elements other than the rib 5, the partition wall 6, the insulating layer 13 and the pair of lower electrodes LE are omitted. The pair of lower electrodes LE corresponds to any one of the lower electrodes LE1, LE2 and LE3 described above. In addition, the partition walls 6x and 6y described above have the same Figure 4 The partition wall 6 shown is of the same design.

[0075] exist Figure 4In the example shown, the lower portion 61 of the partition wall 6 includes a shielding layer (bottom) 611 disposed on the rib 5 and a metal layer (shaft portion) 612 disposed on the shielding layer 611. The shielding layer 611 is formed of a material different from that of the metal layer 612, for example, a metal material such as molybdenum (Mo), titanium (Ti) and titanium nitride (TiN). The metal layer 612 is formed thicker than the shielding layer 611. The metal layer 612 may be a single-layer structure or a stacked structure of different metal materials. As an example, the metal layer 612 is formed of aluminum (Al).

[0076] The upper portion (top portion) 62 is thinner than the lower portion 61. Figure 4 In the example shown, the upper portion 62 includes a first layer 621 disposed on the metal layer 612 and a second layer 622 disposed on the first layer 621. As an example, the first layer 621 is formed of titanium (Ti), and the second layer 622 is formed of ITO.

[0077] exist Figure 4 In the example shown, the width of the lower portion 61 decreases toward the upper portion 62. That is, the side surfaces 61a and 61b of the lower portion 61 are inclined with respect to the third direction Z. The upper portion 62 has an end 62a protruding from the side surface 61a and an end 62b protruding from the side surface 61b.

[0078] The protrusion amount D of the end portions 62a and 62b from the side surfaces 61a and 61b (hereinafter, recorded as the protrusion amount D of the partition wall 6) is, for example, less than 2.0 μm. The protrusion amount D of the partition wall 6 in the present embodiment is equivalent to the distance between the lower ends (shielding layer 611) of the side surfaces 61a and 61b and the end portions 62a and 62b in the width direction (first direction X or second direction Y) of the partition wall 6 orthogonal to the third direction Z.

[0079] In addition, Figure 4 In the example shown, the side surface of the shielding layer 611 is aligned with the side surface of the metal layer 612 to form a plane without a step difference, but for example, the side surface of the shielding layer 611 may be slightly set back from the side surface of the metal layer 612, or may protrude from the side surface of the metal layer 612. Figure 4 The side surfaces of the middle shield layer 611 and the metal layer 612 (that is, the side surfaces 61 a and 61 b ​​of the lower portion 61 ) are inclined with respect to the third direction Z, but the side surfaces may be parallel to the third direction Z.

[0080] The structure of the partition wall 6 and the material of each part of the partition wall 6 can be appropriately selected in consideration of, for example, the method of forming the partition wall 6 .

[0081] Here, in this embodiment, the partition wall 6 is formed in a manner to divide the sub-pixel SP in a plan view. The above-mentioned organic layer OR is formed by, for example, a vacuum evaporation method having anisotropy or directivity. However, when an organic material for forming the organic layer OR is vapor-deposited onto the entire substrate 10 in a state where the partition wall 6 is disposed, the partition wall 6 has a Figure 3 and Figure 4 Since the organic layer OR is almost not formed on the side surface of the partition wall 6, the organic layer OR (display element 20) can be formed so as to be separated for each sub-pixel SP by the partition wall 6.

[0082] Figure 5 to Figure 7 FIG. 2 is a schematic cross-sectional view for explaining a display element 20 formed by using a partition wall 6. Figure 5 to Figure 7 In the figure, the substrate 10, the insulating layer 11 and the circuit layer 12 are omitted. Figure 5 to Figure 7 The sub-pixels SPα, SPβ, and SPγ shown correspond to any of the sub-pixels SP1, SP2, and SP3.

[0083] First, in the state where the partition wall 6 is arranged as described above, Figure 5 As shown, an organic layer OR, an upper electrode UE, a covering layer CP, and a sealing layer SE are sequentially formed on the entire substrate 10 by evaporation. The organic layer OR includes a light-emitting layer that emits light of a color corresponding to the sub-pixel SPα. The organic layer OR is divided into a first organic layer ORa in contact with the lower electrode LE through the opening AP and a second organic layer ORb on the partition wall 6 by the extended partition wall 6, the upper electrode UE is divided into a first upper electrode UEa covering the first organic layer ORa and a second upper electrode UEb covering the second organic layer ORb, and the covering layer CP is divided into a first covering layer CPa covering the first upper electrode UEa and a second covering layer CPb covering the second upper electrode UEb. The first upper electrode UEa is in contact with the lower portion 61 of the partition wall 6. The sealing layer SE continuously covers the first covering layer CPa, the second covering layer CPb, and the partition wall 6.

[0084] Then, if Figure 6 As shown in FIG. 1 , a resist R is formed on the sealing layer SE. The resist R covers the sub-pixel SPα. That is, the resist R is arranged directly above the first organic layer ORa, the first upper electrode UEa, and the first cover layer CPa located in the sub-pixel SPα. The resist R is also located directly above the second organic layer ORb, the second upper electrode UEb, and the second cover layer CPb on the partition wall 6 between the sub-pixel SPα and the sub-pixel SPβ, which is close to the sub-pixel SPα. That is, at least a portion of the partition wall 6 is exposed from the resist R.

[0085] In addition, by etching with the resist R as a mask, as Figure 7As shown, the exposed portions of the organic layer OR, the upper electrode UE, the cover layer CP, and the sealing layer SE from the resist R are removed. Thus, a display element 20 including the lower electrode LE, the first organic layer ORa, the first upper electrode UEa, and the first cover layer CPa is formed in the sub-pixel SPα. On the other hand, the lower electrode LE is exposed in the sub-pixels SPβ and SPγ. In addition, the above-mentioned etching includes, for example, dry etching of the sealing layer SE, wet etching and dry etching of the cover layer CP, wet etching of the upper electrode UE, and dry etching of the organic layer OR.

[0086] When the display element 20 of the sub-pixel SPα is formed as described above, the resist R is removed, and the display elements 20 of the sub-pixels SPβ and SPγ are sequentially formed in the same manner as the sub-pixel SPα.

[0087] As described above with respect to the sub-pixels SPα, SPβ, and SPγ, the display element 20 including the sub-pixels SP1, SP2, and SP3 is formed, and the resin layer 14, the sealing layer 15, and the resin layer 16 are further formed, thereby realizing Figure 3 The structure of the display device DSP is shown.

[0088] Here, it is assumed that the display device DSP of the present embodiment is incorporated into an electronic device such as a smartphone together with a camera and used.

[0089] Figure 8 1 is a top view showing a part of an electronic device incorporating the display device DSP (display panel) of the present embodiment. As described above, in the display device DSP, the display area DA includes a plurality of pixels PX (sub-pixels SP1, SP2, and SP3) arranged in a matrix in the first direction X and the second direction Y. The display device DSP includes a display surface including the display area DA and a back surface opposite to the display surface (hereinafter referred to as the back surface of the display device DSP). In the electronic device incorporating the display device DSP of the present embodiment, a camera 100 for capturing an image is disposed on the back side of the display device DSP.

[0090] In this case, if Figure 8 As shown, in order to expand the display area DA in the electronic device (display device DSP) (expand the range of the display area DA), it is considered to configure the camera 100 at a position overlapping with the display area DA (that is, multiple pixels PX).

[0091] However, when the camera 100 is arranged at a position overlapping with the display area DA in a plan view, there is a possibility that the transmittance of the area overlapping with the camera 100 (that is, the area including the pixel PX) is reduced due to the influence of the pixel circuit 1 and the lower electrode LE of each pixel PX overlapping with the camera 100, and sufficient light may not be incident on the camera 100 (the imaging element therein) through the display device DSP.

[0092] In this case, for example, a structure in which pixels PX are thinned out in the area overlapping with the camera 100 is considered. However, according to this structure in which only pixels PX are thinned out, the resolution of the area overlapping with the camera 100 is reduced, and the camera 100 is easily visible from this area, so there is a possibility that the display quality of the display device DSP is reduced.

[0093] Therefore, the following structure is adopted in this embodiment: the area (size) of the opening of the rib 5 in the area overlapping with the camera 100 in the display area DA (hereinafter referred to as the second display area DA2) is reduced when viewed from above, relative to the area (size) of the opening of the rib 5 in the area not overlapping with the camera 100 in the display area DA (hereinafter referred to as the first display area DA1).

[0094] Fig. 9 An example of the arrangement of the openings AP1, AP2, and AP3 of the rib 5 formed in the first display area DA1 is schematically shown. Fig.10 The arrangement of the openings AP1 , AP2 , and AP3 included in the rib 5 formed in the second display area DA2 is schematically shown.

[0095] In addition, Fig. 9 and Fig.10 , the plurality of openings AP1, AP2, and AP3 of the rib 5 are shown in four pixels PX (sub-pixels SP1, SP2, and SP3). That is, in the present embodiment, the number of openings AP1, AP2, and AP3 per unit area in the first display area DA1 is the same as the number of openings AP1, AP2, and AP3 per unit area in the second display area DA2.

[0096] Here, refer to Fig. 9 and Fig.10 , the area of ​​the opening AP1 in the second display area DA2 is smaller than the area of ​​the opening AP1 in the first display area DA1. Similarly, the area of ​​the opening AP2 in the second display area DA2 is smaller than the area of ​​the opening AP2 in the first display area DA1, and the area of ​​the opening AP3 in the second display area DA2 is smaller than the area of ​​the opening AP3 in the first display area DA1.

[0097] In addition, Fig. 9 and Fig.10 In the example shown, the ratio of the areas of the openings AP1 , AP2 , and AP3 in the first display area DA1 is substantially the same as the ratio of the areas of the openings AP1 , AP2 , and AP3 in the second display area DA2 .

[0098] In addition, Fig. 9 and Fig.10 In the example shown, the openings AP1 , AP2 , and AP3 in the first display area DA1 have a rectangular shape, and the openings AP1 , AP2 , and AP3 in the second display area DA2 have a circular shape.

[0099] In addition, if Fig. 9 As shown, in the first display area DA1, a plurality of openings AP1, AP2, and AP3 are divided by a partition wall 6 formed integrally therewith. Fig.10 As shown, in the second display area DA2, the plurality of openings AP1, AP2, and AP3 are respectively formed in independent island patterns (ie, island shapes), and are partitioned by a plurality of partition walls 6 that independently surround the openings AP1, AP2, and AP3.

[0100] In addition, the above Figure 3 is a schematic cross-sectional view of the display device DSP in the first display area DA1, as shown in the Figure 3 As described in the text, by supplying a common voltage to the partition wall 6 formed in the first display area DA1, the common voltage can be supplied to the upper electrode UE (upper electrodes UE1, UE2 and UE3 overlapping with the openings AP1, AP2 and AP3) in contact with the side surface of the partition wall 6 (lower portion 61) via the partition wall 6.

[0101] On the other hand, since the plurality of partition walls 6 formed in the second display area DA2 are formed as independent island patterns as described above (that is, arranged with gaps between them and other partition walls 6 ), a structure for supplying the common voltage to the plurality of partition walls 6 is required.

[0102] In this case, in the present embodiment, a transparent conductive layer 7 is provided for electrically connecting the plurality of partition walls 6 formed in the second display area DA2. In addition, the transparent conductive layer 7 is formed of a transparent conductive oxide such as ITO or IZO. According to such a structure, a common voltage can be supplied to the plurality of partition walls 6 formed in the second display area DA2, and a high transmittance can be achieved in the area where the transparent conductive layer 7 is provided.

[0103] Fig.11 It is along Fig.10 A schematic cross-sectional view of the display device DSP taken along the line BB in FIG. Figure 3The same parts are denoted by the same reference numerals and detailed description thereof is omitted.

[0104] like Fig.11 As shown, in the second display area DA2 , partition walls 6 are arranged to partition the opening AP1 , and a display element 20 (lower electrode LE1 , first organic layer OR1 a , first upper electrode UE1 a , and first cover layer CP1 a ) is formed at a position overlapping the opening AP1 .

[0105] In addition, the display element 20 is as shown in Figure 5 to Figure 7 Since it is formed as described in , the second organic layer OR1 b , the second upper electrode UE1 b , and the second cover layer CP1 b are arranged on the side of the opening AP1 on the partition wall 6 .

[0106] On the other hand, in the second display area DA2 (that is, the partition area) which does not overlap with the opening AP1 (that is, the lower electrode LE1), Fig.11 A transparent conductive layer 7 (for example, an ITO layer) is arranged on the ribs 5 in a region between the partition wall 6 of the opening AP1 shown in the figure and the partition walls 6 that partition other openings.

[0107] In this case, a portion of the transparent conductive layer 7 is covered by the partition wall 6 (lower portion 61), whereby the partition wall 6 (partition wall 6 that partitions the opening AP1) is electrically connected to the partition walls 6 that partition other openings. In other words, a common voltage is supplied to each of the plurality of partition walls 6 formed in the second display area DA2 via the transparent conductive layer 7.

[0108] Here, refer to Figure 12 to Figure 14 An example of a process for forming the ribs 5, the partition walls 6, and the transparent conductive layer 7 in the second display area DA2 will be described. Figure 12 to Figure 14 In the figure, the substrate 10, the insulating layer 11 and the circuit layer 12 are omitted. Figure 12 to Figure 14 The sub-pixel SPα shown corresponds to any one of the sub-pixels SP1 , SP2 , and SP3 .

[0109] First, if Fig.12 As shown, when the lower electrode LE is formed on the insulating layer 13, the insulating layer 5a of inorganic material processed into the rib 5 is formed to cover the insulating layer 13 and the lower electrode LE, and the transparent conductive layer 7 is formed on the insulating layer 5a.

[0110] The insulating layer 5a is formed by, for example, chemical vapor deposition. The transparent conductive layer 7 is formed by, for example, forming a transparent conductive layer (conductive oxide layer) at least in the entire second display area DA2 by sputtering, and then removing the exposed portion of the resist (not shown) disposed on the transparent conductive layer by wet etching.

[0111] Then, if Fig.13 As shown, the partition wall 6 is formed in a manner that a portion of the transparent conductive layer 7 is covered with the lower portion 61. In addition, the partition wall 6 is formed in the following manner: after forming the first layer for processing into the lower portion 61 and the second layer for processing into the upper portion 62 by sputtering, the exposed portion from the resist (not shown) arranged on the second layer and the first layer is removed by wet etching, dry etching, etc., thereby forming the partition wall 6.

[0112] In addition, a resist patterned in the planar shape of the rib 5 is provided, and the portion of the insulating layer 5a exposed from the resist is removed by dry etching. Fig.14 The rib 5 shown has openings AP (AP1, AP2 and AP3).

[0113] Here, the ribs 5, the partition walls 6, and the transparent conductive layer 7 are formed in the second display area DA2, but the ribs 5 and the partition walls 6 are also formed in the first display area DA1 in the same process as the ribs 5 and the partition walls 6 in the second display area DA2.

[0114] In the case where the ribs 5 and the partition walls 6 are formed in the first display area DA1 and the ribs 5, the partition walls 6 and the transparent conductive layer 7 are formed in the second display area DA2, as in Figure 5 to Figure 7 As described in the above, the display element 20 is formed in each of the openings AP1, AP2, and AP3, and further, the resin layer 14, the sealing layer 15, and the resin layer 16 are formed. Thus, the structure of the display device DSP of the present embodiment is realized.

[0115] In addition, it is assumed that Figure 12 to Figure 14 The ribs 5, the partition walls 6 and the transparent conductive layer 7 are formed as described in the above description, but as long as it can be realized Fig.14 In the structure shown in the figure, the order of forming the rib 5, the partition wall 6 and the transparent conductive layer 7 can also be changed. Specifically, for example, the transparent conductive layer 7 and the partition wall 6 can be formed after the insulating layer 5a formed in a manner of covering the insulating layer 13 and the lower electrode LE is processed into the rib 5. In other words, the openings AP1, AP2 and AP3 can also be formed before the transparent conductive layer 7 and the partition wall 6 are formed.

[0116] As described above, the display device DSP of the present embodiment includes: a substrate 10; a lower electrode LE arranged on the substrate 10; a rib 5 having an opening AP overlapping the lower electrode; a partition wall 6 having a lower portion 61 arranged on the rib 5 and an upper portion 62 protruding from the side of the lower portion 61; an organic layer OR in contact with the lower electrode LE through the opening AP; an upper electrode UE arranged on the organic layer OR; and a sealing layer SE covering the upper electrode UE and the partition wall 6. In addition, in the present embodiment, the lower electrode LE includes: a plurality of lower electrodes LE (first lower electrodes) arranged in a first display area DA (first area) on the substrate 10; and a plurality of lower electrodes LE (second lower electrodes) arranged in a second display area DA2 different from the first display area DA1, and the opening AP includes: a plurality of openings AP (first openings) overlapping the plurality of lower electrodes LE arranged in the first display area DA1; and a plurality of openings AP (second openings) overlapping the plurality of lower electrodes LE arranged in the second display area DA2.

[0117] In this case, in the present embodiment, the partition wall 6 includes: a partition wall 6 (first partition wall) that divides the plurality of openings AP in the first display area DA1; and a plurality of partition walls 6 that divide each of the plurality of openings AP in the second display area DA2, wherein the area of ​​each of the plurality of openings AP in the second display area DA2 is smaller than the area of ​​each of the plurality of openings AP in the first display area DA1. In addition, the plurality of partition walls 6 in the second display area DA2 are respectively arranged in a manner with a gap between them and other partition walls 6, and are electrically connected to the other partition walls 6 through a transparent conductive layer 7 arranged on the rib 5. Since each pixel is independently formed in the second display area DA2 by sealing the organic layer OR with the lower electrode LE, the rib 5, the partition wall 6 and the sealing layer SE as in the first display area DA1, even if one pixel becomes a black spot due to moisture intrusion, etc., the moisture will not diffuse to other pixels, and the diffusion of the black spot of the pixel can be suppressed. In addition, in the present embodiment, the second display area DA2 is arranged at a position overlapping with the camera 100 (imaging element) to which light is incident via the display device DSP, for example.

[0118] In the present embodiment, the above structure allows the light incident on the camera 100 to pass through the transparent conductive layer 7 formed in the second display area DA2, thereby improving the light transmittance in the second display area DA2. Fig.11 As shown, there is no need to arrange the upper electrode UE and the sealing layer SE at a position overlapping with the transparent conductive layer 7, so a high light transmittance can be achieved in the region where the transparent conductive layer 7 is arranged.

[0119] In addition, in the present embodiment, the plurality of partition walls 6 in the second display area DA2 are respectively arranged to cover a portion of the transparent conductive layer 7, and the plurality of partition walls 6 are electrically connected to each other via the transparent conductive layer 7. Therefore, even in the second display area DA2, similarly to the first display area DA1, a common voltage can be appropriately supplied to the upper electrode UE via the plurality of partition walls 6.

[0120] In addition, in the present embodiment, the number of openings AP per unit area in the second display area DA2 can be made the same as the number of openings AP per unit area in the first display area DA1 (that is, the resolution is made the same in the first display area DA1 and the second display area DA2), so the difference in display quality between the first display area DA1 and the second display area DA2 can be reduced. In addition, it is conceivable that by reducing the difference in display quality between the first display area DA1 and the second display area DA2, it is possible to suppress the visual recognition of the boundary between the first display area DA1 and the second display area DA2, or make it difficult to visually recognize the camera 100 located on the back of the display device DSP.

[0121] However, since the area of ​​the openings AP1, AP2, and AP3 in the second display area DA2 is smaller than the area of ​​the openings AP1, AP2, and AP3 in the first display area DA1, the brightness of the pixels PX (sub-pixels SP1, SP2, and SP3) arranged in the second display area DA2 is lower than the brightness of the pixels PX (sub-pixels SP1, SP2, and SP3) arranged in the first display area DA1. Therefore, in the present embodiment, it is preferred to reduce the difference in brightness between the pixels PX arranged in the first display area DA1 and the second display area DA2 by adjusting the voltage supplied to the pixels PX (sub-pixels SP1, SP2, and SP3) arranged in the second display area DA1.

[0122] In addition, in the present embodiment, for example, it is described that the ratio of the areas of the openings AP1, AP2, and AP3 in the first display area DA1 is substantially the same as the ratio of the areas of the openings AP1, AP2, and AP3 in the second display area DA2, but the ratios may be different. Specifically, for example, it is described that in the first display area DA1, the area of ​​the opening AP2 is larger than the area of ​​the opening AP1, and the area of ​​the opening AP3 is larger than the area of ​​the opening AP2, but the areas of the openings AP1, AP2, and AP3 in the second display area DA2 may be the same.

[0123] In addition, the areas (opening ratios) of the openings AP1, AP2, and AP3 in the second display area DA2 may be designed based on, for example, the performance of the camera 100 disposed on the back side of the display device DSP (such as the amount of light required by the camera 100).

[0124] In addition, when a higher transmittance is required according to the performance of the camera 100, Fig.15 As shown, a structure may be adopted in which pixels PX arranged in the second display area DA2 are interspersed (that is, the number of openings AP per unit area in the second display area DA2 is made smaller than the number of openings AP per unit area in the first display area DA1, and the area occupied by the transparent conductive layer 7 is increased in the second display area DA2).

[0125] In addition, Fig.10 In the example shown, the openings AP1, AP2, and AP3 in the second display area DA2 are respectively circular in shape, but the openings AP1, AP2, and AP3 in the second display area DA2 may have other shapes as long as their areas are smaller than those of the openings AP1, AP2, and AP3 in the first display area DA1. Fig.16 and Fig.17 In addition, the openings AP1, AP2 and AP3 in the second display area DA2 may have different shapes. Fig.16 and Fig.17 In the case of the rectangular or other shaped openings AP1, AP2 and AP3 shown in the figure, the above Fig.15 The structure of the thinning-out pixel PX described in FIG.

[0126] In addition, in the present embodiment, light is incident on the camera 100 by passing through the transparent conductive layer 7 disposed between the plurality of partition walls 6. However, if the plurality of partition walls 6 form slits, there is a possibility that the light passing through (transmitting) such slits is diffracted, and diffraction fringes may be formed in the camera 100 (the shooting surface of the imaging element) located below the slits. In this case, compared with the case where the partition walls 6 are formed in a straight line, when the partition walls 6 are formed in a curved shape, the direction (angle) in which the light passing through the slits formed by the partition walls 6 is diffracted can be dispersed, so that interference fringes of a degree that affects the image captured by the camera 100 can be formed on the shooting surface. That is, the shapes of the openings AP1, AP2, AP3 and the partition walls 6 in the second display area DA2 are preferably designed from the viewpoint of not affecting the image captured by the camera 100.

[0127] In addition, in this embodiment, it is assumed that the camera 100 (the imaging element included therein) is disposed on the back of the display device DSP, but this embodiment can be applied to a case where a sensor including a light receiving element that converts incident light into an electrical signal or a device having the sensor is disposed on the back of the display device DSP. That is, the display device DSP of this embodiment can be configured to improve the light transmittance in a predetermined area of ​​the display area DA, and there is no limitation on the components disposed on the back of the display device DSP.

[0128] In addition, in the present embodiment, a case is described in which the area of ​​each of the plurality of openings AP in the second display area DA2 is smaller than the area of ​​each of the plurality of openings AP in the first display area DA1, but the present embodiment may also be a structure in which, for example, the area of ​​each of the sub-pixels SP1, SP2, and SP3 arranged in the second display area DA is smaller than the area of ​​each of the sub-pixels SP1, SP2, and SP3 arranged in the first display area DA1.

[0129] As described above, all display devices and display device manufacturing methods that can be implemented by those skilled in the art by appropriately changing the design of the display device and display device manufacturing method described as the embodiments of the present invention also fall within the scope of the present invention as long as they include the gist of the present invention.

[0130] Within the scope of the present invention, those skilled in the art can think of various variations, which should be interpreted as also belonging to the scope of the present invention. For example, those skilled in the art can add, delete or design changes to the above-mentioned embodiments to obtain a solution, or add, omit or change the conditions of the process, as long as they have the gist of the present invention, they are also included in the scope of the present invention.

[0131] In addition, regarding other effects brought about by the forms described in the above-mentioned embodiments, effects that can be clearly seen from the description of this specification or effects that can be appropriately thought of by those skilled in the art should naturally be interpreted as effects brought about by the present invention.

Claims

1. A display device, characterized in that: have: Base material; A lower electrode disposed on the substrate; a rib having an opening overlapping the lower electrode; a partition wall having a lower portion disposed on the rib and an upper portion protruding from a side surface of the lower portion; an organic layer contacting the lower electrode through the opening; as well as an upper electrode disposed on the organic layer, The lower electrode includes: a plurality of first lower electrodes arranged in a first region on the substrate; and a plurality of second lower electrodes arranged in a second region different from the first region. The openings include: a plurality of first openings overlapping with the plurality of first lower electrodes; and a plurality of second openings overlapping with the plurality of second lower electrodes. The partition wall includes: a first partition wall for partitioning the plurality of first openings; and a plurality of second partition walls for partitioning each of the plurality of second openings. The area of ​​each of the plurality of second openings is smaller than the area of ​​each of the plurality of first openings. The plurality of second partition walls are respectively arranged with gaps between them and other second partition walls, and are connected to the other second partition walls via the transparent conductive layer arranged on the ribs.

2. The display device according to claim 1, characterized in that The second region is arranged at a position overlapping with a light receiving element that receives light via the display device.

3. The display device according to claim 1, characterized in that The number of the second openings per unit area in the second region is the same as the number of the first openings per unit area in the first region.

4. The display device according to claim 1, characterized in that The number of the second openings per unit area in the second region is smaller than the number of the first openings per unit area in the first region.

5. The display device according to claim 1, characterized in that The shape of the second opening is different from the shape of the first opening.

6. The display device according to claim 5, characterized in that: The shape of the first opening is a rectangular shape, The second opening has a circular shape.

7. The display device according to claim 1, characterized in that: The plurality of second partition walls are respectively arranged to cover a portion of the transparent conductive layer.

8. The display device according to claim 1, characterized in that: have: a covering layer disposed on the upper electrode; and a sealing layer disposed on the cover layer, The covering layer and the sealing layer are not disposed on the transparent conductive layer.

9. A display device, characterized in that: have: Base material; A lower electrode disposed on the substrate; a rib having an opening overlapping with the lower electrode; a partition wall having a lower portion disposed on the rib and an upper portion protruding from a side surface of the lower portion; an organic layer contacting the lower electrode through the opening; as well as an upper electrode disposed on the organic layer, The lower electrode includes: a plurality of first lower electrodes arranged in a first region on the substrate; and a plurality of second lower electrodes arranged in a second region different from the first region. The openings include: a plurality of first openings in a rectangular shape overlapping the plurality of first lower electrodes; and a plurality of second openings in a circular shape overlapping the plurality of second lower electrodes. The partition wall includes: a first partition wall for partitioning the plurality of first openings; and a plurality of second partition walls for partitioning each of the plurality of second openings. The plurality of second partition walls are arranged so as to have gaps between each of the second partition walls and connected to the other second partition walls via a transparent conductive layer arranged on the ribs. The second region is arranged at a position overlapping with a light receiving element that receives light.

10. The display device according to claim 9, characterized in that: The number of the second openings per unit area in the second region is the same as the number of the first openings per unit area in the first region.

11. The display device according to claim 9, characterized in that: The number of the second openings per unit area in the second region is smaller than the number of the first openings per unit area in the first region.

12. The display device according to claim 9, characterized in that: The plurality of second partition walls are respectively arranged to cover a portion of the transparent conductive layer.

13. The display device according to claim 9, characterized in that: have: a covering layer disposed on the upper electrode; and a sealing layer disposed on the cover layer, The covering layer and the sealing layer are not disposed on the transparent conductive layer.

14. A method for manufacturing a display device, characterized in that: The following processes are available: forming a lower electrode on the substrate; A step of forming an insulating layer of inorganic material covering the lower electrode; forming a transparent conductive layer on the insulating layer; forming a partition wall having a lower portion disposed on the insulating layer and an upper portion protruding from a side surface of the lower portion; forming an opening in the insulating layer so as to overlap with the lower electrode; forming an organic layer through the opening and in contact with the lower electrode; as well as forming an upper electrode on the organic layer, The lower electrode includes: a plurality of first lower electrodes arranged in a first region on the substrate; and a plurality of second lower electrodes arranged in a second region different from the first region. The transparent conductive layer is formed in the second region which does not overlap with the plurality of second lower electrodes. The openings include: a plurality of first openings overlapping with the plurality of first lower electrodes; and a plurality of second openings overlapping with the plurality of second lower electrodes. The partition wall includes: a first partition wall for partitioning the plurality of first openings; and a plurality of second partition walls for partitioning each of the plurality of second openings. The area of ​​each of the plurality of second openings is smaller than the area of ​​each of the plurality of first openings. Each of the plurality of second partitions is formed to have a gap between each of the second partitions and the other second partitions, and is connected to the other second partitions via the transparent conductive layer.

15. The method for manufacturing a display device according to claim 14, characterized in that: The second region is arranged at a position overlapping with a light receiving element that receives light via the display device.

16. The method for manufacturing a display device according to claim 14, wherein: The number of the second openings per unit area in the second region is the same as the number of the first openings per unit area in the first region.

17. The method for manufacturing a display device according to claim 14, wherein: The number of the second openings per unit area in the second region is smaller than the number of the first openings per unit area in the first region.

18. The method for manufacturing a display device according to claim 14, wherein: The shape of the second opening is different from the shape of the first opening.

19. The method for manufacturing a display device according to claim 18, characterized in that: The shape of the first opening is a rectangular shape, The second opening has a circular shape.

20. The method for manufacturing a display device according to claim 14, wherein: The plurality of second partition walls are respectively arranged to cover a portion of the transparent conductive layer.

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