Display device and method of manufacturing same

Abstract

The invention discloses a display device and a method of manufacturing the same. The display device includes: a base layer having a display area and a non-display area adjacent to the display area; a display element layer including a plurality of light emitting elements overlapping the display area; an encapsulation layer on the display element layer; a first dam in the non-display area; and a second dam in the non-display area and spaced apart from the first dam in a direction away from the display area from a boundary between the display area and the non-display area. An inorganic layer region is defined between the first dam and the second dam, and a recess is defined in the inorganic layer region.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0088152, filed on Jul. 7, 2023, which is hereby incorporated by reference herein in its entirety. Technical Field

[0003] Aspects of embodiments of the present disclosure relate to a display device and a method of manufacturing the display device. Background Art

[0004] Display devices that provide images to users (e.g., televisions, monitors, smart phones, and tablet computers) generally include display panels to display images. Various suitable types of display panels such as liquid crystal display panels, organic light emitting display panels, electrowetting display panels, and electrophoretic display panels are being developed. In response to recent market demands, research is being conducted to solve or prevent defects in display panels caused by foreign matter that has penetrated into the display panel. Summary of the invention

[0005] Embodiments of the present disclosure provide a display device that avoids or mitigates defects in a display panel caused by foreign matter.

[0006] Embodiments of the present disclosure provide a method of manufacturing a display device that avoids or mitigates defects in a display panel caused by foreign matter.

[0007] According to an embodiment of the present disclosure, a display device includes: a substrate layer having a display area and a non-display area adjacent to the display area; a display element layer including a plurality of light emitting elements overlapping the display area; an encapsulation layer on the display element layer; a first dam in the non-display area; and a second dam in the non-display area and spaced apart from the first dam in a direction away from the display area from a boundary between the display area and the non-display area. An inorganic layer area is defined between the first dam and the second dam, and a groove is defined in the inorganic layer area.

[0008] The encapsulation layer may include a first inorganic layer, an organic layer, and a second inorganic layer sequentially disposed on the display element layer, and the second inorganic layer may contact the first inorganic layer in the inorganic layer region.

[0009] The display device may further include: a sensor layer, including a first sensing insulating layer, a first conductive layer, a second sensing insulating layer, a second conductive layer and a third sensing insulating layer sequentially arranged on the encapsulation layer, and the second sensing insulating layer may contact the first sensing insulating layer and the third sensing insulating layer in the inorganic layer region.

[0010] The groove may be defined in the first inorganic layer, the second inorganic layer, the first sensing insulating layer, and the second sensing insulating layer.

[0011] When viewed in plan, the groove may be defined closer to the second dam than to the first dam.

[0012] The third sensing insulating layer may be on the second sensing insulating layer, and may cover the groove.

[0013] A contact hole at which the first conductive layer and the second conductive layer are connected to each other may extend through the second sensing insulating layer, and the groove may be formed through the same process as the contact hole.

[0014] The groove may be spaced apart from the first dam by 25 micrometers or more.

[0015] The groove may have a width equal to or less than 10 micrometers in a first direction parallel to the above direction.

[0016] According to another embodiment of the present disclosure, a display device includes: a substrate layer having a display area and a non-display area adjacent to the display area; a display element layer including a plurality of light-emitting elements overlapping the display area; an encapsulation layer including a first inorganic layer, an organic layer, and a second inorganic layer sequentially arranged on the display element layer; and a sensor layer including a first sensing insulating layer, a first conductive layer, a second sensing insulating layer, a second conductive layer, and a third sensing insulating layer sequentially arranged on the encapsulation layer. A groove is defined in the first inorganic layer, the second inorganic layer, the first sensing insulating layer, and the second sensing insulating layer, and the groove overlaps the non-display area.

[0017] The display device may further include: a first dam in the non-display area; and a second dam in the non-display area and spaced apart from the first dam in a direction away from the display area from a boundary between the display area and the non-display area. An inorganic layer area may be defined between the first dam and the second dam, and the groove may be defined in the inorganic layer area.

[0018] The first inorganic layer, the second inorganic layer, the first sensing insulating layer, the second sensing insulating layer, and the third sensing insulating layer may be sequentially stacked in the inorganic layer region.

[0019] The groove may be spaced apart from the first dam by 25 micrometers or more.

[0020] A contact hole at which the first conductive layer and the second conductive layer are connected to each other may be defined through the second sensing insulating layer, and the groove may be formed through the same process as the contact hole.

[0021] The third sensing insulating layer may be on the second sensing insulating layer, and may cover the groove.

[0022] The groove may have a width equal to or less than 10 micrometers in a first direction parallel to a direction away from the display area from a boundary between the display area and the non-display area.

[0023] According to another embodiment of the present disclosure, a method for manufacturing a display device includes: preparing a display panel, the display panel including a substrate layer defining a display area and a non-display area adjacent to the display area, a circuit layer on the substrate layer, a display element layer on the circuit layer, and an encapsulation layer including a first inorganic layer, an organic layer, and a second inorganic layer sequentially stacked on the display element layer; sequentially stacking a first sensing insulating layer, a first conductive layer, and a second sensing insulating layer on the display panel; forming a hole passing through the first inorganic layer, the second inorganic layer, the first sensing insulating layer, and the second sensing insulating layer overlapping the non-display area; and sequentially stacking a second conductive layer and a third sensing insulating layer on the second sensing insulating layer.

[0024] The method may further include: forming a contact hole at which the first conductive layer and the second conductive layer are connected to each other simultaneously with the forming of the hole.

[0025] The display panel may further include: a first dam in the non-display area; and a second dam spaced apart from the first dam in a direction away from the display area from a boundary between the display area and the non-display area. The forming of the hole may include: etching the first inorganic layer, the second inorganic layer, the first sensing insulating layer, and the second sensing insulating layer in an area spaced apart from the first dam by 25 micrometers or more.

[0026] The forming of the hole may include etching the first inorganic layer, the second inorganic layer, the first sensing insulating layer, and the second sensing insulating layer so that the hole has a width equal to or less than 10 micrometers.

[0027] Since the groove is formed in the inorganic layer region, foreign matter from the outside is discharged upward through the groove. Therefore, the foreign matter is prevented from moving along the display region (or into the display region), and defects in the display panel are reduced or avoided. In addition, since the groove is formed by using the same mask as the mask used to form the contact hole of the input sensor, the manufacturing process of the display device is simplified. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The above and other aspects and features of the present disclosure will become readily apparent by referring to the following detailed description when considered in conjunction with the accompanying drawings, in which:

[0029] Figure 1 is a perspective view of a display device according to an embodiment of the present disclosure;

[0030] Figure 2 is a cross-sectional view of a display device according to an embodiment of the present disclosure;

[0031] Figure 3 is a cross-sectional view of a display panel according to an embodiment of the present disclosure;

[0032] Figure 4 is a cross-sectional view of a display panel and an input sensor according to an embodiment of the present disclosure;

[0033] Figure 5 is a plan view of a display panel according to an embodiment of the present disclosure;

[0034] Figure 6 is a plan view of an input sensor according to an embodiment of the present disclosure;

[0035] Figure 7 According to the embodiment of the present disclosure Figure 5 and Figure 6 A cross-sectional view of the display panel and the input sensor taken along line II' in FIG.

[0036] Figures 8 to 10 According to various embodiments Figure 7 an enlarged view of region AA'; and

[0037] FIG. 11A to FIG. 11D 2 is a cross-sectional view illustrating respective steps of a method of manufacturing a display device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0038] It will be understood that when an element or layer is referred to as being "on," "connected to," or "coupled to" another element or layer, it may be directly on, directly connected to, or coupled to the other element or layer, or there may be one or more intervening elements or layers. When an element or layer is referred to as being "directly on," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. For example, when a first element is described as being "coupled to" or "connected to" a second element, the first element may be directly coupled to or connected to the second element, or the first element may be indirectly coupled to or connected to the second element via one or more intervening elements.

[0039] In the figure, for the clarity of illustration, the size of various elements, layers, etc. may be exaggerated. The same reference numerals refer to the same elements. As used herein, the term "and / or" includes any and all combinations of one or more of the listed related items. Further, when describing the embodiments of the present disclosure, the use of "may" relates to "one or more embodiments of the present disclosure". When the expressions such as "at least one of ... " and "any one of ... " are after a column of elements, the entire column of elements is modified instead of the individual elements in the column. For example, the expression "at least one of a, b and c" represents only a, only b, only c, a and b, a and c, b and c, a, b and c, all or their variants. As used herein, the terms "use", "in use" and "used" can be considered to be synonymous with the terms "utilize", "in use" and "utilized" respectively. As used herein, the terms "substantially", "about" and similar terms are used as approximate terms rather than as terms of degree, and are intended to illustrate the inherent deviations of measured values ​​or calculated values ​​that those of ordinary skill in the art will recognize.

[0040] It will be understood that although the terms first, second, etc. can be used to describe various elements in this article, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Therefore, the first element discussed below can be referred to as the second element without departing from the teaching of the present disclosure.

[0041] The terms used herein are for the purpose of describing the embodiments of the present disclosure, and are not intended to limit the present disclosure. As used herein, the singular form "one" is intended to also include the plural form, unless the context clearly indicates otherwise. It will be further understood that when used in this specification, the terms "include" and / or "comprise" indicate the presence of the described features, wholes, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, parts and / or their groups.

[0042] For ease of description, spatially relative terms such as "below," "below," "down," "above," and "on" may be used herein to describe the relationship between an element or feature illustrated in the figures and another (or some) element or feature. It will be understood that spatially relative terms are intended to cover different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figure is turned over, the elements described as "below" or "below" other elements or features will then be oriented as "above" or "on" other elements or features. Therefore, the term "below" can cover both above and below orientations. The device can be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0043] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will be further understood that terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and should not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0044] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0045] Figure 1 is a perspective view of a display device DD according to an embodiment of the present disclosure.

[0046] The display device DD can be activated in response to an electrical signal, and can display an image IM. As an example, the display device DD can be applied to large electronic products such as televisions, outdoor billboards, etc., or can be applied to small and medium-sized electronic products such as monitors, mobile phones, tablet computers, navigation units, game units, etc. However, these are just examples, and the display device DD can be applied to other electronic devices as long as they do not depart from the concept of the present disclosure. In this embodiment, a mobile phone is shown as an example of the display device DD.

[0047] According to an embodiment of the present disclosure, the display device DD may be flexible. The term "flexible" as used herein refers to the property of being able to be bent, including the ability to be completely bent to the ability to be bent to a few nanometers. For example, the display device DD may be a curved display device or a foldable display device. According to other embodiments, the display device DD may be rigid.

[0048] refer to Figure 1 , when viewed in a plane, the display device DD may have a rectangular shape defined by short sides extending in a first direction DR1 and long sides extending in a second direction DR2 crossing the first direction DR1. However, when viewed in a plane, the shape of the display device DD is not limited to the rectangular shape, and the display device DD may have various shapes such as a circular shape and other polygonal shapes.

[0049] The display device DD may display an image IM on the display surface IS in a third direction DR3 substantially perpendicular to a plane defined by the first direction DR1 and the second direction DR2. The image IM exiting from the display device DD may include a still image and a video. Figure 1 A clock widget and an application icon are shown as representative examples of the image IM, but the present disclosure is not limited thereto.

[0050] The display surface IS through which the image IM is displayed may correspond to the front surface of the display device DD and the front surface of the window WM. Hereinafter, the front surface of the window WM will be referred to by the same reference numerals as those of the display surface IS. Figure 1 A flat display surface IS is shown, however, according to various embodiments, the display surface IS of the display device DD may have a curved shape bent from at least one side of a flat surface.

[0051] The front (or upper) surface and the rear (or lower) surface of each component of the display device DD may be opposite to each other in the third direction DR3, and the normal direction of each of the front surface and the rear surface may be substantially parallel to the third direction DR3. The spacing distance between the front surface and the rear surface of each component (or each unit) in the third direction DR3 may correspond to the thickness of the component (or the unit) in the third direction DR3. In the present disclosure, the expression "when viewed in a plane" or "viewed on a plane" means a state viewed in the third direction DR3. The directions indicated by the first direction DR1, the second direction DR2, and the third direction DR3 are relative to each other, and therefore, the directions indicated by the first direction DR1, the second direction DR2, and the third direction DR3 may be changed to other directions.

[0052] The display device DD may sense (or detect) an external input applied thereto from the outside. The external input may include various external inputs provided from outside the display device DD. For example, the external input may include force, pressure, temperature, light, etc. The external input may include an external input (e.g., a hovering input) applied when a touch input (e.g., a pen or a user's hand) is very close to or in close proximity to the display device DD at a reference distance (e.g., a predetermined distance).

[0053] In the present embodiment, a touch input applied by a user US to the front surface of the display device DD is shown as a representative example of an external input. However, this is merely an example, and the external input may include all inputs that cause a change in capacitance and is not particularly limited. In addition, the area of ​​the display device DD in which the external input is sensed should not be limited to the front surface of the display device DD. The display device DD may sense an input applied by a user US to the side surface or rear surface of the display device DD depending on its design.

[0054] refer to Figure 1 , the display device DD may include a window WM and a housing EDC. The window WM and the housing EDC may be coupled to each other to form an outer shape (or appearance) of the display device DD, and may provide an internal space in which components of the display device DD are accommodated. As an example, components of the display device DD (such as a display panel, an input sensor, a protective member, an electronic module, etc.) may be accommodated between the window WM and the housing EDC.

[0055] The front surface IS (or display surface) of the window WM may have a transmission area TA and a frame area BZA. The transmission area TA may be an optically transparent area. Accordingly, the image IM emitted from the display device DD may be displayed through the transmission area TA (e.g., may be displayed through the transmission area TA or may be emitted through the transmission area TA), and the user US may view the image IM. In the present embodiment, the transmission area TA has a quadrilateral shape with rounded corners, however, this is only an example. The transmission area TA may have various shapes and is not particularly limited.

[0056] The border area BZA may be defined as being adjacent to the transmission area TA. As an example, the border area BZA may be disposed outside the transmission area TA and may surround the transmission area TA (e.g., may surround the transmission area TA in a plan view, or may extend around the periphery of the transmission area TA). Accordingly, the transmission area TA may have a shape defined by the border area BZA. However, this is merely an example, and the border area BZA may be disposed adjacent to only one side of the transmission area TA, or may be omitted. In addition, the border area BZA may be disposed at the side surface of the display device DD instead of the front surface of the display device DD.

[0057] The bezel area BZA may have a color (eg, a predetermined color) and may block light. The bezel area BZA of the window WM may prevent a component of the display device DD disposed to overlap with the bezel area BZA (eg, a component disposed below the bezel area BZA) from being viewed from the outside.

[0058] The housing EDC may include glass, plastic or metal material having relatively high rigidity. The housing EDC may protect the components contained therein. To this end, the housing EDC may absorb impact applied thereto from the outside, and may prevent foreign matter and moisture from entering the components of the display device DD contained in the housing EDC. The housing EDC may be provided in a form obtained by connecting a plurality of containing members.

[0059] Figure 2 is a cross-sectional view of a display device DD according to an embodiment of the present disclosure. Figure 2 The stacking structure of various components of the display device DD is schematically shown.

[0060] refer to Figure 2The display device DD may include a display panel DP, an input sensor (or sensor layer) ISP, a protection member PF, an anti-reflection layer RPL, a window WM, and adhesive layers AL1, AL2, and AL3. Components of the display device DD disposed under the window WM may be disposed between the window WM and the housing EDC, and may be accommodated in the housing EDC.

[0061] The display device DD may have an active area AA and a peripheral area NAA. The active area AA may be electrically activated. The display device DD may display an image through the active area AA and may sense an external input through the active area AA. The active area AA may be aligned with the transmissive area TA (see, for example, FIG. 1 ). Figure 1 ) corresponding to.

[0062] The peripheral area NAA may be an area in which elements used to activate the active area AA are disposed. The peripheral area NAA may be defined as being adjacent to the outside of the active area AA. As an example, the peripheral area NAA may surround the active area AA (e.g., may surround the active area AA in a plan view, or may extend around the periphery of the active area AA). The peripheral area NAA may be adjacent to the bezel area BZA (see, e.g., Figure 1 ) corresponding to.

[0063] In the following description, the expression “a region / portion corresponds to another region / portion” means “a region / portion overlaps another region / portion”; however, these regions / portions are not limited to having the same size or the same shape unless otherwise specifically defined.

[0064] The display panel DP may display an image in response to an electrical signal. According to an embodiment, the display panel DP may be a light-emitting display panel, however, it is not particularly limited. For example, the display panel DP may be an organic light-emitting display panel, an inorganic light-emitting display panel, or a quantum dot light-emitting display panel. The light-emitting layer of the organic light-emitting display panel may include an organic light-emitting material. The light-emitting layer of the inorganic light-emitting display panel may include an inorganic light-emitting material. The light-emitting layer of the quantum dot light-emitting display panel may include quantum dots and / or quantum rods. An organic light-emitting display panel will be described below as a representative example of the display panel DP.

[0065] The input sensor ISP may be disposed on the display panel DP. The input sensor ISP may be disposed directly on the display panel DP without a separate adhesive member. That is, the input sensor ISP may be formed on the substrate surface provided by the display panel DP through a continuous process after the display panel DP is formed, however, the present disclosure is not limited thereto or thereby. According to an embodiment, the input sensor ISP may be attached to the upper surface of the display panel DP through an adhesive member after being manufactured through a process separate from the display panel DP.

[0066] The input sensor ISP can sense an external input applied thereto from the outside and can obtain coordinate information about the external input. The input sensor ISP can operate in various ways such as a capacitive way, a resistive way, an infrared way, or a pressure way, and is not particularly limited.

[0067] The protection member PF may be disposed on the rear surface of the display panel DP. The protection member PF may include at least one of a protection film layer, an impact absorbing layer, and a support plate layer to protect the display panel DP from external impact.

[0068] The protective film layer may include a flexible polymer material such as polyethylene terephthalate or polyimide, and may protect the display panel DP. The impact absorbing layer may include sponge, foam, or urethane resin, and may absorb external impact applied to the display panel DP. The supporting plate layer may include a metal material having relatively high rigidity such as stainless steel, aluminum, or an alloy thereof, and may support the display panel DP under the display panel DP. The material of the protective member PF is not particularly limited as long as the protective member PF can protect the display panel DP.

[0069] An anti-reflection layer RPL may be disposed on the input sensor ISP. The anti-reflection layer RPL may reduce reflectivity of external light incident on the anti-reflection layer RPL from above the display device DD.

[0070] According to an embodiment, the anti-reflection layer RPL may include a retarder and / or a polarizer. The retarder may include a λ / 2 (e.g., half-wave) retarder and / or a λ / 4 (e.g., quarter-wave) retarder. The polarizer may be a film type or a liquid crystal coating type. The film type polarizer may include a stretched synthetic resin film, and the liquid crystal coating type polarizer may include liquid crystals arranged in an orientation (e.g., a predetermined orientation). However, the retarder and the polarizer are not limited to or by this, and the retarder and the polarizer may be implemented as one polarizing film.

[0071] According to an embodiment, the anti-reflection layer RPL may include a color filter. The color filter may be arranged according to (or in consideration of) the arrangement and emission color of the pixels included in the display panel DP. The color filter may receive external light and may filter the external light into the same color as the emission color of the pixel. The anti-reflection layer RPL may further include a black matrix disposed adjacent to the color filter.

[0072] According to an embodiment, the anti-reflection layer RPL may include a destructive interference structure. For example, the destructive interference structure may include a first reflective layer and a second reflective layer disposed at different layers from each other. The first reflected light and the second reflected light respectively reflected by the first reflective layer and the second reflective layer may undergo destructive interference, and thus, the anti-reflection layer RPL may reduce the reflectivity of external light.

[0073] The window WM may be provided on the display panel DP. The window WM may have a shape corresponding to the shape of the display panel DP. The window WM may cover the entire outer surface of the display panel DP and may protect the display panel DP from external impact and scratches.

[0074] The window WM may include an optically transparent insulating material. As an example, the window WM may include glass, sapphire or a polymer. The window WM may have a single-layer or multi-layer structure. The window WM may further include a functional layer such as an anti-fingerprint layer, a phase control layer, a hard coating layer, etc., disposed on the optically transparent substrate.

[0075] The adhesive layers AL1, AL2, and AL3 may include a first adhesive layer AL1, a second adhesive layer AL2, and a third adhesive layer AL3. The first adhesive layer AL1 may be disposed between the display panel DP and the protection member PF, and the display panel DP and the protection member PF may be coupled to each other through the first adhesive layer AL1. The second adhesive layer AL2 may be disposed between the anti-reflection layer RPL and the input sensor ISP, and the anti-reflection layer RPL and the input sensor ISP may be coupled to each other through the second adhesive layer AL2. The third adhesive layer AL3 may be disposed between the window WM and the anti-reflection layer RPL, and the window WM and the anti-reflection layer RPL may be coupled to each other through the third adhesive layer AL3. According to various embodiments, at least one of the first adhesive layer AL1, the second adhesive layer AL2, and the third adhesive layer AL3 may be omitted.

[0076] Each of the first adhesive layer AL1, the second adhesive layer AL2 and the third adhesive layer AL3 may include a transparent adhesive such as an optically clear adhesive (OCA) film, an optically clear resin (OCR) or a pressure-sensitive adhesive (PSA) film; however, the adhesive included in the first adhesive layer AL1, the second adhesive layer AL2 and the third adhesive layer AL3 is not limited to or restricted to this.

[0077] The display device DD may further include: an electronic module including various functional modules for driving the display panel DP; and a power module for supplying power required for the overall operation of the display device DD. As an example, the display device DD may include a camera module as a representative example of the electronic module.

[0078] Figure 3is a cross-sectional view of a display panel DP according to an embodiment of the present disclosure.

[0079] refer to Figure 3 , the display panel DP may include a base layer BL, a circuit layer DP-CL, a display element layer DP-OL and an encapsulation layer TFE.

[0080] The base layer BL may provide a base surface on which the circuit layer DP-CL is disposed. The base layer BL may be a rigid substrate; however, it is not limited thereto or thereby. According to another embodiment, the base layer BL may be a flexible substrate.

[0081] The base layer BL may have a display area DA and a non-display area NDA. The display area DA of the display panel DP may be activated in response to an electrical signal, and an image may be displayed through (or on) the display area DA. According to an embodiment, the display area DA of the display panel DP may be connected to the window WM (see, for example, FIG. Figure 1 ) of the transmissive area TA (see, for example, Figure 1 ) and a display device DD (see e.g. Figure 2 ) of the effective area AA (see e.g. Figure 2 ) corresponding to.

[0082] According to an embodiment, pads, driving circuits or driving lines for driving various elements provided in the display area DA, and various signal lines for providing electrical signals to the various elements may be provided in the non-display area NDA. The non-display area NDA of the display panel DP may be connected to the window WM (see, for example, Figure 1 ) of the border area BZA (see e.g. Figure 1 ) and a display device DD (see e.g. Figure 2 ) of the peripheral region NAA (see e.g. Figure 2 ) Corresponding to the bezel area BZA, components disposed in the non-display area NDA of the display panel DP may be prevented from being viewed from the outside.

[0083] The circuit layer DP-CL may be disposed on the base layer BL. The circuit layer DP-CL may include a driving element, a signal line, a signal pad, and at least one insulating layer.

[0084] The display element layer DP-OL may be disposed on the circuit layer DP-CL. The display element layer DP-OL may include a light emitting element disposed to overlap the display area DA. The light emitting element in the display element layer DP-OL may be electrically connected to a driving element in the circuit layer DP-CL, and may provide source light via the display area DA in response to a signal from the driving element.

[0085] The encapsulation layer TFE may be disposed on the display element layer DP-OL and may encapsulate the light emitting element. The encapsulation layer TFE may include a plurality of insulating layers. The insulating layer of the encapsulation layer TFE may be disposed to improve the optical efficiency of the light emitting element or to protect the light emitting element.

[0086] Figure 4 is a cross-sectional view of a display panel DP and an input sensor ISP according to an embodiment of the present disclosure.

[0087] refer to Figure 4 , the input sensor ISP may include a first sensing insulating layer IS-IL1, a first conductive layer IS-CL1, a second sensing insulating layer IS-IL2, a second conductive layer IS-CL2, and a third sensing insulating layer IS-IL3. The first sensing insulating layer IS-IL1 of the input sensor ISP may be directly disposed on the encapsulation layer TFE. According to another embodiment, the first sensing insulating layer IS-IL1 of the input sensor ISP may be omitted.

[0088] Each of the first conductive layer IS-CL1 and the second conductive layer IS-CL2 may have a single layer structure or a multi-layer structure. The conductive layer having a multi-layer structure may include: two or more layers including a transparent conductive layer and a metal layer. The conductive layer having a multi-layer structure may include: a metal layer including (or containing) metals different from each other.

[0089] The first conductive layer IS-CL1 and the second conductive layer IS-CL2 may include at least one of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), PEDOT, metal nanowires, and graphene as a transparent conductive layer. The first conductive layer IS-CL1 and the second conductive layer IS-CL2 may include at least one of molybdenum, silver, titanium, copper, aluminum, and alloys thereof as a metal layer. As an example, each of the first conductive layer IS-CL1 and the second conductive layer IS-CL2 may have a three-layer structure of titanium / aluminum / titanium. A metal with relatively high durability and low reflectivity may be applied as (or used as) an outer layer of the conductive layer, and a metal with high conductivity may be applied as (or used as) an inner layer of the conductive layer.

[0090] The first conductive layer IS-CL1 and the second conductive layer IS-CL2 may include a sensing pattern of an input sensor ISP, which will be described later. The sensing pattern may include a sensing electrode and a signal line connected to the sensing electrode.

[0091] Each of the first sensing insulating layer IS-IL1, the second sensing insulating layer IS-IL2, and the third sensing insulating layer IS-IL3 may include an inorganic layer or an organic layer. The inorganic layer may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. However, the materials used for the first sensing insulating layer IS-IL1, the second sensing insulating layer IS-IL2, and the third sensing insulating layer IS-IL3 are not limited thereto or are not limited thereto. According to an embodiment, each of the first sensing insulating layer IS-IL1 and the second sensing insulating layer IS-IL2 may include an organic layer. As an example, each of the first sensing insulating layer IS-IL1 and the second sensing insulating layer IS-IL2 may include an inorganic layer, and the third sensing insulating layer IS-IL3 may include an organic layer.

[0092] Figure 5 is a plan view of a display panel DP according to an embodiment of the present disclosure. Figure 5 Some of the components in the display panel DP are shown on a plane.

[0093] refer to Figure 5 , the display panel DP may include a base layer BL, a plurality of pixels PX, a plurality of signal lines electrically connected to the pixels PX, a scan driver SDV, a data driver DDV, and an emission driver EDV.

[0094] As described above, the base layer BL may have a display area DA and a non-display area NDA. The base layer BL may provide a base surface on which electrical elements and circuits of the display panel DP are disposed. Figure 5 In the embodiment, the base layer BL has a rectangular shape substantially parallel to the first direction DR1 and the second direction DR2 when viewed in a plane; however, the shape of the base layer BL is not limited thereto or thereby. According to an embodiment, the base layer BL may be designed in various ways (e.g., may have various shapes) depending on the structure of the display device DD.

[0095] Each of the pixels PX may include a light emitting element and a pixel driving circuit configured to include a plurality of transistors (e.g., a switching transistor, a driving transistor, etc.) connected to the light emitting element and at least one capacitor. Each of the pixels PX may emit light in response to an electrical signal applied thereto. The pixels PX may be arranged in the display area DA; however, this is merely an example. According to an embodiment, transistors of some pixels among the pixels PX may be arranged in the non-display area NDA, and the positions of these pixels are not particularly limited.

[0096] Each of the scan driver SDV, the data driver DDV, and the emission driver EDV may be disposed in the non-display area NDA of the display panel DP. According to an embodiment, the scan driver SDV and the emission driver EDV may be disposed in the non-display area NDA to be adjacent to each long side of the base layer BL, respectively. The data driver DDV may be disposed in the non-display area NDA to be adjacent to one short side of the base layer BL. However, it is not limited thereto or thereby. According to an embodiment, at least one of the scan driver SDV, the data driver DDV, and the emission driver EDV may be disposed to overlap with the display area DA. Therefore, the size of the non-display area NDA may be reduced, and the border area BZA of the display device DD may be reduced.

[0097] The data driver DDV may be manufactured in the form of an integrated circuit chip and may be mounted on the non-display area NDA of the display panel DP, however, it should not be limited thereto or thereby. According to an embodiment, the data driver DDV may be electrically connected to the display panel DP after being mounted on a separate flexible circuit board connected to the display panel DP.

[0098] According to an embodiment, at least a portion of the non-display area NDA of the display panel DP may be bent. As an example, the display panel DP may be bent so that a portion of the non-display area NDA in which the data driver DDV is disposed may overlap a portion of the display panel DP in which the display area DA is defined when viewed in a plane; however, the display panel DP is not limited thereto or thereby. According to an embodiment, the data driver DDV may be mounted on a separate flexible circuit board, and the flexible circuit board may be bent to be connected to one end of the display panel DP. Accordingly, the bezel area BZA of the display device DD may be reduced.

[0099] The signal lines may include a plurality of scan lines SL1 to SLm, a plurality of data lines DL1 to DLn, a plurality of emission lines EL1 to ELm, first and second control lines CSL1 and CSL2, power lines PL, and a plurality of connection lines CNL. Each of m and n is a natural number greater than 0.

[0100] Each of the pixels PX may be connected to a corresponding scan line among the scan lines SL1 to SLm, a corresponding data line among the data lines DL1 to DLn, and a corresponding emission line among the emission lines EL1 to ELm. Other types of signal lines may be provided in the display panel DP depending on the configuration of the pixel driving circuit of the pixel PX.

[0101] The scan lines SL1 to SLm may extend in the first direction DR1 and may be connected to the scan driver SDV. The data lines DL1 to DLn may extend in the second direction DR2 and may be connected to the data driver DDV. The emission lines EL1 to ELm may extend in the first direction DR1 and may be connected to the emission driver EDV.

[0102] The power line PL may extend in the second direction DR2 and may be disposed in the non-display area NDA. The power line PL may be disposed between the display area DA and the emission driver EDV, however, it is not limited thereto or thereby. For example, in another embodiment, the power line PL may be disposed between the display area DA and the scan driver SDV.

[0103] The connection line CNL may extend in the first direction DR1 and may be arranged in the second direction DR2 (for example, may be adjacent to each other in the second direction DR2). The connection line CNL may be connected to the power line PL and the pixel PX. The connection line CNL may be disposed in a layer different from the layer in which the power line PL is disposed and may be electrically connected to the power line PL; however, it is not limited thereto or thereby. According to an embodiment, the connection line CNL may be disposed in the same layer as the power line PL and may be provided (or formed) integrally with the power line PL. The first voltage may be applied to the pixel PX via the power line PL and the connection line CNL connected to the power line PL.

[0104] The first control line CSL1 may be connected to the scan driver SDV. The second control line CSL2 may be connected to the emission driver EDV.

[0105] The pad PD may be disposed adjacent to the lower end of the non-display area NDA. The pad PD may be disposed closer to the lower end of the display panel DP than the data driver DDV (e.g., the pad PD may be disposed between the lower end of the display panel DP and the data driver DDV). The pad PD may be arranged in the first direction DR1. The display device DD may include a circuit board including a timing controller for controlling operations of the scan driver SDV, the data driver DDV, and the emission driver EDV and a voltage generator for generating a voltage, and the pad PD may be connected to the circuit board of the display device DD.

[0106] Each of the pads PD may be connected to a corresponding signal line among the signal lines. The power line PL and the first and second control lines CSL1 and CSL2 may be connected to the pads PD. The data lines DL1 to DLn may be connected to the corresponding pads PD via the data driver DDV. As an example, the data lines DL1 to DLn may be connected to the data driver DDV, and the data driver DDV may be connected to the pads PD corresponding to the data lines DL1 to DLn, respectively.

[0107] The scan driver SDV may generate a plurality of scan signals in response to the scan control signal. The scan signals may be applied to the pixels PX via the scan lines SL1 to SLm. The data driver DDV may generate a plurality of data voltages corresponding to the image signals in response to the data control signal. The data voltages may be applied to the pixels PX via the data lines DL1 to DLn. The emission driver EDV may generate a plurality of emission signals in response to the emission control signal. The emission signals may be applied to the pixels PX via the emission lines EL1 to ELm.

[0108] The pixel PX may receive a data voltage in response to a scan signal. The pixel PX may emit light having a brightness corresponding to the data voltage in response to an emission signal, and thus may display an image. The emission time of the pixel PX may be controlled by the emission signal. Accordingly, the display panel DP may display an image through the display area DA by using the pixel PX.

[0109] Figure 6 is a plan view of an input sensor ISP according to an embodiment of the present disclosure. Figure 6 Some of the components of the input sensor ISP are shown on a plane.

[0110] refer to Figure 4 and Figure 6 , the input sensor ISP may include a first sensing insulating layer IS-IL1, a first conductive layer IS-CL1, a second sensing insulating layer IS-IL2, a second conductive layer IS-CL2, and a third sensing insulating layer IS-IL3. The first conductive layer IS-CL1 and the second conductive layer IS-CL2 of the input sensor ISP may include a first electrode group EG1, a second electrode group EG2, a first sensing signal line group SG1 connected to the first electrode group EG1, and a second sensing signal line group SG2 connected to the second electrode group EG2. The first electrode group EG1 and the second electrode group EG2 may be disposed in the sensing area I-AA, and the first sensing signal line group SG1 and the second sensing signal line group SG2 may be disposed in the line area I-NAA.

[0111] Figure 6 The shapes of the first electrode group EG1 and the second electrode group EG2 shown in FIG. 1 are merely examples, and the shapes of the first electrode group EG1 and the second electrode group EG2 may be designed in various ways depending on the structure and purpose of the display device DD.

[0112] The first sensing insulating layer IS-IL1 may provide a substrate surface on which the electrodes and lines of the input sensor ISP are disposed. However, according to another embodiment, the first sensing insulating layer IS-IL1 of the input sensor ISP may be omitted, and in such an embodiment, the electrodes and lines of the input sensor ISP may be disposed on a substrate surface provided by the display panel DP. Figure 6 An embodiment is shown in which the first sensing insulating layer IS-IL1 has a rectangular shape parallel to each of the first direction DR1 and the second direction DR2 when viewed in a plane; however, the shape of the first sensing insulating layer IS-IL1 is not limited to the rectangular shape. The shape of the first sensing insulating layer IS-IL1 may be selected according to the display panel DP (see, for example, FIG. Figure 5 ) of the basal layer BL (see e.g. Figure 5 )'s shape is designed in various ways.

[0113] The first sensing insulating layer IS-IL1 may have a sensing region I-AA and a line region I-NAA. The sensing region I-AA may be a region in which an external input provided from outside the display device DD is sensed. The line region I-NAA may be a region in which a line for providing an electrical signal for activating the sensing region I-AA is disposed. The sensing region I-AA may be connected to the display panel DP (see, for example, Figure 5 ) of the display area DA (see, for example, Figure 5 ), and the line area I-NAA may correspond to the display panel DP (see, for example Figure 5 ) of the non-display area NDA (see, for example, Figure 5 ) corresponding to.

[0114] In the present embodiment, the input sensor ISP may be, but is not limited to, a sensor operating in a capacitive mode. The input sensor ISP may obtain information about an external input based on a change in capacitance between the first electrode group EG1 and the second electrode group EG2. One of the first electrode group EG1 and the second electrode group EG2 may receive a driving signal, and the other of the first electrode group EG1 and the second electrode group EG2 may output a change in capacitance between the first electrode group EG1 and the second electrode group EG2 as a sensing signal. However, this is merely an example. The driving method of the input sensor ISP of the display device DD is not limited to or restricted to this.

[0115] The first electrode group EG1 may include first sensing electrodes IE1-1 to IE1-8. The second electrode group EG2 may include second sensing electrodes IE2-1 to IE2-6. Figure 6An embodiment is shown in which the first electrode group EG1 includes eight first sensing electrodes IE1-1 to IE1-8 and the second electrode group EG2 includes six second sensing electrodes IE2-1 to IE2-6; however, the number of sensing electrodes is not limited thereto or thereby.

[0116] The first sensing electrodes IE1-1 to IE1-8 may extend in the first direction DR1. Each of the first sensing electrodes IE1-1 to IE1-8 may form a row substantially parallel to the first direction DR1. The first sensing electrodes IE1-1 to IE1-8 may be arranged in the second direction DR2.

[0117] Each of the first sensing electrodes IE1-1 to IE1-8 may include a first sensor portion SP1 and a first connection portion CP1. The first sensor portions SP1 forming one first sensing electrode may be arranged in the first direction DR1. Each of the first connection portions CP1 may connect two first sensor portions SP1 adjacent to each other in the first direction DR1 among the first sensor portions SP1. The first sensor portion SP1 may be disposed on a different layer from the first connection portion CP1 and may be connected to the first connection portion CP1. As an example, the first sensor portion SP1 may be disposed on the first sensing insulating layer IS-IL1 and may be included in the first conductive layer IS-CL1, and the first connection portion CP1 may be disposed on the second sensing insulating layer IS-IL2 and may be included in the second conductive layer IS-CL2.

[0118] The second sensing electrodes IE2-1 to IE2-6 may extend in the second direction DR2. Each of the second sensing electrodes IE2-1 to IE2-6 may form a column substantially parallel to the second direction DR2. The second sensing electrodes IE2-1 to IE2-6 may be arranged in the first direction DR1.

[0119] Each of the second sensing electrodes IE2-1 to IE2-6 may include a second sensor portion SP2 and a second connection portion CP2. The second sensor portions SP2 forming one second sensing electrode may be arranged in the second direction DR2. Each of the second connection portions CP2 may connect two second sensor portions SP2 adjacent to each other in the second direction DR2 among the second sensor portions SP2. The second sensor portion SP2 may be disposed on the same layer as the second connection portion CP2, and may be provided (or formed) integrally with the second connection portion CP2. As an example, the second sensor portion SP2 and the second connection portion CP2 may be disposed on the first sensing insulating layer IS-IL1, and may be included in the first conductive layer IS-CL1. For example, when viewed in a plane, the first connection portion CP1 may intersect the second connection portion CP2 while being electrically insulated from the second connection portion CP2.

[0120] The lengths or sizes of the first sensing electrodes IE1-1 to IE1-8 and the second sensing electrodes IE2-1 to IE2-6 may vary depending on the arrangement of the sensing electrodes and the size of the sensing area I-AA.

[0121] Each of the first sensor portion SP1, the second sensor portion SP2, the first connection portion CP1, and the second connection portion CP2 may be conductive. Each of the first sensor portion SP1, the second sensor portion SP2, the first connection portion CP1, and the second connection portion CP2 may be formed of the first conductive layer IS-CL1 or the second conductive layer IS-CL2.

[0122] Figure 6 An embodiment in which the first sensor portion SP1 and the second sensor portion SP2 each have a rhombus shape is shown; however, this is merely an example. According to another embodiment, each of the first sensor portion SP1 and the second sensor portion SP2 may have various shapes. In addition, Figure 6 An embodiment in which each of the first connection portions CP1 has a straight line shape is shown, however, this is merely an example. According to another embodiment, each of the first connection portions CP1 may be changed to a curved line form having an inverted "V" shape (e.g., "∧") offset from the second connection portion CP2 (e.g., so as not to overlap with the second connection portion CP2) and / or a curved line form having a shape "∨" similar to a V shape.

[0123] When viewed in a plane, the first sensing electrodes IE1-1 to IE1-8 and the second sensing electrodes IE2-1 to IE2-6 may be aligned with the display panel DP (see, for example, Figure 5 ) of the display area DA (see, for example, Figure 5) overlap. Accordingly, the first sensing electrodes IE1-1 to IE1-8 and the second sensing electrodes IE2-1 to IE2-6 may include an optically transparent conductive material. In addition, the first sensing electrodes IE1-1 to IE1-8 and the second sensing electrodes IE2-1 to IE2-6 may form (or may be arranged in) a grid pattern. The first sensing electrodes IE1-1 to IE1-8 and the second sensing electrodes IE2-1 to IE2-6 may be provided in various ways and are not particularly limited as long as the visibility of the image displayed by the display panel DP is not degraded.

[0124] The first sensing signal line group SG1 may include the same number of first sensing signal lines as the number of first sensing electrodes IE1-1 to IE1-8. The first sensing signal line may be connected to one of the two ends (e.g., opposite ends) of the first sensing electrodes IE1-1 to IE1-8. As an example, the first sensing signal line group SG1 may be divided into two groups, which are respectively defined as a first signal line group SG1-1 disposed on one side of the line area I-NAA and a second signal line group SG1-2 disposed on the other side of the line area I-NAA.

[0125] The first signal line group SG1-1 may be connected to the left side of some of the first sensing electrodes IE1-1 to IE1-8. The second signal line group SG1-2 may be connected to the right side of the remaining sensing electrodes that are not connected to the first signal line group SG1-1 among the first sensing electrodes IE1-1 to IE1-8. The first signal line group SG1-1 and the second signal line group SG1-2 may be spaced apart from each other in the first direction DR1 with the sensing area I-AA therebetween. When the first sensing signal lines of the first sensing signal line group SG1 are divided into two groups disposed on both sides, the width of the line area I-NAA may be reduced.

[0126] For example, the first signal line group SG1-1 may be electrically connected to sensing electrodes forming odd rows among the first sensing electrodes IE1-1 to IE1-8, and the second signal line group SG1-2 may be electrically connected to sensing electrodes forming even rows among the first sensing electrodes IE1-1 to IE1-8.

[0127] However, the arrangement of the first sensing signal lines of the first sensing signal line group SG1 is not limited thereto or thereby. As an example, the first sensing signal lines may be connected to both ends of the first sensing electrodes IE1-1 to IE1-8. According to an embodiment, all the first sensing signal lines of the first sensing signal line group SG1 may be connected to the left side of the first sensing electrodes IE1-1 to IE1-8 or to the right side of the first sensing electrodes IE1-1 to IE1-8 without being divided into two groups.

[0128] The second sensing signal line group SG2 may include the same number of second sensing signal lines as the number of second sensing electrodes IE2-1 to IE2-6. The second sensing signal lines may be connected to one of both ends (eg, opposite ends) of the second sensing electrodes IE2-1 to IE2-6. Figure 6 , the second sensing signal lines of the second sensing signal line group SG2 may be connected to lower ends of the second sensing electrodes IE2 - 1 to IE2 - 6 , respectively.

[0129] Each of the sensing signal lines of the first sensing signal line group SG1 and the second sensing signal line group SG2 may be connected to a corresponding sensing pad PD-I among the sensing pads PD-I arranged in the first direction DR1. The sensing pads PD-I may be connected to the same circuit board as the display panel DP, or the sensing pads PD-I may be connected to a circuit board separate from the circuit board connected to the display panel DP and may be independently controlled.

[0130] The sensing pad PD-I may be disposed at a different layer from the pad PD of the display panel DP; however, it is not limited thereto or thereby. According to an embodiment, the sensing pad PD-I may be disposed at the same layer as the pad PD of the display panel DP, and the ends of the sensing signal lines of the input sensor ISP may be electrically connected to the corresponding sensing pads PD-I through contact holes (e.g., contact openings), respectively.

[0131] Figure 7 According to the embodiment of the present disclosure Figure 5 and Figure 6 2 is a cross-sectional view of the display panel DP and the input sensor ISP taken along line II′ in FIG. Figure 7 1 shows a cross section of the display panel DP and the input sensor ISP in the display area DA and the non-display area NDA adjacent to the display area DA. Figure 7 In the drawings, the same reference numerals denote Figures 1 to 6 The same elements are the same elements in FIG. 1 , and thus a detailed description of the same elements will be omitted.

[0132] refer to Figure 7 The display panel DP may include a base layer BL, a circuit layer DP-CL, a display element layer DP-OL, and an encapsulation layer TFE. The details of the components of the display panel DP described above may be applied to, for example, Figure 7 Components of the display panel DP shown in FIG.

[0133] The base layer BL may include a glass substrate, a metal substrate, a polymer substrate, or an organic / inorganic composite material substrate. The base layer BL may include a synthetic resin layer. As an example, the synthetic resin layer may include at least one of acrylic resin, methacrylic resin, polyisoprene resin, vinyl resin, epoxy resin, urethane resin, cellulose resin, siloxane resin, polyamide resin, perylene resin, and polyimide resin; however, the material for the base layer BL is not limited thereto or thereby.

[0134] The circuit layer DP-CL may be disposed on the base layer BL. The circuit layer DP-CL may include a conductive pattern, a semiconductor pattern, and at least one insulating layer. During the manufacturing process of the display panel DP, an insulating layer, a semiconductor layer, and a conductive layer may be formed on the base layer BL by a coating process or a deposition process. Then, the insulating layer, the semiconductor layer, and the conductive layer may be selectively patterned by several photolithography processes. After completing these processes, the semiconductor pattern, the conductive pattern, and the signal line included in the circuit layer DP-CL may be formed.

[0135] Figure 7 The first insulating layer 10, the second insulating layer 20, the third insulating layer 30, the fourth insulating layer 40, the fifth insulating layer 50 and the sixth insulating layer 60, the semiconductor pattern and the conductive pattern included in the circuit layer DP-CL are shown. However, Figure 7 The cross section of the circuit layer DP-CL shown in FIG. 1 is merely an example, and the stacking structure of the circuit layer DP-CL may be changed in various ways depending on a process, a process method, or a configuration of a pixel.

[0136] The first insulating layer 10 may be disposed on the base layer BL. The first insulating layer 10 may include an inorganic layer and may be provided on the base layer BL as a barrier layer. The first insulating layer 10 provided as a barrier layer may prevent foreign matter from entering the first insulating layer 10 from the outside. The first insulating layer 10 may include at least one of a silicon oxide layer and a silicon nitride layer. According to an embodiment, the first insulating layer 10 provided as a barrier layer may include a silicon oxide layer and a silicon nitride layer alternately stacked with the silicon oxide layer.

[0137] The second insulating layer 20 may be disposed on the first insulating layer 10. The second insulating layer 20 may include an inorganic layer and may be provided on the base layer BL as a buffer layer. The second insulating layer 20 provided as a buffer layer may improve adhesion between the base layer BL and the semiconductor pattern or the conductive pattern. The second insulating layer 20 may include at least one of a silicon oxide layer and a silicon nitride layer, and the second insulating layer 20 provided as a buffer layer may include a silicon oxide layer and a silicon nitride layer alternately stacked with the silicon oxide layer.

[0138] The pixels PX may be disposed on the second insulating layer 20. Each of the pixels PX may have an equivalent circuit including a transistor TR, a light emitting element EL, and at least one capacitor, and the equivalent circuit of the pixel PX may be changed in various ways. According to the equivalent circuit of the pixel PX, the semiconductor pattern may be arranged throughout the pixels PX (for example, may be arranged throughout the pixels PX in a specific rule or pattern). Figure 7 Some components of the pixel PX are shown as representative examples.

[0139] The transistor TR may include a semiconductor pattern SP and a gate GE. The semiconductor pattern SP may be disposed on the second insulating layer 20. The semiconductor pattern SP may include a silicon semiconductor, and may include a crystalline silicon semiconductor such as a polycrystalline silicon semiconductor or an amorphous silicon semiconductor; however, it is not limited thereto or thereby. The semiconductor pattern SP may include an oxide semiconductor. The semiconductor pattern SP may include various materials as long as the semiconductor pattern SP has semiconductor characteristics, and it is not particularly limited thereto.

[0140] The source Sa, drain Da, and channel Aa of the transistor TR may be formed by a semiconductor pattern SP. The semiconductor pattern SP may have a plurality of regions that are distinguished from each other depending on their respective conductivity. As an example, the semiconductor pattern SP may have different electrical characteristics depending on whether it is doped, whether it is doped with an N-type dopant or a P-type dopant, or whether the metal oxide is reduced. The region in which the metal oxide is reduced (hereinafter referred to as the reduction region) has a greater conductivity than the region in which the metal oxide is not reduced (hereinafter referred to as the non-reduction region). The portion of the semiconductor pattern having a relatively high conductivity may be used as an electrode or a signal line, and may correspond to the source Sa and drain Da of the transistor TR. The undoped or unreduced portion of the semiconductor pattern having a relatively low conductivity may correspond to the channel Aa (or active area) of the transistor TR.

[0141] The semiconductor pattern SP may have a first region with high conductivity and a second region with low conductivity. The first region may be doped with an N-type dopant or a P-type dopant. A P-type transistor may include a doped region doped with a P-type dopant, and an N-type transistor may include a doped region doped with an N-type dopant. The second region may be a non-doped region, or may be doped at a concentration lower than that of the first region.

[0142] The third to sixth insulating layers 30 to 60 may be stacked on the semiconductor pattern SP. The third to sixth insulating layers 30 to 60 may include an inorganic layer or an organic layer. As an example, the inorganic layer may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. The organic layer may include a phenolic polymer, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorine polymer, a paraxylene polymer, a vinyl alcohol polymer, or a mixture thereof. However, the material used for the insulating layer is not limited thereto or thereby.

[0143] The third insulating layer 30 may be disposed on the second insulating layer 20 and may cover the semiconductor pattern SP. The third insulating layer 30 may be disposed between the semiconductor pattern SP and the gate GE of the transistor TR. According to an embodiment, the third insulating layer 30 may be an inorganic layer having a single layer or multi-layer structure.

[0144] The gate GE may be disposed on the third insulating layer 30. The gate GE may be a portion of the conductive pattern of the circuit layer DP-CL. When viewed in a plane, the gate GE may overlap the channel Aa of the transistor TR. The gate GE may be used as a mask in a process of doping the semiconductor pattern SP.

[0145] Figure 7 The transistor TR shown in FIG is merely an example, and the source Sa or the drain Da may be an electrode formed independently of the semiconductor pattern SP. In such an embodiment, after penetrating (or passing through) the insulating layer, the source Sa and the drain Da may contact the semiconductor pattern SP or may be connected to the semiconductor pattern SP. According to an embodiment, the gate GE may be disposed under the semiconductor pattern SP. The transistor TR may have various structures and should not be particularly limited.

[0146] The fourth insulating layer 40 may be disposed on the third insulating layer 30 and may cover the gate GE. According to an embodiment, the fourth insulating layer 40 may be an inorganic layer having a single layer or a multi-layer structure. The fifth insulating layer 50 may be disposed on the fourth insulating layer 40. According to an embodiment, the fifth insulating layer 50 may be an organic layer having a single layer or a multi-layer structure.

[0147] The first connection electrode CN1 may be disposed on the fourth insulating layer 40. The second connection electrode CN2 may be disposed on the fifth insulating layer 50. The first connection electrode CN1 may be electrically connected to the semiconductor pattern SP via a contact hole (e.g., a contact opening) defined through the third insulating layer 30 and the fourth insulating layer 40. The second connection electrode CN2 may be electrically connected to the first connection electrode CN1 via a contact hole (e.g., a contact opening) defined through the fifth insulating layer 50. The sixth insulating layer 60 may be disposed on the fifth insulating layer 50, and may cover the second connection electrode CN2.

[0148] At least one of the first connection electrode CN1 and the second connection electrode CN2 may be omitted. According to an embodiment, an additional connection electrode may be provided to connect the light emitting element EL and the transistor TR. The electrical connection method between the light emitting element EL and the transistor TR may be changed in various ways depending on the number of insulating layers provided between the light emitting element EL and the transistor TR, and is not particularly limited.

[0149] The circuit layer DP-CL may include a scan driver SDV disposed on the base layer BL. Figure 7 The cross section of the scan driver SDV disposed in the non-display area NDA is schematically shown; however, the present embodiment should not be limited thereto or thereby. According to another embodiment, at least some components of the scan driver SDV may be disposed in the display area DA and may overlap with the light emitting element EL.

[0150] The scan driver SDV may include a driving transistor TR-D, a first signal line CL1, and a second signal line CL2. The driving transistor TR-D may be disposed on the second insulating layer 20. The driving transistor TR-D may be formed on the same layer as the transistor TR of the pixel PX; however, it should not be limited thereto or thereby. The driving transistor TR-D may be disposed on a different layer than the transistor TR of the pixel PX.

[0151] The driving transistor TR-D may include a semiconductor pattern SP, a gate GE, a source IE, and a drain OE. Each of the gate GE, the source IE, and the drain OE may be formed as an electrode and may be formed independently of the semiconductor pattern SP. The source IE and the drain OE may be disposed on the fourth insulating layer 40 and may be connected to the semiconductor pattern SP via a contact hole (e.g., a contact opening) defined through the third insulating layer 30 and the fourth insulating layer 40.

[0152] The structure described above is merely an example, and according to another embodiment, the driving transistor TR-D may have the same structure as the transistor TR of the pixel PX. In such an embodiment, since the driving transistor TR-D may be formed by the same process as the transistor TR of the pixel PX, the process may be simplified and the process cost may be reduced.

[0153] The first signal line CL1 and the second signal line CL2 may be disposed at different layers from each other. According to an embodiment, the first signal line CL1 may be disposed at the same layer as the gate GE of the driving transistor TR-D, and the second signal line CL2 may be disposed at the same layer as the source IE or drain OE of the driving transistor TR-D. The first signal line CL1 and the second signal line CL2 may electrically connect the driving transistor TR-D to other components of the scan driver SDV. This is merely an example, and according to another embodiment, one of the first signal line CL1 and the second signal line CL2 may be omitted.

[0154] The display element layer DP-OL may be disposed on the circuit layer DP-CL. The display element layer DP-OL may include a light emitting element EL and a pixel defining layer PDL. The light emitting element EL may be electrically connected to the transistor TR to form a pixel PX. The light emitting element EL may be disposed in the display area DA and may emit light. As an example, the light emitting element EL may include an organic light emitting element, a quantum dot light emitting element, a micron LED, or a nano LED; however, it is not limited thereto or thereby. According to an embodiment, the light emitting element EL may include various embodiments as long as light can be generated or the amount of light can be controlled according to an electrical signal.

[0155] The light emitting element EL may include a first electrode AE, a light emitting layer EM, and a second electrode CE. The first electrode AE ​​may be disposed on the sixth insulating layer 60. The first electrode AE ​​may be connected to the second connection electrode CN2 via a contact hole (eg, a contact opening) defined through the sixth insulating layer 60.

[0156] The pixel defining layer PDL may be disposed on the first electrode AE ​​and the sixth insulating layer 60 and may expose at least a portion of the first electrode AE. For example, a light emitting opening OP may be defined through the pixel defining layer PDL to expose at least a portion of the first electrode AE.

[0157] The pixel defining layer PDL may be formed of a polymer resin. As an example, the pixel defining layer PDL may include a polyacrylate resin or a polyimide resin. In addition to the polymer resin, the pixel defining layer PDL may also include an inorganic material. According to an embodiment, the pixel defining layer PDL may include an inorganic material. As an example, the pixel defining layer PDL may include silicon nitride (SiN x ), silicon oxide (SiO x ) or silicon oxynitride (SiO x N y ).

[0158] The pixel defining layer PDL may include a light absorbing material. The pixel defining layer PDL may include a black colorant. The black colorant may include a black pigment or a black dye. The black colorant may include carbon black, a metal material such as chromium, or an oxide thereof.

[0159] The light emitting layer EM may be disposed on the first electrode AE. The light emitting layer EM may be disposed in a region corresponding to the light emitting opening OP in the pixel defining layer PDL. The light emitting layer EM may provide (e.g., may emit) light having a predetermined color. The light emitting layer EM may include an organic light emitting material and / or an inorganic light emitting material. As an example, the light emitting layer EM may include a fluorescent material or a phosphorescent material, an organic metal complex light emitting material, or a quantum dot.

[0160] The second electrode CE may be disposed on the light emitting layer EM. The second electrode CE may be commonly disposed throughout the pixels PX. The second electrode CE may receive a common voltage, and the second electrode CE may be referred to as a common electrode.

[0161] The light emitting element EL may further include a light emitting functional layer disposed between the first electrode AE ​​and the second electrode CE. As an example, the light emitting element EL may include a hole transport layer or a hole injection layer disposed between the first electrode AE ​​and the light emitting layer EM and an electron transport layer or an electron injection layer disposed between the light emitting layer EM and the second electrode CE.

[0162] The first voltage may be applied to the first electrode AE ​​via the transistor TR, and the common voltage may be applied to the second electrode CE. The holes and electrons injected into the light emitting layer EM may be recombined with each other to generate excitons. When the excitons return from the excited state to the ground state, the light emitting element EL may emit light through the display area DA.

[0163] The display panel DP may include a power supply pattern ES and a conductive pattern CP connected to the second electrode CE. The power supply pattern ES may be disposed in the non-display area NDA, and the conductive pattern CP may be disposed on the power supply pattern ES. The conductive pattern CP may extend from the power supply pattern ES to the display area DA. The conductive pattern CP may electrically connect the power supply pattern ES to the second electrode CE, and the power supply pattern ES may supply a power supply voltage to the second electrode CE.

[0164] The encapsulation layer TFE may be disposed on the display element layer DP-OL and may cover the light emitting element EL. The encapsulation layer TFE may encapsulate the light emitting element EL. The encapsulation layer TFE may include at least one insulating layer, and the insulating layer may be an inorganic layer or an organic layer. According to an embodiment, the encapsulation layer TFE may include a plurality of insulating layers, at least one of which may be an organic layer, and at least another of which may be an inorganic layer. Figure 7An embodiment in which the encapsulation layer TFE includes a first inorganic layer IL1, an organic layer OL, and a second inorganic layer IL2 is shown as an example. The first inorganic layer IL1 may be disposed on the second electrode CE. The organic layer OL may be disposed on the first inorganic layer IL1. The second inorganic layer IL2 may be disposed on the organic layer OL and may cover the organic layer OL. However, the stacking structure of the encapsulation layer TFE is not limited thereto or thereby.

[0165] The first inorganic layer IL1 and the second inorganic layer IL2 may protect the light emitting element EL from moisture and / or oxygen. As an example, the first inorganic layer IL1 and the second inorganic layer IL2 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide; however, it is not limited thereto or thereby. The first inorganic layer IL1 and the second inorganic layer IL2 may extend from the display area DA and may be disposed in the non-display area NDA. The first inorganic layer IL1 may cover the power supply pattern ES and the conductive pattern CP, and the second inorganic layer IL2 may contact the first inorganic layer IL1 in the non-display area NDA.

[0166] The organic layer OL may protect the light emitting element EL from foreign matter such as dust particles. As an example, the organic layer OL may include an acrylic resin; however, the material of the organic layer OL is not limited thereto or thereby. The organic layer OL may be formed by providing a liquid polymer resin on the first inorganic layer IL1 and curing the liquid polymer resin. The liquid polymer resin may be formed by a vapor deposition method, a printing method, or a slit coating method; however, it is not limited thereto or thereby. According to an embodiment, the organic layer OL may be formed by an inkjet process.

[0167] The input sensor ISP may be disposed on the display panel DP. Figure 4 As shown in FIG, the input sensor ISP may include first, second and third sensing insulating layers IS-IL1, IS-IL2 and IS-IL3 and first and second conductive layers IS-CL1 and IS-CL2.

[0168] The first sensing insulating layer IS-IL1 may be disposed on the encapsulation layer TFE. The first sensing insulating layer IS-IL1 may be formed through a continuous process after forming the encapsulation layer TFE, and the first sensing insulating layer IS-IL1 may be in contact with the uppermost layer of the encapsulation layer TFE. Figure 7 , the first sensing insulating layer IS-IL1 may contact the second inorganic layer IL2 provided as the uppermost layer of the encapsulation layer TFE. The first sensing insulating layer IS-IL1 may extend from the display area DA and may be disposed in the non-display area NDA.

[0169] The first conductive layer IS-CL1 of the input sensor ISP (see for example Figure 4 ) and a second conductive layer IS-CL2 (see e.g. Figure 4 ) can include Figure 6 The sensing electrodes or sensing signal lines shown in . Figure 7 A cross section of the components of the input sensor ISP is schematically shown, and the following description is based on Figure 7 ; however, the arrangement of the components of the input sensor ISP is not limited thereto or thereby.

[0170] The first sensor portion SP1 and the second connection portion CP2 may be formed of the first conductive layer IS-CL1 and may be disposed on the first sensing insulating layer IS-IL1. The second sensor portion SP2 may also be disposed on the first sensing insulating layer IS-IL1. The first sensor portion SP1, the second sensor portion SP2, and the second connection portion CP2 may be disposed to overlap the display area DA. The second sensing insulating layer IS-IL2 may be disposed on the first sensing insulating layer IS-IL1 and may cover the first sensor portion SP1, the second sensor portion SP2, and the second connection portion CP2. The second sensing insulating layer IS-IL2 may extend from the display area DA and may be disposed in the non-display area NDA.

[0171] The first connection portion CP1 may be formed of the second conductive layer IS-CL2 and may be disposed on the second sensing insulating layer IS-IL2. The first connection portion CP1 may be electrically connected to the first sensor portion SP1 via a contact hole (e.g., a contact opening) CH defined to pass through the second sensing insulating layer IS-IL2. When viewed in a plane, the first connection portion CP1 may overlap with the second connection portion CP2 and may be electrically insulated from the second connection portion CP2 by the second sensing insulating layer IS-IL2.

[0172] The sensor portion and the connection portion of the input sensor ISP may form a grid pattern and may be disposed in an area corresponding to an area in which the pixel defining layer PDL is disposed. Accordingly, the input sensor ISP may not affect the luminous efficiency of the light emitting element EL (e.g., may not reduce the luminous efficiency of the light emitting element EL); however, it is not limited thereto or thereby. According to another embodiment, the input sensor ISP may have a single shape pattern overlapping the light emitting element EL and may include a transparent conductive material.

[0173] The second conductive layer IS-CL2 (see e.g. Figure 4 ) can form a sensing signal line. Figure 7A portion of the sensing signal line of the first signal line group SG1-1 described above is shown as an example. The sensing signal line may be disposed on the second sensing insulating layer IS-IL2; however, it is not limited thereto or thereby. According to an embodiment, the sensing signal line may be a portion of the first conductive layer IS-CL1. The sensing signal line may be disposed in the non-display area NDA.

[0174] The third sensing insulating layer IS-IL3 may be disposed on the second sensing insulating layer IS-IL2 and may cover the first connection portion CP1 and the sensing signal line. The third sensing insulating layer IS-IL3 may extend from the display area DA and may also be disposed in the non-display area NDA.

[0175] When viewed in a plane, the conductive pattern CP may be disposed between the sensing signal line and the scan driver SDV, and may overlap the sensing signal line and the scan driver SDV. The conductive pattern CP may be used as a shielding electrode. For example, the conductive pattern CP may prevent parasitic capacitance from being generated between the sensing signal line and the scan driver SDV. Accordingly, the phenomenon that the signal applied to the sensing signal line is changed (e.g., affected) by the scan driver SDV and generates noise may be reduced or avoided.

[0176] The display panel DP may include a flow control dam FDM, a first dam DM1, and a second dam DM2. The flow control dam FDM, the first dam DM1, and the second dam DM2 may be disposed in the non-display area NDA.

[0177] The flow control dam FDM may be disposed outside the organic layer OL. The flow control dam FDM may control the flow of the organic layer OL toward the outer edge of the base layer BL. The flow control dam FDM may be covered by the first inorganic layer IL1. Figure 7 A structure in which the flow control dam FDM is disposed on the power pattern ES is shown as an example; however, the present disclosure is not limited thereto or thereby. According to another embodiment, the flow control dam FDM may be disposed closer to the outside of the non-display area NDA than the power pattern ES, and may not overlap with the power pattern ES. For example, the position of the flow control dam FDM is not limited as long as the flow of the organic layer OL is controlled.

[0178] The flow control dam FDM may have a multi-layer structure. As an example, the flow control dam FDM may include a first layer D1_F and a second layer D2_F. At least one of the first layer D1_F and the second layer D2_F included in the flow control dam FDM may be formed in a process of forming at least one of the insulating layers 10, 20, 30, 40, 50 and 60 of the circuit layer DP-CL and the pixel defining layer PDL of the display element layer DP-OL. As an example, the first layer D1_F may be formed by the same process as the sixth insulating layer 60, and the second layer D2_F may be formed by the same process as the pixel defining layer PDL; however, these are merely examples. According to another embodiment, the flow control dam FDM may have a single-layer structure, or may have a structure including more than Figure 7 The layers shown in the figure are multi-layer structures with more layers.

[0179] The first dam DM1 may be disposed outside the flow control dam FDM. The first dam DM1 may be covered by the first inorganic layer IL1. Figure 7 A structure in which the first dam DM1 overlaps a portion of the power pattern ES is shown; however, the present disclosure is not limited thereto or thereby. According to an embodiment, the first dam DM1 may be disposed closer to the outside of the non-display area NDA than the power pattern ES and may not overlap the power pattern ES. For example, the position of the first dam DM1 is not limited.

[0180] The first dam DM1 may have a multi-layer structure. As an example, the first dam DM1 may include a first layer D1 formed by the same process as the fifth insulating layer 50, a second layer D2 formed by the same process as the sixth insulating layer 60, a third layer D3 formed by the same process as the pixel defining layer PDL, and a fourth layer D4 formed by a separate process; however, this is merely an example. According to an embodiment, at least a portion of the first dam DM1 may be formed synchronously (e.g., substantially simultaneously) with at least one of the insulating layers 10, 20, 30, 40, 50, and 60 of the circuit layer DP-CL and the pixel defining layer PDL of the display element layer DP-OL. In addition, the first dam DM1 may have a single-layer structure, or may have a structure including a plurality of layers. Figure 7 The layers shown in the figure are multi-layer structures with more layers.

[0181] The second dam DM2 may be disposed outside the first dam DM1. The second dam DM2 may be spaced apart from the first dam DM1 in a direction away from the display area DA from the boundary between the display area DA and the non-display area NDA (e.g., in a direction opposite to the first direction DR1). A portion of the second dam DM2 may be covered by the first inorganic layer IL1, and the other portion of the second dam DM2 may be covered by the second inorganic layer IL2; however, this is merely an example. According to an embodiment, the second dam DM2 may be covered by the first inorganic layer IL1. For example, the second dam DM2 is not limited as long as the second dam DM2 is covered by an inorganic layer.

[0182] The second dam DM2 may reduce the amount of damage in the display device DD (see, e.g. Figure 1 ) from the outside, and thus cracks can be prevented from being generated in the insulating layer. The second dam DM2 may include a covering member CM and a plurality of insulating patterns IP. The insulating patterns IP may be arranged to be spaced apart from each other in the first direction DR1, and may extend in the second direction DR2. Spaces may be defined between the insulating patterns IP. The covering member CM may completely cover the insulating patterns IP, and may prevent foreign matter such as particles or prevent some parts of the insulating patterns IP from being separated from the insulating patterns IP. The covering member CM may fill in the spacing spaces between the insulating patterns IP.

[0183] Each of the insulating patterns IP may include a first layer IP1 and a second layer IP2. The first layer IP1 may be disposed on the second insulating layer 20, and the second layer IP2 may be disposed on the first layer IP1. The first layer IP1 may be formed by the same process as the third insulating layer 30, and the second layer IP2 may be formed by the same process as the fourth insulating layer 40.

[0184] An inorganic layer area ILA may be defined between the first dam DM1 and the second dam DM2. The inorganic layer area ILA may be an area where only inorganic layers are stacked. The first inorganic layer IL1, the second inorganic layer IL2, the first sensing insulating layer IS-IL1, the second sensing insulating layer IS-IL2, and the third sensing insulating layer IS-IL3 may be sequentially stacked in the inorganic layer area ILA. As an example, in the inorganic layer area ILA, the second inorganic layer IL2 may be disposed on the first inorganic layer IL1 to contact the first inorganic layer IL1, and the first sensing insulating layer IS-IL1 may be disposed on the second inorganic layer IL2 to contact the second inorganic layer IL2. In addition, the second sensing insulating layer IS-IL2 may be disposed on the first sensing insulating layer IS-IL1 to contact the first sensing insulating layer IS-IL1, and the third sensing insulating layer IS-IL3 may be disposed on the second sensing insulating layer IS-IL2 to contact the second sensing insulating layer IS-IL2. For example, the second sensing insulating layer IS-IL2 may contact the first and third sensing insulating layers IS-IL1 and IS-IL3 in the inorganic layer area ILA. The inorganic layer area ILA may define a groove HM therein.

[0185] Figures 8 to 10 According to various embodiments Figure 7 Magnified view of area AA' in FIG.

[0186] refer to Figure 7 and Figure 8 , a groove HM may be defined in the inorganic layer area ILA. For example, the groove HM may overlap the non-display area NDA. The groove HM may be defined in the first inorganic layer IL1, the second inorganic layer IL2, the first sensing insulating layer IS-IL1, and the second sensing insulating layer IS-IL2. As an example, the inner surface of the first inorganic layer IL1, the inner surface of the second inorganic layer IL2, the inner surface of the first sensing insulating layer IS-IL1, and the inner surface of the second sensing insulating layer IS-IL2 may define the groove HM. The third sensing insulating layer IS-IL3 may be disposed on the second sensing insulating layer IS-IL2 and may cover the groove HM.

[0187] The first conductive layer IS-CL1 (see e.g. Figure 4 ) (eg, a first sensor portion SP1 (see, eg, Figure 6 )) and a second conductive layer IS-CL2 (see e.g. Figure 4 ) (eg, a first connection portion CP1 (see, eg, Figure 6 The contact hole CH at which the contact holes CH are connected to each other is defined to pass through the second sensing insulating layer IS-IL2, and the groove HM may be formed by the same process as the contact hole CH. As an example, the contact hole CH may be formed by using a mask MK (see, for example Fig. 11C ) to form the groove HM in the inorganic layer area ILA.

[0188] According to an embodiment of the present disclosure, since the groove HM is formed in the inorganic layer area ILA, foreign matter from the outside can be discharged upward through the groove HM. Accordingly, the foreign matter can be prevented from moving through the display area DA, and thus defects of the display panel DP can be reduced or prevented.

[0189] The above description about the groove HM of the inorganic layer area ILA can be applied to Figures 8 to 10 In the following, the description will focus on the grooves respectively Figures 8 to 10 The differences between grooves HM, HM-1 and HM-2 are shown in FIG.

[0190] refer to Figure 8 , the groove HM may be defined to be closer to the second dam DM2 than to the first dam DM1. The groove HM may be spaced apart from the first dam DM1 by about 25 micrometers or more. That is, the spacing distance L between the first dam DM1 and the groove HM may be equal to or greater than about 25 micrometers. The width D of the groove HM in the first direction DR1 may be equal to or greater than about 1 micrometer and equal to or less than about 10 micrometers.

[0191] refer to Fig. 9 , the groove HM-1 may be defined to be closer to the first dam DM1 than to the second dam DM2. As an example, Fig. 9 The spacing distance L-1 between the groove HM-1 and the first dam DM1 may be less than Figure 8 The spacing distance L between the groove HM in the inorganic layer area ILA and the first dam DM1. The spacing distance L-1 between the first dam DM1 and the groove HM-1 may be equal to or greater than about 25 micrometers. That is, the position of the groove HM-1 defined in the inorganic layer area ILA is not limited as long as the spacing distance L-1 between the first dam DM1 and the groove HM-1 is equal to or greater than about 25 micrometers. In addition, the width D-1 of the groove HM-1 in the first direction DR1 may be equal to or greater than about 1 micrometer and equal to or less than about 10 micrometers.

[0192] refer to Fig.10 , the groove HM-2 may be defined to be closer to the second dam DM2 than to the first dam DM1. The spacing distance L-2 between the first dam DM1 and the groove HM-2 may be equal to or greater than about 25 micrometers. The width D-2 of the groove HM-2 in the first direction DR1 may be greater than Figure 8 For example, the width D-2 of the groove HM-2 defined in the inorganic layer area ILA in the first direction DR1 is not limited as long as the width D-2 of the groove HM-2 in the first direction DR1 is equal to or less than about 10 micrometers.

[0193] FIG. 11A to FIG. 11D 1 is a cross-sectional view illustrating each step of a method for manufacturing a display device according to an embodiment of the present disclosure. FIG. 11A to FIG. 11D In the drawings, the same reference numerals denote Figures 1 to 10 The same elements are the same elements in FIG. 1 , and therefore, detailed description of the same elements will be omitted.

[0194] According to an embodiment of the present disclosure, a method for manufacturing a display device may include: preparing a preliminary display panel, the preliminary display panel including a base layer defining a display area and a non-display area adjacent to the display area, a display element layer arranged on the base layer, and an encapsulation layer including a first inorganic layer, an organic layer, and a second inorganic layer sequentially stacked on the display element layer; sequentially stacking a first sensing insulating layer, a first conductive layer, and a second sensing insulating layer on the preliminary display panel; forming a hole (e.g., an opening) passing through the first inorganic layer, the second inorganic layer, the first sensing insulating layer, and the second sensing insulating layer overlapping the non-display area; and sequentially stacking a second conductive layer and a third sensing insulating layer on the second sensing insulating layer.

[0195] refer to Fig.11A The method of manufacturing a display device may include preparing a display panel DP. The display panel DP may include a base layer BL, a circuit layer DP-CL, a display element layer DP-OL, and an encapsulation layer TFE.

[0196] The base layer BL may have (or may define) a display area DA and a non-display area NDA adjacent to the display area DA. The circuit layer DP-CL may be disposed on the base layer BL, and the display element layer DP-OL may be disposed on the circuit layer DP-CL. The display element layer DP-OL may include pixels PX arranged to overlap with the display area DA. The encapsulation layer TFE may include a first inorganic layer IL1, an organic layer OL, and a second inorganic layer IL2 stacked in sequence.

[0197] The display panel DP may further include a first dam DM1 and a second dam DM2 disposed in the non-display area NDA. The second dam DM2 may be spaced apart from the first dam DM1 in a direction away from the display area DA from a boundary between the display area DA and the non-display area NDA.

[0198] refer to Fig. 11B The method of manufacturing a display device may include sequentially stacking a first sensing insulating layer IS-IL1, a first conductive layer IS-CL1 (see, for example, Figure 4 ) and a second sensing insulating layer IS-IL2. As an example, the first sensing insulating layer IS-IL1 may be formed on the display panel DP, and the first conductive layer IS-CL1 may be formed on the first sensing insulating layer IS-IL1. Fig. 11B The second connection portion CP2 and the first sensor portion SP1, which are parts of the first conductive layer IS-CL1, are shown as examples. The first conductive layer IS-CL1 may include the first sensor portion SP1, the second sensor portion SP2 (see, for example Figure 6 ) and the second connection part CP2. After forming the first conductive layer IS-CL1, a second sensing insulating layer IS-IL2 may be formed on the first conductive layer IS-CL1. The second sensing insulating layer IS-IL2 may cover the first sensor part SP1, the second sensor part SP2, and the second connection part CP2.

[0199] refer to Fig. 11C , the method of manufacturing a display device may include forming a groove HM in the first inorganic layer IL1, the second inorganic layer IL2, the first sensing insulating layer IS-IL1, and the second sensing insulating layer IS-IL2. The groove HM may be formed in the inorganic layer area ILA defined in the non-display area NDA. That is, the groove HM may overlap the non-display area NDA.

[0200] The formation of the recess HM may include forming a first conductive layer IS-CL1 (see, for example, Figure 4 ) (eg, the first sensor portion SP1) and the second conductive layer IS-CL2 (see, eg, Figure 4 ) is connected to each other at a portion (e.g., the first connection portion CP1) of the first inorganic layer IL1, the second inorganic layer IL2, the first sensing insulating layer IS-IL1, and the second sensing insulating layer IS-IL2. The process of forming the groove HM may be substantially the same as the process of forming the contact hole CH. As an example, the groove HM may be formed in the first inorganic layer IL1, the second inorganic layer IL2, the first sensing insulating layer IS-IL1, and the second sensing insulating layer IS-IL2 by using the same mask MK as the mask MK used to form the contact hole CH.

[0201] For example, the mask MK may be aligned above the display panel DP. The mask MK may have a plurality of mask openings M_HM and M_CH defined therethrough. The mask openings M_HM and M_CH may include a groove mask opening M_HM and a contact hole mask opening M_CH. The groove mask opening M_HM may be defined to correspond to a region where the groove HM is to be formed, and the contact hole mask opening M_CH may be defined to correspond to a region where the contact hole CH is to be formed. After the mask MK is set, at least a portion of the first inorganic layer IL1, at least a portion of the second inorganic layer IL2, at least a portion of the first sensing insulating layer IS-IL1, and at least a portion of the second sensing insulating layer IS-IL2 may be removed by an exposure process, and thus the groove HM and the contact hole CH may be formed.

[0202] The formation of the groove HM may include etching the first inorganic layer IL1, the second inorganic layer IL2, the first sensing insulating layer IS-IL1, and the second sensing insulating layer IS-IL2 in a region spaced apart from the first dam DM1 by about 25 micrometers or more. In addition, the groove HM formed by etching the first inorganic layer IL1, the second inorganic layer IL2, the first sensing insulating layer IS-IL1, and the second sensing insulating layer IS-IL2 may have a width equal to or less than about 10 micrometers.

[0203] According to an embodiment of the present disclosure, when the groove HM is formed in the inorganic layer area ILA, foreign matter from the outside can be discharged upward through the groove HM. Accordingly, the foreign matter can be prevented from moving into the display area DA or moving through the display area DA, and thus defects of the display panel DP can be reduced or prevented. In addition, since the groove HM is formed by using the same mask MK as the mask MK used to form the contact hole CH of the input sensor ISP, the method of manufacturing the display device can be simplified.

[0204] refer to Fig.11D , the method of manufacturing a display device may include sequentially stacking a second conductive layer IS-CL2 and a third sensing insulating layer IS-IL3 on the second sensing insulating layer IS-IL2. As an example, the second conductive layer IS-CL2 may be formed on the second sensing insulating layer IS-IL2, and the third sensing insulating layer IS-IL3 may be formed on the second conductive layer IS-CL2. Fig.11D The first connection portion CP1 which is a portion of the second conductive layer IS-CL2 is shown as an example The third sensing insulation layer IS-IL3 may be formed to cover the groove HM in the inorganic layer area ILA.

[0205] Although the embodiments of the present disclosure have been described, it should be understood that the present disclosure should not be limited to these embodiments, but a person skilled in the art may make various changes and modifications within the spirit and scope of the present disclosure as defined by the claims and their equivalents. Therefore, the disclosed subject matter should not be limited to any single embodiment described herein, and the scope of the present disclosure should be determined according to the claims and their equivalents.

Claims

1. A display device, comprising: A substrate layer having a display area and a non-display area adjacent to the display area; A display element layer, comprising a plurality of light emitting elements overlapping the display area; an encapsulation layer, on the display element layer; a first dam, in the non-display area; as well as a second dam in the non-display area and spaced apart from the first dam in a direction away from the display area from a boundary between the display area and the non-display area; wherein an inorganic layer region is defined between the first dam and the second dam, and Wherein, grooves are defined in the inorganic layer region.

2. The display device according to claim 1, wherein: The encapsulation layer includes a first inorganic layer, an organic layer, and a second inorganic layer sequentially arranged on the display element layer, and The second inorganic layer is in contact with the first inorganic layer in the inorganic layer region.

3. The display device according to claim 2, further comprising: a sensor layer, comprising a first sensing insulating layer, a first conductive layer, a second sensing insulating layer, a second conductive layer and a third sensing insulating layer sequentially arranged on the packaging layer, The second sensing insulating layer is in contact with the first sensing insulating layer and the third sensing insulating layer in the inorganic layer region.

4. The display device according to claim 3, wherein: The groove is defined in the first inorganic layer, the second inorganic layer, the first sensing insulating layer, and the second sensing insulating layer.

5. The display device according to claim 3, wherein: When viewed in plan, the groove is defined closer to the second dam than to the first dam.

6. The display device according to claim 3, wherein: The third sensing insulating layer is on the second sensing insulating layer and covers the groove.

7. The display device according to claim 3, wherein: A contact hole at which the first conductive layer and the second conductive layer are connected to each other extends through the second sensing insulating layer, and Wherein, the groove and the contact hole are formed by the same process.

8. The display device according to any one of claims 1 to 7, wherein: The groove is spaced apart from the first dam by 25 micrometers or more.

9. The display device according to any one of claims 1 to 7, wherein: The groove has a width equal to or less than 10 micrometers in a first direction parallel to the direction.

10. A display device, comprising: A substrate layer having a display area and a non-display area adjacent to the display area; A display element layer, comprising a plurality of light emitting elements overlapping the display area; an encapsulation layer, comprising a first inorganic layer, an organic layer, and a second inorganic layer sequentially arranged on the display element layer; as well as a sensor layer, comprising a first sensing insulating layer, a first conductive layer, a second sensing insulating layer, a second conductive layer and a third sensing insulating layer sequentially arranged on the packaging layer, wherein the first inorganic layer, the second inorganic layer, the first sensing insulating layer and the second sensing insulating layer define grooves therein, and Wherein, the groove overlaps with the non-display area.

11. The display device according to claim 10, further comprising: a first dam, in the non-display area; as well as a second dam in the non-display area and spaced apart from the first dam in a direction away from the display area from a boundary between the display area and the non-display area; wherein an inorganic layer region is defined between the first dam and the second dam, and Wherein, the groove is defined in the inorganic layer region.

12. The display device according to claim 11, wherein: The first inorganic layer, the second inorganic layer, the first sensing insulating layer, the second sensing insulating layer, and the third sensing insulating layer are sequentially stacked in the inorganic layer region.

13. The display device according to claim 11 or 12, wherein: The groove is spaced apart from the first dam by 25 micrometers or more.

14. The display device according to claim 10, wherein: A contact hole at which the first conductive layer and the second conductive layer are connected to each other is defined through the second sensing insulating layer, and Wherein, the groove and the contact hole are formed by the same process.

15. The display device according to claim 10, wherein: The third sensing insulating layer is on the second sensing insulating layer and covers the groove.

16. The display device according to claim 10, wherein: The groove has a width equal to or less than 10 micrometers in a first direction parallel to a direction away from a boundary between the display area and the non-display area from the display area.

17. A method for manufacturing a display device, the method comprising: preparing a display panel including a base layer defining a display area and a non-display area adjacent to the display area, a circuit layer on the base layer, a display element layer on the circuit layer, and an encapsulation layer including a first inorganic layer, an organic layer, and a second inorganic layer sequentially stacked on the display element layer; sequentially stacking a first sensing insulating layer, a first conductive layer, and a second sensing insulating layer on the display panel; forming a hole through the first inorganic layer, the second inorganic layer, the first sensing insulating layer, and the second sensing insulating layer overlapping the non-display area; as well as A second conductive layer and a third sensing insulating layer are sequentially stacked on the second sensing insulating layer.

18. The method according to claim 17, wherein: The method further includes forming a contact hole at which the first conductive layer and the second conductive layer are connected to each other simultaneously with forming the hole.

19. The method according to claim 17 or 18, wherein: The display panel further comprises: a first dam, in the non-display area; and a second dam spaced apart from the first dam in a direction away from the display area from a boundary between the display area and the non-display area, and The forming of the hole includes etching the first inorganic layer, the second inorganic layer, the first sensing insulating layer, and the second sensing insulating layer in a region spaced apart from the first dam by 25 micrometers or more.

20. The method according to claim 17 or 18, wherein: The forming of the hole includes etching the first inorganic layer, the second inorganic layer, the first sensing insulating layer, and the second sensing insulating layer so that the hole has a width equal to or less than 10 micrometers.

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