Silicon carbide MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) inverter circuit and control method thereof

Abstract

Provided is a silicon carbide MOSFET inverter circuit in which a first silicon carbide MOSFET and a second silicon carbide MOSFET are connected in series, the current density of a transient current being less than 1000 A / cm2 during an OFF period of the MOSFET to be controlled, and the gate of the MOSFET to be controlled being turned on such that the saturation current period is less than 5 [mu] s during the OFF period. Provided is a method for controlling a silicon carbide MOSFET inverter circuit in which a first silicon carbide MOSFET and a second silicon carbide MOSFET are connected in series, the method comprising: a step for turning off the MOSFET to be controlled; and a step in which the gate of the MOSFET to be controlled is turned on such that the saturation current period is less than 5 [mu] s during an off period of the MOSFET to be controlled, the current density of the transient current being less than 1000 A / cm2 during the off period.

Description

Technical Field

[0001] The invention relates to a silicon carbide MOSFET inverter circuit and a control method of the silicon carbide MOSFET inverter circuit. Background Art

[0002] Patent Document 1 describes a “silicon carbide MOSFET inverter circuit capable of suppressing the propagation of stacking faults during dead time”.

[0003] Prior art literature Patent Literature Patent Document 1: Japanese Patent No. 6977469 Patent Document 2: Japanese Patent No. 6878802 Summary of the invention

[0004] Technical Solution In a first aspect of the present invention, a silicon carbide MOSFET inverter circuit is provided, wherein a first silicon carbide MOSFET and a second silicon carbide MOSFET are connected in series, and during the off period of the controlled MOSFET, the current density of the transient current flowing through the built-in diode of the controlled MOSFET is less than 1000A / cm 2 During the off period, the gate of the controlled MOSFET is turned on in such a manner that the saturation current period during which the transient current becomes a saturation current is less than 5 μs. The controlled MOSFET is the first silicon carbide MOSFET or the second silicon carbide MOSFET.

[0005] In the silicon carbide MOSFET inverter circuit, the controlled object MOSFET may have: a drift region of the first conductivity type, which is arranged on a silicon carbide semiconductor substrate; a base region of the second conductivity type, which is arranged above the drift region in the semiconductor substrate; and a high concentration region of the second conductivity type, whose doping concentration in the semiconductor substrate is higher than the doping concentration of the base region, and when viewed from above, the area ratio of the high concentration region to the area of ​​the drift region may be less than 50%.

[0006] In any of the above-mentioned silicon carbide MOSFET inverter circuits, the area ratio may be greater than or equal to 44% and less than or equal to 48%.

[0007] In any of the above silicon carbide MOSFET inverter circuits, the doping concentration of the high concentration region may be 4E18cm -3 Above and 1E19cm -3 the following.

[0008] In any of the above-mentioned silicon carbide MOSFET inverter circuits, the controlled object MOSFET may have: a drift region of the first conductivity type, which is arranged in a silicon carbide semiconductor substrate; a base region of the second conductivity type, which is arranged above the drift region in the semiconductor substrate; a high concentration region of the second conductivity type, whose doping concentration in the semiconductor substrate is higher than the doping concentration of the base region; a plurality of groove portions, which extend along a predetermined extension direction on the front side of the semiconductor substrate; and a plurality of contact regions of the second conductivity type, which extend along the extension direction of the plurality of groove portions between adjacent groove portions among the plurality of groove portions, and have a doping concentration higher than the doping concentration of the base region, and the high concentration region may include a plurality of first high concentration portions, and the plurality of first high concentration portions extend respectively below each of the plurality of groove portions along the extension direction of the plurality of groove portions.

[0009] In any of the above silicon carbide MOSFET inverter circuits, the high concentration region may include a plurality of second high concentration portions, each of which extends below each of the plurality of contact regions along the extension direction of the plurality of groove portions.

[0010] In any of the above-mentioned silicon carbide MOSFET inverter circuits, the high concentration region may include a plurality of third high concentration portions extending in stripes across the plurality of first high concentration portions and the plurality of second high concentration portions along an arrangement direction of the plurality of groove portions.

[0011] In any of the above silicon carbide MOSFET inverter circuits, a distance between adjacent third high concentration portions in the extending direction of the plurality of groove portions among the plurality of third high concentration portions provided in a stripe shape may be 24 μm or more and 40 μm or less.

[0012] In any of the above silicon carbide MOSFET inverter circuits, in a plan view, an area ratio of the high concentration region to an area of ​​the drift region may be less than 50%.

[0013] In any of the above silicon carbide MOSFET inverter circuits, the doping concentration of the high concentration region may be 4E18cm -3 Above and 1E19cm -3 the following.

[0014] In any of the above-mentioned silicon carbide MOSFET inverter circuits, the controlled object MOSFET may have: a drift region of the first conductivity type, which is arranged in a silicon carbide semiconductor substrate; a base region of the second conductivity type, which is arranged above the drift region in the semiconductor substrate; a high concentration region of the second conductivity type, whose doping concentration in the semiconductor substrate is higher than that of the base region; a plurality of groove portions, which extend along a predetermined extension direction on the front side of the semiconductor substrate; and a plurality of contact regions of the second conductivity type, which are separated from each other and configured in an island shape between adjacent groove portions among the plurality of groove portions, and whose doping concentration is higher than that of the base region, and the high concentration region may include a plurality of first high concentration portions, and the plurality of first high concentration portions extend along the extension direction below each of the plurality of groove portions.

[0015] In any of the above silicon carbide MOSFET inverter circuits, each of the plurality of contact regions may be provided so as to be in contact with a first high concentration portion, of the plurality of first high concentration portions, provided below each of the adjacent trench portions.

[0016] In any of the above silicon carbide MOSFET inverter circuits, a spacing distance between adjacent contact regions in the extending direction of the plurality of groove portions among the plurality of contact regions may be 2 μm or more and 4 μm or less.

[0017] In any of the above silicon carbide MOSFET inverter circuits, in a plan view, an area ratio of the high concentration region to an area of ​​the drift region may be less than 50%.

[0018] In any of the above-mentioned silicon carbide MOSFET inverter circuits, the area ratio may be greater than or equal to 44% and less than or equal to 48%.

[0019] Any of the above-mentioned silicon carbide MOSFET inverter circuits may include: a first diode connected in anti-parallel to the first silicon carbide MOSFET; and a second diode connected in anti-parallel to the second silicon carbide MOSFET.

[0020] In any of the above silicon carbide MOSFET inverter circuits, the bus voltage applied to the controlled MOSFET may be less than 2 / 3 of the withstand voltage of the controlled MOSFET.

[0021] In a second embodiment of the present invention, a control method for a silicon carbide MOSFET inverter circuit is provided, which is a control method for a silicon carbide MOSFET inverter circuit formed by connecting a first silicon carbide MOSFET and a second silicon carbide MOSFET in series, and the control method for the silicon carbide MOSFET inverter circuit comprises: a step of turning off the MOSFET to be controlled; and a step of turning on the gate of the MOSFET to be controlled during the off period of the MOSFET to be controlled, in such a way that the saturation current period during which the transient current flowing through the built-in diode of the MOSFET to be controlled becomes a saturation current is less than 5 μs, and during the off period, the current density of the transient current is less than 1000 A / cm 2 , the controlled object MOSFET is the first silicon carbide MOSFET or the second silicon carbide MOSFET.

[0022] It should be noted that the above invention summary does not list all the features of the present invention. In addition, sub-combinations of these feature groups can also constitute inventions. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 An example of a silicon carbide MOSFET inverter circuit 100 is shown.

[0024] Figure 2A An example of a temporal change in the drain-source voltage Vds of the MOSFET 20 to be controlled is shown.

[0025] Figure 2B Show Figure 2A Magnified view of area S in FIG.

[0026] Figure 3 An example of a change over time of the current flowing through the built-in diode of the controlled MOSFET 20 is shown.

[0027] Figure 4 An example of the on-voltage increase rate ΔVon of the controlled MOSFET 20 relative to the length of the saturation current period is shown.

[0028] Figure 5A An example of the upper surface of the MOSFET 20 to be controlled is shown.

[0029] Figure 5B An example of a cross section including the high concentration region 230 of the MOSFET 20 to be controlled is shown.

[0030] Figure 5C Show Figure 5A An example of the A-A' section in FIG.

[0031] Figure 5D Show Figure 5A An example of the BB' section in FIG.

[0032] Fig. 6A A modified example of the upper surface of the MOSFET 20 to be controlled is shown.

[0033] Figure 6B A modified example of the cross section including the high concentration region 230 of the MOSFET 20 to be controlled is shown.

[0034] Figure 6C Show Fig. 6A An example of the CC' section in FIG.

[0035] Fig.6D Show Fig. 6A An example of the D-D' section in FIG.

[0036] Figure 7 An example of a flowchart of a method for controlling the silicon carbide MOSFET inverter circuit 100 is shown.

[0037] Explanation of symbols 10: DC power supply; 12: smoothing capacitor; 20: controlled MOSFET; 21: first built-in diode; 22: first silicon carbide MOSFET; 23: first diode; 25: second built-in diode; 26: second silicon carbide MOSFET; 27: second diode; 30: control circuit; 40: load; 100: silicon carbide MOSFET inverter circuit; 210: semiconductor substrate; 211: front side; 212: back side; 214: base region ; 215: contact region; 216: source region; 217: drift region; 218: first drift portion; 219: second drift portion; 220: buffer zone; 230: high concentration region; 232: first high concentration portion; 234: second high concentration portion; 236: third high concentration portion; 238: insulating film; 240: groove portion; 242: gate conductive portion; 244: gate insulating film; 248: contact electrode; 250: barrier metal; 252: source electrode; 254: drain electrode. DETAILED DESCRIPTION

[0038] Hereinafter, the present invention will be described by way of the embodiments of the invention, but the following embodiments do not limit the invention involved in the claims. In addition, all combinations of features described in the embodiments are not necessarily essential to the technical means of the invention.

[0039] In this specification, one side in a direction parallel to the depth direction of the semiconductor substrate is referred to as "upper", and the other side is referred to as "lower". One of the two main surfaces of a substrate, layer, or other component is referred to as an upper surface, and the other is referred to as a lower surface. The directions of "upper", "lower", "front", and "back" are not limited to the direction of gravity or the installation direction toward the substrate when the silicon carbide MOSFET inverter circuit is actually installed.

[0040] In this specification, technical matters may be described using rectangular coordinate axes of X, Y, and Z. In this specification, a plane parallel to the upper surface of a semiconductor substrate is referred to as an XY plane, and a depth direction of the semiconductor substrate is referred to as a Z axis.

[0041] In each embodiment, an example is shown in which the first conductivity type is set to N type and the second conductivity type is set to P type, but the first conductivity type may be set to P type and the second conductivity type may be set to N type. In this case, the conductivity types of the substrate, layer, region, etc. in each embodiment become opposite polarities to each other.

[0042] In this specification, the layers and regions prefixed with N or P respectively indicate that electrons or holes are majority carriers. In addition, + and - marked in N and P respectively indicate that the doping concentration is higher and lower than that of the layers and regions not marked with + and -.

[0043] Figure 1 An example of a silicon carbide MOSFET inverter circuit 100 is shown. The silicon carbide MOSFET inverter circuit 100 includes a first silicon carbide MOSFET 22, a second silicon carbide MOSFET 26, and a control circuit 30. The silicon carbide MOSFET inverter circuit 100 may include a first diode 23 and a second diode 27. The silicon carbide MOSFET inverter circuit 100 may be connected to a DC power supply 10, a smoothing capacitor 12, and a load 40. The silicon carbide MOSFET inverter circuit 100 may also be connected in parallel to the load 40 to adopt an H bridge. In addition, three groups may be connected in parallel to adopt a three-phase inverter.

[0044] The silicon carbide MOSFET inverter circuit 100 is an inverter circuit in which a first silicon carbide MOSFET 22 and a second silicon carbide MOSFET 26 are connected in series. The silicon carbide MOSFET inverter circuit 100 may be an inverter circuit that converts a DC voltage applied from a DC power source 10 into an AC voltage. The DC voltage of the DC power source 10 may be smoothed by a smoothing capacitor 12 and then input to the silicon carbide MOSFET inverter circuit 100. The AC voltage converted by the silicon carbide MOSFET inverter circuit 100 may be applied to a load 40.

[0045] The first silicon carbide MOSFET 22 includes a first built-in diode 21. The first built-in diode 21 may be a parasitic diode formed between a source electrode and a drain electrode due to the structure of the first silicon carbide MOSFET 22.

[0046] The first diode 23 is connected in reverse parallel to the first silicon carbide MOSFET 22. The first diode 23 may be a Schottky barrier diode. The first diode 23 may shunt the current flowing in the first built-in diode 21 when the first silicon carbide MOSFET 22 is regenerated, or may prevent the current from flowing in the first built-in diode 21. By providing the first diode 23, the expansion of the stacking fault generated by the current flowing in the first built-in diode 21 when the first silicon carbide MOSFET 22 is regenerated can be suppressed, and the increase in the on-resistance and the on-voltage of the first silicon carbide MOSFET 22 can be suppressed.

[0047] The second silicon carbide MOSFET 26 includes a second built-in diode 25. The second built-in diode 25 may be a parasitic diode formed between a source electrode and a drain electrode due to the second silicon carbide MOSFET 26.

[0048] The second diode 27 is connected in reverse parallel to the second silicon carbide MOSFET 26. The second diode 27 may be a Schottky barrier diode. The second diode 27 may shunt the current flowing through the second built-in diode 25 when the second silicon carbide MOSFET 26 is regenerated, or may prevent the current from flowing through the second built-in diode 25. By providing the second diode 27, the expansion of the stacking fault generated by the current flowing through the second built-in diode 25 when the second silicon carbide MOSFET 26 is regenerated can be suppressed, and the increase in the on-resistance and the on-voltage of the second silicon carbide MOSFET 26 can be suppressed.

[0049] In the following description, the MOSFET that is controlled when the inverter circuit is operating is referred to as a controlled MOSFET 20 . That is, the controlled MOSFET 20 is the first silicon carbide MOSFET 22 or the second silicon carbide MOSFET 26 .

[0050] The control circuit 30 controls the on / off of the controlled MOSFET 20 by applying a gate voltage to the controlled MOSFET 20. In addition, a bus voltage is applied to the controlled MOSFET 20 from the DC power supply 10. The bus voltage applied to the controlled MOSFET 20 during normal operation may be less than 2 / 3 of the withstand voltage of the controlled MOSFET 20. Figure 1In the embodiment, the control circuit 30 is provided in the first silicon carbide MOSFET 22 and the second silicon carbide MOSFET 26, respectively, but the present invention is not limited thereto. That is, the control circuit 30 may be provided as an integrated circuit as long as it is a circuit capable of controlling the first silicon carbide MOSFET 22 and the second silicon carbide MOSFET 26, respectively.

[0051] Figure 2A An example of a change in the drain-source voltage Vds of the first silicon carbide MOSFET 22 over time is shown. The horizontal axis represents the time T, and the vertical axis represents the drain-source voltage Vds of the first silicon carbide MOSFET 22. The withstand voltage of the controlled MOSFET 20 of this example is 1200 V, and the bus voltage is 800 V. That is, the bus voltage applied to the controlled MOSFET 20 of this example is 2 / 3 of the withstand voltage of the controlled MOSFET 20.

[0052] The first silicon carbide MOSFET 22 to which the bus voltage 800V is applied is in the on state before time T=0μs. The second silicon carbide MOSFET 26 is in the off state before time T=0μs. At time T=0μs, since the first silicon carbide MOSFET 22 is turned off, a current is applied to the second built-in diode 25 of the second silicon carbide MOSFET 26, and the second built-in diode 25 is in the on state until time T=7.5μs. At time T=2.0μs, a gate voltage is applied to the second silicon carbide MOSFET 26, and the second silicon carbide MOSFET 26 is turned on. At time T=7.5μs, since the gate voltage is stopped from being applied to the second silicon carbide MOSFET 26 by the control circuit 30, the second silicon carbide MOSFET 26 is turned off. Then, at time T=16.5μs, the bus voltage is applied again by the control circuit 30, and the first silicon carbide MOSFET 22 is turned on. These actions can be repeated every 40μs.

[0053] Figure 2B Show Figure 2A Magnified view of area S in FIG. Figure 2B This is an enlarged view of the range from time T=0 μs to time T=5 μs. Figure 2B The dashed line represents an approximate curve of the drain-source voltage Vds. At time T=0 μs, a transient current flows through the second built-in diode 25 of the second silicon carbide MOSFET 26, so the second built-in diode 25 is in a current-carrying state.

[0054] While the second internal diode 25 is energized, holes are injected into the energized portion to cause conductivity modulation, and the drain-source voltage Vds rises gently. Figure 2BThe gentle voltage rise from T=0μs to T=5μs indicates that the hole injection amount gradually increases and the conductivity gradually decreases. Moreover, if the hole injection amount is above a certain level, the conductivity modulation is saturated, and the drain-source voltage Vds in the off state is also saturated. Figure 2B This indicates that the drain-source voltage Vds is saturated at time T=5 μs. That is, the amount of holes injected into the second silicon carbide MOSFET 26 is smaller before time T=5 μs than after time T=5 μs.

[0055] In the case of a defect in the crystal of the semiconductor substrate in the silicon carbide MOSFET, if a current flows in the built-in diode, holes are injected, and recombination of electrons and holes occurs in the semiconductor substrate. Due to the recombination energy generated at this time, the stacking fault, which is a type of crystal defect in the silicon carbide semiconductor substrate, will expand. Therefore, before time T=5μs, compared with after time T=5μs, the amount of holes injected into the second silicon carbide MOSFET 26 is small, so the frequency of electron-hole recombination is also small, and the expansion of the stacking fault is also small.

[0056] Figure 3 FIG. 1 shows an example of a change over time in the current flowing through the second built-in diode 25 of the second silicon carbide MOSFET 26 . The horizontal axis represents time T, and the vertical axis represents the current flowing through the second built-in diode 25 of the second silicon carbide MOSFET 26 . Figure 3 The moment T in corresponds to Figure 2A and Figure 2B That is, at time T=0 μs, the first silicon carbide MOSFET 22 is switched to the off state.

[0057] At time T=0 μs, a transient current starts to flow through the second built-in diode 25, and the transient current becomes a saturation current Ic. During the off period of the first silicon carbide MOSFET 22, the current density of the transient current flowing through the second built-in diode 25 of the second silicon carbide MOSFET 26 can be less than 1000 A / cm 2 That is, the current density of the saturation current Ic can be less than 1000A / cm 2 As an example, the current density of the saturation current Ic is 900A / cm 2. The above describes the operation of the second silicon carbide MOSFET 26 and the second built-in diode 25 during the off period of the first silicon carbide MOSFET 22. However, for the first silicon carbide MOSFET 22 and the first built-in diode 21 during the off period of the second silicon carbide MOSFET 26, the phases of conduction and shutdown are only offset by 90 degrees, and the operation is performed in the same cycle. In this way, during the off period of the controlled MOSFET, the current density of the transient current flowing in the built-in diode of the controlled MOSFET can be less than 1000A / cm 2 That is, during the turn-off period of the first silicon carbide MOSFET 22, the current density of the transient current flowing in the second built-in diode 25 of the second silicon carbide MOSFET 26 may be less than 1000 A / cm 2 During the turn-off period of the second silicon carbide MOSFET 26, the current density of the transient current flowing in the first built-in diode 21 of the first silicon carbide MOSFET 22 may also be less than 1000 A / cm 2 .

[0058] During the off period of the MOSFET 20 to be controlled, the control circuit 30 turns on the gate of the MOSFET 20 to be controlled so that the saturation current period during which the transient current becomes the saturation current Ic is less than 5μs. The control circuit 30 of this example turns on the gate of the MOSFET 20 to be controlled at time T=5μs. The saturation current period of this example is the period from T>0μs to T=5μs, and is less than 5μs. By turning on the gate of the MOSFET 20 to be controlled, current can flow on the channel side, and the current flowing in the built-in diode can be reduced. Figure 3 In the example, the current flowing through the built-in diode decreases from time T=5μs to time T=8μs. In this way, during the off period of the controlled MOSFET 20, the control is performed in a manner that suppresses the current flowing through the built-in diode by turning on the gate of the controlled MOSFET 20, which is the controlled object, is called synchronous control.

[0059] By synchronously controlling the MOSFET 20 to be controlled, the stacking fault in the MOSFET 20 to be controlled can be suppressed. That is, by synchronously controlling the MOSFET 20 to be controlled, the saturation current period during which the transient current becomes the saturation current Ic is less than 5 μs, thereby reducing the current flowing in the built-in diode during the period when the amount of holes injected into the MOSFET 20 to be controlled is small, reducing the frequency of recombination between electrons and holes, and suppressing the stacking fault. In addition, by suppressing the expansion of the stacking fault, the increase in the on-resistance and the on-voltage of the MOSFET 20 to be controlled can be suppressed, and the defect of the MOSFET 20 to be controlled can be reduced.

[0060] Figure 4 An example of the on-voltage rise rate ΔVon of the controlled MOSFET 20 relative to the length of the saturation current period is shown. The vertical axis represents the rise rate of the on-voltage relative to the on-voltage in the initial state after the controlled MOSFET 20 is operated a predetermined number of times, and the horizontal axis represents the length of the saturation current period when the controlled MOSFET 20 is operated a predetermined number of times. That is, the on-voltage rise rate ΔVon is shown when the controlled MOSFET 20 is operated a predetermined number of times so that the length of the saturation current period becomes 2μs, 3μs, 4μs, or 5μs. If the controlled MOSFET 20 is operated a certain number of times or more, the on-voltage rise rate ΔVon of the controlled MOSFET 20 is saturated. Figure 4 The predetermined number of times in is the number of times greater than or equal to the certain number, and the on-voltage increase rate ΔVon is a saturated value.

[0061] like Figure 4 As shown, by synchronously controlling the MOSFET 20 to make the saturation current period shorter than 5 μs, it is possible to reduce the failure of the MOSFET 20. That is, the on-voltage increase rate ΔVon of the MOSFET 20 is smaller than 5% which is a criterion for determining failure.

[0062] In order to suppress the expansion of stacking faults, the current density of the transient current and the pulse width of the transient current are sometimes limited. The silicon carbide MOSFET inverter circuit 100 of this example can relax these limitations by performing synchronous control during the off period of the control object MOSFET 20, and can reduce the constraints when driving the silicon carbide MOSFET inverter circuit 100. In addition, by increasing the current density of the current flowing through the built-in diode and / or extending the period during which the current flows through the built-in diode, the current amount used for regeneration of the control object MOSFET 20 can be increased, and the regeneration efficiency of the control object MOSFET 20 can be improved.

[0063] In order to suppress the propagation of stacking faults, for example, Figure 1 In the embodiment, a diode connected in reverse parallel to the MOSFET 20 to be controlled is provided, as in the first diode 23 and the second diode 27 of the embodiment. That is, by providing such a diode, there is a case where the current flowing in the built-in diode when the MOSFET 20 to be controlled is regenerated is suppressed. According to the present embodiment, by synchronously controlling the MOSFET 20 to be controlled, the saturation current period during which the transient current becomes the saturation current Ic is made less than 5μs, thereby reducing the current flowing in the built-in diode during the period during which the amount of holes injected into the MOSFET 20 to be controlled is small, and therefore, it is not necessarily necessary to provide the first diode 23 and the second diode 27. That is, the silicon carbide MOSFET inverter circuit 100 of the present example may not include the first diode 23 and the second diode 27. In the case where the first diode 23 and the second diode 27 are not provided, the silicon carbide MOSFET inverter circuit 100 can be miniaturized and inexpensive.

[0064] Figure 5A An example of the upper surface of the control target MOSFET 20 is shown. The control target MOSFET 20 has a contact region 215, a source region 216, and a groove portion 240 on the front surface of the silicon carbide semiconductor substrate 210. The control target MOSFET 20 has a high concentration region 230 below the front surface of the silicon carbide semiconductor substrate 210. That is, since the high concentration region 230 is not exposed on the front surface of the silicon carbide semiconductor substrate 210, it is indicated by a dotted line. The high concentration region 230 includes a first high concentration portion 232, a second high concentration portion 234, and a third high concentration portion 236.

[0065] The controlled MOSFET 20 has a plurality of grooves 240 extending in a predetermined extending direction on the front surface of the semiconductor substrate 210. The extending direction of the grooves 240 in this example is the Y-axis direction.

[0066] The controlled MOSFET 20 has a plurality of contact regions 215 of the second conductivity type, extending along the extension direction of the plurality of grooves 240, between adjacent grooves 240. As an example, a contact region 215a of the plurality of contact regions 215 extends along the Y-axis direction between adjacent grooves 240a and 240b of the plurality of grooves 240. As an example, the contact region 215 is of P+ type.

[0067] The high concentration region 230 is a region of the second conductivity type. The high concentration region 230 may be a region that functions as a hole injection path.

[0068] The high concentration region 230 includes a plurality of first high concentration portions 232 extending below each of the plurality of groove portions 240 in the extending direction of the plurality of groove portions 240. In this example, the first high concentration portion 232 extends in the Y-axis direction which is the extending direction of the groove portion 240.

[0069] The high concentration region 230 includes a plurality of second high concentration portions 234 extending in the extending direction of the plurality of groove portions 240 below each of the plurality of contact regions 215. In this example, the second high concentration portion 234 extends in the Y-axis direction, which is the extending direction of the groove portion 240.

[0070] The high concentration region 230 includes a plurality of third high concentration portions 236, which extend in stripes across the plurality of first high concentration portions 232 and the plurality of second high concentration portions 234 along the arrangement direction of the plurality of groove portions 240. The arrangement direction of the plurality of groove portions 240 in this example is the X-axis direction, and the third high concentration portions 236 extend in stripes across the plurality of first high concentration portions 232 and the plurality of second high concentration portions 234 along the X-axis direction which is the arrangement direction of the plurality of groove portions 240. The third high concentration portion 236 may be provided as a bridge portion for conducting the plurality of first high concentration portions 232 with the plurality of second high concentration portions 234.

[0071] Figure 5B FIG. 2 shows an example of a cross section including the high concentration region 230 of the MOSFET 20 to be controlled. Figure 5A FIG. 2 is an example of a cross section of a surface including a region indicated by a dotted line in FIG. MOSFET 20 to be controlled includes a second drift portion 219 described later in a surface including a high concentration region 230 .

[0072] The width W1 of the first high concentration portion 232 may be greater than or equal to 0.7 μm and less than or equal to 1.1 μm. As an example, the width W1 of the first high concentration portion 232 is 0.9 μm.

[0073] The width W2 of the second high concentration portion 234 may be greater than or equal to 0.55 μm and less than or equal to 0.95 μm. As an example, the width W2 of the second high concentration portion 234 is 0.75 μm.

[0074] The spacing distance between the third high concentration portions 236 adjacent to each other in the extension direction of the plurality of groove portions 240 among the plurality of third high concentration portions 236 arranged in a stripe shape may be 24 μm or more and 40 μm or less. That is, the spacing distance L1 between the third high concentration portions 236a, 236b adjacent to each other in the Y-axis direction which is the extension direction of the groove portion 240 among the plurality of third high concentration portions 236 may be 24 μm or more and 40 μm or less. As an example, the spacing distance L1 is 32 μm. The width W3 of the third high concentration portion 236 may be 0.8 μm or more and 1.2 μm or less. As an example, the width W3 of the third high concentration portion 236 is 1.0 μm.

[0075] In a top view, the area ratio of the high concentration region 230 to the area of ​​the drift region 217 may be less than 50%. Figure 5B The proportion of the area of ​​the region shown may be less than 50%. The drift region 217 will be described later.

[0076] By setting the width W1 of the first high concentration portion 232 , the width W2 of the second high concentration portion 234 , the width W4 of the third high concentration portion 236 , and the spacing distance L1 between the third high concentration portions 236 as described above, the area ratio of the high concentration region 230 to the area of ​​the drift region 217 can be made less than 50%.

[0077] By making the area ratio of the high concentration region 230 to the area of ​​the drift region 217 less than 50%, the amount of hole injection during the period when the current flows in the built-in diode can be suppressed. That is, by making the area ratio of the second conductive type high concentration region 230, which is the main factor for hole injection, less than 50%, the amount of hole injection during the period when the current flows in the built-in diode can be suppressed. If the amount of hole injection during the period when the current flows in the built-in diode is suppressed, the frequency of electron-hole recombination can be reduced, and the expansion of stacking faults can be suppressed. In addition, by suppressing the expansion of stacking faults, the increase in the on-resistance of the controlled object MOSFET 20 and the increase in the on-voltage can be suppressed, and the defect of the controlled object MOSFET 20 can be reduced.

[0078] Figure 5C Show Figure 5A. The MOSFET 20 to be controlled has a base region 214, a contact region 215, a source region 216, a drift region 217, a buffer region 220, a high concentration region 230, and a groove portion 240 in a semiconductor substrate 210 of silicon carbide. The MOSFET 20 to be controlled has an insulating film 238, a contact electrode 248, a barrier metal 250, and a source electrode 252 above the semiconductor substrate 210. The MOSFET 20 to be controlled has a drain electrode 254 below the semiconductor substrate 210.

[0079] The buffer region 220 is a region of the first conductivity type provided on the back surface 212 of the semiconductor substrate 210. As an example, the buffer region 220 is of N+ type.

[0080] The drift region 217 includes a first drift portion 218 and a second drift portion 219. The first drift portion 218 is a region of the first conductivity type disposed above the buffer region 220. As an example, the first drift portion 218 is of N-type. The doping concentration of the first drift portion 218 may be lower than the doping concentration of the buffer region 220. The second drift portion 219 is a region of the first conductivity type disposed above the first drift portion 218. As an example, the second drift portion 219 is of N-type. The doping concentration of the second drift portion 219 may be higher than the doping concentration of the first drift portion 218, and may be lower than the doping concentration of the buffer region 220.

[0081] The base region 214 is a region of the second conductivity type provided above the drift region 217. As an example, the base region 214 is of P type.

[0082] The doping concentration of the contact region 215 is higher than the doping concentration of the base region 214. As an example, the contact region 215 is of P+ type.

[0083] The source region 216 is a region of the first conductivity type disposed above the base region 214 . As an example, the source region 216 is of N+ type. The doping concentration of the source region 216 may be higher than the doping concentration of the drift region 217 .

[0084] The doping concentration of the high concentration region 230 is higher than the doping concentration of the base region 214. The doping concentration of the high concentration region 230 may be 4E18 cm -3 Above and 1E19cm -3 As an example, the doping concentration of the high concentration region 230 is 7E18 cm -3 .

[0085] When viewed from above, the area ratio of the high concentration region 230 to the area of ​​the drift region 217 may be less than 50%, but is not limited thereto. The area ratio of the high concentration region 230 may be set to a value that suppresses the amount of hole injection according to the doping concentration of the high concentration region 230. In addition, the area ratio of the high concentration region 230 may be appropriately set according to the doping concentrations of the base region 214, the contact region 215, the source region 216, the drift region 217, etc. That is, the width W1 of the first high concentration portion 232, the width W2 of the second high concentration portion 234, the width W4 of the third high concentration portion 236, and the spacing distance L1 of the third high concentration portion 236 may be set to a value that suppresses the amount of hole injection according to the doping concentration of the high concentration region 230, or may be set according to the doping concentrations of the base region 214, the contact region 215, the source region 216, the drift region 217, etc.

[0086] The groove portion 240 may be provided to penetrate the source region 216 and the base region 214 to reach the second drift portion 219. The method of the groove portion 240 penetrating the source region 216 and the base region 214 is not limited to the method of manufacturing in the order of forming the groove portion 240 after forming the source region 216 and the base region 214. A method of forming the source region 216 and the base region 214 on the sidewall of the groove portion 240 after forming the groove portion 240 is also included in the method of the groove portion 240 penetrating the source region 216 and the base region 214.

[0087] The groove portion 240 has a gate conductive portion 242 and a gate insulating film 244. The gate insulating film 244 is formed in a manner covering the inner wall of the groove portion 240. The gate insulating film 244 can be formed by oxidizing the semiconductor of the inner wall of the groove portion 240. The gate conductive portion 242 is formed inside the groove portion 240 at a position further inside than the gate insulating film 244. The gate insulating film 244 insulates the gate conductive portion 242 from the semiconductor substrate 210. The gate conductive portion 242 is formed of a conductive material such as polysilicon. The groove portion 240 is covered by the insulating film 238 on the front surface 211 of the semiconductor substrate 210.

[0088] The contact electrode 248 is disposed above the contact region 215 on the front surface 211 of the semiconductor substrate 210. The contact electrode 248 may be a silicide layer formed by heat treatment after depositing a metal film. As an example, the material of the contact electrode 248 includes nickel silicide. The contact electrode 248 may reduce the contact resistance between the source electrode 252 and the semiconductor substrate 210.

[0089] The barrier metal 250 is provided to cover the insulating film 238 and the contact electrode 248. The material of the barrier metal 250 may include titanium or titanium nitride.

[0090] The source electrode 252 is provided above the semiconductor substrate 210 via the insulating film 238. The source electrode 252 is formed of a material including a metal. At least a portion of the source electrode 252 may be formed of a metal such as aluminum, or a metal alloy such as an aluminum-silicon alloy (AlSi) or an aluminum-silicon-copper alloy (AlSiCu).

[0091] The drain electrode 254 is formed on the back surface 212 of the semiconductor substrate 210. The drain electrode 254 is formed of a conductive material such as metal.

[0092] Figure 5D Show Figure 5A An example of the BB' section in FIG. Figure 5D is a cross section including the third high concentration portion 236 and a cross section not including the third high concentration portion 236 Figure 5C The cross-section is different. Other structures can be Figure 5C same.

[0093] Fig. 6A FIG. 2 shows a modified example of the upper surface of the MOSFET 20 to be controlled. In this example, the contact region 215 is Figure 5A The difference between the contact region 215 of the embodiment of the present invention is that the contact region 215 is not set to extend along the Y axis which is the extension direction of the groove portion 240. That is, the control target MOSFET 20 of this example has a plurality of contact regions 215 of the second conductivity type, which are arranged in an island shape between adjacent groove portions 240 among the plurality of groove portions 240 and are separated from the adjacent groove portions 240, and the doping concentration is higher than the doping concentration of the base region 214. For example, the contact region 215a is arranged in an island shape between adjacent groove portions 240a and 240b among the plurality of groove portions 240 and is separated from the adjacent groove portions 240a and 240b.

[0094] The spacing distance between the contact regions 215 adjacent to each other in the extension direction of the grooves 240 among the plurality of contact regions 215 may be 2 μm or more and 4 μm or less. That is, the spacing distance L2 between the contact regions 215b and 215c adjacent to each other in the Y-axis direction, which is the extension direction of the grooves 240 among the plurality of contact regions 215 may be 2 μm or more and 4 μm or less. As an example, the spacing distance L2 is 3 μm.

[0095] Figure 6B FIG. 2 shows a modified example of a cross section of the MOSFET 20 to be controlled including the high concentration region 230. Figure 5BThe difference of the embodiment is that the second high concentration portion 234 and the third high concentration portion 236 are not included in the high concentration region 230 of this example. That is, the high concentration region 230 of this example includes a plurality of first high concentration portions 232, and the plurality of first high concentration portions 232 extend along the extension direction below each of the plurality of groove portions 240. The first high concentration portion 232 extends along the Y-axis direction which is the extension direction of the groove portion 240. The width W1' of the first high concentration portion 232 may be greater than 1.0 μm and less than 1.4 μm. As an example, the width W1' of the first high concentration portion 232 is 1.2 μm.

[0096] In a plan view, the area ratio of the high concentration region 230 to the area of ​​the drift region 217 may be less than 50%, or may be greater than 44% and less than 48%. Figure 6B In the cross section of FIG. 2 , the area of ​​the high concentration region 230 may be smaller than the area of ​​the second drift portion 219. Figure 6B The proportion of the area of ​​the region shown may be less than 50%, or may be greater than 44% and less than 48%.

[0097] By setting the width W1' of the first high concentration portion 232 and the spacing distance L2 of the first high concentration portion 232 as described above, the area ratio of the high concentration region 230 to the area of ​​the drift region 217 can be made less than 50%, and can be set to be greater than 44% and less than 48%. By making the area ratio of the high concentration region 230 to the area of ​​the drift region 217 less than 50%, the amount of hole injection during the period when the current flows in the built-in diode can be suppressed. That is, by making the area ratio of the second conductive type high concentration region 230, which is the main factor of hole injection, less than 50%, the amount of hole injection during the period when the current flows in the built-in diode can be suppressed. If the amount of hole injection during the period when the current flows in the built-in diode is suppressed, the frequency of electron-hole recombination can be reduced, and the expansion of stacking faults can be suppressed. In addition, by suppressing the expansion of stacking faults, the increase in the on-resistance and the increase in the on-voltage of the controlled object MOSFET 20 can be suppressed, and the defect of the controlled object MOSFET 20 can be reduced.

[0098] The width W1′ of the first high concentration portion 232 and the spacing distance L2 of the first high concentration portion 232 can be set to values ​​that suppress the amount of hole injection according to the doping concentration of the high concentration region 230 , and can also be set according to the doping concentration of the base region 214 , the contact region 215 , the source region 216 , the drift region 217 , etc.

[0099] Figure 6C Show Fig. 6A An example of the C-C' section in. Figure 5CThe embodiment of FIG. 1 is different in that the contact region 215 is not provided between adjacent groove portions 240 , and the second high concentration portion 234 located below the contact region 215 is not provided.

[0100] Fig.6D Show Fig. 6A An example of the D-D' section in Figure 5D The embodiment of FIG. 1 is different in that the second high concentration portion 234 located below the contact region 215 is not provided, and the third high concentration portion 236 crossing the first high concentration portion 232 and the second high concentration portion 234 is not provided.

[0101] In the control target MOSFET 20 of this example, each of the plurality of contact regions 215 is provided in contact with the first high concentration portion 232 provided below each adjacent groove portion 240 among the plurality of first high concentration portions 232. For example, the contact region 215a is provided in contact with the first high concentration portions 232a and 232b provided below each adjacent groove portion 240a and 240b among the plurality of first high concentration portions 232. The contact region 215 may be provided as a bridge portion for conducting the plurality of first high concentration portions 232.

[0102] FIG. 6A to FIG. 6D Examples and FIG. 5A to FIG. 5D Compared with the embodiment of the present invention, the MOSFET 20 to be controlled can be formed with a simple structure. In addition, since the MOSFET 20 to be controlled can be formed with a simple structure, the cell pitch of the MOSFET 20 to be controlled can be narrowed, making it miniaturized.

[0103] Figure 7 An example of a flowchart of a method for controlling the silicon carbide MOSFET inverter circuit 100 is shown. This example shows an example of a flowchart of a method for controlling the silicon carbide MOSFET inverter circuit 100, but is not limited thereto.

[0104] In S100, the MOSFET 20 to be controlled is turned on. Thus, the MOSFET 20 to be controlled is turned on, which is equivalent to Figure 2A The state before T=0μs.

[0105] In S102, the MOSFET 20 to be controlled is turned off. This step is equivalent to Figure 2A At the time point of T=0 μs, the off period of the control target MOSFET 20 begins.

[0106] In S104, the gate of the MOSFET to be controlled is turned on. Thus, the synchronous control of the MOSFET 20 to be controlled is started. This step is equivalent to Figure 3That is, in S104, during the off period of the MOSFET 20 to be controlled, the gate of the MOSFET 20 to be controlled can be turned on in such a way that the saturation current period during which the transient current flowing through the built-in diode of the MOSFET 20 to be controlled becomes the saturation current Ic is less than 5 μs. Figure 4 As shown in FIG. 1 , when the saturation current period is less than 5 μs, the defect of the MOSFET 20 to be controlled can be reduced. Therefore, the gate of the MOSFET 20 to be controlled can be turned on so that the saturation current period is 2 μs, the gate of the MOSFET 20 to be controlled can be turned on so that the saturation current period is 3 μs, the gate of the MOSFET 20 to be controlled can be turned on so that the saturation current period is 4 μs, or the gate of the MOSFET 20 to be controlled can be turned on so that the saturation current period is less than 5 μs. In addition, during the off period of the MOSFET 20 to be controlled, the current density of the transient current flowing through the built-in diode of the MOSFET 20 to be controlled can be less than 1000 A / cm 2 That is, the current density of the saturation current Ic can be less than 1000A / cm 2 As an example, the current density of the saturation current Ic is 900A / cm 2 .

[0107] By synchronously controlling the MOSFET 20 to be controlled, the stacking fault in the MOSFET 20 to be controlled can be suppressed. That is, by synchronously controlling the MOSFET 20 to be controlled, the saturation current period during which the transient current becomes the saturation current Ic is less than 5 μs, thereby reducing the current flowing in the built-in diode during the period when the amount of holes injected into the MOSFET 20 to be controlled is small, and the frequency of recombination of electrons and holes can be reduced, thereby suppressing the expansion of the stacking fault. In addition, by suppressing the expansion of the stacking fault, the increase in the on-resistance and the on-voltage of the MOSFET 20 to be controlled can be suppressed, and the defect of the MOSFET 20 to be controlled can be reduced.

[0108] In S106, the gate of the MOSFET 20 to be controlled is turned off. This step is equivalent to Figure 3 At the time point of T=8 μs, the synchronous control of the MOSFET 20 to be controlled is terminated.

[0109] In S108, the MOSFET 20 to be controlled is turned on. Thus, the MOSFET 20 to be controlled becomes conductive, and the off period of the MOSFET 20 to be controlled ends. This step is equivalent to Figure 2A The time point of T=16.5μs.

[0110] The controlled MOSFET 20 can repeatedly operate by periodically repeating steps S100 to S108. That is, S100 and S108 may represent the same step.

[0111] Although the present invention has been described above using the embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It is obvious to those skilled in the art that various changes or improvements can be made to the above embodiments. According to the description of the claims, the method to which such changes or improvements are made can also be included in the technical scope of the present invention.

[0112] It should be noted that the execution order of each process such as actions, sequences, steps and stages in the apparatus, system, program and method shown in the claims, specifications and drawings can be implemented in any order unless it is specifically stated "before...", "in advance", etc., and the result of the previous process is not used in the subsequent process. Even if the action flow in the claims, specifications and drawings is described using "first", "next", etc. for convenience, it does not mean that it must be implemented in this order.

Claims

1. A silicon carbide MOSFET inverter circuit, characterized in that: It is a silicon carbide MOSFET inverter circuit formed by connecting the first silicon carbide MOSFET and the second silicon carbide MOSFET in series. During the off period of the MOSFET to be controlled, the current density of the transient current flowing through the internal diode of the MOSFET to be controlled is less than 1000A / cm 2 , During the off period, the gate of the MOSFET to be controlled is turned on so that the saturation current period during which the transient current becomes a saturation current is less than 5 μs. The controlled MOSFET is the first silicon carbide MOSFET or the second silicon carbide MOSFET.

2. The silicon carbide MOSFET inverter circuit according to claim 1, characterized in that: The control object MOSFET has: A drift region of a first conductivity type, which is disposed on a semiconductor substrate of silicon carbide; A base region of a second conductivity type, which is arranged above the drift region in the semiconductor substrate; as well as A high-concentration region of a second conductivity type, in the semiconductor substrate, has a doping concentration higher than that of the base region, When viewed from above, an area ratio of the high concentration region to the area of ​​the drift region is less than 50%.

3. The silicon carbide MOSFET inverter circuit according to claim 2, characterized in that: The area ratio is greater than or equal to 44% and less than or equal to 48%.

4. The silicon carbide MOSFET inverter circuit according to claim 3, characterized in that: The doping concentration of the high concentration region is 4E18cm -3 Above and 1E19cm -3 the following.

5. The silicon carbide MOSFET inverter circuit according to claim 1, characterized in that: The controlled object MOSFET has: A drift region of a first conductivity type, which is disposed on a semiconductor substrate of silicon carbide; A base region of a second conductivity type, which is arranged above the drift region in the semiconductor substrate; a high-concentration region of a second conductivity type, wherein the doping concentration of the region is higher than the doping concentration of the base region in the semiconductor substrate; a plurality of groove portions extending along a predetermined extension direction on the front side of the semiconductor substrate; as well as a plurality of contact regions of the second conductivity type, which extend respectively along the extension direction of the plurality of groove portions between adjacent groove portions among the plurality of groove portions, and whose doping concentration is higher than that of the base region; The high concentration region includes a plurality of first high concentration portions extending below each of the plurality of groove portions along the extending direction of the plurality of groove portions, respectively.

6. The silicon carbide MOSFET inverter circuit according to claim 5, characterized in that: The high concentration region includes a plurality of second high concentration portions extending below each of the plurality of contact regions along the extending direction of the plurality of groove portions.

7. The silicon carbide MOSFET inverter circuit according to claim 6, characterized in that: The high concentration region includes a plurality of third high concentration portions extending in a stripe shape across the plurality of first high concentration portions and the plurality of second high concentration portions along an arrangement direction of the plurality of groove portions.

8. The silicon carbide MOSFET inverter circuit according to claim 7, characterized in that: A distance between third high concentration portions adjacent to each other in the extending direction of the plurality of groove portions among the plurality of third high concentration portions provided in the stripe shape is 24 μm or more and 40 μm or less.

9. The silicon carbide MOSFET inverter circuit according to claim 7, characterized in that: When viewed from above, an area ratio of the high concentration region to the area of ​​the drift region is less than 50%.

10. The silicon carbide MOSFET inverter circuit according to claim 9, characterized in that: The doping concentration of the high concentration region is 4E18cm -3 Above and 1E19cm -3 the following.

11. The silicon carbide MOSFET inverter circuit according to claim 1, characterized in that: The controlled object MOSFET has: A drift region of a first conductivity type, which is disposed on a semiconductor substrate of silicon carbide; A base region of a second conductivity type, which is arranged above the drift region in the semiconductor substrate; a high-concentration region of a second conductivity type, wherein the doping concentration of the region is higher than the doping concentration of the base region in the semiconductor substrate; a plurality of groove portions extending along a predetermined extension direction on the front side of the semiconductor substrate; as well as A plurality of contact regions of the second conductivity type are disposed in an island shape between adjacent groove portions among the plurality of groove portions, separated from the adjacent groove portions, and have a doping concentration higher than that of the base region. The high concentration region includes a plurality of first high concentration portions extending below each of the plurality of groove portions along the extending direction.

12. The silicon carbide MOSFET inverter circuit according to claim 11, characterized in that: Each of the plurality of contact regions is provided so as to be in contact with a first high concentration portion, among the plurality of first high concentration portions, which is provided below each of the adjacent groove portions.

13. The silicon carbide MOSFET inverter circuit according to claim 12, characterized in that: The spacing distance between adjacent contact regions in the extending direction of the plurality of groove portions among the plurality of contact regions is 2 μm or more and 4 μm or less.

14. The silicon carbide MOSFET inverter circuit according to claim 12, characterized in that: When viewed from above, an area ratio of the high concentration region to the area of ​​the drift region is less than 50%.

15. The silicon carbide MOSFET inverter circuit according to claim 14, characterized in that: The area ratio is greater than or equal to 44% and less than or equal to 48%.

16. The silicon carbide MOSFET inverter circuit according to claim 15, characterized in that: The doping concentration of the high concentration region is 4E18cm -3 Above and 1E19cm -3 the following.

17. The silicon carbide MOSFET inverter circuit according to any one of claims 1 to 16, characterized in that: The silicon carbide MOSFET inverter circuit has: A first diode connected in reverse parallel to the first silicon carbide MOSFET; and A second diode is connected in reverse parallel to the second silicon carbide MOSFET.

18. The silicon carbide MOSFET inverter circuit according to any one of claims 1 to 16, characterized in that: The bus voltage applied to the controlled MOSFET is 2 / 3 or less of the withstand voltage of the controlled MOSFET.

19. A control method for a silicon carbide MOSFET inverter circuit, characterized in that: The invention relates to a control method of a silicon carbide MOSFET inverter circuit formed by connecting a first silicon carbide MOSFET and a second silicon carbide MOSFET in series. The control method of the silicon carbide MOSFET inverter circuit comprises: The step of turning off the MOSFET to be controlled; and The step of turning on the gate of the MOSFET to be controlled so that the saturation current period during which the transient current flowing through the built-in diode of the MOSFET to be controlled becomes the saturation current is less than 5 μs during the off period of the MOSFET to be controlled, During the shutdown period, the current density of the transient current is less than 1000A / cm 2 , The controlled MOSFET is the first silicon carbide MOSFET or the second silicon carbide MOSFET.

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