Resistance testing device of semiconductor device and testing method thereof

Abstract

The invention discloses a resistance testing device of a semiconductor device and a testing method thereof. According to the method, similar test keys and resistor structures are ingeniously connected in series, a resistor which is the same as an active area resistor is introduced to serve as a second resistor, the same test steps are adopted, then the equipment internal resistance and the real resistance value are accurately calculated, interference of the equipment internal resistance can be effectively eliminated, and an accurate resistance test result is obtained. And meanwhile, the internal resistance value of the test equipment shows relatively high stability in the whole test process, and the fluctuation is extremely small. The stable internal resistance of the equipment enables a highly accurate and reliable result to be obtained when the internal resistance of the equipment is calculated and a test resistance value is corrected.

Description

Technical Field

[0001] The invention belongs to the field of semiconductor manufacturing, and in particular relates to a resistance testing device and a testing method for a semiconductor device. Background Art

[0002] In the field of semiconductor manufacturing, with the development of technology, the size of semiconductor devices is getting smaller and smaller, while the complexity is getting higher and higher. In order to monitor the manufacturing process of semiconductor devices and ensure the reliability of semiconductor devices, the usual practice is to form a test structure (test key) in the semiconductor device. By testing the electrical parameters of the specific test structure on the wafer, the quality and stability of the semiconductor manufacturing process can be evaluated to ensure the quality of semiconductor devices leaving the factory.

[0003] As a key component in circuit design, the accuracy of resistance has a direct impact on circuit performance. In the semiconductor industry, the commonly used resistance test method is to monitor the resistance of a graphic test square (resistance test structure), commonly known as RS (resistance square). This test method can provide important data about the resistance value, which is crucial for circuit design and performance optimization. Although the graphic test square resistance is a widely accepted test method, it has some limitations. It has not been proposed that the resistance value measured by the test structure is not the actual resistance value, but is interfered by the internal resistance of the test equipment. This internal resistance of the equipment will affect the normal resistance test value, thereby affecting the accurate evaluation of the performance of the semiconductor device.

[0004] Therefore, the main challenge facing the existing technology is how to accurately measure the resistance value in semiconductor devices while eliminating or reducing the impact of the internal resistance of the device on the test results. This is crucial to improving the reliability and performance of semiconductor devices and is also a key factor in ensuring the quality of the semiconductor manufacturing process. Summary of the invention

[0005] The present invention aims to solve the problem of internal resistance interference of equipment in the existing resistance testing method, and provides a resistance testing structure of a semiconductor device and a testing method thereof, so as to improve the performance and reliability of the semiconductor device.

[0006] The present invention is implemented as follows. In the first aspect, the present invention provides a resistance test structure of a semiconductor device, wherein the semiconductor device includes a substrate, an active area, a gate, an insulating layer, and a metal interconnection; wherein the active area is located in the substrate; the active area has an ion implantation area; and the resistance test structure is located on the ion implantation area.

[0007] The resistance test structure includes a first test key, a first resistor, a second test key, a second resistor, and a third test key; wherein the first resistor is the active area resistor to be tested, and the second resistor is the same resistor as the first resistor structure.

[0008] Preferably, the active area resistor is a self-aligned metal silicide active area resistor, and the second resistor is a self-aligned metal silicide active area resistor.

[0009] Preferably, the ion implantation region uses N-type or P-type heavily doped ions.

[0010] In a second aspect, the present invention provides a resistance testing method, specifically: The active area resistor is used as the first resistor, and the resistor with the same structure as the first resistor is used as the second resistor, and then the first test key, the first resistor, the second test key, the second resistor, and the third test key are connected in series; During the first test, apply voltage V1 to the first test key. At this time, current will flow in the entire test circuit. Test the current I1 passing through the second test key and calculate the resistance test value of the first resistor. ; In the second test, the voltage V1 is also applied to the first test key. At this time, the current will flow in the entire test circuit. The current I2 passing through is tested on the third test key, and the resistance test value of the second resistor is calculated. ; according to and Considering the resistance mathematical expression of the internal resistance of the device, combined with the relationship between the voltage V1 and the current I1, and the relationship between the voltage V1 and the current I2, the true values ​​of the first resistor and the second resistor are finally obtained through mathematical deduction.

[0011] As a preference, and The mathematical expression for resistance taking into account the internal resistance of the device is: Formula (1) Formula (2) Where R1 represents the true value of the first resistor, R2 represents the true value of the second resistor, Indicates the internal resistance of the device.

[0012] Preferably, the relationship between the voltage V1 and the current I1 is as follows: Formula (3)

[0013] Preferably, the relationship between the voltage V1 and the current I2 is as follows: Formula (4) According to formula (3), we can get: Formula (5) Further expansion of formula (3): Formula (6) According to formula (4), we can get: Formula (7) Subtract formula (7) from formula (6) to obtain : Formula (8) Finally Substituting into formulas (1)-(2), we can obtain the true value R1 of the first resistor and the true value R2 of the second resistor.

[0014] The beneficial effects of the present invention are: The present invention can effectively eliminate the interference of the internal resistance of the device and obtain accurate resistance test results by cleverly connecting similar test keys and resistance structures in series, strictly adopting the same test steps, and then accurately calculating the internal resistance of the device and the true resistance value. By introducing a resistor with the same structure as the first resistance as the second resistor, the internal resistance value of the test device shows high stability and minimal fluctuations during the entire test process. The stable internal resistance of the device enables highly accurate and reliable results to be obtained when calculating the internal resistance of the device and correcting the test resistance value. This wide range of applicability fully reflects the powerful advantages of the present invention in the field of resistance testing of semiconductor devices, can meet the diverse needs for resistance testing in the manufacturing process of different types of semiconductor devices, provides strong technical support for the development of semiconductor technology, and promotes the continuous advancement and optimization of semiconductor manufacturing processes. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solution of the present invention, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0016] Figure 1 It is a layout of the prior art test resistor.

[0017] Figure 2 It is a test circuit diagram of a resistor in the prior art.

[0018] Figure 3 This is the test resistor layout provided by the present invention.

[0019] Figure 4The present invention provides a test circuit diagram for testing a resistor.

[0020] Figure 5 This is a test resistor layout for an N-type active area block resistor provided by an embodiment of the present invention.

[0021] Figure 6 yes Figure 5 A cross-sectional view of the first resistor.

[0022] Figure 7 The present invention is Figure 5 The test structure. DETAILED DESCRIPTION

[0023] As can be seen from the background technology, the resistance value measured by the traditional resistance testing method is not the real resistance value, but is interfered by the internal resistance of the testing equipment.

[0024] FIG1 shows the layout structure of the test resistor in the prior art, which includes a first test key and a second test key, with a TestKey (test structure) connected between the two. From the perspective of the layout, this traditional design is relatively simple, and is only connected to the test structure through a single test key, lacking effective consideration of the impact of the internal resistance of the device. In practical applications, this structure may cause interference to the test signal during transmission because there is no special design to isolate or compensate for the impact of the internal resistance of the device. For example, when the test current passes through the test key and TestKey, due to the existence of the internal resistance of the device, an additional voltage drop will be generated at both ends, so that the measured voltage is not completely the actual voltage at both ends of the TestKey, which in turn affects the calculation accuracy of the resistance value.

[0025] FIG2 clearly presents the test circuit diagram of the prior art, from which it can be clearly seen that a resistor is connected in series between the test structure and the test device, namely the internal resistance of the device. In actual test operations, according to the basic principle of series circuits, when current flows through the entire circuit, the internal resistance of the device will inevitably share part of the voltage. This means that the voltage measured by the test equipment is actually the superposition of the voltage across the test structure and the voltage across the internal resistance of the device, rather than the true voltage across the test structure. Therefore, the resistance value calculated based on Ohm's law will inevitably deviate from the actual value. This interference of the internal resistance of the device has not been properly resolved in traditional test methods, which seriously restricts the accuracy and reliability of resistance testing and becomes a key challenge faced by prior art in the field of semiconductor device resistance testing.

[0026] In order to solve the above technical problems, the present invention provides a novel resistance test structure and test method for semiconductor devices. Figure 3-Figure 4 .

[0027] First, the first test key, the first resistor, the second test key, the second resistor and the third test key are precisely connected in series to form a complete test circuit loop, wherein the first resistor is an active area resistor, and the second resistor is a resistor designed next to the original active area resistor that is the same as the first resistor.

[0028] Specifically, the first resistor can be cleverly designed as a self-aligned metal silicide active area resistor, and its structural feature is that it uses advanced self-aligned process technology to form a metal silicide layer on the active area, thereby effectively reducing contact resistance and improving conductivity. The second resistor is designed to be a resistor with the same structure as the first resistor. This design can make full use of the characteristics of polysilicon, such as good controllability and stability, while further optimizing the resistance performance with the help of the metal silicide layer. This unique test structure design lays a solid foundation for accurately measuring the resistance of semiconductor devices. By reasonably arranging the connection methods of each component, it can effectively separate and measure the characteristics of different types of resistors, thereby overcoming the problems existing in traditional test methods.

[0029] The active area is the key area in a semiconductor device that enables current conduction and functional operation. For example, in a transistor, the active area is the area where the source, drain and channel are located. The self-aligned metal silicide active area is distributed in this active area and works together with other parts to achieve the electrical performance of the device. The formation of the self-aligned metal silicide active area is a complex process involving multiple steps. First, on a semiconductor structure that has completed the previous processes such as active area doping, a layer of metal film is uniformly deposited on the surface of the active area by physical vapor deposition (PVD) or chemical vapor deposition (CVD). Commonly used metals include titanium (Ti), cobalt (Co) or nickel (Ni). Then, a high-temperature annealing treatment is performed. During the annealing process, the metal atoms react chemically with the silicon atoms in the active area to form a metal silicide layer on the silicon surface, such as titanium silicide (TiSi2), cobalt silicide (CoSi2) or nickel silicide (NiSi). In this process, the self-alignment technology of lithography and etching processes is used to precisely control the formation position of metal silicide, so that it is formed only in specific areas of the active area (such as the source, drain and channel connection parts and other key areas where resistance needs to be reduced), and is precisely aligned with other structures in the active area, thereby obtaining a self-aligned metal silicide active area.

[0030] During the test, a fixed voltage value V1 (commonly known as Force voltage) is accurately applied to the first test key for the first test. At this time, the current will flow in the entire test circuit. Due to the series characteristics of the circuit, the current will pass through the first resistor, the internal resistance of the device and other components in sequence. Then, a high-precision current measuring instrument is used on the second test key to test the current I1 passing through. According to Ohm's law (R = V / I), the resistance test value of the first resistor calculated at this time is It is not its true value because there is inevitably internal resistance of the device in the test circuit. According to the principle of resistance voltage division in series circuit, the accurate mathematical expression of internal resistance can be obtained. (where R1 is the actual value of the first resistor and the internal resistance is the internal resistance of the device). Further applying Ohm's law to this circuit part, we can get , after deformation, we get (Formula 1). This formula clarifies the quantitative relationship between resistance, voltage, current and internal resistance of the device under the first test conditions, providing an important basis for subsequent calculations.

[0031] Then the second test is performed, and the voltage V1 is applied stably on the first test key to maintain the consistency of the test conditions. This time, the current I2 is measured on the third test key. According to the principle similar to the first test, the resistance test value of the second resistor is calculated. , which satisfies the relation (R2 is the actual value of the second resistor). At the same time, since the current has different paths in the circuit, the relationship between the voltage V1 and the current I2 is: (Because the current passes through the first resistor, the second resistor and an internal resistance of the device, and since the second resistor is the same as the first resistor, it can be considered that the current passes through two first resistors and an internal resistance of the device), after deformation, we get (Formula 2).

[0032] By combining equation 1 and equation 2, this is a process based on precise circuit theory and mathematical derivation. Multiplying equation 1 by 2 gives Then subtract formula 2 from this formula, , after rigorous mathematical simplification, the internal resistance of the device can be calculated After accurately determining the internal resistance of the device, and , which can be obtained by substituting the measured and And the calculated , accurately calculate the true values ​​of the first resistor and the second resistor. This step-by-step derivation and calculation process fully reflects the scientific nature and accuracy of the test method of the present invention, effectively eliminates the interference of the internal resistance of the device on the test results, and realizes high-precision measurement of the resistance of semiconductor devices.

[0033] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0034] refer to Figure 5 , showing a schematic diagram of an embodiment of a resistance measurement structure of the present invention.

[0035] Figure 5 The test layout structure of the N-type active area block resistance is shown in detail. In this layout, the green contact holes play a key connecting role, and they closely connect the metal test keys (i.e., the first test key and the second test key) to the active area. On the AA (Active Area) active area, P-type well ions and N-type heavily doped ions are injected through a precisely controlled ion implantation process. This ion implantation process is a key step in semiconductor manufacturing, and its purpose is to precisely adjust the electrical properties of the active area to form a specific conductive area. Subsequently, after a series of complex process steps, metal silicide is formed in this area to achieve a high-quality connection with the test key. This structural design enables the active area to form a stable, low-resistance conductive channel, ensuring that the test signal can be transmitted accurately and efficiently. A test structure, i.e., the first resistor, is carefully set between the first test key and the second test key. Its structure and characteristics are crucial for accurately measuring the resistance of the active area. From Figure 6 In the cross-sectional view of the first resistor, the fine relationship between the various layers of the structure can be clearly seen, including the AA active area, the precisely implanted ion implantation layer, the metal silicide formed on the ion implantation layer, and the close connection with the test key. This detailed structural display helps to deeply understand the formation mechanism and test principle of the resistor, and provides an indispensable basis for accurately designing test methods and deeply analyzing test results. For example, from Figure 6 The contact interface between the metal silicide and the active area can be carefully observed. Its quality and characteristics directly affect the resistance value. Therefore, relevant process parameters such as ion implantation dose, energy, metal silicide formation temperature, etc. need to be strictly controlled during the manufacturing process to ensure the accuracy and reliability of the test results.

[0036] exist Figure 7 The test structure shown shows that an embodiment of the present invention cleverly adds a test structure, i.e., a second resistor, between the second test key and the third test key, and the second resistor has the same structure as the first resistor. This symmetrical structural design not only helps to simplify the calculation process and improve the test efficiency, but is also based on a deep understanding of the principles of circuit symmetry and repeatability. During the test process, by strictly following the predetermined test steps, accurately applying voltage and measuring current on different test keys, the resistance test value can be accurately obtained, and the true value of the internal resistance and resistance of the device can be calculated according to the precise calculation method described above. Similarly, for the test of the resistance between the two layers of metal in the figure, a similar test structure and method can also be used, and appropriate adjustments can be made according to specific process requirements, such as optimizing the position and connection method of the test key according to factors such as the material, thickness, and spacing of the metal layer to achieve accurate resistance testing. During the entire test process, the test environment, such as temperature, humidity, electromagnetic interference, etc., needs to be strictly controlled to ensure the accuracy and repeatability of the test results.

[0037] In the test circuit diagram of the present invention ( Figure 4 ), a third test key is innovatively added, which together with the first test key, the first resistor, the second test key, and the second resistor constitute a more complete test circuit loop. By accurately applying voltage and measuring current on different test keys, sufficient information can be obtained to accurately calculate the true value of the device's internal resistance and resistance. This improved test circuit structure overcomes the limitations of traditional test circuits and effectively solves the problem of device internal resistance interference. For example, after applying a fixed voltage V1 to the first test key, by measuring the currents I1 and I2 on the second test key and the third test key respectively, the calculation method described in detail above can be used to accurately calculate the true value of the device's internal resistance and resistance. This design makes the test process more scientific and rigorous, and improves the accuracy and reliability of resistance testing.

[0038] The resistance test structure of the present invention can be flexibly designed into a self-aligned metal silicide active area resistor, and this design is based on a deep understanding of semiconductor material properties and device structures. The self-aligned metal silicide process can ensure the formation of an accurate and high-quality metal silicide layer in the active area and polysilicon area, thereby greatly reducing the contact resistance and improving the stability and reliability of the resistor. This structural design can not only meet the precise testing requirements for different types of resistors, but also adapt to the increasingly complex structures and diversified performance requirements of semiconductor devices, providing a more accurate and reliable solution for semiconductor device resistance testing.

[0039] The internal resistance value of the test device shows high stability and minimal fluctuations throughout the test process. The stable internal resistance of the device enables highly accurate and reliable results to be obtained when calculating the internal resistance of the device and correcting the test resistance value.

[0040] The resistance testing method of the present invention has excellent versatility. In addition to the above-mentioned test structures and methods for active area resistance, metal through-hole resistance, etc., it can also be widely used in the testing of various types of resistance structures. For example, a P-type active area block resistance test structure can be carefully designed. Its principle is similar to that of an N-type active area block resistance, but it differs in the type of ion implantation and process parameters. By accurately controlling the implantation dose, energy and other parameters of the P-type ions, a P-type active area with specific electrical characteristics is formed, and then the resistance test is performed using the test method of the present invention. For N-type polysilicon block resistance testing, polysilicon has a unique crystal structure and electrical properties. When testing, it is necessary to consider the influence of factors such as the grain size and grain boundary characteristics of polysilicon on resistance. By forming a suitable metal silicide contact structure on polysilicon and applying voltage and measuring current on a specific test key according to the test method of the present invention, its resistance value can be accurately measured. Similarly, the testing of different types of resistance structures such as P-type polysilicon block resistors, NW block resistors, active area contact hole resistors, polysilicon contact resistors, etc., although each has a unique structure and characteristics, can all adopt the testing method of the present invention. When testing these different types of resistors, although the test structure will vary depending on the type of resistor, the core principle of the test method remains the same. That is, by cleverly connecting similar test keys and resistance structures in series, strictly adopting the same test steps (applying a fixed voltage on a specific test key and measuring the current on other test keys), and then accurately calculating the internal resistance of the device and the true resistance value, the interference of the internal resistance of the device can be effectively eliminated, and accurate resistance test results can be obtained. This wide applicability fully reflects the powerful advantages of the present invention in the field of resistance testing of semiconductor devices, can meet the diverse needs of resistance testing in the manufacturing process of different types of semiconductor devices, and provides strong technical support for the development of semiconductor technology, and promotes the continuous advancement and optimization of semiconductor manufacturing processes.

[0041] The above is a preferred embodiment of the present invention. It should be pointed out that a person skilled in the art can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications are also considered to be within the scope of protection of the present invention.

Claims

1. A resistance test structure of a semiconductor device, the semiconductor device comprising a substrate, an active area, a gate, an insulating layer, and a metal interconnection; wherein the active area is located in the substrate; the active area has an ion implantation area; the resistance test structure is located on the ion implantation area; characterized in that: The resistance test structure includes a first test key, a first resistor, a second test key, a second resistor, and a third test key; wherein the first resistor is the active area resistor to be tested, and the second resistor is the same resistor as the first resistor structure.

2. A resistance test structure for a semiconductor device according to claim 1, characterized in that: The active region resistor is a self-aligned metal silicide active region resistor.

3. A resistance test structure for a semiconductor device according to claim 2, characterized in that: The second resistor is a self-aligned metal silicide active area resistor.

4. The resistance test structure of a semiconductor device according to claim 1, characterized in that: The ion implantation region is heavily doped with N-type or P-type ions.

5. A resistance testing method based on the resistance testing structure according to any one of claims 1 to 4, characterized in that: The method is specifically: The active area resistor is used as the first resistor, and the resistor with the same structure as the first resistor is used as the second resistor. Then, the first test key, the first resistor, the second test key, the second resistor, and the third test key are connected in series. During the first test, apply voltage V1 to the first test key. At this time, current will flow in the entire test circuit. Test the current I1 passing through the second test key and calculate the resistance test value of the first resistor. ; In the second test, the voltage V1 is also applied to the first test key. At this time, the current will flow in the entire test circuit. The current I2 passing through is tested on the third test key, and the resistance test value of the second resistor is calculated. ; according to and Considering the resistance mathematical expression of the internal resistance of the device, combined with the relationship between the voltage V1 and the current I1, and the relationship between the voltage V1 and the current I2, the true values ​​of the first resistor and the second resistor are finally obtained through mathematical deduction.

6. The resistance testing method according to claim 5, characterized in that: and The mathematical expressions of resistance considering the internal resistance of the device are as follows: Formula (1) Formula (2) Where R1 represents the true value of the first resistor, R2 represents the true value of the second resistor, Indicates the internal resistance of the device.

7. The resistance testing method according to claim 6, characterized in that: The relationship between voltage V1 and current I1 is as follows: Formula (3).

8. The resistance testing method according to claim 7, characterized in that: The relationship between voltage V1 and current I2 is as follows: Formula (4).

9. The resistance testing method according to claim 8, characterized in that: The specific process of obtaining the true values ​​of the first resistor and the second resistor through mathematical derivation is as follows: According to formula (3), we can get: Formula (5) Further expansion of formula (3): Formula (6) According to formula (4), we can get: Formula (7) Subtract formula (7) from formula (6) to obtain : Formula (8) Finally Substituting into formulas (1)-(2), we can obtain the true value R1 of the first resistor and the true value R2 of the second resistor.

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