Data processing and transmission system based on MLVDS bus and FPGA module

Abstract

A data processing and transmission system based on an MLVDS bus and an FPGA module relates to the technical field of digital control and comprises a power distribution unit, a main control unit and a plurality of functional units. The power output end of the power distribution unit is electrically connected with the power input ends of the main control unit and the plurality of functional units respectively; the main control unit is electrically connected with the plurality of functional units through an MLVDS bus and an IIC bus respectively; in the system, the main control unit and each functional unit have higher communication rate and stably transmitted signals.

Description

Technical Field

[0001] The present invention relates to the field of digital control technology, and in particular to a data processing and transmission system based on an MLVDS bus and an FPGA module. Background Art

[0002] In digital instrumentation and control equipment, as the functional requirements of the system become more and more diverse, it is becoming increasingly difficult to complete all electrical functions with just a single board. Various functions must be classified and developed, and boards with different functions must be used to complete different application functions. Therefore, data communication processing between the main controller board and each functional board through the carrier board becomes particularly important.

[0003] Traditional inter-board communication often uses RS485, CAN bus, LVDS bus and other methods to complete the communication between boards. The RS485 bus uses differential signals to ensure low power consumption and excellent anti-interference performance. When driving signals for long-distance transmission, RS485 has a higher swing and a wider common-mode input range, which helps to achieve a longer transmission distance. However, its transmission rate is not high, and it is rarely used in scenarios where there are requirements for speed.

[0004] The CAN bus communication only needs a pair of differential lines to complete the communication between multiple node boards, but there is no master-slave distinction between the boards, and each node can send data to the bus. Each node obtains the right to use the bus through the priority of the data frame, which will result in the host not being able to get a timely response when it needs to obtain data from a specific board. At the same time, the CAN bus communication rate is also low, and its performance is difficult to meet the actual application requirements when transmitting large data packets.

[0005] In addition, the LVDS bus signal swing is low, 350mV, corresponding to very low power consumption, and the communication rate reaches 3.125Gbps. Its simple termination method, low power consumption and noise make LVDS the first choice for high-speed, low-power applications. However, LVDS is a high-speed point-to-point application communication standard, which is more used in point-to-point usage scenarios. For the application scenarios of multiple slave cards, there are problems such as large volume and complex circuit scale.

[0006] Therefore, we propose a system in which the communication rate between boards is high and the signals between the master and slave boards can be transmitted stably. Summary of the invention

[0007] In order to overcome the deficiencies in the background technology, the present invention discloses a data processing and transmission system based on an MLVDS bus and an FPGA module.

[0008] In order to achieve the above-mentioned invention object, the present invention adopts the following technical scheme:

[0009] A data processing and transmission system based on an MLVDS bus and an FPGA module, comprising a power distribution unit, a main control unit and a plurality of functional units;

[0010] The power output end of the power distribution unit is electrically connected to the power input ends of the main control unit and the multiple functional units respectively;

[0011] The main control unit is electrically connected to a plurality of functional units via an MLVDS bus and an IIC bus respectively.

[0012] Preferably, the power distribution unit includes a power protection module, a DC-DC module and a power output module, wherein the power protection module is electrically connected to a 24VDC power supply outside the system, and the power protection module is provided with two output terminals, wherein the first output terminal outputs 3.3VDC to the power output module through the DC-DC module, and the second output terminal directly outputs 24VDC to the power output module, and the power output module is electrically connected to the main control unit and multiple functional units, respectively.

[0013] Preferably, the main control unit and the functional control unit both include an MLVDS bus transceiver, an IIC hot-swap buffer, an FPGA module, an MCU module, a control module and a power management module, wherein the MLVDS bus transceiver is electrically connected to a communication port of the MLVDS bus, the IIC hot-swap buffer is electrically connected to a communication port of the IIC bus, and the MLVDS bus transceiver and the IIC hot-swap buffer are both electrically connected to the FPGA module; the FPGA module is electrically connected to the MCU module, and the MCU module is electrically connected to the control module; and the power management module is used to be electrically connected to a power distribution unit.

[0014] Preferably, the control module of the main control unit is electrically connected to the host, and the control module of the functional unit is electrically connected to the actuator.

[0015] Preferably, the data exchange between the main control unit and the functional unit adopts a FIFO cache mechanism.

[0016] Preferably, the communication rate of the MLVDS bus is 100 Mbps.

[0017] Preferably, the FPGA modules of the main control unit and the functional unit all adopt 8B / 10B encoding and decoding and CRC checking.

[0018] Preferably, the FPGA module of the main control unit and the FPGA module of the functional unit are both provided with a communication protocol for realizing communication isolation between the main control unit and the functional unit.

[0019] Preferably, the MCU modules of the main control unit and the functional unit both adopt a 32-bit Cortex-M4 core.

[0020] Preferably, the FPGA modules of the main control unit and the functional unit are each provided with a plurality of registers, and the plurality of registers are respectively:

[0021] Interrupt status register used to indicate the current status of the FPGA module:

[0022] A transmit FIFO status register for recording the transmit FIFO status;

[0023] A data length register for storing the length information of a data packet to be sent or received;

[0024] a destination address register for storing a destination address of a data packet;

[0025] A receive FIFO status register for recording the receive FIFO status;

[0026] Receive error register used to record the number of errors in received packets.

[0027] Due to the adoption of the above-mentioned technical solution, the present invention has the following beneficial effects:

[0028] The present invention discloses a data processing and transmission system based on an MLVDS bus and an FPGA module, which realizes the communication connection between a main controller unit and multiple functional units through the MLVDS bus, and can effectively improve the communication rate between the units; and the IIC bus can ensure the stability of the communication connection between the main controller unit and multiple functional units;

[0029] In addition, 8B / 10B encoding and CRC check are used in the data transmission process as an error detection mechanism to further improve the correctness of data transmission. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 A structural schematic diagram of the present invention;

[0031] Figure 2 Schematic diagram of the internal data interaction process between the main control unit and the functional unit.

[0032] In the figure: 1. Power distribution unit; 11. Power protection module; 12. DC-DC module; 13. Power output module; 2. Main control unit; 21. MLVDS bus transceiver; 22. IIC hot-swap buffer; 23. FPGA module; 24. MCU module; 25. Control module; 26. Power management module; 3. MLVDS bus; 4. IIC bus; 5. Functional unit. DETAILED DESCRIPTION

[0033] The technical solution of the present invention will be described below in conjunction with the drawings in the embodiments of the present invention. In the description, it should be understood that if there are terms such as "upper", "lower", "front", "back", "left", "right" and the like indicating directions or positional relationships, they are only corresponding to the drawings of the present invention, for the convenience of describing the present invention, and do not indicate or imply that the devices or components referred to must have a specific direction:

[0034] Embodiment 1 is:

[0035] Combined with Figure 1 The data processing and transmission system based on the MLVDS bus and FPGA module comprises a power distribution unit 1, a main control unit 2 and a plurality of functional units 5;

[0036] The power output end of the power distribution unit 1 is electrically connected to the power input ends of the main control unit 2 and the multiple functional units 5 respectively;

[0037] The main control unit 2 is electrically connected to a plurality of functional units 5 via an MLVDS bus 3 and an IIC bus 4 respectively;

[0038] The communication connection between the main controller unit and the multiple functional units 5 is realized through the MLVDS bus 3, which can effectively improve the communication rate between the units; and the IIC bus 4 can ensure the stability of the communication connection between the main controller unit and the multiple functional units 5;

[0039] In addition, this system adopts an asynchronous communication method with one master and multiple slaves, which effectively avoids data confusion on the MLVDS bus 3. The writing and reading of data on the functional board are initiated by the main control unit 2. Each functional unit 5 only needs to send the data sent to the host to the main control unit 2 based on the data received from the main control unit 2, and the main control unit 2 will then send it to the host.

[0040] Embodiment 2 is:

[0041] On the basis of Example 1, the power distribution unit 1 is further defined, that is, the power distribution unit 1 includes a power protection module 11, a DC-DC module 12 and a power output module 13, wherein the power protection module 11 is electrically connected to a 24VDC power supply outside the system, and the power protection module 11 has a voltage stabilization function, that is, ensuring that a constant 3.3V and 24V DC voltage is provided to the main control unit 2 and the functional unit 5 to maintain the stability of the system operation; an overvoltage protection function, which can cut off the power supply when the power supply voltage exceeds a predetermined threshold to prevent excessive voltage from damaging the electronic components in the system; an undervoltage protection function, which cuts off the power supply when the power supply voltage is lower than the minimum voltage required for operation to avoid instability of the system or data loss due to insufficient voltage; a short-circuit protection function, which prevents damage to the circuit caused by a current surge caused by a short circuit; an overcurrent protection function, which limits the current to not exceed a certain set value to prevent the circuit from being burned by excessive current; an electromagnetic interference suppression function, which reduces noise interference on the power line and improves the quality of the power supply, thereby ensuring the normal operation of the system; a power monitoring function, which monitors the power supply status, such as voltage level, current consumption, etc., so as to promptly detect and handle power supply problems;

[0042] The power protection module 11 is provided with two output ends, wherein the first output end outputs 3.3VDC to the power output module 13 through the DC-DC module 12, and the second output end directly outputs 24VDC to the power output module 13. The power output module 13 is electrically connected to the main control unit 2 and the multiple functional units 5 respectively, and can provide two direct currents of different voltages to the main control unit 2 and the multiple functional units 5 at the same time to meet the power requirements of different components in each unit.

[0043] Embodiment 3 is:

[0044] On the basis of Example 1, the main control unit 2 is further defined, and the main control unit 2 and the functional control unit both include an MLVDS bus transceiver 21, an IIC hot-swap buffer 22, an FPGA module 23, an MCU module 24, a control module 25 and a power management module 26, wherein the MLVDS bus transceiver 21 is electrically connected to a communication port of the MLVDS bus 3, the IIC hot-swap buffer 22 is electrically connected to a communication port of the IIC bus 4, and the MLVDS bus transceiver 21 and the IIC hot-swap buffer 22 are both electrically connected to the FPGA module 23; the FPGA module 23 is electrically connected to the MCU module 24, and the MCU module 24 is electrically connected to the control module 25; the power management module 26 is used to be electrically connected to the power distribution unit 1;

[0045] As required, the control module 25 of the main control unit 2 is electrically connected to the host, and the control module 25 of the functional unit 5 is electrically connected to the actuator, wherein the host is used to issue various control commands to the main control unit 2, and the functional unit 5 is used to receive specific commands transmitted by the main control unit 2 to control the action of the actuator; in addition, the data exchange between the main control unit 2 and the functional unit 5 adopts a FIFO cache mechanism; in particular, the communication rate of the MLVDS bus 3 is 100Mbps; as required, the FPGA modules 23 of the main control unit 2 and the functional unit 5 both adopt 8B / 10B encoding and decoding and CRC check; and the FPGA module 23 of the main control unit 2 and the FPGA module 23 of the functional unit 5 are both provided with a communication protocol for realizing communication isolation between the main control unit 2 and the functional unit 5;

[0046] In this example, the transmission of the entire system data on the MLVDS bus 3 is controlled by the main controller, and other functional boards cannot actively send data to the MLVDS bus 3. The main control board and the functional board FPGA module 23 are each equipped with a 2kB send FIFO and receive FIFO;

[0047] The specific implementation scheme is as follows:

[0048] 1. The main controller writes data to the function board FPGA module 23 receiving FIFO

[0049] 1) The main controller first queries the internal interrupt status register of the board's own FPGA module 23 to determine whether the FPGA module 23 send FIFO is empty. If the send FIFO status is not empty, it means that the send FIFO is occupied by the main controller FPGA module 23, and the send FIFO status needs to be queried multiple times. During the query process, if the send FIFO is empty, the MCU module 24 writes the data to be sent, the target board address of the data, and the length of the data packet into the corresponding register to indicate data transmission. After reaching a certain number of queries, if the send FIFO is still occupied by the FPGA module 23, the data transmission is abandoned;

[0050] 2) After completing the data filling, the main controller MCU module 24 generates a pulse signal to start sending. After receiving the pulse signal, the FPGA module 23 starts to frame the data, perform CRC check, 8B / 10B encoding, and parallel-to-serial conversion, and sends the data packet to the MLVDS bus 3;

[0051] 3) Due to the use of asynchronous communication, the receiving FIFO of the FPGA module 23 of the functional board may be accessed by the MCU module 24 of the functional board. Therefore, the receiving FIFO and the transmitting FIFO of the functional board are accessed by means of mutual exclusion locks. If the FPGA module 23 of the functional board is writing data into the receiving FIFO, the MCU module 24 of the functional board will not be able to access the receiving FIFO of the FPGA module 23, and vice versa. If the MCU module 24 of the functional board is writing data into the transmitting FIFO of the FPGA module 23, and the FPGA module 23 is reading the data of the transmitting FIFO and sending it to the FPGA module 23 of the main controller, the MCU module 24 of the functional board will not be able to access the transmitting FIFO of the FPGA module 23 at this time, and vice versa;

[0052] 4) After the main controller sends the data, other functional boards on the MLVDS bus 3 can correctly receive the data sent by the main controller. Each functional module compares its own board address with the target board address of the data packet. If the comparison result is consistent, the data packet is received for parsing, otherwise the data packet is directly discarded. If the functional board FPGA module 23 receives the data normally, it will return a receiving status information to the main controller FPGA module 23. The main controller can read the relevant registers inside the FPGA module 23 to determine whether the functional board has received the data sent by the main controller normally. If the main controller receives the status of successful reception of the functional board, the data transmission is terminated; if the main controller does not receive the status of successful reception of the functional board, the data packet is sent to the specified board again. After reaching a certain number of transmissions, if it has not been sent successfully, the transmission of this data packet is abandoned.

[0053] 2. The main controller reads data from the FIFO sent by the function board FPGA module 23

[0054] 1) The function board FPGA module 23 cannot actively send the data of the send FIFO to the main controller. Its sending operation needs to send the data to the MLVDS bus 3 only when the main controller receives a request from the function board FPGA module 23 to send data.

[0055] 2) When the main controller needs to obtain data from the function board, it first sends a frame of data acquisition instruction. After receiving the instruction, the function board returns the status information of the FIFO sent by the function board FPGA module 23 to the main controller. There are three main states of the FIFO of the function board FPGA module 23: the first one: the data of the function board FPGA module 23 can be directly read; the second one: there is no data in the function board sending FIFO; the third one: the function board sending FIFO is occupied by the function board MCU module 24;

[0056] 3) If the function board card sends FIFO in the first state, the function board card FPGA module 23 directly sends the send FIFO data to the main controller FPGA module 23 through the MLVDS bus 3, and the main controller MCU module 24 directly reads the data received by the FPGA module 23 through SPI for processing. If the function board card sends FIFO in the second state, the main controller directly exits the data reading process. If the function board card sends FIFO in the third state, the main controller cyclically reads the function board card send FIFO state. After a certain number of cyclic readings, if the function board card send FIFO is still in an occupied state, the main controller exits this data reading process.

[0057] 3. Function board MCU module 24 sends FIFO write data to function board FPGA module 23

[0058] 1) When the functional board MCU module 24 writes the collected data into the transmit FIFO of the FPGA module 23, it first queries the status of the transmit FIFO in the control register of the FPGA module 23. If the mutex lock of the transmit FIFO is not occupied by the FPGA module 23, the MCU module 24 can seize the mutex lock and write the data into the transmit FIFO of the FPGA module 23. If the mutex lock of the transmit FIFO is occupied by the FPGA module 23, the MCU module 24 cannot write the data into the transmit FIFO of the FPGA module 23. At this time, the MCU module 24 can read the status of the transmit FIFO mutex lock for a certain number of cycles. If the FPGA module 23 releases the mutex lock of the transmit FIFO within a certain number of cycles, the next step is performed. Otherwise, if the transmit FIFO is still occupied by the FPGA module 23 after the loop query is completed, the data writing is exited.

[0059] 2) After obtaining the mutex lock of the FPGA module 23 sending FIFO, the MCU module 24 first clears the FPGA module 23 sending FIFO, then writes the data to be sent into the sending FIFO of the FPGA module 23, fills the length of the data packet into the data length register, and writes the target address of the data stream into the corresponding register. The target address of the function board is the main controller address;

[0060] 3) After the MCU module 24 writes the data into the transmit FIFO of the FPGA module 23, it releases the transmit FIFO mutex lock, allowing the FPGA module 23 of the functional board to seize the mutex lock and access the transmit FIFO.

[0061] 4. The function board MCU module 24 receives the FIFO read data from the function board FPGA module 23

[0062] 1) Check whether the receive FIFO in the interrupt status register of the FPGA module 23 is empty. If the flag is 1, it means that there is no data in the receive FIFO of the FPGA module 23. If the flag is 0, it means that there is unread data in the receive FIFO;

[0063] 2) If there is data in the receiving FIFO of the functional board, the MCU module 24 will first seize the exclusive lock of the receiving FIFO of the FPGA module 23. If the seizure is successful, it means that the MCU module 24 is accessing the receiving FIFO of the FPGA module 23. At this time, the FPGA module 23 cannot access the receiving FIFO to write data into it. Read the receiving FIFO in the interrupt status register of the FPGA module 23 again to see if it is empty. If it is not empty, the MCU module 24 reads the data in the receiving FIFO through the SPI bus according to the length in the receiving data length register. If the seizure fails, loop a certain number of times to query whether the FPGA module 23 releases the exclusive lock of the receiving FIFO. If the MCU module 24 still fails to preempt after a certain number of times, the reception is abandoned;

[0064] 3) After reading the data, the functional board FPGA module 23 will automatically clear the receive FIFO data, and the MCU module 24 will release the mutex lock of the receive FIFO of the FPGA module 23, allowing the FPGA module 23 to seize the receive FIFO access rights and write the received main controller data into the receive FIFO.

[0065] Particularly, the MCU modules 24 of the main control unit 2 and the functional unit 5 both adopt a 32-bit Cortex-M4 core.

[0066] In addition, the internal data interaction process between the main control unit 2 and the functional unit 5 on the MLVDS bus 3 is as follows: Figure 2 As shown:

[0067] ① Functional boards use dedicated functional circuits to implement their own dedicated functions;

[0068] ②MCU is used to control the dedicated function circuit to perform corresponding actions, or obtain data collected by the dedicated function circuit, and communicate with the onboard FPGA through the internal SPI bus;

[0069] ③The function board MCU will obtain the data to be sent and write it into the sending buffer inside the onboard FPGA through the SPI bus;

[0070] ④MCU notifies FPGA to take the buffer data to be sent by controlling the send enable pin;

[0071] ⑤ The data in the sending buffer is packaged into the data to be sent according to the specified frame format through the framing module, and a CRC check is performed;

[0072] ⑥ Encode the packaged frame data in 8B / 10B;

[0073] ⑦ Convert the encoded data stream into a serial data stream through the parallel-to-serial module, and send the serial data to the MLVDS bus 3 according to the bit stream;

[0074] In addition, the process of the functional unit 5 receiving data from the MLVDS bus 3 is as follows:

[0075] ①After receiving the bit stream, the MLVDS bus transceiver 21 recovers the serial data according to the clock;

[0076] ② The serial-to-parallel conversion module converts the received serial data into parallel data, and determines whether it is the data of this board by the destination address of the data stream. If the destination address of the data frame is not the address of this board, the data frame is discarded. If the destination address of the data frame is the address of this board, proceed to the next step.

[0077] ③ Parallel data is decoded into data frames according to 8B / 10B;

[0078] ④ The data frame is parsed according to the agreed format to obtain the valid data actually transmitted, and the CRC check is used to determine whether there is an error in the data transmission process. If there is an error in the transmission process, the data packet is discarded and the value of the receive error register is increased by 1;

[0079] ⑤Write valid data into the FPGA internal receiving buffer;

[0080] ⑥The onboard FPGA notifies the MCU to take the data from the receiving buffer;

[0081] ⑦MCU reads the data in the receiving buffer through the SPI bus.

[0082] Embodiment 4 is:

[0083] On the basis of Example 3, the FPGA module 23 of the main control unit 2 and the functional unit 5 is further limited, wherein the FPGA module 23 of the main control unit 2 and the functional unit 5 are provided with a plurality of registers, and the plurality of registers are respectively:

[0084] Interrupt status register used to indicate the current status of FPGA module 23:

[0085] A transmit FIFO status register for recording the transmit FIFO status;

[0086] A data length register for storing the length information of a data packet to be sent or received;

[0087] a destination address register for storing a destination address of a data packet;

[0088] A receive FIFO status register for recording the receive FIFO status;

[0089] Receive error register used to record the number of errors in received packets.

[0090] The parts of the present invention that are not described in detail are prior art. It is obvious to those skilled in the art that the present invention is not limited to the details of the above-mentioned exemplary embodiments, and the present invention can be implemented in other specific forms without departing from the spirit or basic characteristics of the present invention; therefore, no matter from which point of view, the embodiments should be regarded as exemplary and non-restrictive. The scope of the present invention is limited by the appended claims rather than the above description. Therefore, it is intended to include all changes within the meaning and scope of the equivalent elements of the claims in the present invention, and any figure marks in the claims should not be regarded as limiting the claims involved.

Claims

1. A data processing and transmission system based on MLVDS bus and FPGA module, characterized by: It comprises a power distribution unit (1), a main control unit (2) and a plurality of functional units (5); The power output end of the power distribution unit (1) is electrically connected to the power input ends of the main control unit (2) and the plurality of functional units (5) respectively; The main control unit (2) is electrically connected to a plurality of functional units (5) via an MLVDS bus (3) and an IIC bus (4).

2. The data processing and transmission system based on the MLVDS bus and FPGA module as claimed in claim 1, characterized in that: The power distribution unit (1) comprises a power protection module (11), a DC-DC module (12) and a power output module (13), wherein the power protection module (11) is electrically connected to a 24VDC power supply outside the system, and the power protection module (11) is provided with two output terminals, wherein the first output terminal outputs 3.3VDC to the power output module (13) through the DC-DC module (12), and the second output terminal directly outputs 24VDC to the power output module (13), and the power output module (13) is electrically connected to the main control unit (2) and the plurality of functional units (5), respectively.

3. The data processing and transmission system based on MLVDS bus and FPGA module as claimed in claim 1, characterized in that: The communication rate of the MLVDS bus (3) is 100 Mbps.

4. The data processing and transmission system based on MLVDS bus and FPGA module as claimed in claim 1, characterized in that: The main control unit (2) and the functional control unit both comprise an MLVDS bus transceiver (21), an IIC hot-swap buffer (22), an FPGA module (23), an MCU module (24), a control module (25) and a power management module (26), wherein the MLVDS bus transceiver (21) is electrically connected to a communication port of the MLVDS bus (3), the IIC hot-swap buffer (22) is electrically connected to a communication port of the IIC bus (4), and the MLVDS bus transceiver (21) and the IIC hot-swap buffer (22) are both electrically connected to the FPGA module (23); the FPGA module (23) is electrically connected to the MCU module (24), and the MCU module (24) is electrically connected to the control module (25); and the power management module (26) is used to be electrically connected to the power distribution unit (1).

5. The data processing and transmission system based on MLVDS bus and FPGA module as claimed in claim 4, characterized in that: The data exchange between the main control unit (2) and the functional unit (5) adopts a FIFO buffer mechanism.

6. The data processing and transmission system based on MLVDS bus and FPGA module as claimed in claim 4, characterized in that: The control module (25) of the main control unit (2) is electrically connected to the host, and the control module (25) of the functional unit (5) is electrically connected to the actuator.

7. The data processing and transmission system based on MLVDS bus and FPGA module as claimed in claim 4, characterized in that: The FPGA modules (23) of the main control unit (2) and the functional unit (5) both use 8B / 10B encoding and decoding and CRC checking.

8. The data processing and transmission system based on MLVDS bus and FPGA module as claimed in claim 4, characterized in that: The FPGA module (23) of the main control unit (2) and the FPGA module (23) of the functional unit (5) are both provided with a communication protocol for realizing communication isolation between the main control unit (2) and the functional unit (5).

9. The data processing and transmission system based on MLVDS bus and FPGA module as claimed in claim 4, characterized in that: The main control unit (2) and the MCU module (24) of the functional unit (5) both adopt a 32-bit Cortex-M4 core.

10. The data processing and transmission system based on MLVDS bus and FPGA module as claimed in claim 5, characterized in that: The FPGA modules (23) of the main control unit (2) and the functional unit (5) are each provided with a plurality of registers, and the plurality of registers are respectively: Interrupt status register used to indicate the current status of the FPGA module (23): A transmit FIFO status register for recording the transmit FIFO status; A data length register for storing the length information of a data packet to be sent or received; a destination address register for storing a destination address of a data packet; A receive FIFO status register for recording the receive FIFO status; Receive error register used to record the number of errors in received packets.

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