Band-gap reference circuit, chip, and electronic device

Abstract

The embodiment of the invention provides a band-gap reference circuit, a chip and electronic equipment, the band-gap reference circuit comprises a voltage output module, a switched capacitor module and an integration module, the voltage output module is used for outputting a first voltage and a second voltage, and the first voltage and the second voltage are negatively correlated with absolute temperature; a first voltage difference between the first voltage and the second voltage is in positive correlation with absolute temperature; the switched capacitor module is used for outputting a first temperature coefficient voltage and a first temperature coefficient charge according to the first voltage and the second voltage; the integration module is used for outputting reference voltage irrelevant to absolute temperature according to the first temperature coefficient voltage and the first temperature coefficient charge. The reference voltage is output in a mode of accessing the negative temperature coefficient voltage and integrating the positive temperature coefficient charge, the influence of the offset voltage of the first operational amplifier on the reference voltage can be reduced, and finally the precision of the band-gap reference voltage is improved.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to a bandgap reference circuit, a chip and an electronic device. Background Art

[0002] The bandgap voltage reference (BGR) can output a reference voltage that does not vary with power supply voltage, process and temperature. Due to its unique advantages, the circuit is widely used in various systems (such as voltage regulators, analog / digital converters, data acquisition systems, digital / analog converters, MCUs) to provide a stable reference voltage for the system.

[0003] In the related art, the bandgap reference circuit usually utilizes the virtual short and virtual open characteristics of the operational amplifier to clamp and output the reference voltage. However, due to the asymmetry of the internal components of the operational amplifier, the deviation of the manufacturing process and the influence of the external environment, the operational amplifier usually has an offset voltage. The offset voltage causes the operational amplifier to be unable to accurately clamp the node potentials of the phases to be equal, which leads to the problem of reduced accuracy of the output reference voltage of the bandgap reference circuit. Summary of the invention

[0004] In view of the above problems, the embodiments of the present application provide a bandgap reference circuit, a chip and an electronic device to solve the above technical problems.

[0005] In a first aspect, an embodiment of the present application provides a bandgap reference circuit, comprising:

[0006] A voltage output module, the voltage output module includes a first operational amplifier, the voltage output module is used to output a first voltage and a second voltage, the first voltage and the second voltage are negatively correlated with the absolute temperature, and a first voltage difference between the first voltage and the second voltage is positively correlated with the absolute temperature;

[0007] A switch capacitor module, the switch capacitor module is used to output a first temperature coefficient voltage and a first temperature coefficient charge according to the first voltage and the second voltage;

[0008] An integration module, the integration module is used to access the first temperature coefficient voltage and integrate the first temperature coefficient charge, so as to output a reference voltage that is independent of absolute temperature according to the first temperature coefficient voltage and the first temperature coefficient charge;

[0009] The first temperature coefficient voltage is negatively correlated with the absolute temperature, the first temperature coefficient charge is positively correlated with the absolute temperature, and the first temperature coefficient charge is generated based on the first voltage difference.

[0010] In a second aspect, an embodiment of the present application further provides a chip, comprising the above-mentioned bandgap reference circuit.

[0011] In a third aspect, an embodiment of the present application further provides an electronic device, comprising the above-mentioned chip or bandgap reference circuit.

[0012] The present application outputs a first voltage and a second voltage through a voltage output module, and the first voltage and the second voltage are negatively correlated with the absolute temperature, and the first voltage difference between the first voltage and the second voltage is positively correlated with the absolute temperature. Therefore, the switching capacitor module can output a first temperature coefficient voltage (for example, the first voltage or the second voltage) that is negatively correlated with the absolute temperature according to the first voltage and the second voltage, and output a first temperature coefficient charge that is positively correlated with the absolute temperature according to the first voltage and the second voltage. After the integration module is connected to the first temperature coefficient voltage and integrates the first temperature coefficient charge, the integration module can output a reference voltage that is independent of the absolute temperature.

[0013] That is to say, the present application outputs a reference voltage by connecting a negative temperature coefficient voltage and integrating a positive temperature coefficient charge. Compared with the traditional method of outputting a reference voltage by superimposing a negative temperature coefficient voltage divider and a positive temperature coefficient voltage divider, the first temperature coefficient charge integrated by the present application is independent of the offset voltage of the first operational amplifier, thereby reducing the influence of the offset voltage of the first operational amplifier on the reference voltage, which is ultimately beneficial to improving the accuracy of the bandgap reference voltage.

[0014] These and other aspects of the present application will become more apparent from the description of the following embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0016] Figure 1 A schematic diagram of a bandgap reference circuit in the related art is shown.

[0017] Figure 2 Another schematic diagram of a bandgap reference circuit in the related art is shown.

[0018] Figure 3 A schematic diagram of a bandgap reference circuit in an embodiment of the present application is shown.

[0019] Figure 4 A schematic diagram of a voltage output module in an embodiment of the present application is shown.

[0020] Figure 5 Another schematic diagram of a bandgap reference circuit in an embodiment of the present application is shown.

[0021] Figure 6 A working schematic diagram of a bandgap reference circuit in an embodiment of the present application is shown.

[0022] Figure 7 Another schematic diagram of a bandgap reference circuit in an embodiment of the present application is shown.

[0023] Figure 8 Another schematic diagram of a bandgap reference circuit in an embodiment of the present application is shown.

[0024] Fig. 9 Another schematic diagram of a bandgap reference circuit in an embodiment of the present application is shown.

[0025] Fig.10 Another schematic diagram of a bandgap reference circuit in an embodiment of the present application is shown.

[0026] Fig.11 Another schematic diagram of a bandgap reference circuit in an embodiment of the present application is shown.

[0027] Among them, 10 are voltage output modules, 20 are switch capacitor modules, and 30 are integration modules;

[0028] Reference voltage VBG, first voltage VBE1, second voltage VBE2, first temperature coefficient voltage VBE, first temperature coefficient charge Q0;

[0029] A first operational amplifier AMP1, a second operational amplifier AMP2, an integrating capacitor CI, an integrating switch SI, a first sampling capacitor Cs1, a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, a first capacitor C1, a second sampling capacitor Cs2, a second capacitor C2, a fifth switch S5, a sixth switch S6, a seventh switch S7, an eighth switch S8, and a ninth switch S9. DETAILED DESCRIPTION

[0030] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0031] In order to enable those skilled in the art to better understand the solutions of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present application.

[0032] In the embodiments of the present application, it should be noted that, in this article, relational terms such as first and second, etc. are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.

[0033] Moreover, the terms "comprises," "comprising," or any other variation thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0034] In the description of the embodiments of the present application, words such as "example" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "example" or "for example" in the embodiments of the present application is not to be interpreted as being more preferred or having more advantages than another embodiment or design. The use of words such as "example" or "for example" is intended to present relative concepts in a clear manner.

[0035] In addition, the "plurality" in the embodiments of the present application refers to two or more than two. In view of this, in the embodiments of the present application, "plurality" can also be understood as "at least two". "At least one" can be understood as one or more, for example, one, two or more. For example, including at least one means including one, two or more, and there is no limit on which ones are included. For example, including at least one of A, B and C, then A, B, C, A and B, A and C, B and C, or A, B and C can be included.

[0036] It should be noted that, in the embodiments of the present application, "and / or" describes the association relationship of the associated objects, indicating that three relationships may exist. For example, A and / or B may represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / ", unless otherwise specified, generally indicates that the associated objects before and after are in an "or" relationship.

[0037] It should be noted that in the embodiments of the present application, "connection" can be understood as electrical connection, and the connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be either a direct connection between A and B or an indirect connection between A and B through one or more other electrical components.

[0038] The first pole / first end of each transistor used in the embodiments of the present application is one of the source and the drain, and the second pole / second end of each transistor is the other of the source and the drain. Since the source and drain of the transistor can be symmetrical in structure, the source and drain thereof can be structurally indistinguishable, that is, the first pole / first end and the second pole / second end of the transistor in the embodiments of the present application can be structurally indistinguishable. Exemplarily, in the case where the transistor is a P-type transistor, the first pole / first end of the transistor is the source, and the second pole / second end is the drain; exemplarily, in the case where the transistor is an N-type transistor, the first pole / first end of the transistor is the drain, and the second pole / second end is the source.

[0039] In the circuit structure provided in the embodiments of the present application, the first node, the second node and other nodes do not represent actual existing components, but represent the junction points of related couplings in the circuit diagram, that is, these nodes are nodes formed by the equivalent junction points of related couplings in the circuit diagram.

[0040] The bandgap reference circuit can output a reference voltage that is basically invariant to power supply voltage, process and temperature. Figure 1 , Figure 1 A schematic diagram of a bandgap reference circuit in the related art is shown, wherein the bandgap reference circuit includes a transistor M1, a transistor M2, a transistor M3, an operational amplifier OP1, resistors R1-R2, a transistor QP, a transistor QN and a transistor QM which are current mirrors of each other.

[0041] During the operation of the bandgap reference circuit, the bases of transistors QP, QN and QM are short-circuited with their own collectors respectively, and the base-emitter voltage of the related transistors is a negative temperature coefficient voltage and satisfies the following relationship:

[0042]

[0043] Where k is the Boltzmann constant, T is the absolute temperature, q is the unit charge, and I C is the collector current, I S is the reverse saturation current of the transistor.

[0044] Reverse saturation current I S It is proportional to the emitter area of ​​the transistor. Assuming that the sizes of transistors M1, M2 and M3 are the same (i.e., the collector currents flowing through each transistor are equal), and the ratio of the emitter areas of transistors QP and QN is 1:N, and the ratio of the emitter areas of transistors QP and QM is 1:1, the base-emitter voltage of transistor QP, the base-emitter voltage of transistor QN and the base-emitter voltage of transistor QM can be calculated according to the following formulas:

[0045]

[0046] Due to the virtual short and virtual open characteristics of the operational amplifier OP1, without considering the offset voltage of the operational amplifier OP1, the voltage of the node N is equal to the voltage of the node P, so the current flowing through the resistor R1 (that is, the current I flowing through the resistor R2) is PTAT The magnitude of the current is:

[0047]

[0048] It can be seen that in the above formula, k, q, lnN, and R1 are all constants, so the current flowing through the resistor R1 is a positive temperature coefficient current, and VBE2-VBE1 is also a positive temperature coefficient voltage.

[0049] Therefore, based on the voltage division of the resistor R2 and the voltage division of the transistor QM, the reference voltage Vref outputted by the node O is:

[0050] Vref=VBE3+(VBE2-VBE1)R2 / R1

[0051] In the above formula, VBE3 is a negative temperature coefficient voltage, and VBE2-VBE1 is a positive temperature coefficient voltage. Therefore, by changing the ratio of R2 / R1, a reference voltage Vref that is independent of absolute temperature can be output when the negative temperature coefficient voltage and the positive temperature coefficient voltage are superimposed.

[0052] However, see Figure 2 , because the operational amplifier OP1 actually has an offset voltage Vos, the voltage of node N is not absolutely equal to the voltage of node P. At this time, the current flowing through the resistor R1 (that is, the IPTAT current flowing through the resistor R2) is actually:

[0053] I R1 =(VBE2-VBE1+Vos) / R1

[0054] Wherein, Vos is the offset voltage of the operational amplifier OP1.

[0055] Therefore, the reference voltage Vref outputted by the final node O is actually:

[0056] Vref=VBE3+(VBE2-VBE1+Vos)R2 / R1

[0057] Since R2 / R1 is usually taken as 8.2 or 5, it can be seen from the above formula that the offset voltage Vos of the operational amplifier OP1 is amplified by 8.2 times or 5 times, which leads to the problem of reduced accuracy of the output reference voltage Vref of the bandgap reference circuit.

[0058] To this end, the present application provides a bandgap reference circuit, a chip, and an electronic device, which are described in detail below.

[0059] First, see Figure 3 , Figure 3 A schematic diagram of a bandgap reference circuit in an embodiment of the present application is shown, wherein the bandgap reference circuit includes a voltage output module 10 , a switch capacitor module 20 and an integration module 30 .

[0060] Specifically, the voltage output module 10 includes a first operational amplifier AMP1. The voltage output module 10 can output a first voltage VBE1 and a second voltage VBE2 under the voltage clamping of the first operational amplifier AMP1. The first voltage VBE1 and the second voltage VBE2 are negatively correlated with the absolute temperature, and the first voltage difference between the first voltage VBE1 and the second voltage VBE2 is positively correlated with the absolute temperature, that is, the first voltage VBE1 and the second voltage VBE2 are negative temperature coefficient voltages, and the first voltage difference is a positive temperature coefficient voltage.

[0061] As an example, see Figure 4 , Figure 4 A schematic diagram of a voltage output module 10 in an embodiment of the present application is shown, wherein the voltage output module 10 includes a first operational amplifier AMP1, a PMOS tube MP1 and a PMOS tube MP2 which are current mirrors of each other, a transistor Q1, a transistor Q2 and a resistor R1, the first operational amplifier AMP1 has an offset voltage Vos1, and during the operation of the voltage output module 10, the collectors of the transistors Q1 and Q2 respectively output a first voltage VBE1 and a second voltage VBE2, and the first voltage VBE1 and the second voltage VBE2 respectively satisfy the following relationship:

[0062]

[0063] Where k is the Boltzmann constant, T is the absolute temperature, q is the unit charge, and I C is the collector current of transistor Q1 and transistor Q2, I S is the reverse saturation current of transistor Q2, and m is the ratio between the emitter area of ​​transistor Q1 and the emitter area of ​​transistor Q2.

[0064] Since the reverse saturation current of the transistor decreases when the temperature increases and increases when the temperature decreases, the first voltage VBE1 and the second voltage VBE2 are negatively correlated with the absolute temperature, that is, the first voltage VBE1 and the second voltage VBE2 are negative temperature coefficient voltages.

[0065] At the same time, due to the virtual short and virtual open characteristics of the first operational amplifier AMP1, in consideration of the offset voltage of the operational amplifier OP1, the first voltage difference between the first voltage VBE1 and the second voltage VBE2 satisfies the following relationship:

[0066] △VBE=(VBE2-VBE1)=kT / q*lnm

[0067] Since the ratio m between the emitter area of ​​transistor Q1 and the emitter area of ​​transistor Q2 is a fixed value, lnm is a constant term, and the first voltage difference between the first voltage VBE1 and the second voltage VBE2 is positively correlated with the absolute temperature, that is, the first voltage difference is a positive temperature coefficient voltage.

[0068] It can be understood that the above embodiments are only exemplary embodiments of the voltage output module 10 of the present application and should not be understood as limiting the voltage output module 10 of the present application. Those skilled in the art can make equivalent modification designs to the voltage output module 10 under the guidance of the present application, for example, replacing the transistor Q1 and / or the transistor Q2 with a diode having a PN junction; for example, using a more complex current mirror structure (such as a low-voltage common-source common-gate current source or a wide-swing common-source common-gate current mirror, etc.) to replace Figure 4 The PMOS tube MP1 and the PMOS tube MP2 in it.

[0069] The switching capacitor module 20 can output a first temperature coefficient voltage VBE and a first temperature coefficient charge Q0 according to the first voltage VBE1 and the second voltage VBE2. The first temperature coefficient voltage VBE is negatively correlated with the absolute temperature. The first temperature coefficient charge Q0 is generated based on the first voltage difference. The first temperature coefficient charge Q0 is positively correlated with the absolute temperature. That is, the first temperature coefficient voltage VBE is a negative temperature coefficient voltage, and the first temperature coefficient charge Q0 is a positive temperature coefficient charge, so that the integration module 30 outputs a reference voltage VBG that is independent of the absolute temperature according to the first temperature coefficient voltage VBE and the first temperature coefficient charge Q0.

[0070] In some embodiments of the present application, the first temperature coefficient voltage VBE may be any one of the first voltage VBE1 and the second voltage VBE2. Since the first voltage VBE1 and the second voltage VBE2 are negative temperature coefficient voltages, the switch capacitor module 20 may directly input the first voltage VBE1 or the second voltage VBE2 as the first temperature coefficient voltage VBE to the integration module 30. In some embodiments of the present application, the switch capacitor module 20 may make an equivalent change to the first voltage VBE1 or the second voltage VBE2 (for example, stepping down the first voltage VBE1 according to the resistor voltage division), thereby outputting the first temperature coefficient voltage VBE negatively correlated with the absolute temperature to the integration module 30.

[0071] In some embodiments of the present application, the switch capacitor module 20 can output the first temperature coefficient charge Q0 according to the first voltage difference between the first voltage VBE1 and the second voltage VBE2. Since the first voltage difference between the first voltage VBE1 and the second voltage VBE2 is a positive temperature coefficient voltage, the switch capacitor module 20 can output the first temperature coefficient charge Q0 positively correlated with the absolute temperature to the integration module 30. In some embodiments of the present application, the switch capacitor module 20 can make an equivalent change to the first voltage VBE1 or the second voltage VBE2. Since the first voltage difference between the first voltage VBE1 and the second voltage VBE2 is a positive temperature coefficient voltage, the voltage difference corresponding to the equivalent change is still a positive temperature coefficient voltage. Therefore, the switch capacitor module 20 can output the first temperature coefficient charge Q0 positively correlated with the absolute temperature to the integration module 30 according to the voltage difference corresponding to the change.

[0072] The integration module 30 is used to access the first temperature coefficient voltage VBE and integrate the first temperature coefficient charge Q0, so as to output a reference voltage VBG that is independent of absolute temperature according to the first temperature coefficient voltage VBE and the first temperature coefficient charge Q0. For example, taking the case where the switch capacitor module 20 outputs the first temperature coefficient charge Q0 according to the first voltage difference between the first voltage VBE1 and the second voltage VBE2, the positive temperature coefficient voltage V+ converted by the integration module 30 integrating the first temperature coefficient charge Q0 is:

[0073] V+=(VBE2-VBE1)*k

[0074] Among them, k is the coefficient.

[0075] At the same time, since the integration module 30 is also connected to the first temperature coefficient voltage VBE which is negatively correlated with the absolute temperature, the reference voltage VBG output by the integration module 30 can satisfy the following relationship:

[0076] VBG=VBE+(VBE2-VBE1)*k

[0077] It can be seen that VBE is a negative temperature coefficient voltage, and VBE2-VBE1 is a positive temperature coefficient voltage. Therefore, by changing the value of coefficient k, the positive and negative temperature coefficient voltages can cancel each other out, and finally the reference voltage VBG that is independent of absolute temperature is output.

[0078] It should be noted that the offset voltage Vos1 of the first operational amplifier AMP1 only affects the first voltage VBE1, the second voltage VBE2 and the current flowing through the resistor R1, but does not affect the first voltage difference between the first voltage VBE1 and the second voltage VBE2. Figure 4In the case where the offset voltage Vos1 of the first operational amplifier AMP1 is not considered, the current flowing through the resistor R1 (ie, the collector current of the transistors Q1 and Q2) is:

[0079] I1=(VBE2-VBE1) / R1

[0080] Then the magnitudes of the first voltage VBE1 and the second voltage VBE2 are respectively:

[0081]

[0082] Assume that the voltage difference between the first voltage VBE1 and the second voltage VBE2 and the offset voltage Vos1 of the first operational amplifier AMP1 are:

[0083] VBE2-VBE1=54mv

[0084] Vos1=(VBE2-VBE1) / 4=13.5mv

[0085] Then, considering the offset voltage Vos1 of the first operational amplifier AMP1, the current flowing through the resistor R1 (ie, the collector current of the transistors Q1 and Q2) is:

[0086] I2=(VBE2-VBE1+Vos1) / R1=1.25(VBE2-VBE1) / R1=1.25I1

[0087] Then the magnitudes of the first voltage VBE1 and the second voltage VBE2 are respectively:

[0088]

[0089] Therefore, the first voltage difference between the first voltage VBE1 and the second voltage VBE2 is:

[0090]

[0091] After simplifying the above formula, the first voltage difference between the first voltage VBE1 and the second voltage VBE2 satisfies the following relationship:

[0092]

[0093] At the same time, the voltage variation of the first voltage VBE1 and the second voltage VBE2 caused by the offset voltage of the first operational amplifier AMP1 is:

[0094]

[0095] It can be seen that the first voltage difference between the first voltage VBE1 and the second voltage VBE2 is not affected by the offset voltage Vos1 of the first operational amplifier AMP1, so the first temperature coefficient charge generated based on the first voltage difference is also independent of the offset voltage Vos1 of the first operational amplifier AMP1. Since the voltage change caused by the first voltage VBE1 and the second voltage VBE2 being affected by the offset voltage of the first operational amplifier AMP1 is 5.8mv, according to the reference voltage VBG calculation formula VBG=VBE+(VBE2-VBE1)*k, it can be known that the change in the reference voltage VBG caused by the offset voltage Vos1 of the first operational amplifier AMP1 of the present application is approximately 5.8mv. Compared with the phenomenon that the offset voltage Vos1 of the first operational amplifier AMP1 is amplified by 8.2 times (i.e. 13.5mv*8.2=110.7mv) or 5 times (13.5mv*5=67.5mv) in the traditional technology, the present application reduces the influence of the offset voltage Vos1 of the first operational amplifier AMP1 on the reference voltage VBG, which is ultimately beneficial to improving the accuracy of the reference voltage VBG.

[0096] In some embodiments of the present application, see Figure 5 , Figure 5 Another schematic diagram of the bandgap reference circuit in an embodiment of the present application is shown, wherein the integration module 30 includes a second operational amplifier AMP2, an integration capacitor CI and an integration switch SI; the first end of the integration capacitor CI is connected to the first input end of the second operational amplifier AMP2, and the second end of the integration capacitor CI is connected to the output end of the second operational amplifier AMP2; the first end of the integration switch SI is connected to the first input end of the second operational amplifier AMP2, and the second end of the integration switch SI is connected to the output end of the second operational amplifier AMP2.

[0097] It should be noted that the first input terminal of the second operational amplifier AMP2 is configured to receive the first temperature coefficient charge Q0, and the second input terminal of the second operational amplifier AMP2 is configured to access the first temperature coefficient voltage VBE. When the integration module 30 accesses the first temperature coefficient voltage VBE and integrates the first temperature coefficient charge Q0, the integration switch SI is in an off state. After the integration capacitor CI integrates the first temperature coefficient charge Q0, the voltage difference across the integration capacitor CI is:

[0098] △VCI=Q0 / CI=(VBE2-VBE1)*k

[0099] Due to the virtual short and virtual break characteristics of the second operational amplifier AMP2, the voltage at the first input terminal of the second operational amplifier AMP2 is the first temperature coefficient voltage VBE, so the reference voltage at the output terminal of the second operational amplifier AMP2 is:

[0100] VBG=VBE+(VBE2-VBE1)*k

[0101] It can be seen that after the integration module 30 is connected to the first temperature coefficient voltage VBE and the first temperature coefficient charge Q0, the integration module 30 can output a reference voltage VBG that is independent of absolute temperature.

[0102] In some embodiments, continue to refer to Figure 5 A switch SIB and a stabilizing capacitor C0 which are mutually exclusive with the switch state of the integrating switch SI can also be set at the output end of the second operational amplifier AMP2, that is, in the sampling working state, the switch SI is closed and the SIB is disconnected, and in the integrating working state, the switch SI is disconnected and the SIB is closed, so that a stable reference voltage VBG can be output through the stabilizing capacitor C0 in the integrating working state.

[0103] In some embodiments of the present application, the first temperature coefficient charge Q0 is independent of the offset voltage Vos2 of the second operational amplifier AMP2, that is, the first temperature coefficient charge Q0 is not affected by the offset voltage Vos2 of the second operational amplifier AMP2, thereby reducing the influence of the offset voltage Vos2 of the second operational amplifier AMP2 on the reference voltage VBG.

[0104] For example, see Figure 6 , Figure 6 A working schematic diagram of the bandgap reference circuit in an embodiment of the present application is shown. The switch capacitor module 20 has a sampling working state and an integration working state. In the sampling working state, the switch capacitor module 20 charges and accumulates a first charge based on the first voltage VBE1 and the offset voltage Vos2 of the second operational amplifier AMP2. At this time, the charge amount of the first charge is:

[0105] Q1=(VBE1-Vos2)*Cs

[0106] Wherein, Cs is the capacitance corresponding to the first charge accumulated by the switch capacitor module 20 .

[0107] In the integrating working state, the switched capacitor module 20 charges and accumulates the second charge based on the second voltage VBE2 and the offset voltage Vos2 of the second operational amplifier AMP2. At this time, the charge amount of the second charge is:

[0108] Q2=(VBE2-Vos2)*Cs

[0109] Therefore, when the switched capacitor module 20 switches from the sampling working state to the integrating working state, the charge output by the switched capacitor module 20 is:

[0110] Q0=Q2-Q1=(VBE2-Vos2-VBE1+Vos2)*Cs=(VBE2-VBE1)*Cs

[0111] It can be seen that when the switched capacitor module 20 switches from the sampling working state to the integrating working state, the switched capacitor module 20 can output the first temperature coefficient charge Q0 that is independent of the offset voltage Vos2 of the second operational amplifier AMP2 according to the reduced charge amount.

[0112] As an example, see Figure 7 , Figure 7 Another schematic diagram of the bandgap reference circuit in an embodiment of the present application is shown, wherein the switch capacitor module 20 includes a first sampling capacitor Cs1, a first switch S1 and a second switch S2; the first end of the first sampling capacitor Cs1 is connected to the ground end, and the second end of the first sampling capacitor Cs1 is connected to the first input end of the second operational amplifier AMP2; the first end of the first switch S1 is used to access the first voltage VBE1, and the second end of the first switch S1 is connected to the second input end of the second operational amplifier AMP2; the first end of the second switch S2 is used to access the second voltage VBE2, and the second end of the second switch S2 is connected to the second input end of the second operational amplifier AMP2.

[0113] It should be noted that, in the sampling working state of the switched capacitor module 20, the first switch S1 and the integral switch SI are closed, and the second switch S2 is opened. Due to the virtual short and virtual break characteristics of the second operational amplifier AMP2 and the existence of the offset voltage Vos2 of the second operational amplifier AMP2, the voltage of the second input terminal of the second operational amplifier AMP2 is VBE1, and the first input terminal of the second operational amplifier AMP2 is VBE1+Vos2. Therefore, the first charge accumulated in the first sampling capacitor Cs1 is:

[0114] Q1=(VBE1-Vos2)*Cs1

[0115] In the integration working state of the switched capacitor module 20, the first switch S1 and the integration switch SI are disconnected, and the second switch S2 is disconnected. Similarly, due to the virtual short and virtual break characteristics of the second operational amplifier AMP2 and the existence of the offset voltage Vos2 in the second operational amplifier AMP2, the voltage at the second input terminal of the second operational amplifier AMP2 is VBE2, and the first input terminal of the second operational amplifier AMP2 is VBE2+Vos2. Therefore, the second charge accumulated in the first sampling capacitor Cs1 is:

[0116] Q2=(VBE2-Vos2)*Cs1

[0117] Then, after the capacitor module switches to the integration working state, the first temperature coefficient charge Q0 output by the first sampling capacitor Cs1 is:

[0118] Q0=Q2-Q1=(VBE2-VBE1)*Cs1

[0119] It can be seen that the first temperature coefficient charge Q0 is independent of the offset voltage Vos2 of the second operational amplifier AMP2, and thus the influence of the offset voltage Vos2 of the second operational amplifier AMP2 on the reference voltage VBG can also be reduced.

[0120] It should be pointed out that in the related art, the formula satisfied by the reference voltage VBG is:

[0121] VBG=VBE3+(VBE2-VBE1+Vos1)R2 / R1

[0122] Normally, the ratio of R2 / R1 is 8.2 or 5, that is, the offset voltage Vos1 of the first operational amplifier AMP1 is amplified by 8.2 or 5 times.

[0123] In the above embodiment, it is assumed that the voltage difference between the first voltage VBE1 and the second voltage VBE2, the offset voltage Vos1 of the first operational amplifier AMP1 and the offset voltage Vos2 of the second operational amplifier AMP2 are equal and satisfy the following formula:

[0124] VBE2-VBE1=54mv

[0125] Vos2=Vos1=(VBE2-VBE1) / 4=13.5mv

[0126] The current flowing through resistor R1 (i.e. the collector current of transistors Q1 and Q2) is actually:

[0127] I2=(VBE2-VBE1+Vos1) / R1=1.25(VBE2-VBE1) / R1=1.25I1

[0128] Therefore, the offset voltage Vos1 of the first operational amplifier AMP1 causes the magnitude change of the second voltage VBE2 to be:

[0129]

[0130] Therefore, the output reference voltage VBG of the above embodiment is actually:

[0131] VBG=VBE2+△VBE2+Vos2+(VBE2-VBE1)*Cs / CI

[0132] It can be seen from the above formula that the change in the reference voltage VBG caused by the offset voltage Vos1 of the first operational amplifier AMP1 and the offset voltage Vos2 of the second operational amplifier AMP2 is 13.5mv+5.8mv=18.3mv. Compared with the conventional technology, the offset voltage Vos1 of the first operational amplifier AMP1 is amplified by 8.2 times (i.e., 13.5mv*8.2=110.7mv) or 5 times (13.5mv*5=67.5mv). Although the second operational amplifier of the integration module 30 has an offset voltage Vos, the above embodiment can also significantly reduce the influence of the offset voltage of the operational amplifier on the reference voltage VBG, thereby improving the accuracy of the reference voltage VBG.

[0133] In some embodiments of the present application, the first temperature coefficient charge Q0 is independent of the offset voltage Vos2 of the second operational amplifier AMP2, and the first terminal voltage of the integral capacitor CI is independent of the offset voltage Vos2 of the second operational amplifier AMP2, that is, the calculation formula of the reference voltage VBG can be changed to:

[0134] VBG=VBE2+△VBE2+(VBE2-VBE1)*Cs / CI

[0135] ΔVBE2 is the variation of the second voltage VBE2 caused by the offset voltage Vos1 of the first operational amplifier AMP1, and there is no influence of the offset voltage Vos2 of the second operational amplifier AMP2 on the reference voltage VBG, which is conducive to completely eliminating the influence of the offset voltage Vos2 of the second operational amplifier AMP2.

[0136] As an example, see Figure 8 , Figure 8Another schematic diagram of the bandgap reference circuit in the embodiment of the present application is shown, wherein the switch capacitor module 20 includes a first sampling capacitor Cs1, a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, a fifth switch S5 and a first capacitor C1; the first end of the first switch S1 is used to access the first voltage VBE1, and the second end of the first switch S1 is connected to the first end of the first sampling capacitor Cs1; the second end of the first sampling capacitor Cs1 is connected to the first end of the first capacitor C1, and the second end of the first capacitor C1 is connected to the first input end of the second operational amplifier AMP2; the first end of the second switch S2 is connected to the first end of the first sampling capacitor Cs1, and the second end of the second switch S2 is connected to the ground end; the first end of the third switch S3 is connected to the second end of the first sampling capacitor Cs1, and the second end of the third switch S3 is connected to the ground end; the first end of the fourth switch S4 is used to access the second voltage VBE2, and the second end of the fourth switch S4 is connected to the second input end of the second operational amplifier AMP2; the first end of the fifth switch S5 is connected to the second input end of the second operational amplifier AMP2, and the second end of the fifth switch S5 is connected to the ground end.

[0137] It should be noted that, in the sampling working state of the switched capacitor module 20, the integral switch S1, the second switch S2, the third switch S3 and the fifth switch S5 are closed, and the first switch S1 and the fourth switch S4 are opened. At this time, the amount of charge accumulated in the first sampling capacitor Cs1 is zero, and the amount of charge accumulated in the first capacitor C1 is:

[0138] Qc1=Vos2*C1

[0139] In the integration working state of the switch capacitor module 20, the integration switch SI, the second switch S2, the third switch S3 and the fifth switch S5 are disconnected, and the first switch S1 and the fourth switch S4 are closed. Due to the virtual short and virtual break characteristics of the second operational amplifier AMP2, the voltage at the first input terminal of the second operational amplifier AMP2 is: VBE2+Vos2, and the charge amount of the first capacitor C1 remains unchanged (that is, the voltage difference across the first capacitor C1 remains unchanged). Therefore, the voltage of the first node m1 (that is, the voltage at the first terminal of the integration capacitor CI) satisfies the following relationship:

[0140] VBE2+Vos2-Vm1=Vos2

[0141] Wherein, Vm1 is the voltage of the first node m1.

[0142] That is, the voltage of the first node m1 is the second voltage VBE2, so the amount of charge accumulated in the first sampling capacitor Cs1 is:

[0143] Qcs1=(VBE2-VBE1)*Cs1

[0144] Therefore, the voltage difference generated by the integrated capacitor CI accumulating charges in the integrated working state of the switched capacitor module 20 is:

[0145] VCI=(VBE2-VBE1)*Cs1 / CI

[0146] Combined with the voltage of the first node m1, the reference voltage VBG output by the second operational amplifier AMP2 satisfies the following relationship:

[0147] VBG=VBE2+(VBE2-VBE1)*Cs1 / CI

[0148] It can be seen that in the above embodiment, the offset voltage Vos2 of the second operational amplifier AMP2 is fixed to the first capacitor C1. Not only the charge output by the first sampling capacitor Cs1 (i.e., the first temperature coefficient charge Q0) is independent of the offset voltage Vos2 of the second operational amplifier AMP2, but also the voltage of the first node m1 (i.e., the first terminal voltage of the integrating capacitor CI) is independent of the offset voltage Vos2 of the second operational amplifier AMP2, thereby completely eliminating the influence of the offset voltage of the second operational amplifier AMP2. Compared with the phenomenon that the offset voltage Vos1 of the first operational amplifier AMP1 is amplified by 8.2 times (i.e., 13.5mv*8.2=110.7mv) or 5 times (13.5mv*5=67.5mv) in the conventional technology, at this time, only the offset voltage Vos1 of the first operational amplifier AMP1 causes the change of the reference voltage VBG (i.e., 5.8mv). It can be seen that the above embodiment further reduces the influence of the offset voltage of the operational amplifier on the reference voltage VBG.

[0149] As another example, see Fig. 9 , Fig. 9Another schematic diagram of the bandgap reference circuit in the embodiment of the present application is shown, wherein the switch capacitor module 20 includes a first sampling capacitor Cs1, a first capacitor C1, a first switch S1, a second switch S2, a third switch S3, a second sampling capacitor Cs2, a second capacitor C2, a fourth switch S4, a fifth switch S5, a sixth switch S6, a seventh switch S7 and an eighth switch S8; a first end of the first switch S1 is used to access a first input voltage, and a second end of the first switch S1 is connected to a first end of the first sampling capacitor Cs1; a second end of the first sampling capacitor Cs1 is connected to a first end of the first capacitor C1, and a second end of the first capacitor C1 is connected to a first input end of a second operational amplifier AMP2; a first end of the second switch S2 is connected to a first end of the first sampling capacitor Cs1, and a second end of the second switch S2 is connected to a ground terminal; a first end of the third switch S3 is connected to a second end of the first sampling capacitor Cs1, and a second end of the third switch S4 is connected to a ground terminal; a first end of the third switch S5 is connected to a second end of the first sampling capacitor Cs1, and a second end of the third switch S6 is connected to a ground terminal; a first end of the third switch S6 is connected to a second end of the first sampling capacitor Cs1, and a second end of the third switch S7 is connected to a ground terminal; a first end of the third switch S7 is connected to a second end of the third sampling capacitor Cs8, and a second end of the third switch S8 is connected to a ground terminal; a first end of the third switch S7 is connected to a second end of the third sampling capacitor Cs1 ... The second end of the third switch S3 is connected to the ground end; the first end of the fourth switch S4 is used to access the second voltage VBE2, the second end of the fourth switch S4 is connected to the first end of the second sampling capacitor Cs2, and the second end of the second sampling capacitor Cs2 is connected to the second input end of the second operational amplifier AMP2; the first end of the fifth switch S5 is connected to the first end of the second sampling capacitor Cs2, and the second end of the fifth switch S5 is connected to the ground end; the first end of the sixth switch S6 is connected to the second end of the second sampling capacitor Cs2, and the second end of the sixth switch S6 is connected to the ground end; the first end of the seventh switch S7 is used to access the second voltage VBE2, the second end of the seventh switch S7 is connected to the first end of the second capacitor C2, and the second end of the second capacitor C2 is connected to the second input end of the second operational amplifier AMP2; the first end of the eighth switch S8 is connected to the first end of the second capacitor C2, and the second end of the eighth switch S8 is connected to the ground end.

[0150] It should be noted that, in the sampling working state of the switched capacitor module 20, the integral switch S1, the second switch S2, the third switch S3, the fourth switch S4, the sixth switch S6 and the eighth switch S8 are closed, and the first switch S1, the fifth switch S5 and the seventh switch S7 are opened. At this time, the amount of charge accumulated in the first sampling capacitor Cs1 and the second capacitor C2 is zero, and the amount of charge accumulated in the first capacitor C1 and the second sampling capacitor Cs2 is respectively:

[0151] Qc1=Vos2*C1

[0152] Qcs2=VBE2*Cs2

[0153] In the integral working state of the switched capacitor module 20, the integral switch S1, the second switch S2, the third switch S3, the fourth switch S4, the sixth switch S6 and the eighth switch are opened, and the first switch S1, the fifth switch S5 and the seventh switch S7 are closed. According to the charge conservation law, the voltage of the second node m2 satisfies the following relationship:

[0154] Vm2*Cs2+(Vm2-VBE2)*C2=-VBE2*Cs2

[0155] That is, the voltage of the second node m2 is:

[0156] Vm2=VBE2*(C2-Cs2) / (C2+Cs2)

[0157] Due to the virtual short and virtual open characteristics of the second operational amplifier AMP2, the voltage at the first input terminal of the second operational amplifier AMP2 is: Vm2+Vos2, and the charge amount of the first capacitor C1 remains unchanged (that is, the voltage difference across the first capacitor C1 remains unchanged), so the voltage of the first node m1 satisfies the following relationship:

[0158] Vm2+Vos2-Vm1=Vos2

[0159] Therefore, the voltage of the first node m1 is:

[0160] Vm1=Vm2=VBE2*(C2-Cs2) / (C2+Cs2)

[0161] The first input voltage VIN is generated based on the first voltage VBE1. Since the first input voltage VIN and the first voltage VBE1 satisfy a first ratio, the difference between the capacitance values ​​of the second sampling capacitor Cs2 and the second capacitor C2 satisfies a second ratio relative to the sum of the capacitance values ​​of the second sampling capacitor Cs2 and the second capacitor C2. The first ratio is equal to the second ratio, that is, the first input voltage VIN and the first voltage VBE1 satisfy the following relationship:

[0162] VIN / VBE1=(C2-Cs2) / (C2+Cs2)

[0163] That is, the first input voltage is VIN=(C2-Cs2) / (C2+Cs2)*VBE1. Combined with the voltage of the first node m1, the amount of charge accumulated in the first sampling capacitor Cs1 in the integral working state of the switch capacitor module 20 is:

[0164] Qcs1=(VIN-Vm1)*Cs1=(C2-Cs2) / (C2+Cs2)*(VBE2-VBE1)*Cs1

[0165] Therefore, the reference voltage VBG output by the second operational amplifier AMP2 satisfies the following relationship:

[0166] VBG=(C2-Cs2) / (C2+Cs2)*[VBE2+(VBE2-VBE1)*Cs1 / CI]

[0167] It can be seen that in the above formula, (C2-Cs2) / (C2+Cs2) is a constant term, so the size of the reference voltage VBG can be changed by changing C2 and Cs2, and the positive and negative temperature coefficient voltages can be offset by changing the Cs1 / CI ratio to output a reference voltage VBG that is independent of absolute temperature. In addition, in the above embodiment, the offset voltage Vos2 of the second operational amplifier AMP2 is fixed to the first capacitor C1, and not only the charge output by the first sampling capacitor Cs1 (i.e., the first temperature coefficient charge Q0) is independent of the offset voltage Vos2 of the second operational amplifier AMP2, but also the voltage of the first node m1 (i.e., the first terminal voltage of the integrating capacitor CI) is independent of the offset voltage Vos2 of the second operational amplifier AMP2, thereby completely eliminating the influence of the offset voltage of the second operational amplifier AMP2.

[0168] It should be noted that in some embodiments of the present application, for example, for an embodiment where a first input voltage VIN needs to be provided, the bandgap reference circuit of the present application may also include: Fig. 9 The voltage changing module 40 shown, the first input voltage VIN can be generated by the voltage changing module 40 according to the first voltage VBE1. The voltage changing module 40 may include but is not limited to a resistor voltage divider circuit, a BUCK step-down circuit and other circuits that generate voltage signals, so as to generate the first input voltage VIN that satisfies a first ratio with the first voltage VBE1.

[0169] As another example, see Fig.10 , Fig.10 Another schematic diagram of the bandgap reference circuit in the embodiment of the present application is shown, wherein the switch capacitor module 20 includes a first sampling capacitor Cs1, a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, a first capacitor C1, a fifth switch S5 and a sixth switch S6; the first end of the first switch S1 is used to access the first voltage VBE1, and the second end of the first switch S1 is connected to the first end of the first sampling capacitor Cs1; the second end of the first sampling capacitor Cs1 is connected to the first end of the second switch S2, the second end of the second switch S2 is connected to the first end of the first capacitor C1, and the second end of the first capacitor C1 is connected to the second sampling capacitor Cs1. The first end of the third switch S3 is connected to the second end of the first sampling capacitor Cs1, and the second end of the third switch S3 is connected to the ground end; the first end of the fourth switch S4 is connected to the first end of the first sampling capacitor Cs1, and the second end of the fourth switch S4 is connected to the second end of the second switch S2; the first end of the fifth switch S5 is used to access the second voltage VBE2, and the second end of the fifth switch S5 is connected to the second input end of the second operational amplifier AMP2; the first end of the sixth switch S6 is connected to the second input end of the second operational amplifier AMP2, and the second end of the sixth switch S6 is connected to the ground end.

[0170] It should be noted that, in the sampling working state of the switched capacitor module 20, the integral switch SI, the first switch S1, the second switch S2, the third switch S3 and the sixth switch S6 are closed, and the fourth switch S4 and the fifth switch S5 are opened. At this time, the amount of charge accumulated in the first capacitor C1 and the first sampling capacitor Cs1 is:

[0171] Qc1=Vos2*C1

[0172] Qcs1=VBE1*Cs2

[0173] In the integration working state of the switch capacitor module 20, the integration switch SI, the first switch S1, the second switch S2 and the sixth switch S6 are disconnected, and the third switch S3, the fourth switch S4 and the fifth switch S5 are closed. Due to the virtual short and virtual break characteristics of the second operational amplifier AMP2, the voltage at the first input terminal of the second operational amplifier AMP2 is: Vm2+Vos2, and the charge amount of the first capacitor C1 remains unchanged (that is, the voltage difference across the first capacitor C1 remains unchanged), so the voltage of the first node m1 satisfies the following relationship:

[0174] VBE2+Vos2-Vm1=Vos2

[0175] Therefore, the voltage of the first node m1 and the amount of charge accumulated therein are:

[0176] Vm1=VBE2

[0177] Qcs1=(VBE2-VBE1)*Cs1

[0178] Therefore, the voltage difference generated by the integrated capacitor CI accumulating charges in the integrated working state of the switched capacitor module 20 is:

[0179] VCI=(VBE2-VBE1)*Cs1 / CI

[0180] Combined with the voltage of the first node m1, the reference voltage VBG output by the second operational amplifier AMP2 satisfies the following relationship:

[0181] VBG=VBE2+(VBE2-VBE1)*Cs1 / CI

[0182] It can be seen that in the above embodiment, the offset voltage Vos2 of the second operational amplifier AMP2 is fixed to the first capacitor C1, and not only the charge output by the first sampling capacitor Cs1 (i.e., the first temperature coefficient charge Q0) is independent of the offset voltage Vos2 of the second operational amplifier AMP2, but also the voltage of the first node m1 (i.e., the first terminal voltage of the integrating capacitor) is independent of the offset voltage Vos2 of the second operational amplifier AMP2, thereby completely eliminating the influence of the offset voltage of the second operational amplifier AMP2.

[0183] As another example, see Fig.11 , Fig.11 Another schematic diagram of the bandgap reference circuit in the embodiment of the present application is shown, wherein the switch capacitor module 20 includes a first sampling capacitor Cs1, a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, a first capacitor C1, a second sampling capacitor Cs2, a second capacitor C2, a fifth switch S5, a sixth switch S6, a seventh switch S7, an eighth switch S8 and a ninth switch S9; a first end of the first switch S1 is used to access a first input voltage, and a second end of the first switch S1 is connected to a first end of the first sampling capacitor Cs1; a second end of the first sampling capacitor Cs1 is connected to a first end of the second switch S2, a second end of the second switch S2 is connected to a first end of the first capacitor C1, and a second end of the first capacitor C1 is connected to a first input end of a second operational amplifier AMP2; a first end of the third switch S3 is connected to a second end of the first sampling capacitor Cs1, and a second end of the third switch S3 is connected to a ground terminal; a first end of the fourth switch S4 is connected to a ... The first end of the fifth switch S5 is connected to the first end of the second sampling capacitor Cs1, and the second end of the fourth switch S4 is connected to the second end of the second switch S2; the first end of the fifth switch S5 is used to access the second voltage VBE2, the second end of the fifth switch S5 is connected to the first end of the second sampling capacitor Cs2, and the second end of the second sampling capacitor Cs2 is connected to the second input terminal of the second operational amplifier AMP2; the first end of the sixth switch S6 is connected to the first end of the second sampling capacitor Cs2, and the second end of the sixth switch S6 is connected to the ground terminal; the first end of the seventh switch S7 is connected to the second end of the second sampling capacitor Cs2, and the second end of the seventh switch S7 is connected to the ground terminal; the first end of the eighth switch S8 is used to access the second voltage VBE2, the second end of the eighth switch S8 is connected to the first end of the second capacitor C2, and the second end of the second capacitor C2 is connected to the second input terminal of the second operational amplifier AMP2; the first end of the ninth switch S9 is connected to the first end of the second capacitor C2, and the second end of the ninth switch S9 is connected to the ground terminal.

[0184] It should be noted that, in the sampling working state of the switch capacitor module 20, the integral switch S1, the first switch S1, the second switch S2, the third switch S3, the fifth switch S5, the seventh switch S7 and the ninth switch S9 are closed, and the fourth switch S4, the sixth switch S6 and the eighth switch S8 are opened. At this time, the charge amount of the second capacitor C2 is zero, and the charge amounts accumulated by the first capacitor C1, the first sampling capacitor Cs1 and the second sampling capacitor Cs2 are respectively:

[0185] Qc1=Vos2*C1

[0186] Qcs1=VIN*C1

[0187] Qcs2=VBE2*Cs2

[0188] In the integration working state of the switched capacitor module 20, the integration switch S1, the first switch S1, the second switch S2, the fifth switch S5, the seventh switch S7 and the ninth switch S9 are disconnected, and the third switch S3, the fourth switch S4, the sixth switch S6 and the eighth switch S8 are closed. According to the charge conservation law, the voltage of the second node m2 satisfies the following relationship:

[0189] Vm2*Cs2+(Vm2-VBE2)*C2=-VBE2*Cs2

[0190] That is, the voltage of the second node m2 is:

[0191] Vm2=VBE2*(C2-Cs2) / (C2+Cs2)

[0192] Due to the virtual short and virtual open characteristics of the second operational amplifier AMP2, the voltage at the first input terminal of the second operational amplifier AMP2 is: Vm2+Vos2, and the charge amount of the first capacitor C1 remains unchanged (that is, the voltage difference across the first capacitor C1 remains unchanged), so the voltage of the first node m1 satisfies the following relationship:

[0193] Vm2+Vos2-Vm1=Vos2

[0194] Therefore, the voltage of the first node m1 is:

[0195] Vm1=Vm2=VBE2*(C2-Cs2) / (C2+Cs2)

[0196] The first input voltage VIN is generated by the voltage changing module 40 according to the first voltage VBE1. Since the first input voltage VIN and the first voltage VBE1 satisfy a first ratio, the difference between the capacitance values ​​of the second sampling capacitor Cs2 and the second capacitor C2 relative to the sum of the capacitance values ​​of the second sampling capacitor Cs2 and the second capacitor C2 satisfies a second ratio, and the first ratio is equal to the second ratio, that is, the first input voltage VIN and the first voltage VBE1 satisfy the following relationship:

[0197] VIN / VBE1=(C2-Cs2) / (C2+Cs2)

[0198] That is, the first input voltage is VIN=(C2-Cs2) / (C2+Cs2)*VBE1. Combined with the voltage of the first node m1, the amount of charge accumulated in the first sampling capacitor Cs1 in the integral working state of the switch capacitor module 20 is:

[0199] Qcs1=(VIN-Vm1)*Cs1=(C2-Cs2) / (C2+Cs2)*(VBE2-VBE1)*Cs1

[0200] Therefore, the reference voltage VBG output by the second operational amplifier AMP2 satisfies the following relationship:

[0201] VBG=(C2-Cs2) / (C2+Cs2)*[VBE2+(VBE2-VBE1)*Cs1 / CI]

[0202] It can be seen that in the above formula, (C2-Cs2) / (C2+Cs2) is a constant term, so the size of the reference voltage VBG can be changed by changing C2 and Cs2, and the positive and negative temperature coefficient voltages can be offset by changing the Cs1 / CI ratio to output a reference voltage VBG that is independent of absolute temperature. In addition, in the above embodiment, the offset voltage Vos2 of the second operational amplifier AMP2 is fixed to the first capacitor C1, and not only the charge output by the first sampling capacitor Cs1 (i.e., the first temperature coefficient charge Q0) is independent of the offset voltage Vos2 of the second operational amplifier AMP2, but also the voltage of the first node m1 (i.e., the first terminal voltage of the integrating capacitor CI) is independent of the offset voltage Vos2 of the second operational amplifier AMP2, thereby completely eliminating the influence of the offset voltage of the second operational amplifier AMP2.

[0203] The embodiment of the present application also provides a chip, which includes the above-mentioned bandgap reference circuit. A chip (Integrated Circuit, IC) is also called a chip, and the chip can be, but is not limited to, a SOC (System on Chip) chip or a SIP (system in package) chip. Since the chip of the present application has the bandgap reference circuit described in the above embodiment, it has all the beneficial effects of the bandgap reference circuit in the above embodiment, which will not be repeated here.

[0204] The embodiment of the present application also provides an electronic device, which includes a device body and a chip as described above provided in the device body. The electronic device may be, but is not limited to, a weight scale, a body fat scale, a nutrition scale, an infrared electronic thermometer, a pulse oximeter, a human body composition analyzer, a mobile power supply, a wireless charger, a fast charger, a car charger, an adapter, a display, a USB (Universal Serial Bus) docking station, a stylus, a true wireless headset, a car central control panel, a car, a smart wearable device, a mobile terminal, and a smart home device. Smart wearable devices include, but are not limited to, smart watches, smart bracelets, and cervical massagers. Mobile terminals include, but are not limited to, smart phones, laptops, tablet computers, and POS (point of sales terminal). Smart home devices include, but are not limited to, smart sockets, smart rice cookers, smart sweepers, and smart lights.

[0205] The above are only preferred embodiments of the present application, and are not intended to limit the present application in any form. Although the present application has been disclosed as above with preferred embodiments, it is not intended to limit the present application. Any technical personnel in the field can make some changes or modify the technical contents disclosed above into equivalent embodiments without departing from the scope of the technical solution of the present application. However, any brief modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.

Claims

1. A bandgap reference circuit, characterized in that: include: A voltage output module, the voltage output module comprising a first operational amplifier, the voltage output module being used to output a first voltage and a second voltage, the first voltage and the second voltage being negatively correlated with absolute temperature, and a first voltage difference between the first voltage and the second voltage being positively correlated with absolute temperature; A switch capacitor module, the switch capacitor module is used to output a first temperature coefficient voltage and a first temperature coefficient charge according to the first voltage and the second voltage; an integration module, the integration module being used to access the first temperature coefficient voltage and integrate the first temperature coefficient charge, so as to output a reference voltage according to the first temperature coefficient voltage and the first temperature coefficient charge; The first temperature coefficient voltage is negatively correlated with the absolute temperature, the first temperature coefficient charge is positively correlated with the absolute temperature, and the first temperature coefficient charge is generated based on the first voltage difference.

2. The bandgap reference circuit according to claim 1, wherein: The integration module includes a second operational amplifier, an integration capacitor and an integration switch; The first end of the integrating capacitor is connected to the first input end of the second operational amplifier, and the second end of the integrating capacitor is connected to the output end of the second operational amplifier; The first end of the integration switch is connected to the first input end of the second operational amplifier, and the second end of the integration switch is connected to the output end of the second operational amplifier; The first input terminal of the second operational amplifier is configured to receive the first temperature coefficient charge, and the second input terminal of the second operational amplifier is configured to access the first temperature coefficient voltage.

3. The bandgap reference circuit according to claim 2, characterized in that: The first temperature coefficient charge is independent of an offset voltage of the second operational amplifier.

4. The bandgap reference circuit according to claim 2 or 3, characterized in that: The switch capacitor module includes a first sampling capacitor, a first switch and a second switch; A first end of the first sampling capacitor is connected to the ground end, and a second end of the first sampling capacitor is connected to a first input end of the second operational amplifier; The first end of the first switch is used to access the first voltage, and the second end of the first switch is connected to the second input end of the second operational amplifier; The first end of the second switch is used to access the second voltage, and the second end of the second switch is connected to the second input end of the second operational amplifier.

5. The bandgap reference circuit according to claim 2, wherein: The first temperature coefficient charge is independent of the offset voltage of the second operational amplifier, and the first terminal voltage of the integrating capacitor is independent of the offset voltage of the second operational amplifier.

6. The bandgap reference circuit according to claim 2 or 5, characterized in that: The switch capacitor module includes a first sampling capacitor, a first switch, a second switch, a third switch, a fourth switch, a fifth switch and a first capacitor; The first end of the first switch is used to access the first voltage, and the second end of the first switch is connected to the first end of the first sampling capacitor; The second end of the first sampling capacitor is connected to the first end of the first capacitor, and the second end of the first capacitor is connected to the first input end of the second operational amplifier; A first end of the second switch is connected to a first end of the first sampling capacitor, and a second end of the second switch is connected to a ground end; The first end of the third switch is connected to the second end of the first sampling capacitor, and the second end of the third switch is connected to the ground end; The first end of the fourth switch is used to access the second voltage, and the second end of the fourth switch is connected to the second input end of the second operational amplifier; A first end of the fifth switch is connected to the second input end of the second operational amplifier, and a second end of the fifth switch is connected to the ground end.

7. The bandgap reference circuit according to claim 2 or 5, characterized in that: The switch capacitor module includes a first sampling capacitor, a first capacitor, a first switch, a second switch, a third switch, a second sampling capacitor, a second capacitor, a fourth switch, a fifth switch, a sixth switch, a seventh switch and an eighth switch; The first end of the first switch is used to access the first input voltage, and the second end of the first switch is connected to the first end of the first sampling capacitor; The second end of the first sampling capacitor is connected to the first end of the first capacitor, and the second end of the first capacitor is connected to the first input end of the second operational amplifier; The first end of the second switch is connected to the first end of the first sampling capacitor, and the second end of the second switch is connected to the ground end. The first end of the third switch is connected to the second end of the first sampling capacitor, and the second end of the third switch is connected to the ground end; The first end of the fourth switch is used to access the second voltage, the second end of the fourth switch is connected to the first end of the second sampling capacitor, and the second end of the second sampling capacitor is connected to the second input end of the second operational amplifier; The first end of the fifth switch is connected to the first end of the second sampling capacitor, and the second end of the fifth switch is connected to the ground end. The first end of the sixth switch is connected to the second end of the second sampling capacitor, and the second end of the sixth switch is connected to the ground end; The first end of the seventh switch is used to access the second voltage, the second end of the seventh switch is connected to the first end of the second capacitor, and the second end of the second capacitor is connected to the second input end of the second operational amplifier; A first end of the eighth switch is connected to a first end of the second capacitor, and a second end of the eighth switch is connected to a ground end; The first input voltage is generated based on the first voltage, the first input voltage satisfies a first ratio to the first voltage, the difference between the capacitance values ​​of the second sampling capacitor and the second capacitor satisfies a second ratio relative to the sum of the capacitance values ​​of the second sampling capacitor and the second capacitor, and the first ratio is equal to the second ratio.

8. The bandgap reference circuit according to claim 2 or 5, characterized in that: The switch capacitor module includes a first sampling capacitor, a first switch, a second switch, a third switch, a fourth switch, a first capacitor, a fifth switch and a sixth switch; The first end of the first switch is used to access a first voltage, and the second end of the first switch is connected to the first end of the first sampling capacitor; The second end of the first sampling capacitor is connected to the first end of the second switch, the second end of the second switch is connected to the first end of the first capacitor, and the second end of the first capacitor is connected to the first input end of the second operational amplifier; The first end of the third switch is connected to the second end of the first sampling capacitor, and the second end of the third switch is connected to the ground end; A first end of the fourth switch is connected to a first end of the first sampling capacitor, and a second end of the fourth switch is connected to a second end of the second switch; The first end of the fifth switch is used to access the second voltage, and the second end of the fifth switch is connected to the second input end of the second operational amplifier; A first end of the sixth switch is connected to the second input end of the second operational amplifier, and a second end of the sixth switch is connected to the ground end.

9. The bandgap reference circuit according to claim 2 or 5, characterized in that: The switch capacitor module includes a first sampling capacitor, a first switch, a second switch, a third switch, a fourth switch, a first capacitor, a second sampling capacitor, a second capacitor, a fifth switch, a sixth switch, a seventh switch, an eighth switch and a ninth switch; The first end of the first switch is used to access the first input voltage, and the second end of the first switch is connected to the first end of the first sampling capacitor; The second end of the first sampling capacitor is connected to the first end of the second switch, the second end of the second switch is connected to the first end of the first capacitor, and the second end of the first capacitor is connected to the first input end of the second operational amplifier; The first end of the third switch is connected to the second end of the first sampling capacitor, and the second end of the third switch is connected to the ground end; A first end of the fourth switch is connected to a first end of the first sampling capacitor, and a second end of the fourth switch is connected to a second end of the second switch; The first end of the fifth switch is used to access the second voltage, the second end of the fifth switch is connected to the first end of the second sampling capacitor, and the second end of the second sampling capacitor is connected to the second input end of the second operational amplifier; A first end of the sixth switch is connected to a first end of the second sampling capacitor, and a second end of the sixth switch is connected to a ground end; The first end of the seventh switch is connected to the second end of the second sampling capacitor, and the second end of the seventh switch is connected to the ground end; The first end of the eighth switch is used to access the second voltage, the second end of the eighth switch is connected to the first end of the second capacitor, and the second end of the second capacitor is connected to the second input end of the second operational amplifier; A first end of the ninth switch is connected to the first end of the second capacitor, and a second end of the ninth switch is connected to the ground end; The first input voltage is generated based on the first voltage, the first input voltage satisfies a first ratio to the first voltage, the difference between the capacitance values ​​of the second sampling capacitor and the second capacitor satisfies a second ratio relative to the sum of the capacitance values ​​of the second sampling capacitor and the second capacitor, and the first ratio is equal to the second ratio.

10. A chip, characterized in that: The method comprises a bandgap reference circuit as claimed in any one of claims 1 to 9.

11. An electronic device, characterized in that: Comprising the chip as claimed in claim 10.

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