SIMT stack system and method based on GPGPU thread bundle and medium

Abstract

The invention relates to the technical field of GPGPU (General Purpose Graphics Processing Unit) design, for example, relates to an SIMT (Subscriber Identity Module Table) stack system and method based on GPGPU thread bundles and a medium. The system comprises a thread beam branch information FIFO, a branch detection unit and a stack unit, the thread beam branch information FIFO has a handshake signal and stores thread beam branch information, thread beam branch information synchronization is achieved between a write-in end and a read end of the thread beam branch information FIFO through a handshake protocol, and the thread beam branch information of a needed time sequence is collected. Therefore, unnecessary waste of storage resources is reduced, and the overall execution efficiency of the SIMT module is improved. The branch detection unit skips the branch stack with a small number of active threads, the management logic of the SIMT stack is simplified, unnecessary stack operation is reduced, the stack unit simplifies the design of the stack unit, the stack efficiency is improved, and the time period of data processing is shortened.

Description

Technical Field

[0001] The present application relates to the technical field of general purpose computing graphics processing unit (GPGPU) design, for example, to a SIMT stack system, method and medium based on GPGPU thread bundles. Background Art

[0002] At present, with the continuous leap in GPGPU's parallel computing capabilities, its application areas have been greatly expanded, covering many cutting-edge fields such as high-performance computing, artificial intelligence, machine learning, big data analysis and cloud computing. However, with the rapid growth in the demand for GPGPU's parallel processing capabilities, the problems that emerge during operation are becoming increasingly prominent. In particular, conditional branches in the instruction stream have become one of the key factors affecting GPGPU performance. These conditional branches will disrupt the SIMT (single instruction multiple threads) execution mode and significantly reduce its execution efficiency, because different threads may take different execution paths based on conditional branches, resulting in a large number of execution units waiting or in idle state, which cannot be fully utilized, thereby weakening the overall computing performance of GPGPU.

[0003] In order to maintain the execution efficiency of SIMT as much as possible, the GPGPU architecture generally handles conditional branches by serializing the execution of different threads. The conditional branch will control the execution of each thread separately according to the judgment result obtained when each thread of the thread bundle is running. Here, active masks and SIMT stacks are generally used for management. Common problems in the commonly used SIMT stack structure include: first, the execution state needs to be saved to the SIMT stack and restored at the appropriate time, which adds additional storage and access overhead; second, the management of the SIMT stack requires complex logic and control mechanisms, which increases the complexity and implementation difficulty of the GPGPU architecture.

[0004] Therefore, it is necessary to adopt a more efficient SIMT stack design to reduce storage and access overhead, streamline the management logic of the SIMT stack, reduce unnecessary control signals and state transfers, and adopt a simpler branch processing strategy to simplify the implementation of the SIMT stack.

[0005] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present application, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0006] In order to provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. The summary is not an extensive review, nor is it intended to identify key / critical components or delineate the scope of protection of these embodiments, but rather serves as a prelude to the detailed description that follows.

[0007] The embodiments of the present disclosure provide a GPGPU warp-based SIMT stack system, method, and medium to reduce storage and access overhead during stack implementation, simplify the implementation logic of the SIMT stack, and thereby improve the performance and efficiency of branch processing.

[0008] In some embodiments, the GPGPU thread bundle-based SIMT stack system includes: a thread bundle branch information FIFO, a branch detection unit and a stack unit, the thread bundle branch information FIFO has a handshake signal and stores thread bundle branch information, and realizes thread bundle branch information synchronization between the writing end and the reading end of the thread bundle branch information FIFO through a handshake protocol and collects thread bundle branch information of the required timing; the branch detection unit is connected to the thread bundle branch information FIFO, and is used to receive the handshake signal and thread bundle branch information in the thread bundle branch information FIFO, and receive the branch thread active mask and the thread bifurcation point active mask, and judge whether there is a branch. If no branch occurs, no stack behavior is generated, and the execution of the SIMT stack is skipped. If a branch is generated, the number of active threads of the generated branch is judged, and the active thread mask, npc, rpc and corresponding stack push and pop signals of the branch with a large number of active threads are input into the stack unit, rpc refers to the pc value of the branch with a large number of active threads, npc is the pc value of the next instruction to be executed, and the branch with a small number of active threads skips the stack and is directly executed; the stack unit performs the corresponding stack push or pop operation after receiving the information sent by the branch detection unit.

[0009] Furthermore, there are two pairs of handshake signals for the thread bundle branch information FIFO. One pair is the write-ready signals branch_valid_i and branch_ready_o, which are used to interact with the module at the previous level of the thread bundle branch information FIFO to receive the data with the required timing and store it in the thread bundle branch information FIFO; the other pair is the read-valid signals branch_ready_i and branch_valid_o, which are used to interact with the module behind the thread bundle branch information FIFO, that is, to notify the branch detection unit module to receive data.

[0010] Furthermore, the write-ready signal comes from a non-full signal of the thread warp branch information FIFO, and the read-valid signal comes from a non-empty signal of the thread warp branch information FIFO.

[0011] Furthermore, the thread warp branch information includes the branch path PC, the executing PC, the branch reunion point PC, the eject signal eject, and the thread warp ID that executes the branch instruction.

[0012] Furthermore, the process of the branch detection unit determining whether a branch is generated is as follows: first, the thread activity mask on the if path and the thread activity mask on the else path are obtained according to the received branch thread activity mask and the thread bifurcation point activity mask. The implementation process is to perform a bitwise AND operation on the branch thread activity mask and the thread bifurcation point activity mask to obtain the thread activity mask on the if path, then invert it and perform a bitwise AND operation on the activity mask of the thread bifurcation point to obtain the thread activity mask on the else path, and then perform a branch judgment based on the thread activity masks of the two paths. When they are not all zero at the same time, it is confirmed that a branch has been generated.

[0013] Furthermore, a branch with a large number of active threads has two sets of active thread masks, npc, and rpc, which are the rpc, npc, and thread activity mask of the branch and the rpc, npc, and thread activity mask of the branch reunion point of the branch. The npc of the if branch is the PC being executed plus the address occupied by the number of instructions taken, rpc is the branch reunion point PC, and the active mask is the if path active mask. The npc of the else branch is the branch path PC, rpc is the branch reunion point PC, and the active mask is the else path active mask; the npc and rpc of the branch reunion point are both the branch reunion point PC, and the active mask is the active mask of the thread bifurcation point.

[0014] Furthermore, the branch detection unit also performs stack push and stack pop judgments, and the judgment process is: first receive the reading valid signals branch_ready_i and branch_valid_o, and the stack pop signal eject. When the levels of branch_ready_i and branch_valid_o are both high and the stack pop signal eject is low, the branch detection unit outputs a stack push signal push as high, telling the stack unit to start pushing the current branch information; when the levels of branch_ready_i and branch_valid_o are both high and the stack pop signal eject is high, the branch detection unit outputs a stack pop signal pop as high, telling the stack unit to pop the stack; at the same time, the thread bundle is determined, and the number of thread bundles is cyclically detected. If it is equal to the thread bundle ID of the executing branch instruction at the current moment, the thread bundle ID of the current execution stack is determined.

[0015] Furthermore, push and pop operations are performed in the stack unit. The push operation is to open three arrays as stacks in the stack unit, which are used to store rpc, npc and active mask from the branch detection unit respectively. When the push signal is high, the branch path and the rpc, npc and active mask of the branch reunion point are pushed into the stack at the same time, and the rpc, npc and active mask of the branch path are pushed into the high address, and the rpc, npc and active mask of the branch reunion point are pushed into the low address; the pop operation is when the pop signal is high and the PC value being executed is equal to the rpc at the top of the stack, the rpc, npc and active mask at the top of the stack are popped out first. During the entire branch processing process, the information currently at the top of the stack is gradually popped out until all the data in the stack unit is popped out and the branch processing is completed.

[0016] In some embodiments, the GPGPU warp-based SIMT stack method includes:

[0017] S01. Receive and store the thread bundle branch information through the FIFO module. The FIFO module has a handshake signal. The handshake protocol is used to synchronize information between the writing end and the reading end of the thread bundle branch information FIFO and collect the required timing information. The thread bundle branch information FIFO has two pairs of handshake signals. One pair is the write-ready signal branch_valid_i and branch_ready_o, which are used to interact with the module at the previous level of the thread bundle branch information FIFO, receive the required timing data and store it in the thread bundle branch information FIFO; the other pair is the read-valid signal branch_ready_i and branch_valid_o, which are used to interact with the module behind the thread bundle branch information FIFO, that is, to notify the branch detection unit module to receive data. The thread bundle branch information includes the branch path PC, the PC being executed, the branch reunion point PC, the eject signal eject, and the thread bundle ID that executes the branch instruction.

[0018] S02, the thread bundle branch information and handshake signal stored in the FIFO module are sent to the branch detection unit, and the branch detection unit receives the input branch active thread mask and thread bifurcation point active mask to perform thread branch judgment and stack push and pop judgment;

[0019] The thread branch judgment first obtains the thread activity mask on the if path and the thread activity mask on the else path based on the received branch thread activity mask and the thread bifurcation point activity mask. The implementation process is to perform a bitwise AND operation on the branch thread activity mask and the thread bifurcation point activity mask to obtain the thread activity mask on the if path, then negate it and perform a bitwise AND operation on the activity mask of the thread bifurcation point to obtain the thread activity mask on the else path, and then perform branch judgment based on the thread activity masks of these two paths. When they are not all zero at the same time, it is confirmed that a branch has been generated. If a branch has been generated, subsequent operations are started; in other cases, no branch has been generated, and subsequent operations are not performed; the subsequent operation is to count the active thread bundles on the if and else paths and determine which one has the most active threads, and increase the number of active threads. The active thread mask, npc, and rpc of a branch with a large number of active threads are pushed into the stack unit, and the path information of a branch with a small number of active threads is not stacked and is directly sent to the subsequent module for processing; the branch with a large number of active threads has two sets of active thread masks, npc, and rpc, which are the rpc, npc, and thread active mask of the branch and the rpc, npc, and thread active mask of the branch reunion point of the branch, the npc of the if branch is the PC being executed plus the address occupied by the number of instructions taken, rpc is the branch reunion point PC, and the active mask is the if path active mask, the npc of the else branch is the branch path PC, rpc is the branch reunion point PC, and the active mask is the else path active mask; the npc and rpc of the branch reunion point are both the branch reunion point PC, and the active mask is the active mask of the thread bifurcation point;

[0020] The stack push and pop judgment process is as follows: first, the reading valid signals branch_ready_i and branch_valid_o and the stack eject signal eject are received. When the levels of branch_ready_i and branch_valid_o are both high and the stack eject signal eject is low, the branch detection unit outputs a stack push signal push as high, telling the stack unit to start pushing the current branch information; when the levels of branch_ready_i and branch_valid_o are both high and the stack eject signal eject is high, the branch detection unit outputs a stack pop signal pop as high, telling the stack unit to pop the stack; at the same time, the thread bundle is determined, and the number of thread bundles is cyclically detected. If it is equal to the thread bundle ID of the executing branch instruction at the current moment, the thread bundle ID of the current execution stack is determined;

[0021] S03. The stack unit performs corresponding push and pop operations according to the received active thread mask, npc, rpc and push and pop signals; the push operation is to open three arrays as stacks in the stack unit, which are used to store rpc, npc and active mask from the branch detection unit respectively. When the push signal is high, the branch path and the rpc, npc and active mask of the branch reunion point are pushed into the stack at the same time, and the branch path is pushed into the high address, and the branch reunion point is pushed into the low address; the pop operation is when the pop signal is high and the PC value being executed is equal to the rpc at the top of the stack, the rpc, npc and active mask at the top of the stack are popped out first, and during the entire branch processing process, the information currently at the top of the stack is gradually popped out until all the data in the stack unit is popped out and the branch processing is completed.

[0022] In some embodiments, the storage medium stores program instructions, and when the program instructions are run, the above-mentioned SIMT stack method based on GPGPU thread warps is executed.

[0023] The embodiments of the present disclosure provide a GPGPU warp-based SIMT stack system, method, and medium, which can achieve the following technical effects:

[0024] According to the designed FIFO module with handshake signal, the present invention only stores and reads the thread bundle branch information with the timing required at the moment between the writing end and the reading end of the thread bundle branch information FIFO through the handshake protocol, and skips the branch stack with a small number of active threads through the design of comparing the number of active threads of the if and else paths in the branch detection unit, thereby reducing the storage and access overhead in the stack implementation process, simplifying the implementation logic of the SIMT stack, and improving the performance and efficiency of branch processing.

[0025] The above general description and the following description are exemplary and explanatory only and are not intended to limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] One or more embodiments are exemplarily described by corresponding drawings, which do not limit the embodiments. Elements with the same reference numerals in the drawings are shown as similar elements, and the drawings do not constitute a scale limitation, and wherein:

[0027] Figure 1 It is the principle block diagram of SIMT stack system;

[0028] Figure 2 It is a flow chart of branch judgment;

[0029] Figure 3 It is a flowchart for stack push and stack pop judgment. DETAILED DESCRIPTION

[0030] In order to be able to understand the features and technical contents of the embodiments of the present disclosure in more detail, the implementation of the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present disclosure. In the following technical description, for the convenience of explanation, a full understanding of the disclosed embodiments is provided through multiple details. However, one or more embodiments can still be implemented without these details. In other cases, to simplify the drawings, well-known structures and devices can be simplified for display.

[0031] The terms "first", "second", etc. in the embodiments of the present disclosure are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchanged where appropriate, so as to describe the embodiments of the present disclosure described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions.

[0032] Unless otherwise stated, the term "plurality" means two or more.

[0033] In the embodiment of the present disclosure, the character " / " indicates that the preceding and following objects are in an "or" relationship. For example, A / B indicates: A or B.

[0034] The term "and / or" is a description of the association relationship between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or, A and B.

[0035] The term "correspondence" may refer to an association relationship or a binding relationship. The correspondence between A and B means that there is an association relationship or a binding relationship between A and B.

[0036] Example 1

[0037] This embodiment discloses a SIMT stack system based on GPGPU thread warps, such as Figure 1 As shown, it includes a thread warp branch information FIFO, a branch detection unit and a stack unit.

[0038] The thread bundle branch information FIFO has a handshake signal and stores the thread bundle branch information. The thread bundle branch information is synchronized between the writing end and the reading end of the thread bundle branch information FIFO through the handshake protocol, and the thread bundle branch information of the required timing is collected according to the information interaction between the handshake signals. This module uses the handshake signal to efficiently store the thread branch information (only the thread bundle branch information at the required time is stored), reducing unnecessary waste of storage resources and improving the overall execution efficiency of the SIMT module.

[0039] The branch detection unit is connected to the thread bundle branch information FIFO, and is used to receive the handshake signal and thread bundle branch information in the thread bundle branch information FIFO, and receive the branch thread active mask and thread bifurcation point active mask to determine whether a branch is generated. If no branch occurs, no stack behavior is generated and the execution of the SIMT stack is skipped. If a branch is generated, the number of active threads of the generated branch is determined, and the active thread mask, npc, rpc and corresponding push and pop signals of the branch with a large number of active threads are input into the stack unit. rpc refers to the pc value of the branch with a large number of active threads, and npc is the pc value of the next instruction to be executed. The branch with a small number of active threads skips the stack and is executed directly. The design of the branch detection unit simplifies the management logic of the SIMT stack and reduces unnecessary stack operations.

[0040] The data stack unit can perform a stack pop operation by simultaneously pushing in the RPC, NPC and thread active mask of the branch, as well as the RPC, NPC and thread active mask of the branch reunion point of the branch, and pop out the RPC, NPC and thread active mask of the branch to be executed. This unit simplifies the design of the stack unit, improves the efficiency of the stack, and reduces the time cycle of data processing.

[0041] like Figure 1 As shown in the figure, the specific implementation of the thread bundle branch information FIFO includes two pairs of handshake signals, one pair is branch_valid_i and branch_ready_o (write ready signal, which comes from the non-full signal of fifo), which is used to interact with the module at the previous level, receive accurate data and store it in FIFO; the other pair is branch_ready_i and branch_valid_o (read valid signal, which comes from the non-empty signal of fifo) to interact with the module behind it, that is, to notify the branch detection unit module that it can receive data.

[0042] The thread warp branch information stored in the thread warp branch information FIFO includes the branch path PC and the PC being executed, the branch reunion point PC, the eject signal eject, and the thread warp ID that executes the branch instruction.

[0043] In this embodiment, the specific implementation of the branch detection unit module function includes two parts. First, the judgment of the generation of thread branches is completed, as shown in the attached Figure 2As shown. First, the thread active mask on the if path and the thread active mask on the else path are obtained according to the received branch thread active mask and the thread bifurcation point active mask. The implementation process is to perform a bitwise AND operation on the branch thread active mask and the thread bifurcation point active mask to obtain the thread active mask on the if path, and then negate it and perform a bitwise AND operation on the active mask of the thread bifurcation point to obtain the thread active mask on the else path. The advantage of this design is that even if the branch path continues to branch, the thread active mask on the else path can be automatically obtained. Then, the branch judgment is performed according to the thread active masks of the two paths. When they are not all zero at the same time, it can be confirmed that a branch has been generated. If a branch is generated, the next step is started; in other cases, no branch is generated, and no subsequent operations are performed. Then, the number of active threads is judged according to the thread active masks of the if and else paths. If the number of active threads is large, its active thread mask, npc, and rpc are first pushed into the stack unit, and the path information with a small number of active threads is directly sent to the subsequent module for processing without stacking. Next is the determination of npc, rpc and active mask. The npc of the if path is the PC being executed plus the address occupied by the number of instructions taken, rpc is the branch reunion point PC, and the active mask is the active mask of the if path; the npc of the else path is the branch path PC, rpc is the branch reunion point PC, and the active mask is the active mask of the else path; the npc and rpc of the branch reunion point are both the branch reunion point PC, and the active mask is the active mask of the thread fork point.

[0044] Second, complete the judgment of stack push and stack pop, as shown in the attached Figure 3 As shown. First, the branch_ready_i, branch_valid_o signals and eject are received. According to the branch_ready_i and branch_valid_o signals, when their levels are both high and the eject signal eject is low, the push signal push is high, which tells the stack unit to start pushing the current branch information. When the branch_ready_i and branch_valid_o signals are both high and the eject signal eject is high, at this time, the pop signal pop is high, which tells the stack unit to pop the stack. At the same time, the thread bundle is determined, and the number of thread bundles is cyclically detected. If it is equal to the thread bundle ID of the executing branch instruction at the current moment, the thread bundle ID of the current execution stack can be determined.

[0045] In this embodiment, the specific implementation of the functions in the stack unit is: first, the stack push operation, which opens up three arrays of a certain depth in the stack unit as stacks, which are respectively used to store the rpc, npc and active mask from the branch detection unit module. When the stack push signal is high, the rpc, npc and active mask of the branch path and the branch reunion point are pushed in at the same time, and the branch path is pushed into the high address, and the branch reunion point is pushed into the low address, that is, the high address is used as the top of the stack. The second is the stack pop operation. When the stack pop signal is high and the PC value being executed is equal to the rpc at the top of the stack, the rpc, npc and active mask at the top of the stack are popped out first. During the entire branch processing process, the information currently at the top of the stack is gradually popped out until all the data in the stack unit is popped out, and the branch processing is completed.

[0046] Example 2

[0047] This embodiment discloses a SIMT stacking method based on a GPGPU warp, comprising the following steps:

[0048] S01. Receive and store thread bundle branch information through the FIFO module. The FIFO module has a handshake signal. The handshake protocol is used to synchronize information between the write end and the read end of the thread bundle branch information FIFO and collect the required timing information. There are two pairs of handshake signals of the thread bundle branch information FIFO. One pair is the write-ready signal branch_valid_i and branch_ready_o, which are used to interact with the module at the previous level of the thread bundle branch information FIFO to receive the required timing data and store it in the thread bundle branch information FIFO. The other pair is the read-valid signal branch_ready_i and branch_valid_o, which are used to interact with the module behind the thread bundle branch information FIFO, that is, to notify the branch detection unit module to receive data. The thread bundle branch information includes the branch path PC, the PC being executed, the branch reunion point PC, the eject signal eject, and the thread bundle ID that executes the branch instruction.

[0049] S02. The valid thread bundle branch information and handshake signal stored in the FIFO module are sent to the branch detection unit. Meanwhile, the branch detection unit receives the input branch active thread mask and thread bifurcation point active mask to perform thread branch judgment and stack push and pop judgment.

[0050] The thread branch judgment first obtains the thread active mask on the if path and the thread active mask on the else path based on the received branch thread active mask and the active mask of the thread bifurcation point. The implementation process is to perform a bitwise AND operation on the branch thread active mask and the active mask of the thread bifurcation point to obtain the thread active mask on the if path, and then invert it and perform a bitwise AND operation with the active mask of the thread bifurcation point to obtain the thread active mask on the else path. Then, the branch judgment is performed based on the thread active masks of these two paths. When they are not all zero at the same time, it is confirmed that a branch has been generated. If a branch has been generated, subsequent operations are started; in other cases, no branches have been generated, and subsequent operations are not performed; the subsequent operation is to count the active thread bundles of the if and else paths and determine which one has more active threads, and push the active thread mask, npc, and rpc of the one with more active threads into the stack unit. The path information with a small number of active threads is not stacked and is directly sent to the subsequent module for processing; the branch with a large number of active threads has two sets of active thread masks, npc, and rpc. pc and rpc are the rpc, npc and thread active mask of the branch and the rpc, npc and thread active mask of the branch reunion point of the branch respectively. The npc of the if branch is the PC being executed plus the address occupied by the number of instructions taken, rpc is the branch reunion point PC, and the active mask is the if path active mask. The npc of the else branch is the branch path PC, rpc is the branch reunion point PC, and the active mask is the else path active mask. The npc and rpc of the branch reunion point are both the branch reunion point PC, and the active mask is the active mask of the thread bifurcation point.

[0051] The stack push and pop judgment process is as follows: first, the reading valid signals branch_ready_i and branch_valid_o and the stack pop signal eject are received. When the levels of branch_ready_i and branch_valid_o are both high and the stack pop signal eject is low, the branch detection unit outputs the stack push signal push as high, telling the stack unit to start pushing the current branch information; when the levels of branch_ready_i and branch_valid_o are both high and the stack pop signal eject is high, the branch detection unit outputs the stack pop signal pop as high, telling the stack unit to pop the stack; at the same time, the thread bundle is determined, and the number of thread bundles is cyclically detected. If it is equal to the thread bundle ID of the executing branch instruction at the current moment, the thread bundle ID of the current execution stack is determined.

[0052] S03. The stack unit performs corresponding push and pop operations according to the received active thread mask, npc, rpc and push and pop signals; the push operation is to open three arrays as stacks in the stack unit, which are used to store rpc, npc and active mask from the branch detection unit respectively. When the push signal is high, the branch path and the rpc, npc and active mask of the branch reunion point are pushed into the stack at the same time, and the branch path is pushed into the high address, and the branch reunion point is pushed into the low address; the pop operation is when the pop signal is high and the PC value being executed is equal to the rpc at the top of the stack, the rpc, npc and active mask at the top of the stack are popped out first, and during the entire branch processing process, the information currently at the top of the stack is gradually popped out until all the data in the stack unit is popped out and the branch processing is completed.

[0053] Example 3

[0054] An embodiment of the present disclosure provides a computer-readable storage medium storing computer-executable instructions, wherein the computer-executable instructions are configured to execute the above-mentioned GPGPU warp-based SIMT stack method.

[0055] The computer-readable storage medium mentioned above may be a transient computer-readable storage medium or a non-transitory computer-readable storage medium.

[0056] The technical solution of the embodiment of the present disclosure can be embodied in the form of a software product, which is stored in a storage medium and includes one or more instructions for enabling a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in the embodiment of the present disclosure. The aforementioned storage medium may be a non-transient storage medium, including: a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and other media that can store program codes, or a transient storage medium.

[0057] The above description and accompanying drawings fully illustrate the embodiments of the present disclosure so that those skilled in the art can practice them. Other embodiments may include structural, logical, electrical, process and other changes. The embodiments represent possible changes only. Unless explicitly required, separate components and functions are optional, and the order of operation may vary. The parts and features of some embodiments may be included in or replace the parts and features of other embodiments. Moreover, the words used in this application are only used to describe the embodiments and are not used to limit the scope of protection. As used in the description in the text, unless the context clearly indicates, the singular forms of "a", "an" and "the" are intended to include plural forms as well. Similarly, the term "and / or" as used in this application refers to any and all possible combinations of listings containing one or more associated ones. In addition, when used in the present application, the term "comprise" and its variants "comprises" and / or comprising refer to the presence of stated features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof. In the absence of further restrictions, the elements defined by the sentence "comprising a ..." do not exclude the presence of other identical elements in the process, method or device comprising the elements. In this article, each embodiment may focus on the differences from other embodiments, and the same and similar parts between the embodiments may refer to each other. For the methods, products, etc. disclosed in the embodiments, if they correspond to the method part disclosed in the embodiments, then the relevant parts can refer to the description of the method part.

[0058] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software may depend on the specific application and design constraints of the technical solution. The technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the embodiments of the present disclosure. The technicians may clearly understand that for the convenience and simplicity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments, and will not be repeated here.

[0059] In the embodiments disclosed herein, the disclosed methods and products (including but not limited to devices, equipment, etc.) can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units can be only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between each other shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms. The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to implement this embodiment. In addition, each functional unit in the embodiment of the present disclosure may be integrated in a processing unit, or each unit may exist physically alone, or two or more units may be integrated in one unit.

Claims

1. A SIMIT stack system based on GPGPU thread bundles, characterized by: It includes a thread bundle branch information FIFO, a branch detection unit and a stack unit. The thread bundle branch information FIFO has a handshake signal and stores thread bundle branch information. The thread bundle branch information is synchronized between the writing end and the reading end of the thread bundle branch information FIFO through a handshake protocol and the thread bundle branch information of the required timing is collected; The branch detection unit is connected to the thread bundle branch information FIFO, and is used to receive the handshake signal and thread bundle branch information in the thread bundle branch information FIFO, and receive the branch thread activity mask and the thread bifurcation point activity mask to determine whether a branch is generated. If no branch occurs, no stack behavior is generated and the execution of the SIMT stack is skipped. If a branch is generated, the number of active threads of the generated branch is determined, and the active thread mask, npc, rpc and corresponding push and pop signals of the branch with a large number of active threads are input into the stack unit. rpc refers to the pc value of the branch with a large number of active threads, and npc is the pc value of the next instruction to be executed. The branch with a small number of active threads skips the stack and is executed directly. After receiving the information sent by the branch detection unit, the stack unit performs the corresponding push or pop operation.

2. The SIMT stack system based on GPGPU warps according to claim 1, characterized in that: There are two pairs of handshake signals for the thread bundle branch information FIFO. One pair is the write-ready signals branch_valid_i and branch_ready_o, which are used to interact with the module at the previous level of the thread bundle branch information FIFO, receive the data with the required timing and store it in the thread bundle branch information FIFO; the other pair is the read-valid signals branch_ready_i and branch_valid_o, which are used to interact with the module behind the thread bundle branch information FIFO, that is, to notify the branch detection unit module to receive data.

3. The SIMT stack system based on GPGPU warps according to claim 2, characterized in that: The write-ready signal comes from the non-full signal of the thread warp branch information FIFO, and the read-valid signal comes from the non-empty signal of the thread warp branch information FIFO.

4. The SIMT stack system based on GPGPU warps according to claim 2, characterized in that: The thread warp branch information includes the branch path PC, the executing PC, the branch reunion point PC, the eject signal eject, and the thread warp ID that executes the branch instruction.

5. The SIMT stack system based on GPGPU warps according to claim 1, characterized in that: The process of the branch detection unit determining whether a branch is generated is as follows: first, the thread activity mask on the if path and the thread activity mask on the else path are obtained according to the received branch thread activity mask and the thread bifurcation point activity mask. The implementation process is to perform a bitwise AND operation on the branch thread activity mask and the thread bifurcation point activity mask to obtain the thread activity mask on the if path, then invert it and perform a bitwise AND operation on the activity mask of the thread bifurcation point to obtain the thread activity mask on the else path, and then perform a branch judgment based on the thread activity masks of the two paths. When they are not all zero at the same time, it is confirmed that a branch has been generated.

6. The SIMT stack system based on GPGPU warps according to claim 1, characterized in that: A branch with a large number of active threads has two sets of active thread masks, npc, and rpc, which are the rpc, npc, and thread active mask of the branch and the rpc, npc, and thread active mask of the branch reunion point of the branch. The npc of the if branch is the PC being executed plus the address occupied by the number of instructions taken, rpc is the branch reunion point PC, and the active mask is the if path active mask. The npc of the else branch is the branch path PC, rpc is the branch reunion point PC, and the active mask is the else path active mask; the npc and rpc of the branch reunion point are both the branch reunion point PC, and the active mask is the active mask of the thread bifurcation point.

7. The SIMT stack system based on GPGPU warps according to claim 4, characterized in that: The branch detection unit also performs stack push and stack pop judgments, and the judgment process is: first receive the reading valid signals branch_ready_i and branch_valid_o, and the stack pop signal eject. When the levels of branch_ready_i and branch_valid_o are both high and the stack pop signal eject is low, the branch detection unit outputs the stack push signal push as high, telling the stack unit to start pushing the current branch information; when the levels of branch_ready_i and branch_valid_o are both high and the stack pop signal eject is high, the branch detection unit outputs the stack pop signal pop as high, telling the stack unit to pop the stack; at the same time, the thread bundle is determined, and the number of thread bundles is cyclically detected. If it is equal to the thread bundle ID of the execution branch instruction at the current moment, the thread bundle ID of the current execution stack is determined.

8. The SIMT stack system based on GPGPU warps according to claim 6, characterized in that: Push and pop operations are performed in the stack unit. The push operation is to open three arrays as stacks in the stack unit, which are used to store rpc, npc and active mask from the branch detection unit respectively. When the push signal is high, the branch path and the rpc, npc and active mask of the branch reunion point are pushed into the stack at the same time, and the rpc, npc and active mask of the branch path are pushed into the high address, and the rpc, npc and active mask of the branch reunion point are pushed into the low address; the pop operation is when the pop signal is high and the PC value being executed is equal to the rpc at the top of the stack, the rpc, npc and active mask at the top of the stack are popped out first. During the entire branch processing process, the information currently at the top of the stack is gradually popped out until all the data in the stack unit is popped out and the branch processing is completed.

9. A SIMT stacking method based on GPGPU thread bundles, characterized in that: The following steps are involved: S01. Receive and store the thread bundle branch information through the FIFO module. The FIFO module has a handshake signal. The handshake protocol is used to synchronize information between the writing end and the reading end of the thread bundle branch information FIFO and collect the required timing information. The thread bundle branch information FIFO has two pairs of handshake signals. One pair is the write-ready signal branch_valid_i and branch_ready_o, which are used to interact with the module at the previous level of the thread bundle branch information FIFO, receive the required timing data and store it in the thread bundle branch information FIFO; the other pair is the read-valid signal branch_ready_i and branch_valid_o, which are used to interact with the module behind the thread bundle branch information FIFO, that is, to notify the branch detection unit module to receive data. The thread bundle branch information includes the branch path PC, the PC being executed, the branch reunion point PC, the eject signal eject, and the thread bundle ID that executes the branch instruction. S02, the thread bundle branch information and handshake signal stored in the FIFO module are sent to the branch detection unit, and the branch detection unit receives the input branch active thread mask and thread bifurcation point active mask to perform thread branch judgment and stack push and pop judgment; The thread branch judgment first obtains the thread activity mask on the if path and the thread activity mask on the else path according to the received branch thread activity mask and the thread bifurcation point activity mask. The implementation process is to perform a bitwise AND operation on the branch thread activity mask and the thread bifurcation point activity mask to obtain the thread activity mask on the if path, then negate it and perform a bitwise AND operation on the activity mask of the thread bifurcation point to obtain the thread activity mask on the else path, and then perform branch judgment based on the thread activity masks of these two paths. When they are not all zero at the same time, it is confirmed that a branch has been generated. If a branch has been generated, subsequent operations are started; in other cases, no branch has been generated, and subsequent operations are not performed; the subsequent operation is to count the active thread bundles of the if and else paths and determine which one has a larger number of active threads, and push the active thread mask, npc, and rpc of the path with a larger number of active threads into the stack unit. The path information with a smaller number of active threads is not stacked and is directly sent to the subsequent module for processing; A branch with a large number of active threads has two sets of active thread masks, npc, and rpc, which are the rpc, npc, and thread active mask of the branch and the rpc, npc, and thread active mask of the branch reunion point. The npc of the if branch is the PC being executed plus the address occupied by the number of instructions taken, rpc is the branch reunion point PC, and the active mask is the if path active mask. The npc of the else branch is the branch path PC, rpc is the branch reunion point PC, and the active mask is the else path active mask. The npc and rpc of the branch reunion point are both the branch reunion point PC, and the active mask is the thread bifurcation point active mask. The stack push and pop judgment process is as follows: first, the reading valid signals branch_ready_i and branch_valid_o and the stack eject signal eject are received. When the levels of branch_ready_i and branch_valid_o are both high and the stack eject signal eject is low, the branch detection unit outputs a stack push signal push as high, telling the stack unit to start pushing the current branch information; when the levels of branch_ready_i and branch_valid_o are both high and the stack eject signal eject is high, the branch detection unit outputs a stack pop signal pop as high, telling the stack unit to pop the stack; at the same time, the thread bundle is determined, and the number of thread bundles is cyclically detected. If it is equal to the thread bundle ID of the executing branch instruction at the current moment, the thread bundle ID of the current execution stack is determined; S03. The stack unit performs corresponding stack push and pop operations according to the received active thread mask, npc, rpc and push and pop signals; The push operation is to open three arrays in the stack unit as stacks, which are used to store the rpc, npc and active mask from the branch detection unit respectively. When the push signal is high, the branch path and the rpc, npc and active mask of the branch reunion point are pushed into the stack at the same time, and the branch path is pushed into the high address, and the branch reunion point is pushed into the low address; the pop operation is when the pop signal is high and the PC value being executed is equal to the rpc at the top of the stack, the rpc, npc and active mask at the top of the stack are popped out first. During the entire branch processing process, the information currently at the top of the stack is gradually popped out until all the data in the stack unit is popped out, and the branch processing is completed.

10. A storage medium storing program instructions, characterized in that: When the program instructions are run, the SIMT stack method based on GPGPU warps is executed as claimed in claim 9.

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