System-on-chip control method, system-on-chip and computer equipment
By using real-time clock registers in the system on chip to jointly handle the sleep state of multiple systems, the problem of not being able to handle the sleep state of multiple systems in the prior art is solved, and the system is low power consumption and independent maintenance are achieved.
Patent Information
- Application Number
- CN202411159872.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-22
- Publication Date
- 2025-01-10
AI Technical Summary
The prior art is difficult to effectively deal with the dormancy problem of multiple systems, especially when there are many functional modules in vehicle-mounted scenarios, the dormancy treatment solution of a single system cannot be applied to multiple systems.
By introducing a real-time clock register in the on-chip system, the first system receives a sleep instruction and sends it to the second system, both of which perform sleep operations and write their respective sleep states into the real-time clock registers to implement multiple systems collaborative sleep processing.
It realizes unified control and independent processing of multiple systems, facilitates maintenance, and monitors the sleep state of each system through real-time clock registers, improving the system's low power consumption and user experience.
Smart Images
Figure CN119292676A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of device control, and in particular to a control method of a system on chip, a system on chip and a computer device. Background Art
[0002] At present, device hibernation is usually performed for a single system (for example, the Android system). However, in some scenarios (for example, in-vehicle scenarios), there are many functional modules, and the functions of each functional module are implemented in multiple systems. It is necessary to perform hibernation processing for multiple systems. The hibernation processing solution for a single system is not suitable for the hibernation processing of multiple systems, and it is impossible to perform hibernation processing for multiple systems. Summary of the invention
[0003] The present application provides a control method of a system on chip, a system on chip and a computer device, so as to solve the problem that multiple systems cannot be put into sleep mode.
[0004] According to a first aspect of an embodiment of the present application, a control method of a system on chip is provided, which is applied to a system on chip, wherein the system on chip includes a first system and at least one second system, wherein the first system includes a real-time clock register, and the method includes:
[0005] The first system receives the sleep instruction, and sends the sleep instruction to the second system;
[0006] The first system performs a sleep operation based on the sleep instruction to obtain a sleep state of the first system;
[0007] The second system performs a sleep operation based on the sleep instruction, obtains a sleep state of the second system, and sends the sleep state of the second system to the first system;
[0008] The first system writes the sleep status of each of the first system and the second system into the real-time clock register.
[0009] Optionally, the second system performs a sleep operation based on the sleep instruction, including:
[0010] The second system stores the data of the second system in the memory based on the sleep instruction and executes the kernel sleep process;
[0011] When the second system determines that the kernel has not entered the sleep mode, the second system returns to the step of executing the kernel sleep process until the second system determines that the kernel has entered the sleep mode.
[0012] Optionally, the method further comprises:
[0013] The first system controls other modules in the system on chip except the real-time clock register and the memory to power off.
[0014] Optionally, the first system further includes a first core and a second core;
[0015] The first system receives the sleep instruction and sends the sleep instruction to the second system, including:
[0016] The first core receives a sleep instruction, and sends the sleep instruction to the second system;
[0017] The first system performs a sleep operation based on the sleep instruction to obtain a sleep state of the first system, including:
[0018] The first core sends the sleep instruction to the second core; the first core performs a sleep operation based on the sleep instruction to obtain a sleep state of the first core; the second core performs a sleep operation based on the sleep instruction to obtain a sleep state of the second core, and sends the sleep state of the second core to the first core;
[0019] The first system writes the sleep states of the first system and the second system into the real-time clock register, including:
[0020] The first core writes the sleep states of the first core, the second core, and the second system into the real-time clock register.
[0021] Optionally, the method further comprises:
[0022] The real-time clock register obtains a wake-up instruction, and based on the wake-up instruction, converts the state values of the first system and the second system in the real-time clock register from a sleep state to a wake-up state;
[0023] The first system reads the wake-up status of the first system and the second system in the real-time clock register;
[0024] The first system performs a wake-up operation based on the wake-up state of the first system;
[0025] The first system sends the wake-up status of the second system to the second system;
[0026] The second system performs a wake-up operation based on a wake-up state of the second system.
[0027] Optionally, the first system further includes a first core and a second core;
[0028] The first system reads the wake-up status of the first system and the second system in the real-time clock register, including:
[0029] The second core reads the wake-up status of the first core, the second core and the second system in the real-time clock register;
[0030] The first system performs a wake-up operation based on the wake-up state of the first system, including:
[0031] The second core starts the preload module in the second core based on the wake-up state of the second core, performs a wake-up operation and loads the second core; the second core performs a wake-up operation based on the wake-up state of the first core and loads the first core;
[0032] The first system sends the wake-up state of the second system to the second system, including:
[0033] The second core sends the wake-up status of the second system to the second system.
[0034] Optionally, the first system includes a real-time operating system, and the at least one second system includes an Android system and / or a microkernel real-time operating system.
[0035] Optionally, the first core includes a security core, and the second core includes an initial startup core.
[0036] According to a second aspect of an embodiment of the present application, there is provided a system on chip, comprising a first system and at least one second system, wherein the first system comprises a real-time clock register;
[0037] The system on chip is configured to implement the system on chip control method described in the first aspect.
[0038] According to a third aspect of an embodiment of the present application, a computer device is provided, comprising the system on chip described in the second aspect.
[0039] In the present application, the system on chip includes a first system and at least one second system, the first system includes a real-time clock register, the first system receives a sleep instruction, and sends the sleep instruction to the second system, the first system performs a sleep operation based on the sleep instruction, obtains the sleep state of the first system, the second system performs a sleep operation based on the sleep instruction, obtains the sleep state of the second system, and sends the sleep state of the second system to the first system, and the first system writes the sleep state of the first system and the second system into the real-time clock register. The above scheme controls the sleep process of each system in the entire system on chip in the first system as a whole, and realizes the sleep processing of multiple systems. Moreover, each system in the system on chip independently processes its own sleep logic, and each system in the system on chip is independent of each other, which is convenient for independent maintenance of each system in the system on chip. In addition, the sleep state of each of the first system and the second system is written into the real-time clock register, so that the sleep state of each system in the system on chip can be known through the real-time clock register. BRIEF DESCRIPTION OF THE DRAWINGS
[0040] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.
[0041] Figure 1 A schematic flow chart of a control method of a system on chip provided in an embodiment of the present application;
[0042] Figure 2 A schematic diagram of a process of executing a sleep operation based on a sleep instruction in an Android system provided in an embodiment of the present application;
[0043] Figure 3 A schematic diagram of a process flow of a system-on-chip sleep method provided in an embodiment of the present application;
[0044] Figure 4 A schematic flow chart of a control method of a system on chip provided in an embodiment of the present application;
[0045] Figure 5 A flowchart of a method for waking up a system on a chip provided in an embodiment of the present application;
[0046] Figure 6 A schematic diagram of the structure of a system on chip provided in an embodiment of the present application;
[0047] Figure 7 A schematic diagram of the structure of a system on chip provided in an embodiment of the present application;
[0048] Figure 8 A schematic diagram of the structure of a system on chip provided in an embodiment of the present application. DETAILED DESCRIPTION
[0049] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.
[0050] Exemplary Methods
[0051] See also Figure 1 In an exemplary embodiment, a control method of a system on chip is provided, which is applied to the system on chip, the system on chip comprising a first system and at least one second system, the first system comprising a real-time clock register.
[0052] In an exemplary embodiment, a system on chip (SoC), also known as a system-level chip, is a system or product formed by combining multiple integrated circuits with specific functions on a chip, which includes a complete hardware system and the embedded software it carries.
[0053] In the exemplary embodiment, the first system includes both hardware and software; the second system includes both hardware and software.
[0054] In an exemplary embodiment, a real-time clock (RTC) register is a hardware device in the first system.
[0055] In some embodiments, the first system includes a real-time operating system, and at least one second system includes an Android system and / or a microkernel real-time operating system.
[0056] In an exemplary embodiment, a real-time operating system (RTOS) is an operating system that ensures that a specific function is completed within a certain time limit.
[0057] In an exemplary embodiment, Android is a free and open source mobile operating system based on the Linux kernel, which is an open source computer operating system kernel.
[0058] In an exemplary embodiment, the at least one second system may further include other Linux kernel-based operating systems besides the Android system.
[0059] In an exemplary embodiment, the microkernel real-time operating system may be a QNX system, which is a Unix-like real-time operating system. Unix is a powerful multi-user, multi-tasking operating system that supports a variety of processor architectures. According to the classification of operating systems, it is a time-sharing operating system. The microkernel structure of the QNX system is a significant feature that distinguishes it from other operating systems. In the microkernel structure of the QNX system, the kernel is independently located in a protected address space, and the driver, network protocol and application are in the program space.
[0060] In an exemplary embodiment, at least one second system may include an Android system, may include a microkernel real-time operating system, may include an Android system and a microkernel real-time operating system, or may include other operating systems. In the following embodiments, at least one second system including an Android system and a QNX system is used as an example for explanation, but this is not limited to this.
[0061] like Figure 1 As shown, the process of the control method of the system on chip mainly includes:
[0062] Step 101: The first system receives a sleep instruction and sends the sleep instruction to the second system.
[0063] In some embodiments, there are multiple implementations of the first system receiving the sleep instruction, including but not limited to the following implementations:
[0064] Method 1
[0065] The MCU (Micro Control Unit) receives a sleep instruction from a CAN (Controller Area Network) bus, and sends the sleep instruction to the first system.
[0066] Method 2
[0067] The MCU receives the sleep instruction from the CAN bus, and sends the sleep instruction to the VHAL (Virtual Hardware Abstraction Layer) of the Android system. The VHAL of the Android system sends the sleep instruction to the first system through inter-core communication.
[0068] In an exemplary embodiment, the MCU sends a sleep instruction to the VHAL of the Android system. The MCU may send a sleep instruction to the microcontroller hardware abstraction layer (McuHAL) of the Android system, and the microcontroller hardware abstraction layer of the Android system reports the sleep instruction to the VHAL of the Android system.
[0069] In some embodiments, the first system sends the sleep instruction to the second system, and the first system may send the sleep instruction to the second system through inter-core communication.
[0070] Step 102: The first system executes a sleep operation based on the sleep instruction to obtain a sleep state of the first system.
[0071] In some embodiments, the first system performs a sleep operation based on a sleep instruction, including: the first system stores data of the first system in a memory based on the sleep instruction and performs a sleep process.
[0072] In an exemplary embodiment, the memory may include a random access memory (RAM), a read-only memory (ROM), or a flash memory (Flash Memory). The random access memory includes a static random access memory (SRAM) and a dynamic random access memory (DRAM), and the dynamic random access memory includes DDR (Double Data Rate Synchronous Dynamic Random Access Memory).
[0073] There are many types of hibernation technologies, one of which is STR (suspend to RAM). In STR mode, the system saves the data of the current running status in the memory, and then shuts down non-core devices to reduce energy consumption. Because the memory requires power to maintain data, this mode still consumes a certain amount of power, but it is far less than the normal working state. When resuming, the system can quickly read data from the memory and restore to the state before standby. Before entering STR, the system will prepare data and synchronize the file system to ensure data integrity and consistency. After that, the device drivers will enter the low power state in turn, and finally reach the low power state of the entire system.
[0074] Based on the sleep instruction, the first system stores the data of the first system in the memory and executes the sleep process, that is, the first system sleeps in the STR mode to reduce the power consumption of the first system.
[0075] In an exemplary embodiment, the sleep state of the first system includes that the first system has entered a STR sleep mode.
[0076] Step 103: The second system performs a sleep operation based on the sleep instruction, obtains a sleep state of the second system, and sends the sleep state of the second system to the first system.
[0077] In some embodiments, the second system performs a sleep operation based on a sleep instruction, including: the second system stores data of the second system in a memory based on the sleep instruction and executes a kernel sleep process.
[0078] Based on the sleep instruction, the second system stores the data of the second system in the memory and executes the kernel sleep process, that is, the second system sleeps in the STR mode to reduce the power consumption of the second system.
[0079] In the exemplary embodiment, taking the second system including the QNX system as an example, the specific process of the second system performing the sleep operation based on the sleep instruction is introduced as follows:
[0080] After receiving the sleep instruction, the sleep processing (STR) module in the driver layer of the QNX system sets the power state to the power driver module in the driver layer. The power driver module notifies each driver device in the driver layer to go through the suspend process. Each driver device executes the suspend function. The power driver module notifies the sleep processing module in the driver layer to save the data of the QNX system and stores the data of the QNX system to the specified location of the memory.
[0081] In the exemplary embodiment, taking the second system including the Android system as an example, the specific process of the second system performing the sleep operation based on the sleep instruction is introduced. Figure 2 As shown, the process of executing the sleep operation based on the sleep instruction of the Android system mainly includes:
[0082] Step 201 , after receiving the sleep instruction, the sleep processing (STR) module in the driver layer of the Android system injects a power key event (power key event) and sends the power key event to the application framework (Framework) layer of the Android system.
[0083] In an exemplary embodiment, step 201 may include: after receiving the sleep instruction, the sleep processing module in the driver layer of the Android system injects a power key event into the input module in the driver layer of the Android system, and the input module in the driver layer of the Android system reports the power key event to the input event dispatcher (InputDispatcher) module in the application framework layer of the Android system.
[0084] Step 202, the application framework layer of the Android system processes the power button event, calls the goToSleep interface to start the sleep process, and sends a sleep broadcast to the application (APP) layer of the Android system.
[0085] In an exemplary embodiment, step 202 may include: the input event scheduling module in the application framework layer of the Android system reports the power key event to the phone window management (PhoneWindowManager) module in the application framework layer, the phone window management module in the application framework layer processes the power key event, calls the power management service (PowerManagerService) module in the application framework layer to enter the sleep interface to go through the sleep process, and does some sleep preparation work in the power management service module, such as sending a sleep broadcast "android.intent.action.GOTO_STR" to the application layer of the Android system, the application layer listens to the sleep broadcast and performs sleep operations, such as releasing wakelock (keeping the wakeup lock), turning off the screen, etc.
[0086] Step 203: the system layer of the Android system stores the data of the Android system in the memory, and the kernel of the Android system starts to sleep.
[0087] In an exemplary embodiment, step 203 may include: the power management service module in the application framework layer sets the power state to the power driver module in the driver layer of the Android system, the power driver module notifies each driver device in the driver layer to go through the suspend process, each driver device executes the suspend function, the power driver module notifies the sleep processing module in the driver layer to save the data of the Android system, and the system layer of the Android system stores the data of the Android system in a preset location in the memory (for example: / sys / power / state).
[0088] At present, the sleep solution in the car is mainly implemented based on the Linux kernel sleep. The sleep process based on the Linux kernel usually includes the following process: MCU sends the sleep command to VHAL (virtual hardware abstraction layer), VHAL processes and sends the sleep command to the application framework layer, the application framework layer sleeps the upper application and releases the wakelock (keeps the wake lock), the system layer obtains the state of the wakelock and writes mem (Memory) to / sys / power / state, and finally enters the Linux kernel sleep process.
[0089] In the present application, the MCU sends a sleep instruction to the VHAL (virtual hardware abstraction layer). After processing, the VHAL does not directly send the sleep instruction to the application framework layer. Instead, the VHAL sends the sleep instruction to the first system through inter-core communication. The first system sends the sleep instruction to the second system, and the second system performs a sleep operation based on the sleep instruction.
[0090] In some other embodiments, the second system performs a sleep operation based on the sleep instruction, including:
[0091] The second system stores the data of the second system in the memory based on the sleep instruction and executes the kernel sleep process;
[0092] When the second system determines that the kernel has not entered the sleep mode, the second system returns to the step of executing the kernel sleep process until the second system determines that the kernel has entered the sleep mode.
[0093] In an exemplary embodiment, taking the second system including the Android system as an example, the data of the second system is stored in the memory, and the kernel hibernation process is executed, including: calling the initAutosuspend interface at the system layer of the Android system, and determining whether there is a wakelock (maintaining the wake-up lock); if there is a wakelock, returning to execute the step of calling the initAutosuspend interface at the system layer of the Android system; if there is no wakelock, storing the data of the Android system at a preset location in the memory, and starting the kernel hibernation process.
[0094] At present, once the kernel sleep process fails, STR will be directly exited, resulting in the second system being unable to enter low power mode. However, in this application, when the second system determines that the kernel has not entered sleep mode, it returns to the step of executing the kernel sleep process until the second system determines that the kernel has entered sleep mode. If the kernel sleep process fails, the cause of the failure will be avoided and the kernel sleep process will be re-executed. This state will not affect the upper-layer application. In actual use, the customer will not perceive whether it has failed, and the actual state observed is that the STR has been successfully entered.
[0095] When the Android kernel is in sleep mode, it often fails to sleep due to various abnormal wakeup sources. If the kernel fails to sleep, some devices will still consume power, resulting in poor implementation of low power consumption. Therefore, based on the sleep process of the Android system, the system layer process is optimized. When the Android kernel fails to sleep, multiple retries are used to perform multiple sleep processing on the Linux kernel, which effectively reduces the probability of sleep wakeup failure and improves the user experience.
[0096] In the case of kernel hibernation failure, the kernel hibernation process is repeated, which effectively reduces the probability of hibernation failure.
[0097] In an exemplary embodiment, after the kernel sleep process is performed, it is determined whether the kernel enters the sleep (STR) mode. If it is determined that the kernel enters the sleep mode, the process ends. If it is determined that the kernel does not enter the sleep mode, it returns to execute the step of determining whether there is a wakelock (maintaining the wake-up lock).
[0098] In some embodiments, determining that the core has not entered the sleep mode may include reading a sleep exception status.
[0099] In an exemplary embodiment, the sleep state of the second system includes that the second system has entered a STR sleep mode.
[0100] Step 104: the first system writes the sleep status of the first system and the second system into the real-time clock register.
[0101] In some embodiments, after step 104, the control method of the system on chip further includes: the MCU reads the sleep status of each of the first system and the second system from the real-time clock register.
[0102] In an exemplary embodiment, Figure 3 As shown, the first system includes an RTOS system, and at least one second system includes an Android system and a QNX system. The process of the dormancy method of the system on chip mainly includes:
[0103] Step 301, the MCU sends a sleep instruction to the VHAL of the Android system.
[0104] Step 302: The VHAL of the Android system sends a sleep instruction to the RTOS system through inter-core communication.
[0105] Step 303: The RTOS system executes a sleep operation based on the sleep instruction to obtain a sleep state of the RTOS system.
[0106] Step 304: The RTOS system sends a sleep instruction to the Android system and the QNX system through inter-core communication, and receives the sleep status feedback from the Android system and the QNX system.
[0107] Step 305 , the RTOS system writes the sleep states of the RTOS system, the Android system, and the QNX system into the real-time clock register in the RTOS system.
[0108] Step 306: The MCU reads the sleep status of the RTOS system, the Android system, and the QNX system from the real-time clock register.
[0109] In some embodiments, there is only one core in the first system;
[0110] Step 101 includes: a core in a first system receives a sleep instruction, and sends the sleep instruction to a second system;
[0111] Step 102 includes: the core in the first system performs a sleep operation based on the sleep instruction to obtain a sleep state of the core in the first system;
[0112] Step 104 includes: the core in the first system writes the sleep states of the core in the first system and the second system into a real-time clock register.
[0113] In some other embodiments, the first system further includes a first core and a second core;
[0114] Step 101 includes: the first core receives a sleep instruction, and sends the sleep instruction to the second system;
[0115] Step 102 includes: the first core sends a sleep instruction to the second core; the first core performs a sleep operation based on the sleep instruction to obtain a sleep state of the first core; the second core performs a sleep operation based on the sleep instruction to obtain a sleep state of the second core, and sends the sleep state of the second core to the first core;
[0116] Step 104 includes: the first core writes the sleep states of the first core, the second core, and the second system into a real-time clock register.
[0117] The first system also includes a first core and a second core, and the first system includes multiple cores. The above scheme controls the sleep process of each system in the entire on-chip system in the first core of the first system as a whole, and realizes the sleep processing of multiple systems and the sleep processing of multiple cores in the first system. Moreover, each system in the on-chip system independently processes its own sleep logic, and each system in the on-chip system is independent of each other, which is convenient for independent maintenance of each system in the on-chip system. The first core and the second core in the first system independently process their own sleep logic, and each core in the first system is independent of each other, which is convenient for independent maintenance of each core in the first system. In addition, the sleep status of the first core, the second core and the second system is written into the real-time clock register, so that the sleep status of each system in the on-chip system and each core in the first system can be known through the real-time clock register.
[0118] In some embodiments, the first core includes a security core and the second core includes an initial boot core.
[0119] In an exemplary embodiment, the safety core refers to the Safety core, which is used to perform watchdog operations and message callbacks of the entire system on chip (for example, the first core receives the sleep state of the second core and the sleep state of the second system). The initial startup core refers to the Secure core, which is used to boot the entire system on chip and is the first core started in the system on chip.
[0120] In some embodiments, the first system further includes a first core, a second core, and a third core;
[0121] Step 101 includes: the first core receives a sleep instruction, and sends the sleep instruction to the second system;
[0122] Step 102 includes: the first core sends a sleep instruction to the second core and the third core; the first core performs a sleep operation based on the sleep instruction to obtain a sleep state of the first core; the second core performs a sleep operation based on the sleep instruction to obtain a sleep state of the second core, and sends the sleep state of the second core to the first core; the third core performs a sleep operation based on the sleep instruction to obtain a sleep state of the third core, and sends the sleep state of the third core to the first core;
[0123] Step 104 includes: the first core writes the sleep states of the first core, the second core, the third core and the second system into the real-time clock register.
[0124] In some embodiments, the third core includes a screen control core.
[0125] In an exemplary embodiment, the screen control core refers to the MP core, and the MP core is used for screen control and IVM (Interactive Visual Media, interactive video media format) business logic.
[0126] In an exemplary embodiment, the first core, the second core and the third core complete information exchange through inter-core communication.
[0127] In some embodiments, the first system includes an RTOS system, the at least one second system includes an Android system and a QNX system, the first system further includes a Safety core, a Secure core, and an MP core, and the process of the hibernation method of the system on chip mainly includes:
[0128] The MCU receives the sleep command from the CAN bus, and sends the sleep command to the VHAL of the Android system. The VHAL of the Android system sends the sleep command to the Safety core of the RTOS system through inter-core communication.
[0129] After receiving the sleep command, the Safety core of the RTOS system starts a timer and then sends the sleep command to the Android system and QNX system through inter-core communication.
[0130] The RTOS system executes the sleep operation based on the sleep instruction to obtain the sleep status of the Safety core, the Secure core and the MP core in the RTOS system;
[0131] After receiving the sleep command, the sleep processing (STR) module in the driver layer of the Android system injects a power key event, and then the Android system executes the sleep process;
[0132] After receiving the sleep instruction, the sleep processing (STR) module in the driver layer of the QNX system sends a sleep signal to the specified process through the process management (proc-man) module;
[0133] During the sleep process of the Android system and the QNX system, the Safety core of the RTOS system waits for the WDT (Watch Dog Timer) message. After receiving the sleep status feedback from the Android system and the QNX system, the Safety core, the Secure core and the MP core of the RTOS system, the Android system and the QNX system are written into the real-time clock register in the RTOS system.
[0134] The PMU (Power Management Unit) of the system on chip controls the board to power off, and only retains the power of the real-time clock register and DDR (double data rate synchronous dynamic random access memory).
[0135] In some embodiments, the control method of the system on chip further includes: the first system controls other modules in the system on chip except the real-time clock register and the memory to power off.
[0136] The real-time clock register is used to store the sleep state of the first system and the second system, and is kept active. When waking up, it is also awakened by the real-time clock register, so the real-time clock register needs to be powered on. The memory is used to store the data of the first system and the second system, and the data is read from the memory when waking up, so the memory needs to be powered on. The first system controls the power-off of other modules in the system-on-chip except the real-time clock register and the memory, which can reduce the power consumption of the entire system-on-chip.
[0137] In some embodiments, Figure 4 As shown, the control method of the system on chip also includes:
[0138] Step 401: The real-time clock register obtains a wake-up instruction, and based on the wake-up instruction, changes the state values of the first system and the second system in the real-time clock register from the sleep state to the wake-up state.
[0139] In some embodiments, there are multiple implementations of obtaining the wake-up instruction from the real-time clock register, including but not limited to the following implementations:
[0140] Method 1
[0141] The MCU receives the wake-up signal from the CAN bus, pulls the wakeup pin of the on-chip system to a high level, generates a wake-up instruction, and the real-time clock register receives the wake-up instruction.
[0142] Method 2
[0143] The MCU receives the wake-up signal from the IGN (Ignition Switch) hard line, pulls the wakeup pin of the on-chip system to a high level, generates a wake-up instruction, and the real-time clock register receives the wake-up instruction.
[0144] In an exemplary embodiment, the status value in the real-time clock register includes two types, one is the default value (cold start), and the other is the sleep state. When the first system successfully sleeps and the second system successfully sleeps, the first system writes the sleep state of the first system and the second system into the real-time clock register, and the status value of the first system in the real-time clock register is updated from the default value to the sleep state, and the status value of the second system in the real-time clock register is updated from the default value to the sleep state; if the first system fails to sleep, the status value of the first system in the real-time clock register is still the default value; if the second system fails to sleep, the status value of the second system in the real-time clock register is still the default value. After the real-time clock register obtains the wake-up instruction, the status value of the sleep state in the real-time clock register will be converted to the wake-up state, and the status value of the default value remains unchanged.
[0145] In some embodiments, after the real-time clock register obtains the wake-up instruction, DIL (Digital Integrated Logic) is run and the DDR self-refresh mode is exited.
[0146] Step 402: The first system reads the wake-up status of the first system and the second system in the real-time clock register.
[0147] Step 403: The first system performs a wake-up operation based on the wake-up state of the first system.
[0148] In some embodiments, the first system performs a wake-up operation based on the wake-up state of the first system, including: the first system reads data of the first system from the memory based on the wake-up state of the first system and performs a wake-up process.
[0149] Step 404: the first system sends the wake-up status of the second system to the second system.
[0150] In some embodiments, there is only one core in the first system;
[0151] Step 402 includes: the core in the first system reads the wake-up status of the core in the first system and the second system in the real-time clock register;
[0152] Step 403 includes: the core in the first system starts the preload module in the core in the first system based on the wake-up state of the core in the first system, performs a wake-up operation and loads the core in the first system;
[0153] Step 404 includes: the core in the first system sends the wake-up state of the second system to the second system.
[0154] In some other embodiments, the first system further includes a first core and a second core;
[0155] Step 402 includes: the second core reads the wake-up status of the first core, the second core and the second system in the real-time clock register;
[0156] Step 403 includes: the second core starts the preload module in the second core based on the wake-up state of the second core, performs a wake-up operation and loads the second core; the second core performs a wake-up operation based on the wake-up state of the first core and loads the first core;
[0157] Step 404 includes: the second core sends the wake-up state of the second system to the second system.
[0158] The first system also includes a first core and a second core, and the first system includes multiple cores. The above scheme controls the wake-up process of each system in the entire on-chip system in the second core of the first system as a whole, and realizes the wake-up processing of multiple systems and the wake-up processing of multiple cores in the first system. Moreover, each system in the on-chip system independently processes its own wake-up logic, and each system in the on-chip system is independent of each other, which is convenient for independent maintenance of each system in the on-chip system. In the first system, the first core and the second core independently process their own wake-up logic, and each core in the first system is independent of each other, which is convenient for independent maintenance of each core in the first system.
[0159] In some embodiments, the first core includes a security core and the second core includes an initial boot core.
[0160] In an exemplary embodiment, the safety core refers to the Safety core, which is used to perform watchdog operations and message callbacks of the entire system on chip (for example, the first core receives the sleep state of the second core and the sleep state of the second system). The initial startup core refers to the Secure core, which is used to boot the entire system on chip and is the first core started in the system on chip.
[0161] In some embodiments, the first system further includes a first core, a second core, and a third core;
[0162] Step 402 includes: the second core reads the wake-up status of the first core, the second core, the third core and the second system in the real-time clock register;
[0163] Step 403 includes: the second core starts the preload module in the second core based on the wake-up state of the second core, performs a wake-up operation and loads the second core; the second core performs a wake-up operation based on the wake-up state of the first core and loads the first core; the second core sends the wake-up state of the third core to the third core, and the third core performs a wake-up operation based on the wake-up state of the third core;
[0164] Step 404 includes: the second core sends the wake-up state of the second system to the second system.
[0165] In some embodiments, the third core includes a screen control core.
[0166] In an exemplary embodiment, the screen control core refers to the MP core, and the MP core is used for screen control and IVM (Interactive Visual Media, interactive video media format) business logic.
[0167] In an exemplary embodiment, the first core, the second core and the third core complete information exchange through inter-core communication.
[0168] Step 405: The second system performs a wake-up operation based on the wake-up state of the second system.
[0169] The above scheme controls the wake-up process of each system in the entire SoC in the first system, and realizes the wake-up processing of multiple systems. Moreover, each system in the SoC processes its own wake-up logic independently, and each system in the SoC is independent of each other, which is convenient for independent maintenance of each system in the SoC.
[0170] In some embodiments, the second system performs a wake-up operation based on the wake-up state of the second system, including: the second system reads data of the second system from the memory based on the wake-up state of the second system and performs a wake-up process.
[0171] In the exemplary embodiment, taking the second system including the QNX system as an example, the specific process of the second system performing the wake-up operation based on the wake-up state of the second system is introduced as follows:
[0172] After the sleep processing (STR) module in the driver layer of the QNX system receives the wake-up status of the QNX system, it reads the data of the QNX system from the memory and sets the power status to the power driver module in the driver layer. The power driver module notifies each driver device in the driver layer to go through the wake-up (resume) process, and each driver device executes the wake-up (resume) function.
[0173] In the exemplary embodiment, taking the second system including the Android system as an example, the specific process of the second system performing the wake-up operation based on the wake-up state of the second system is introduced as follows:
[0174] After receiving the wake-up status of the Android system, the sleep processing (STR) module in the driver layer of the Android system reads the data of the Android system from the memory and injects the power key event into the input module in the driver layer of the Android system. The input module in the driver layer of the Android system reports the power key event to the input event dispatching (InputDispatcher) module in the application framework (Framework) layer of the Android system. The input event dispatching module in the application framework layer of the Android system reports the power key event to the phone window management (PhoneWindowManager) module in the application framework layer. The phone window management module in the application framework layer processes the power key event and calls the wake-up interface of the power management service (PowerManagerService) module in the application framework layer to perform the wake-up process. In the wake-up process of the power management service module, a wake-up broadcast is sent to the application (APP) layer of the Android system. In the wake-up process of the power management service module, the power state is set to the power driver module in the driver layer of the Android system. The power driver module notifies each driver device in the driver layer to perform the wake-up process, and each driver device executes the wake-up function.
[0175] In an exemplary embodiment, Figure 5 As shown, the first system includes an RTOS system, and at least one second system includes an Android system and a QNX system. The process of the wake-up method of the system on chip mainly includes:
[0176] Step 501, the MCU receives a wake-up signal from the CAN bus, pulls the wake-up pin of the system on chip to a high level, generates a wake-up instruction, and the real-time clock register in the RTOS system receives the wake-up instruction.
[0177] Step 502 : Based on the wake-up instruction, the real-time clock register converts the state values of the RTOS system, the Android system, and the QNX system in the real-time clock register from the sleep state to the wake-up state.
[0178] Step 503: The RTOS system reads the wake-up status of the RTOS system, the Android system, and the QNX system in the real-time clock register.
[0179] Step 504: The RTOS system performs a wake-up operation based on the wake-up state of the RTOS system.
[0180] Step 505 : The RTOS system sends the wake-up status of the Android system to the Android system, and the RTOS system sends the wake-up status of the QNX system to the QNX system.
[0181] Step 506: The MCU synchronizes the power state to the Android system, and the Android system performs a wake-up operation based on the wake-up state of the Android system.
[0182] Step 507: The QNX system performs a wake-up operation based on the wake-up state of the QNX system.
[0183] In some embodiments, the first system includes an RTOS system, the at least one second system includes an Android system and a QNX system, the first system further includes a Safety core, a Secure core, and an MP core, and the process of the wake-up method of the system on chip mainly includes:
[0184] The MCU receives the wake-up signal from the CAN bus or IGN hard line, pulls the wakeup pin of the on-chip system to a high level, generates a wake-up command, and the real-time clock register receives the wake-up command;
[0185] After the real-time clock register receives the wake-up command, it runs DIL and exits the DDR self-refresh mode;
[0186] Based on the wake-up instruction, the real-time clock register converts the state values of the Safety core, Secure core and MP core in the RTOS system, the Android system and the QNX system from the sleep state to the wake-up state;
[0187] The Secure core in the RTOS system reads the wake-up status of the Safety core, Secure core, and MP core in the real-time clock register as well as the Android system and QNX system;
[0188] The Secure core in the RTOS system starts the preloaded module in the Secure core based on the wake-up state of the Secure core, performs a wake-up operation, and loads the Secure core; the Secure core performs a wake-up operation based on the wake-up state of the Safety core and loads the Safety core;
[0189] The Secure core in the RTOS system sends the wake-up status of the MP core to the MP core, sends the wake-up status of the Android system to the Android system, and sends the wake-up status of the QNX system to the QNX system;
[0190] The MP core performs a wake-up operation based on the wake-up state of the MP core;
[0191] The Android system performs a wake-up operation based on the wake-up state of the Android system;
[0192] The QNX system performs a wake-up operation based on the wake-up state of the QNX system.
[0193] In an exemplary embodiment, if the first system fails to hibernate, the state value of the first system in the real-time clock register is still the default value; if the second system fails to hibernate, the state value of the second system in the real-time clock register is still the default value. After the real-time clock register obtains the wake-up instruction, the state value of the real-time clock register that is in the hibernation state will be converted to the wake-up state, and the state value that is the default value will remain unchanged. If the state value of the first system in the real-time clock register received by the first system is the default value, the first system performs a restart operation without reading the data of the first system from the memory. If the state value of the second system in the real-time clock register received by the second system is the default value, the second system performs a restart operation without reading the data of the second system from the memory.
[0194] In summary, in the present application, the system on chip includes a first system and at least one second system, the first system includes a real-time clock register, the first system receives a sleep instruction, and sends the sleep instruction to the second system, the first system performs a sleep operation based on the sleep instruction, obtains the sleep state of the first system, the second system performs a sleep operation based on the sleep instruction, obtains the sleep state of the second system, and sends the sleep state of the second system to the first system, and the first system writes the sleep state of the first system and the second system into the real-time clock register. The above scheme generally controls the sleep process of each system in the entire system on chip in the first system, and realizes the sleep processing of multiple systems. Moreover, each system in the system on chip independently processes its own sleep logic, and each system in the system on chip is independent of each other, which is convenient for independent maintenance of each system in the system on chip. In addition, the sleep state of each of the first system and the second system is written into the real-time clock register, so that the sleep state of each system in the system on chip can be known through the real-time clock register.
[0195] Exemplary Systems
[0196] Accordingly, the embodiment of the present application also provides a system on chip, such as Figure 6 As shown, the system on chip includes a first system 601 and at least one second system 602, and the first system 601 includes a real-time clock register 6011;
[0197] The system on chip is configured to implement the control method of the system on chip provided by any of the above embodiments of the present application.
[0198] Figure 6 Only one second system 602 is shown. As required, the number of the second systems 602 may be one or at least two, and the present application does not impose any limitation thereto.
[0199] The system on chip provided in this embodiment belongs to the same application concept as the control method of the system on chip provided in the above embodiment of this application, and can execute the control method of the system on chip provided in any of the above embodiments of this application, and has the corresponding functional modules and beneficial effects of the control method of the system on chip. For the technical details not fully described in this embodiment, please refer to the specific processing content of the control method of the system on chip provided in the above embodiment of this application, which will not be repeated here.
[0200] In some embodiments, the system on chip is configured to implement the following steps:
[0201] The first system receives the sleep instruction, and sends the sleep instruction to the second system;
[0202] The first system performs a sleep operation based on the sleep instruction to obtain a sleep state of the first system;
[0203] The second system performs a sleep operation based on the sleep instruction, obtains a sleep state of the second system, and sends the sleep state of the second system to the first system;
[0204] The first system writes the sleep status of each of the first system and the second system into the real-time clock register.
[0205] The above scheme controls the sleep process of each system in the entire on-chip system in the first system, and realizes the sleep processing of multiple systems. Moreover, each system in the on-chip system independently processes its own sleep logic, and each system in the on-chip system is independent of each other, which is convenient for independent maintenance of each system in the on-chip system. In addition, the sleep status of each of the first system and the second system is written into the real-time clock register, which is convenient for knowing the sleep status of each system in the on-chip system through the real-time clock register.
[0206] Optionally, the second system performs a sleep operation based on the sleep instruction, including:
[0207] The second system stores the data of the second system in the memory based on the sleep instruction and executes the kernel sleep process;
[0208] When the second system determines that the kernel has not entered the sleep mode, the second system returns to the step of executing the kernel sleep process until the second system determines that the kernel has entered the sleep mode.
[0209] Optionally, the system on chip is further configured to implement the following steps:
[0210] The first system controls other modules in the system on chip except the real-time clock register and the memory to power off.
[0211] Alternatively, if Figure 7 As shown, the first system 601 includes a real-time clock register 6011, a first core 6012 and a second core 6013;
[0212] The first system receives the sleep instruction and sends the sleep instruction to the second system, including:
[0213] The first core receives a sleep instruction, and sends the sleep instruction to the second system;
[0214] The first system performs a sleep operation based on the sleep instruction to obtain a sleep state of the first system, including:
[0215] The first core sends the sleep instruction to the second core; the first core performs a sleep operation based on the sleep instruction to obtain a sleep state of the first core; the second core performs a sleep operation based on the sleep instruction to obtain a sleep state of the second core, and sends the sleep state of the second core to the first core;
[0216] The first system writes the sleep states of the first system and the second system into the real-time clock register, including:
[0217] The first core writes the sleep states of the first core, the second core, and the second system into the real-time clock register.
[0218] Alternatively, if Figure 8 As shown, the first system 601 includes a real-time clock register 6011, a first core 6012, a second core 6013 and a third core 6014;
[0219] The first system receives the sleep instruction and sends the sleep instruction to the second system, including:
[0220] The first core receives a sleep instruction, and sends the sleep instruction to the second system;
[0221] The first system performs a sleep operation based on the sleep instruction to obtain a sleep state of the first system, including:
[0222] The first core sends the sleep instruction to the second core and the third core; the first core performs a sleep operation based on the sleep instruction to obtain a sleep state of the first core; the second core performs a sleep operation based on the sleep instruction to obtain a sleep state of the second core, and sends the sleep state of the second core to the first core; the third core performs a sleep operation based on the sleep instruction to obtain a sleep state of the third core, and sends the sleep state of the third core to the first core;
[0223] The first system writes the sleep states of the first system and the second system into the real-time clock register, including:
[0224] The first core writes the sleep states of the first core, the second core, the third core, and the second system into the real-time clock register.
[0225] Optionally, the system on chip is further configured to implement the following steps:
[0226] The real-time clock register obtains a wake-up instruction, and based on the wake-up instruction, converts the state values of the first system and the second system in the real-time clock register from a sleep state to a wake-up state;
[0227] The first system reads the wake-up status of the first system and the second system in the real-time clock register;
[0228] The first system performs a wake-up operation based on the wake-up state of the first system;
[0229] The first system sends the wake-up status of the second system to the second system;
[0230] The second system performs a wake-up operation based on a wake-up state of the second system.
[0231] The above scheme controls the wake-up process of each system in the entire SoC in the first system, and realizes the wake-up processing of multiple systems. Moreover, each system in the SoC processes its own wake-up logic independently, and each system in the SoC is independent of each other, which is convenient for independent maintenance of each system in the SoC.
[0232] Optionally, the first system includes a real-time clock register, a first core and a second core;
[0233] The first system reads the wake-up status of the first system and the second system in the real-time clock register, including:
[0234] The second core reads the wake-up status of the first core, the second core and the second system in the real-time clock register;
[0235] The first system performs a wake-up operation based on the wake-up state of the first system, including:
[0236] The second core starts the preload module in the second core based on the wake-up state of the second core, performs a wake-up operation and loads the second core; the second core performs a wake-up operation based on the wake-up state of the first core and loads the first core;
[0237] The first system sends the wake-up state of the second system to the second system, including:
[0238] The second core sends the wake-up status of the second system to the second system.
[0239] Optionally, the first system includes a real-time clock register, a first core, a second core and a third core;
[0240] The first system reads the wake-up status of the first system and the second system in the real-time clock register, including:
[0241] The second core reads the wake-up status of the first core, the second core, the third core and the second system in the real-time clock register;
[0242] The first system performs a wake-up operation based on the wake-up state of the first system, including:
[0243] The second core starts the preload module in the second core based on the wake-up state of the second core, performs a wake-up operation and loads the second core; the second core performs a wake-up operation based on the wake-up state of the first core and loads the first core; the second core sends the wake-up state of the third core to the third core, and the third core performs a wake-up operation based on the wake-up state of the third core;
[0244] The first system sends the wake-up state of the second system to the second system, including:
[0245] The second core sends the wake-up status of the second system to the second system.
[0246] Optionally, the first system includes a real-time operating system, and the at least one second system includes an Android system and / or a microkernel real-time operating system.
[0247] In an exemplary embodiment, a real-time operating system (RTOS) is an operating system that ensures that a specific function is completed within a certain time limit.
[0248] In an exemplary embodiment, Android is a free and open source mobile operating system based on the Linux kernel, which is an open source computer operating system kernel.
[0249] In an exemplary embodiment, the at least one second system may further include other Linux kernel-based operating systems besides the Android system.
[0250] In an exemplary embodiment, the microkernel real-time operating system may be a QNX system, which is a Unix-like real-time operating system. Unix is a powerful multi-user, multi-tasking operating system that supports a variety of processor architectures. According to the classification of operating systems, it is a time-sharing operating system. The microkernel structure of the QNX system is a significant feature that distinguishes it from other operating systems. In the microkernel structure of the QNX system, the kernel is independently located in a protected address space, and the driver, network protocol and application are in the program space.
[0251] In an exemplary embodiment, at least one second system may include an Android system, may include a microkernel real-time operating system, may include an Android system and a microkernel real-time operating system, and may also include other operating systems.
[0252] Optionally, the first core includes a security core, and the second core includes an initial startup core.
[0253] In an exemplary embodiment, the safety core refers to the Safety core, which is used to perform watchdog operations and message callbacks of the entire system on chip (for example, the first core receives the sleep state of the second core and the sleep state of the second system). The initial startup core refers to the Secure core, which is used to boot the entire system on chip and is the first core started in the system on chip.
[0254] In some embodiments, the third core includes a screen control core.
[0255] In an exemplary embodiment, the screen control core refers to the MP core, and the MP core is used for screen control and IVM (Interactive Visual Media, interactive video media format) business logic.
[0256] Exemplary Computer Devices
[0257] Correspondingly, an embodiment of the present application further provides a computer device, which includes the system on chip provided by any of the above embodiments of the present application.
[0258] For technical details not fully described in this embodiment, please refer to the specific processing content of the on-chip system provided in the above embodiments of the present application, and will not be repeated here.
[0259] In some embodiments, the computer device may be a computer, a laptop, a smart terminal, a handheld terminal, a wearable device, or any other device. It may also be a vehicle-mounted computer device or system.
[0260] In some embodiments, the computer device further includes an MCU (Micro Control Unit) and a memory.
[0261] In an exemplary embodiment, the memory may include a random access memory (RAM), a read-only memory (ROM), or a flash memory (Flash Memory). The random access memory includes a static random access memory (SRAM) and a dynamic random access memory (DRAM), and the dynamic random access memory includes DDR (Double Data Rate Synchronous Dynamic Random Access Memory).
[0262] For the aforementioned method embodiments, for the sake of simplicity, they are all described as a series of action combinations, but those skilled in the art should be aware that the present application is not limited by the order of the actions described, because according to the present application, some steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the present application.
[0263] It should be noted that each embodiment in this specification is described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other. For system embodiments, since they are basically similar to method embodiments, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.
[0264] The steps in the methods of each embodiment of the present application can be adjusted in order, combined and deleted according to actual needs, and the technical features recorded in each embodiment can be replaced or combined.
[0265] The modules and sub-modules in the systems and devices in the embodiments of the present application can be merged, divided and deleted according to actual needs.
[0266] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the system embodiments described above are only schematic. For example, the division of modules or sub-modules is only a logical function division. There may be other division methods in actual implementation, such as multiple sub-modules or modules can be combined or integrated into another module, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or modules, which can be electrical, mechanical or other forms.
[0267] The modules or submodules described as separate components may or may not be physically separated, and the components of the modules or submodules may or may not be physical modules or submodules, that is, they may be located in one place, or they may be distributed on multiple network modules or submodules. Some or all of the modules or submodules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
[0268] In addition, each functional module or submodule in each embodiment of the present application may be integrated into one processing module, or each module or submodule may exist physically separately, or two or more modules or submodules may be integrated into one module. The above-mentioned integrated modules or submodules may be implemented in the form of hardware or in the form of software functional modules or submodules.
[0269] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.
[0270] The steps of the method or algorithm described in conjunction with the embodiments disclosed herein may be implemented directly by hardware, software units executed by a processor, or a combination of the two. The software units may be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
[0271] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.
[0272] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. A control method of a system on chip, characterized in that: Applied to a system on chip, the system on chip includes a first system and at least one second system, the first system includes a real-time clock register, and the method includes: The first system receives the sleep instruction, and sends the sleep instruction to the second system; The first system performs a sleep operation based on the sleep instruction to obtain a sleep state of the first system; The second system performs a sleep operation based on the sleep instruction, obtains a sleep state of the second system, and sends the sleep state of the second system to the first system; The first system writes the sleep status of each of the first system and the second system into the real-time clock register.
2. The method according to claim 1, characterized in that The second system performs a sleep operation based on the sleep instruction, including: The second system stores the data of the second system in the memory based on the sleep instruction and executes the kernel sleep process; When the second system determines that the kernel has not entered the sleep mode, the second system returns to the step of executing the kernel sleep process until the second system determines that the kernel has entered the sleep mode.
3. The method according to claim 2, characterized in that The method further comprises: The first system controls other modules in the system on chip except the real-time clock register and the memory to power off.
4. The method according to claim 1, characterized in that: The first system also includes a first core and a second core; The first system receives the sleep instruction and sends the sleep instruction to the second system, including: The first core receives a sleep instruction, and sends the sleep instruction to the second system; The first system performs a sleep operation based on the sleep instruction to obtain a sleep state of the first system, including: The first core sends the sleep instruction to the second core; the first core performs a sleep operation based on the sleep instruction to obtain a sleep state of the first core; the second core performs a sleep operation based on the sleep instruction to obtain a sleep state of the second core, and sends the sleep state of the second core to the first core; The first system writes the sleep states of the first system and the second system into the real-time clock register, including: The first core writes the sleep states of the first core, the second core, and the second system into the real-time clock register.
5. The method according to claim 1, characterized in that The method further comprises: The real-time clock register obtains a wake-up instruction, and based on the wake-up instruction, converts the state values of the first system and the second system in the real-time clock register from a sleep state to a wake-up state; The first system reads the wake-up status of the first system and the second system in the real-time clock register; The first system performs a wake-up operation based on the wake-up state of the first system; The first system sends the wake-up status of the second system to the second system; The second system performs a wake-up operation based on a wake-up state of the second system.
6. The method according to claim 5, characterized in that The first system also includes a first core and a second core; The first system reads the wake-up status of the first system and the second system in the real-time clock register, including: The second core reads the wake-up status of the first core, the second core and the second system in the real-time clock register; The first system performs a wake-up operation based on the wake-up state of the first system, including: The second core starts the preload module in the second core based on the wake-up state of the second core, performs a wake-up operation and loads the second core; the second core performs a wake-up operation based on the wake-up state of the first core and loads the first core; The first system sends the wake-up state of the second system to the second system, including: The second core sends the wake-up status of the second system to the second system.
7. The method according to any one of claims 1 to 6, characterized in that: The first system includes a real-time operating system, and the at least one second system includes an Android system and / or a microkernel real-time operating system.
8. The method according to claim 4 or 6, characterized in that: The first core includes a security core, and the second core includes an initial startup core.
9. A system on chip, characterized in that: comprising a first system and at least one second system, wherein the first system comprises a real-time clock register; The system on chip is configured to implement the system on chip control method according to any one of claims 1 to 8.
10. A computer device, characterized in that: Comprising the system on chip as claimed in claim 9.