Control circuit and server

Abstract

The invention discloses a control circuit and a server in the technical field of computers. According to the control circuit provided by the invention, the complex programmable logic devices connected with the substrate management controller and the functions of the complex programmable logic devices can be automatically checked, and firmware re-burning can be automatically carried out on the complex programmable logic devices with abnormal functions, so that the diagnosis and detection efficiency of the complex programmable logic devices is improved; each CPLD in the server can be quickly recovered, the operation and maintenance cost of the server is reduced, and normal operation of the server can be guaranteed.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a control circuit and a server. Background Art

[0002] At present, BMC (Baseboard Management Controller) is the main control chip for out-of-band management of the mainboard in the server. It can obtain the timing monitoring error of the mainboard CPLD (Complex Programmable Logic Device), the hard disk position information and hard disk lighting information of the backplane CPLD, the fan speed information and fan control information of the fan CPLD, etc. When any CPLD is initialized abnormally and cannot respond to BMC instructions, the operation and maintenance personnel need to replace the corresponding CPLD, re-burn the CPLD firmware, and re-power on the machine to restore the function of the corresponding CPLD, which increases the server operation and maintenance costs and affects the normal operation of the server.

[0003] Therefore, how to quickly restore each CPLD in the server is a problem that those skilled in the art need to solve. Summary of the invention

[0004] In view of this, the purpose of this application is to provide a control circuit and a server to quickly restore each CPLD in the server. The specific scheme is as follows:

[0005] In a first aspect, the present application provides a control circuit, comprising: a baseboard management controller, an enable controller connected to the baseboard management controller, and at least one complex programmable logic device; the enable controller is also connected to the at least one complex programmable logic device;

[0006] Wherein, the enabling controller is used to set a corresponding device sequence for the at least one complex programmable logic device according to a signal value of a pin connected to the at least one complex programmable logic device;

[0007] The baseboard management controller is used to read the target device sequence from the enabling controller; if the target device sequence is recorded in a preset device list, and the device code corresponding to the target device sequence in the preset relationship table is inconsistent with the target device code read from the corresponding target complex programmable logic device, then re-burn the firmware FW of the target complex programmable logic device when confirming that the value of the abnormal flag bit corresponding to the target complex programmable logic device is the first target value; after the burning is completed, send a restart instruction to the enabling controller, and set the value of the abnormal flag bit to the second target value;

[0008] The enabling controller is used to restart the target complex programmable logic device according to the restart instruction.

[0009] Optionally, the control circuit further comprises: a power switch connected between the enabling controller and the at least one complex programmable logic device;

[0010] Correspondingly, the enabling controller is used to control the power switch to be opened according to the restart instruction so as to power off the target complex programmable logic device; and control the power switch to be closed so as to power on the target complex programmable logic device.

[0011] Optionally, the baseboard management controller is used to determine the target complex programmable logic device having a binding relationship with the target device sequence in the preset device list, and read the target device code from the target complex programmable logic device.

[0012] Optionally, the baseboard management controller generates a notification message indicating that the target complex programmable logic device is correct if the device code corresponding to the target device sequence in the preset relationship table is consistent with the target device code, and sets the value of the exception flag to the first target value.

[0013] Optionally, the baseboard management controller is used to determine that the complex programmable logic device corresponding to the target device sequence is not a local device if the target device sequence is not recorded in the preset device list.

[0014] Optionally, the baseboard management controller is used to detect whether the target device sequence is recorded in the preset device list after the target complex programmable logic device is restarted;

[0015] When the target device sequence is recorded in the preset device list, detecting whether the device code corresponding to the target device sequence in the preset relationship table is consistent with the target device code read from the target complex programmable logic device;

[0016] If they are consistent, a notification message is generated indicating that the target complex programmable logic device is correct, and the abnormal flag bit is set to the first target value;

[0017] If they are inconsistent, the value of the abnormal flag bit corresponding to the target complex programmable logic device is detected; when the value of the abnormal flag bit is the second target value, a notification message of the target complex programmable logic device error is generated.

[0018] Optionally, the baseboard management controller is used to control the initialization of the target complex programmable logic device after the target complex programmable logic device is restarted;

[0019] After the initialization is completed, device status flag information is read from the target complex programmable logic device;

[0020] If the device status flag information is abnormal and this is the first initialization operation after power-on, controlling the target complex programmable logic device to be reinitialized;

[0021] After reinitialization, executing the step of reading device status flag information from the target complex programmable logic device, and detecting whether the newly read device status flag information is abnormal;

[0022] If the device status flag information is abnormal and this is not the first initialization operation after power-on, a notification message of the target complex programmable logic device error is generated;

[0023] If the device status flag information is normal, a notification message indicating that the target complex programmable logic device is correct is generated, and the abnormal flag bit is set to the first target value.

[0024] Optionally, the baseboard management controller, the enabling controller and the at least one complex programmable logic device communicate via the same type of bus.

[0025] In a second aspect, the present application provides a server, comprising: a control circuit as described in any one of the above items.

[0026] Optionally, the server further includes: a host processor; the host processor is connected to a baseboard management controller in the control circuit.

[0027] It can be seen from the above scheme that the present application provides a control circuit, including: a baseboard management controller, an enable controller connected to the baseboard management controller, and at least one complex programmable logic device; the enable controller is also connected to the at least one complex programmable logic device; wherein the enable controller is used to set a corresponding device sequence for the at least one complex programmable logic device according to a signal value of a pin connected to the at least one complex programmable logic device; the baseboard management controller is used to read a target device sequence from the enable controller; if the target device sequence is recorded in a preset device list, and the device code corresponding to the target device sequence in a preset relationship table is inconsistent with the target device code read from the corresponding target complex programmable logic device, then when it is confirmed that the value of the abnormal flag bit corresponding to the target complex programmable logic device is the first target value, the firmware of the target complex programmable logic device is re-burned; after the burning is completed, a restart instruction is sent to the enable controller, and the value of the abnormal flag bit is set to the second target value; the enable controller is used to restart the target complex programmable logic device according to the restart instruction.

[0028] It can be seen that the control circuit provided by the present application can automatically check the preset device list in the server, and automatically compare the complex programmable logic devices recorded in the preset device list with the consistency and function of the complex programmable logic devices actually connected to the baseboard management controller. When the complex programmable logic device functions abnormally, it is confirmed that the abnormal flag bit corresponding to the corresponding complex programmable logic device is the first target value, and the firmware of the complex programmable logic device is re-burned; after the burning is completed, a restart instruction is sent to the enabling controller, so that the enabling controller restarts the complex programmable logic device according to the restart instruction to try to restore the function of the corresponding complex programmable logic device. This solution can automatically check the complex programmable logic devices and their functions connected to the baseboard management controller, and can also automatically re-burn the firmware of the complex programmable logic devices with abnormal functions, thereby improving the diagnosis and detection efficiency of the complex programmable logic devices, being able to quickly restore each CPLD in the server, reducing the server operation and maintenance costs, and ensuring the normal operation of the server.

[0029] Correspondingly, a server provided by the present application also has the above-mentioned technical effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0031] Figure 1 A schematic diagram of a control circuit disclosed in this application;

[0032] Figure 2 This is another schematic diagram of a control circuit disclosed in this application;

[0033] Figure 3 A flow chart of a control method disclosed in this application;

[0034] Figure 4 A schematic diagram of an electronic device disclosed in this application;

[0035] Figure 5 A server structure diagram provided for this application;

[0036] Figure 6 A terminal structure diagram provided for this application. DETAILED DESCRIPTION

[0037] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other examples obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0038] At present, BMC, as the main control chip for out-of-band management of the motherboard in the server, can obtain the timing monitoring error of the motherboard CPLD, the hard disk presence information and hard disk lighting information of the backplane CPLD, the fan speed information and fan control information of the fan CPLD, etc. When any CPLD is initialized abnormally and cannot respond to BMC instructions, the operation and maintenance personnel need to replace the corresponding CPLD, re-burn the CPLD firmware, and re-power on the machine to restore the function of the corresponding CPLD, which increases the server operation and maintenance costs and affects the normal operation of the server. To this end, the present application provides a control circuit that can quickly restore each CPLD in the server.

[0039] See also Figure 1 As shown, an embodiment of the present application discloses a control circuit, including: a baseboard management controller, an enable controller connected to the baseboard management controller, and at least one complex programmable logic device; the enable controller is also connected to at least one complex programmable logic device.

[0040] The enabling controller is used to set a corresponding device sequence for at least one complex programmable logic device according to a signal value of a pin connected to the at least one complex programmable logic device.

[0041] A baseboard management controller is used to read a target device sequence from an enabling controller; if the target device sequence is recorded in a preset device list, and the device code corresponding to the target device sequence in a preset relationship table is inconsistent with the target device code read from the corresponding target complex programmable logic device, then after confirming that the value of the abnormal flag bit corresponding to the target complex programmable logic device is the first target value, the firmware of the target complex programmable logic device is re-burned; after the burning is completed, a restart instruction is sent to the enabling controller, and the value of the abnormal flag bit is set to the second target value.

[0042] The enabling controller is used to restart the target complex programmable logic device according to the restart instruction.

[0043] In this embodiment, the control circuit can automatically check the preset device list in the server, and automatically compare the complex programmable logic devices recorded in the preset device list with the complex programmable logic devices actually connected to the baseboard management controller for consistency and whether the functions are abnormal. When the complex programmable logic device functions abnormally, the firmware of the complex programmable logic device is re-burned when it is confirmed that the abnormal flag bit corresponding to the corresponding complex programmable logic device is the first target value; after the burning is completed, a restart instruction is sent to the enabling controller, so that the enabling controller restarts the complex programmable logic device according to the restart instruction to try to restore the function of the corresponding complex programmable logic device. This solution can automatically check the complex programmable logic devices and their functions connected to the baseboard management controller, and can also automatically re-burn the firmware of the complex programmable logic devices with abnormal functions, thereby improving the diagnosis and detection efficiency of the complex programmable logic devices, being able to quickly restore each CPLD in the server, reducing the server operation and maintenance costs, and ensuring the normal operation of the server.

[0044] In one example, the control circuit also includes: a power switch connected between the enable controller and at least one complex programmable logic device; accordingly, the enable controller is used to control the power switch to be disconnected according to a restart instruction to power off the target complex programmable logic device; and control the power switch to be closed to power on the target complex programmable logic device.

[0045] In one example, a baseboard management controller is used to determine a target complex programmable logic device having a binding relationship with a target device sequence in a preset device list, and read the target device code from the target complex programmable logic device.

[0046] In one example, a baseboard management controller generates a notification message indicating that a target complex programmable logic device is correct if the device code corresponding to the target device sequence in a preset relationship table is consistent with the target device code, and sets the value of the abnormal flag bit to the first target value.

[0047] In one example, a baseboard management controller is used to determine that a complex programmable logic device corresponding to the target device sequence is not a local device if the target device sequence is not recorded in a preset device list.

[0048] In one example, a baseboard management controller is used to detect whether a target device sequence is recorded in a preset device list after a target complex programmable logic device is restarted; when the target device sequence is recorded in the preset device list, detect whether a device code corresponding to the target device sequence in a preset relationship table is consistent with a target device code read from the target complex programmable logic device; if they are consistent, generate a notification message indicating that the target complex programmable logic device is correct, and set an abnormal flag bit to a first target value; if they are inconsistent, detect the value of an abnormal flag bit corresponding to the target complex programmable logic device; when the abnormal flag bit is set to a second target value, generate a notification message indicating that the target complex programmable logic device is wrong.

[0049] In one example, a baseboard management controller is used to control the initialization of a target complex programmable logic device after the target complex programmable logic device is restarted; after the initialization is completed, the device status flag information is read from the target complex programmable logic device; if the device status flag information is abnormal and this is the first initialization operation after power-on, the target complex programmable logic device is controlled to be reinitialized; after reinitialization, the step of reading the device status flag information from the target complex programmable logic device is executed, and whether the newly read device status flag information is abnormal is detected; if the device status flag information is abnormal and this is not the first initialization operation after power-on, a notification message of a target complex programmable logic device error is generated; if the device status flag information is normal, a notification message of a target complex programmable logic device being correct is generated, and the abnormal flag bit is set to the first target value.

[0050] In one example, the baseboard management controller, the enabling controller, and the at least one complex programmable logic device communicate via the same type of bus (eg, I2C).

[0051] In one embodiment, Figure 2As shown in the figure, an additional I / O expander is attached to the I2C bus for communication between BMC and CPLD as an enabling controller. The chip has 8 IOs, of which 0-6 are set as input signals. The unique Board ID (i.e., device sequence) is set through the pull-up and pull-down resistors of different boards, which corresponds to the board PN (Part number, corresponding device code) burned into the CPLD. The corresponding relationship table is recorded in the storage of BMC. The Board ID set by the pull-up and pull-down resistors is highly stable and will not change due to problems such as firmware burning. Therefore, it is used as a comparison standard for judging PN abnormalities caused by firmware problems inside the CPLD. BMC can obtain the Board ID through I2C and compare it with the board PN inside the CPLD; the 8th bit of the chip is set as an output signal, which is connected to a Power Switch. BMC controls the power on and off of the CPLD by controlling the opening and closing of the Power Switch, so that the CPLD reloads the firmware to achieve reinitialization. The above operations are all completed by BMC through the same I2C bus, and there is no need to add BMC IO.

[0052] like Figure 3 As shown in the figure, the process from power-on to CPLD fault diagnosis and recovery is as follows:

[0053] 1. Turn on the server.

[0054] 2. BMC reads bits 0-6 of the IO expander through I2C to determine the Board ID of the connected backplane. BMC reads the CPLD register to obtain the CPLD status information to determine whether the CPLD is normal. BMC reads the register in the CPLD to obtain the board PN information.

[0055] 3. BMC first confirms whether the read Board ID is in the Board ID list preset in BMC. If it is not in the list, it means that the connected board is not a board that can be installed on this model, and BMC will report an error log.

[0056] 4. If the Board ID is in the preset list, it means the board is correct. Then compare the Board ID with the board PN obtained from the CPLD to see if they match. If they do not match, it means that there is an error in the CPLD firmware burning file of the board.

[0057] 5. After the BMC detects a firmware problem, check whether the firmware problem flag bit recorded in the BMC is set. The flag bit is set to mark whether the corresponding CPLD detects a firmware problem for the first time after initialization. If it is not set, it means that the problem is encountered for the first time. Then use the CPLD burning file pre-stored in the BMC to re-burn the CPLD firmware. After the burning is completed, turn off and then turn on the Power Switch that controls the CPLD power supply to re-power on the CPLD for initialization.

[0058] 6. Then the BMC will re-check the board PN and Board ID. If they do not match, the firmware problem flag is set, indicating that this is not the first time the problem has occurred. Re-burning the firmware cannot solve the problem, and the BMC will report the firmware error log.

[0059] 7. If the backplane PN and Board ID match after re-burning or the first power-on, the BMC determines whether the initialization is normal based on the CPLD status register read. If the status is abnormal, check whether the initialization problem flag bit recorded internally is set. Whether the flag bit is set is used to mark whether the corresponding CPLD has been restarted. If it is not set, it means that the problem is encountered for the first time. In this case, the Power Switch that controls the CPLD power supply is turned off and then turned on to re-power on the CPLD for initialization.

[0060] 8. Then the BMC will re-check the CPLD status. If it is abnormal, because the above two flags are set at this time, it means that re-burning and re-initialization cannot solve the problem, and the BMC will report the CPLD initialization error log.

[0061] 9. If the CPLD status is normal after power-on initialization or the first startup, the BMC will reset the firmware problem flag and the initialization problem flag, the diagnosis and recovery process ends, and the machine enters normal working state.

[0062] It can be seen that in this example, the CPLD is powered by the Power Switch, and the BMC can control its shutdown and startup through I2C to reinitialize the CPLD; the board sets the Board ID, and the BMC can obtain it through I2C and compare it with the board PN burned into the CPLD; the BMC determines whether the board is used incorrectly by reading the Board ID, determines whether the CPLD is burned incorrectly by comparing the Board ID with the board PN, and determines whether the CPLD is initialized incorrectly by obtaining the CPLD status. This can effectively solve the following problems: incorrect use of boards equipped with CPLD, incorrect burning of board CPLD firmware, and incorrect initialization of board CPLD.

[0063] A server provided in an embodiment of the present application is introduced below. The server described below can be referenced to other embodiments described in this document.

[0064] An embodiment of the present application discloses a server, including: the control circuit described in any of the above embodiments.

[0065] In one example, the server further includes: a host processor; the host processor is connected to a baseboard management controller in the control circuit.

[0066] In this embodiment, the control circuit includes: a baseboard management controller, an enable controller connected to the baseboard management controller, and at least one complex programmable logic device; the enable controller is further connected to the at least one complex programmable logic device.

[0067] The enabling controller is used to set a corresponding device sequence for at least one complex programmable logic device according to a signal value of a pin connected to the at least one complex programmable logic device.

[0068] A baseboard management controller is used to read a target device sequence from an enabling controller; if the target device sequence is recorded in a preset device list, and the device code corresponding to the target device sequence in a preset relationship table is inconsistent with the target device code read from the corresponding target complex programmable logic device, then after confirming that the value of the abnormal flag bit corresponding to the target complex programmable logic device is the first target value, the firmware of the target complex programmable logic device is re-burned; after the burning is completed, a restart instruction is sent to the enabling controller, and the value of the abnormal flag bit is set to the second target value.

[0069] The enabling controller is used to restart the target complex programmable logic device according to the restart instruction.

[0070] In one example, the control circuit also includes: a power switch connected between the enable controller and at least one complex programmable logic device; accordingly, the enable controller is used to control the power switch to be disconnected according to a restart instruction to power off the target complex programmable logic device; and control the power switch to be closed to power on the target complex programmable logic device.

[0071] In one example, a baseboard management controller is used to determine a target complex programmable logic device having a binding relationship with a target device sequence in a preset device list, and read the target device code from the target complex programmable logic device.

[0072] In one example, a baseboard management controller generates a notification message indicating that a target complex programmable logic device is correct if the device code corresponding to the target device sequence in a preset relationship table is consistent with the target device code, and sets the value of the abnormal flag bit to the first target value.

[0073] In one example, a baseboard management controller is used to determine that a complex programmable logic device corresponding to the target device sequence is not a local device if the target device sequence is not recorded in a preset device list.

[0074] In one example, a baseboard management controller is used to detect whether a target device sequence is recorded in a preset device list after the target complex programmable logic device is restarted;

[0075] When the target device sequence is recorded in the preset device list, it is detected whether the device code corresponding to the target device sequence in the preset relationship table is consistent with the target device code read from the target complex programmable logic device; if they are consistent, a notification message indicating that the target complex programmable logic device is correct is generated, and the value of the abnormal flag bit is set to the first target value; if they are inconsistent, the value of the abnormal flag bit corresponding to the target complex programmable logic device is detected; when the value of the abnormal flag bit is set to the second target value, a notification message indicating that the target complex programmable logic device is wrong is generated.

[0076] In one example, a baseboard management controller is used to control the initialization of a target complex programmable logic device after the target complex programmable logic device is restarted; after the initialization is completed, the device status flag information is read from the target complex programmable logic device; if the device status flag information is abnormal and this is the first initialization operation after power-on, the target complex programmable logic device is controlled to be reinitialized; after reinitialization, the step of reading the device status flag information from the target complex programmable logic device is executed, and whether the newly read device status flag information is abnormal is detected; if the device status flag information is abnormal and this is not the first initialization operation after power-on, a notification message of a target complex programmable logic device error is generated; if the device status flag information is normal, a notification message of a target complex programmable logic device being correct is generated, and the abnormal flag bit is set to the first target value.

[0077] In one example, the baseboard management controller, the enabling controller, and the at least one complex programmable logic device communicate via the same type of bus.

[0078] Among them, for more specific working processes of each module and unit in this embodiment, reference can be made to the corresponding contents disclosed in the aforementioned embodiments, which will not be repeated here.

[0079] It can be seen that this embodiment provides a server that can automatically check the complex programmable logic devices and their functions connected to the baseboard management controller, and can also automatically re-burn the firmware of the complex programmable logic devices with abnormal functions, thereby improving the diagnosis and detection efficiency of the complex programmable logic devices, and can quickly restore each CPLD in the server, thereby reducing the server operation and maintenance costs and ensuring the normal operation of the server.

[0080] An electronic device provided by an embodiment of the present application is introduced below, and the electronic device described below can be cross-referenced with other embodiments described herein. The electronic device can be the baseboard management controller, enabling controller, and complex programmable logic device described above.

[0081] See also Figure 4 As shown, the embodiment of the present application discloses an electronic device, including:

[0082] Memory 401, used for storing computer programs;

[0083] The processor 402 is used to execute the computer program to implement the method disclosed in any of the above embodiments.

[0084] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: according to the signal value of the pin connected to the at least one complex programmable logic device, a corresponding device sequence is set for the at least one complex programmable logic device.

[0085] In this embodiment, when the processor executes the computer program stored in the memory, the following steps can be specifically implemented: reading the target device sequence from the enabling controller; if the target device sequence is recorded in the preset device list, and the device code corresponding to the target device sequence in the preset relationship table is inconsistent with the target device code read from the corresponding target complex programmable logic device, then re-burning the firmware of the target complex programmable logic device after confirming that the value of the abnormal flag bit corresponding to the target complex programmable logic device is the first target value; after the burning is completed, sending a restart instruction to the enabling controller, and setting the value of the abnormal flag bit to the second target value.

[0086] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: restarting the target complex programmable logic device according to the restart instruction.

[0087] In this embodiment, when the processor executes the computer program stored in the memory, the following steps can be specifically implemented: controlling the power switch to be disconnected according to the restart instruction to power off the target complex programmable logic device; controlling the power switch to be closed to power on the target complex programmable logic device.

[0088] In this embodiment, when the processor executes the computer program stored in the memory, the following steps can be specifically implemented: determining a target complex programmable logic device having a binding relationship with a target device sequence in a preset device list, and reading the target device code from the target complex programmable logic device.

[0089] In this embodiment, when the processor executes the computer program stored in the memory, the following steps can be specifically implemented: if the device code corresponding to the target device sequence in the preset relationship table is consistent with the target device code, a notification message indicating that the target complex programmable logic device is correct is generated, and the exception flag bit is set to the first target value.

[0090] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: if the target device sequence is not recorded in the preset device list, it is determined that the complex programmable logic device corresponding to the target device sequence is not a local device.

[0091] In this embodiment, when the processor executes the computer program stored in the memory, the following steps can be specifically implemented: detecting whether the target device sequence is recorded in the preset device list; when the target device sequence is recorded in the preset device list, detecting whether the device code corresponding to the target device sequence in the preset relationship table is consistent with the target device code read from the target complex programmable logic device; if they are consistent, generating a notification message indicating that the target complex programmable logic device is correct, and setting the value of the abnormal flag bit to the first target value; if they are inconsistent, detecting the value of the abnormal flag bit corresponding to the target complex programmable logic device; when the value of the abnormal flag bit is the second target value, generating a notification message indicating that the target complex programmable logic device is wrong.

[0092] In this embodiment, when the processor executes the computer program stored in the memory, the following steps can be specifically implemented: after the target complex programmable logic device is restarted, the target complex programmable logic device is controlled to be initialized; after the initialization is completed, the device status flag information is read from the target complex programmable logic device; if the device status flag information is abnormal and this is the first initialization operation after power-on, the target complex programmable logic device is controlled to be reinitialized; after reinitialization, the step of reading the device status flag information from the target complex programmable logic device is executed, and whether the newly read device status flag information is abnormal is detected; if the device status flag information is abnormal and this is not the first initialization operation after power-on, a notification message of the target complex programmable logic device error is generated; if the device status flag information is normal, a notification message of the target complex programmable logic device being correct is generated, and the abnormal flag bit is set to the first target value.

[0093] Further, the present application also provides the following embodiments: Figure 5 The server shown in Figure 6 Terminal shown. Figure 5 and Figure 6 All of them are structural diagrams of electronic devices according to an exemplary embodiment, and the contents in the diagrams cannot be regarded as any limitation on the scope of use of the present application.

[0094] Figure 5 A schematic diagram of the structure of a server provided in an embodiment of the present application. The server may specifically include: at least one processor, at least one memory, a power supply, a communication interface, an input / output interface, and a communication bus. The memory is used to store a computer program, and the computer program is loaded and executed by the processor to implement the relevant steps in the control disclosed in any of the aforementioned embodiments.

[0095] In this embodiment, the power supply is used to provide working voltage for each hardware device on the server; the communication interface can create a data transmission channel between the server and external devices, and the communication protocol it follows is any communication protocol that can be applied to the technical solution of the present application, and is not specifically limited here; the input and output interface is used to obtain external input data or output data to the outside world, and its specific interface type can be selected according to specific application needs and is not specifically limited here.

[0096] In addition, the memory as a carrier for resource storage can be a read-only memory, random access memory, disk or CD, etc. The resources stored thereon include operating system, computer programs and data, etc. The storage method can be temporary storage or permanent storage.

[0097] The operating system is used to manage and control the hardware devices and computer programs on the server to realize the operation and processing of the data in the memory by the processor, and it can be Windows Server, Netware, Unix, Linux, etc. In addition to computer programs that can be used to complete the control method disclosed in any of the above embodiments, the computer program can also further include computer programs that can be used to complete other specific tasks. In addition to data such as application update information, the data can also include data such as application developer information.

[0098] Figure 6 A schematic diagram of the structure of a terminal provided in an embodiment of the present application, the terminal may specifically include but is not limited to a smart phone, a tablet computer, a laptop computer or a desktop computer, etc.

[0099] Generally, the terminal in this embodiment includes: a processor and a memory.

[0100] Among them, the processor may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor may be implemented in at least one hardware form of DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), and PLA (Programmable Logic Array). The processor may also include a main processor and a coprocessor. The main processor is a processor for processing data in the awake state, also known as a CPU (Central Processing Unit); the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, the processor may be integrated with a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor may also include an AI (Artificial Intelligence) processor, which is used to process computing operations related to machine learning.

[0101] The memory may include one or more computer non-volatile storage media, which may be non-transitory. The memory may also include high-speed random access memory, and non-volatile memory, such as one or more disk storage devices, flash memory storage devices. In this embodiment, the memory is at least used to store the following computer program, wherein, after the computer program is loaded and executed by the processor, it can implement the relevant steps in the control method performed by the terminal side disclosed in any of the aforementioned embodiments. In addition, the resources stored in the memory may also include an operating system and data, etc., and the storage method may be temporary storage or permanent storage. Among them, the operating system may include Windows, Unix, Linux, etc. The data may include, but is not limited to, update information of the application.

[0102] In some embodiments, the terminal may also include a display screen, an input and output interface, a communication interface, a sensor, a power supply, and a communication bus.

[0103] Those skilled in the art will understand that Figure 6 The structure shown in the figure does not constitute a limitation on the terminal, and may include more or fewer components than those shown in the figure.

[0104] A non-volatile storage medium provided in an embodiment of the present application is introduced below. The non-volatile storage medium described below can be cross-referenced with other embodiments described herein.

[0105] A non-volatile storage medium for storing a computer program, wherein the computer program, when executed by a processor, implements the control method disclosed in the above-mentioned embodiment. The non-volatile storage medium is a computer-readable non-volatile storage medium, which, as a carrier for storing resources, may be a read-only memory, a random access memory, a disk or an optical disk, etc. The resources stored thereon include an operating system, a computer program and data, etc., and the storage method may be temporary storage or permanent storage.

[0106] A computer program product provided in an embodiment of the present application is introduced below. The computer program product described below can be cross-referenced with other embodiments described in this document.

[0107] A computer program product comprises a computer program / instruction, which implements the steps of the aforementioned disclosed control method when executed by a processor.

[0108] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0109] The steps of the method or algorithm described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of non-volatile storage medium known in the art.

[0110] Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A control circuit, characterized in that: include: A baseboard management controller, an enable controller connected to the baseboard management controller, and at least one complex programmable logic device; the enable controller is also connected to the at least one complex programmable logic device; Wherein, the enabling controller is used to set a corresponding device sequence for the at least one complex programmable logic device according to a signal value of a pin connected to the at least one complex programmable logic device; The baseboard management controller is used to read the target device sequence from the enabling controller; if the target device sequence is recorded in a preset device list, and the device code corresponding to the target device sequence in the preset relationship table is inconsistent with the target device code read from the corresponding target complex programmable logic device, then re-burn the firmware of the target complex programmable logic device when confirming that the value of the abnormal flag bit corresponding to the target complex programmable logic device is the first target value; after the burning is completed, send a restart instruction to the enabling controller, and set the value of the abnormal flag bit to the second target value; The enabling controller is used to restart the target complex programmable logic device according to the restart instruction.

2. The control circuit according to claim 1, characterized in that: The control circuit further comprises: a power switch connected between the enabling controller and the at least one complex programmable logic device; Correspondingly, the enabling controller is used to control the power switch to be opened according to the restart instruction so as to power off the target complex programmable logic device; and control the power switch to be closed so as to power on the target complex programmable logic device.

3. The control circuit according to claim 1, characterized in that: The baseboard management controller is used to determine the target complex programmable logic device that has a binding relationship with the target device sequence in the preset device list, and read the target device code from the target complex programmable logic device.

4. The control circuit according to claim 1, characterized in that: The baseboard management controller is used to generate a notification message that the target complex programmable logic device is correct when the device code corresponding to the target device sequence in the preset relationship table is consistent with the target device code, and sets the value of the abnormal flag bit to the first target value.

5. The control circuit according to claim 1, characterized in that: The baseboard management controller is used to determine that the complex programmable logic device corresponding to the target device sequence is not a local device if the target device sequence is not recorded in the preset device list.

6. The control circuit according to claim 1, characterized in that: The baseboard management controller is used to detect whether the target device sequence is recorded in the preset device list after the target complex programmable logic device is restarted; When the target device sequence is recorded in the preset device list, detecting whether the device code corresponding to the target device sequence in the preset relationship table is consistent with the target device code read from the target complex programmable logic device; If they are consistent, a notification message is generated indicating that the target complex programmable logic device is correct, and the abnormal flag bit is set to the first target value; If they are inconsistent, the value of the abnormal flag bit corresponding to the target complex programmable logic device is detected; when the value of the abnormal flag bit is the second target value, a notification message of the target complex programmable logic device error is generated.

7. The control circuit according to any one of claims 1 to 6, characterized in that: The baseboard management controller is used to control the initialization of the target complex programmable logic device after the target complex programmable logic device is restarted; After the initialization is completed, device status flag information is read from the target complex programmable logic device; If the device status flag information is abnormal and this is the first initialization operation after power-on, controlling the target complex programmable logic device to be reinitialized; After reinitialization, executing the step of reading device status flag information from the target complex programmable logic device, and detecting whether the newly read device status flag information is abnormal; If the device status flag information is abnormal and this is not the first initialization operation after power-on, a notification message of the target complex programmable logic device error is generated; If the device status flag information is normal, a notification message indicating that the target complex programmable logic device is correct is generated, and the abnormal flag bit is set to the first target value.

8. The control circuit according to any one of claims 1 to 6, characterized in that: The baseboard management controller, the enabling controller and the at least one complex programmable logic device communicate via the same type of bus.

9. A server, characterized in that: include: A control circuit as claimed in any one of claims 1 to 8.

10. The server according to claim 9, characterized in that The server further comprises: a host processor; the host processor is connected to a baseboard management controller in the control circuit.

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