Cached timecode marking method

Abstract

The invention discloses a time code marking method for a high-speed cache, and relates to the technical field of high-speed cache. The method comprises: using a sampling clock and a write counter to count sampled data; processing a second pulse of an external time service into a synchronous signal of the sampling clock as a latch mark and a reset mark of an output value of the write counter; detecting the second pulse under the sampling clock, and reset the write counter by the second pulse, wherein the counter corresponding to the data D0 bit is 0, the latch value generated by the first second pulse is not written into a first-in-first-out queue, and the latch values ​​of subsequent second pulses are written into the first-in-first-out queue; reading the sampled data from the cache at the rate of the sampling clock for restoration, and when the first data is read out, the count value is assumed to be 0, and then before the latch value is loaded into a comparator, one data is read out under each sampling clock, and the read counter is incremented by 1; the invention can restore accurate time code marking.

Description

Technical Field

[0001] The present invention relates to the technical field of high-speed cache, and in particular to a time code marking method of high-speed cache. Background Art

[0002] Each high-speed acquisition system has higher and higher requirements for the accuracy of timing. In system design, high-speed data streams often enter the high-speed CACHE cache area. If the tag relationship between the sampled data and the timing timestamp is not processed, the relationship between the sampled data and the timing in the CACHE will be destroyed. In the face of how to accurately ensure the accuracy of the data time code in the high-speed CACHE, usually, if the sampled data stream rate is not high and the high-speed cache area has sufficient capacity and throughput, the sampled data stream and timestamp can all be written as write data to the high-speed CACHE, accurately latching the data and timestamp, but this method has high requirements for hardware and performance costs. Especially when the sampling rate is high, the requirements for the capacity and throughput performance of the CACHE are also increased, and the equipment cost and implementation difficulty are correspondingly increased. Summary of the invention

[0003] In order to solve the problems existing in the prior art, the purpose of the present invention is to provide a high-speed cache time code marking method. The present invention utilizes timing second pulses and a small amount of circuit resources to achieve accurate restoration of the time code of high-speed sampled data streams through CACHE without improving the CACHE throughput performance.

[0004] To achieve the above object, the technical solution adopted by the present invention is: a time code marking method for high-speed cache, comprising the following steps:

[0005] Step 1: Use the sampling clock and the write counter WCNT to count the sampled data as a time code mark;

[0006] Step 2: Process the asynchronous second pulse of the external timing into the synchronization signal of the sampling clock as the latch flag and clear flag of the output value of the write counter WCNT;

[0007] Step 3, detect the second pulse under the sampling clock as the condition for starting to write data into the cache CAHCHE; clear the write counter by the second pulse, the counter corresponding to the data D0 bit is 0, the latch value generated by the first second pulse is not written into the first-in first-out queue FIFO, and the latch value of the subsequent second pulse is written into the first-in first-out queue FIFO; when the latch value of the next second pulse of 0 arrives, latch the write counter value, and clear the write counter WCNT at the same time, and write the latched counter value into the first-in first-out queue FIFO;

[0008] Step 4, the read counter RCNT uses the sampling clock to read data, and reads the sampled data from the cache at the rate of the sampling clock to restore. When the first data is read out, its count value is defaulted to 0. After that, one data is read out at each sampling clock before the latch value is loaded into the comparator. The read counter RCNT increases by 1 until the next latch value of 0 for the second pulse arrives, and the same operation is performed.

[0009] As a further improvement of the present invention, in step 3, the write performance rate of the write counter WCNT of the cache CAHCHE is greater than the sampling data rate.

[0010] As a further improvement of the present invention, in step 4, the principle of reading data by the read counter RCNT is that the first-in first-out queue FIFO is read only if it is not empty.

[0011] As a further improvement of the present invention, in the comparator of step 4, the latched count value is read from the first-in-first-out queue FIFO, loaded into the comparator, and RCNT is compared with the latched value. When the two are equal, the read counter RCNT is cleared and the comparator no longer works until the next latched value is read from the first-in-first-out queue FIFO and loaded into the comparator.

[0012] As a further improvement of the present invention, TF is assumed to be the delay from the first second pulse to the first data read, and T0 is the delay from the second pulse to the completion of loading of the read side latch, then TF and T0 must satisfy: T0<1 second-TF, which is used to avoid the read side RCNT count value being greater than the latch value and the latch value has not yet been loaded into the comparator.

[0013] The beneficial effects of the present invention are:

[0014] The present invention has low requirements on the hardware performance of CACHE and uses very few circuit resources. High-speed sampling data passes through CACHE to restore accurate time code marks. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a principle flow chart of an embodiment of the present invention;

[0016] Figure 2 Schematic diagram of the comparator loading latch value in an embodiment of the present invention. DETAILED DESCRIPTION

[0017] The embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0018] Example

[0019] like Figure 1 As shown, a high-speed cache time code marking method includes:

[0020] In a high-speed sampling system, each sampling clock generates a sample of data. The sampling clock is used to count the sampled data as a time code mark.

[0021] The second pulse is the external timing of the system. The sampling clock is used to process the asynchronous second pulse into the synchronization signal of the sampling clock. It is the latch flag of the output value of the write counter WCNT and also serves as the clear flag of the write counter WCNT.

[0022] Under the sampling clock, the second pulse flag is detected as the condition for data to start writing into the cache CAHCHE. At this time, since the second pulse clears the write counter WCNT, the counter corresponding to the data D0 bit is 0. The latched write counter value generated by the first second pulse F is not written into the first-in first-out queue FIFO, and the subsequent second pulse latched write counter values ​​must be written into the FIFO.

[0023] Each sampling clock generates a sampling data. The write performance rate of the cache write side must be greater than the sampling data rate, otherwise data loss will occur, resulting in inaccurate timestamps.

[0024] The read side of CAHE also uses the sampling clock to read data, and restores the sampled data read from CACHE at the rate of the sampling clock to ensure that the data rate on both the read and write sides is balanced.

[0025] For example Figure 1 As shown in the figure, since the write counter is cleared by the second pulse, the counter value of the first data written must be zero. The read side also sets a counter under the sampling clock. When the first data is read out, its count value is 0 by default. After that, before the latch value is loaded into the comparator, one data is read out under each clock, and the read counter increases by 1.

[0026] When the next second pulse 0 arrives, the write counter value is latched and the write counter is cleared. The latched counter CNT0 value is written into the FIFO. The read side of the FIFO is read if it is not empty. CNT0 is read and loaded into the comparator to compare CNT0 with the running read counter. When the read counter reaches CNT0, the read side counter is cleared for one beat, and subsequent read operations continue to increment each read counter by 1. Until the next latched count value arrives, the same operation is performed again.

[0027] In the comparator, when the read counter RCNT reaches the latch value read out by the FIFO, the comparator will no longer work until the latch value of the next second pulse is loaded into the comparator.

[0028] This completes the accurate restoration of the timing counter mark of the data after it passes through the CACHE.

[0029] In this embodiment, when the next second pulse 0 generates a latch counter, the delay until the latch value is read from the FIFO and loaded into the comparator must be relatively small. Otherwise, when the count value on the read side is greater than the latch value, the latch value has not yet been loaded into the comparator, resulting in incorrect timestamp marking.

[0030] like Figure 2 As shown, let TF be the delay from the first second pulse to the first data read out. T0 is the delay from the second pulse to the completion of loading the read side latch. Then T0<1 second-TF. If this condition is met, it can be ensured that the read side count value is not greater than the latch value and the latch value has not yet loaded the comparator.

[0031] The above-mentioned embodiments only express the specific implementation of the present invention, and the description thereof is relatively specific and detailed, but it cannot be understood as limiting the scope of the present invention. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, which all belong to the protection scope of the present invention.

Claims

1. A cache time code marking method, characterized in that: The following steps are involved: Step 1: Use the sampling clock and the write counter WCNT to count the sampled data as a time code mark; Step 2: Process the asynchronous second pulse of the external timing into the synchronization signal of the sampling clock as the latch flag and clear flag of the output value of the write counter WCNT; Step 3, detect the second pulse under the sampling clock as the condition for starting to write data into the cache CAHCHE; clear the write counter by the second pulse, the counter corresponding to the data D0 bit is 0, the latch value generated by the first second pulse is not written into the first-in first-out queue FIFO, and the latch value of the subsequent second pulse is written into the first-in first-out queue FIFO; When the next second pulse with a latch value of 0 arrives, the write counter value is latched, and the write counter WCNT is cleared at the same time, and the latched counter value is written into the first-in first-out queue FIFO; Step 4, the read counter RCNT uses the sampling clock to read data, and reads the sampled data from the cache at the rate of the sampling clock to restore. When the first data is read out, its count value is defaulted to 0. After that, one data is read out at each sampling clock before the latch value is loaded into the comparator. The read counter RCNT increases by 1 until the next latch value of 0 for the second pulse arrives, and the same operation is performed.

2. The cache time code marking method according to claim 1, characterized in that: In step 3, the write performance rate of the write counter WCNT of the cache CAHCHE is greater than the sampled data rate.

3. The time code marking method of cache according to claim 1, characterized in that: In step 4, the reading counter RCNT reads data in accordance with the principle that the first-in first-out queue FIFO is read only when it is not empty.

4. The cache time code marking method according to claim 1, characterized in that: In the comparator of step 4, the latched count value is read from the first-in first-out queue FIFO, loaded into the comparator, and RCNT is compared with the latched value. When the two are equal, the read counter RCNT is cleared and the comparator no longer works until the next latched value is read from the first-in first-out queue FIFO and loaded into the comparator.

5. The time code marking method of cache according to claim 4, characterized in that: Assume TF is the delay from the first second pulse to the first data read, and T0 is the delay from the second pulse to the completion of loading the read side latch. Then TF and T0 must satisfy: T0<1 second-TF, which is used to prevent the read side RCNT count value from being greater than the latch value and the latch value has not yet been loaded into the comparator.

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