Method for transmitting PCIe data in real time by multi-core processor

Abstract

The invention discloses a method for transmitting PCIe data in real time by a multi-core processor, which adopts a bare computer / RTOS application module to continuously poll a flag bit of PCIe DMA (Direct Memory Access), and compared with the prior art of passively responding to PCIe DMA interruption, the continuous polling actively initiated by the bare computer / RTOS application module can identify the transmission state of the PCIe DMA more quickly, more real-timely and more stably, so that the real-time transmission of the PCIe DMA is realized. The time interval for initiating PCIe DMA data carrying each time is relatively stable, so that the real-time performance and stability of PCIe communication are improved, and the real-time performance of PCIe data transmission is well ensured; besides, an RPMSG framework commonly used for inter-core communication is abandoned, the Mailbox at the bottom layer is adopted to interrupt communication, the notification of the bare computer / RTOS application module can be transmitted to the main core more quickly through the Mailbox interrupt communication, and therefore it is better guaranteed that the main core reads PCIe data in time.

Description

Technical Field

[0001] The present invention relates to the field of PCIe communication technology, and in particular to a method for a multi-core processor to transmit PCIe data in real time. Background Art

[0002] PCIe (Peripheral Component Interconnect express) is a high-speed serial computer expansion bus standard used to connect a computer's motherboard and external devices. Its original name was "3GIO" and was proposed by Intel in 2001 to replace the old PCI, PCI-X and AGP bus standards.

[0003] like Figure 1 As shown in FIG. 1 , the commonly used PCIe communication framework in the market, the multi-core processor SoC includes two cores Core0 and Core1. The multi-core processor acts as a PCIe RC (Root Complex) end and communicates with an external PCIe EP (Endpoint) device for PCIe data. The multi-core processor runs an operating system (Linux, etc.). In general, the application program ( Figure 1 The Linux Application 1) in the PCIe DMA controls the PCIe DMA to move data (moving PCIe data from the EP device to the memory of the RC end, or from the memory of the RC end to the EP device), and responds to the PCIe DMA interrupt to identify whether the current PCIe data transfer is completed (receiving an interrupt indicates that the transfer is completed), and determines the next PCIe DMA data transfer operation by responding to the interrupt. However, due to the numerous tasks of the operating system, the interrupt response may not be timely, resulting in an unstable time interval for each initiation of PCIe DMA to move data, with large jitter, that is, the real-time performance of PCIe data transmission cannot be guaranteed. Summary of the invention

[0004] 1. Technical issues to be resolved

[0005] In view of the deficiencies in the prior art, the present invention provides a method for real-time transmission of PCIe data by a multi-core processor, which can solve the above technical problems.

[0006] (II) Technical solution

[0007] To solve the above technical problems, the present invention provides the following technical solution: a method for real-time transmission of PCIe data by a multi-core processor, comprising the following steps:

[0008] S1. Isolate a first core and a second core of a multi-core processor to respectively run different systems, wherein the first core is used to run a first system, and the second core is used to run a second system;

[0009] S2, the first application module of the first system controls the PCIe data access module to transmit the current PCIe data with the external PCIe EP device;

[0010] S3, the first application module continuously polls the flag bit of the PCIe data access module to determine whether the PCIe data access module has completed the transmission of the current PCIe data;

[0011] S4. If it is determined that the PCIe data access module has completed the transmission of the current PCIe data, the first application module notifies the second system to read the PCIe data transmitted this time, and the first application module controls the PCIe data access module to perform the next PCIe data transmission.

[0012] Preferably, the first system is a bare metal or RTOS.

[0013] Preferably, the second system is Linux.

[0014] Preferably, the PCIe data access module is PCIe DMA.

[0015] Preferably, step S2 specifically includes: the first application module sends a data transmission instruction to the PCIe DMA, and after receiving the data transmission instruction, the PCIe DMA further transmits the current PCIe data with the PCIe EP device.

[0016] Preferably, the multi-core processor includes a shared memory, and the transmission of PCIe data includes: transmitting the PCIe data from the PCIe EP device to the shared memory via PCIeDMA, or transmitting the PCIe data from the shared memory to the PCIeEP device via PCIeDMA.

[0017] Preferably, after step S4, the method further includes step S5: a second application module of the second system reads the PCIe data transmitted to the shared memory this time, and further, the second application module processes the PCIe data.

[0018] Preferably, in step S4, the first application module uses Mailbox to interrupt communication to notify the second system to read the PCIe data transmitted this time.

[0019] Preferably, the PCIe EP device is an FPGA acquisition card or a PCIe hard disk.

[0020] (III) Beneficial effects

[0021] Compared with the prior art, the present invention provides a method for real-time transmission of PCIe data by a multi-core processor, which has the following beneficial effects: the present invention adopts a first application module to continuously poll the flag bit of the PCIe data access module. Compared with the prior art that passively responds to the PCIe DMA interrupt, the continuous polling actively initiated by the first application module of the present invention can realize faster, more real-time and more stable identification of the transmission status of the PCIe data access module, so that the time interval for each initiation of PCIe data transfer is more stable, thereby improving the real-time and stability of PCIe communication, and better ensuring the real-time performance of PCIe data transmission. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It is a principle block diagram of PCIe communication in the prior art;

[0023] Figure 2 A principle block diagram of a method for real-time transmission of PCIe data by a multi-core processor of the present invention;

[0024] Figure 3 The present invention provides a flow chart of a method for real-time transmission of PCIe data by a multi-core processor. DETAILED DESCRIPTION

[0025] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0026] The present invention provides a method for real-time transmission of PCIe data by a multi-core processor, comprising the following steps:

[0027] S1. Isolate the first core and the second core of the multi-core processor to run different systems respectively, wherein the first core is used to run the first system and the second core is used to run the second system. It can be understood that the multi-core processor can be specifically a CPU or a SoC (System on Chip), etc. The multi-core processor includes multiple cores: Core0, Core1, etc.

[0028] Preferably, the first system is a bare metal or RTOS (bare metal / RTOS): a bare metal is also called a front-end and back-end system, and a bare metal directly runs programs in an environment without operating system (OS) support; and RTOS (Real Time OS) is a real-time operating system, which means that when external events or data are generated, it can be accepted and processed at a fast enough speed, and the results of its processing can control the production process or respond quickly to the processing system within a specified time, dispatch all available resources to complete real-time tasks, and control all real-time tasks to run in a coordinated and consistent manner. In addition, the second system can be Linux, and the second system can also be other operating systems such as Windows and Android. The second core can be used as the main core of a multi-core processor, which runs the operating system core; and the first core can be used as a slave core.

[0029] S2. The first application module of the first system controls the PCIe data access module to transmit the current PCIe data with the external PCIe EP device.

[0030] PCIe (Peripheral Component Interconnect express) is a high-speed serial computer expansion bus standard. PCIe devices can be divided into RC (Root Complex) end and EP (Endpoint) devices according to their functions and roles. The above multi-core processor is used as the RC end. Specifically, PCIe EP devices are FPGA acquisition cards or PCIe hard disks.

[0031] Preferably, the PCIe data access module is PCIe DMA (Direct Memory Access), which allows the device to directly exchange data with the system memory, and PCIe DMA is used to achieve high-speed transmission of PCIe data.

[0032] Step S2 is specifically as follows: the first application module sends a data transmission instruction to the PCIe DMA, and after receiving the data transmission instruction, the PCIe DMA further transmits the current PCIe data with the PCIe EP device.

[0033] Specifically, the multi-core processor includes a shared memory; the transmission of the above PCIe data includes: transmitting the PCIe data from the PCIe EP device to the shared memory through the PCIe DMA, or transmitting the PCIe data from the shared memory to the PCIe EP device through the PCIe DMA. The first application module is specifically a bare metal application module or an RTOS application module (i.e., a bare metal / RTOS application module).

[0034] S3. The first application module continuously polls the flag bit (TAG) of the PCIe data access module to determine whether the PCIe data access module has completed the transmission of the current PCIe data. That is, the first application module actively initiates and continuously polls the flag bit of the PCIe DMA. It can be understood that the flag bit is used to indicate the data transmission status of the PCIe DMA. When the first application module polls the flag bit of the PCIe DMA and the value thereof corresponds to the indication of the data transmission completion status, it indicates that the PCIe DMA has completed the transmission of the current PCIe data.

[0035] S4. If it is determined that the PCIe data access module has completed the transmission of the current PCIe data, the first application module immediately notifies the second system to read the PCIe data transmitted this time, and the first application module controls the PCIe data access module and the PCIe EP device to perform the next PCIe data transmission.

[0036] Preferably, in step S4, the first application module uses Mailbox to interrupt communication to notify the second system to read the PCIe data transmitted this time. Figure 1 As shown, in the prior art, after the PCIe data transmission is completed, the first application (Linux Application1) usually uses the RPMSG framework to communicate with the second application (Linux Application2) between cores to notify the second application to read the PCIe data transmitted to the memory. However, the present invention abandons the RPMSG framework commonly used for inter-core communication and instead uses the underlying Mailbox interrupt communication. Since the traditional RPMSG framework performs functional encapsulation based on Mailbox, the operation of the RPMSG framework is relatively time-consuming. Therefore, the present invention uses Mailbox interrupt communication to allow the notification of the first application module (bare metal / RTOS application module) to be transmitted to the second system of the second core more quickly. It can be understood that Mailbox is a hardware resource of the CPU and has corresponding registers that can be operated. Therefore, a simple interrupt communication function can be constructed by directly reading and writing registers, which can effectively improve the efficiency of inter-core communication.

[0037] Further, the second system includes a second application module, which is specifically a Linux application module, and the first application module uses Mailbox to interrupt communication to notify the second application module to read PCIe data. In addition, after step S4, step S5 is also included: the second application module of the second system reads the PCIe data transmitted to the shared memory this time, and further, the second application module processes the PCIe data.

[0038] It can be understood that the present invention is based on the AMP framework, by isolating a core (i.e., the first core mentioned above) from the multi-core processor to run the first system (bare metal or RTOS), and uses the core to control PCIeDMA for PCIe data transfer. AMP (Asymmetric Multi-Processing), that is, an asymmetric multi-processing architecture. An asymmetric system refers to multiple cores that run different operating systems or bare metal applications relatively independently, such as Linux+RTOS / bare metal, but require a master core to control the entire system and other slave cores. Each processor core is isolated from each other and has its own memory. It can independently run different tasks and multiple cores can communicate with each other.

[0039] In addition, preferably, in other embodiments, the above-mentioned step S3 may also include: the PCIe data access module sends a data transmission completion notification to the first application module. Further, when the first application module first polls to obtain the flag bit corresponding to the completion of the transmission of the current PCIe data or when the first application module first receives the above-mentioned data transmission completion notification, it is correspondingly judged that the PCIe data access module has completed the transmission of the current PCIe data, so as to execute the subsequent step S4. In this way, it is possible to better avoid errors occurring in the process of polling the flag bit by the first application module, resulting in misjudgment and delayed judgment of the PCIe data transmission status, thereby better ensuring the real-time nature of PCIe data transmission.

[0040] Compared with the prior art, the present invention provides a method for real-time transmission of PCIe data by a multi-core processor, which has the following beneficial effects: (1) The present invention adopts a first application module to continuously poll the flag bit of the PCIe data access module. Compared with the prior art that passively responds to the PCIe DMA interrupt, the continuous polling actively initiated by the first application module of the present invention can realize faster, more real-time and more stable identification of the transmission status of the PCIe data access module (PCIe DMA), so that the time interval for each initiation of PCIe DMA to transfer data is more stable, thereby improving the real-time and stability of PCIe communication and better ensuring the real-time performance of PCIe data transmission. (2) By isolating a core of the multi-core processor for running a bare metal or RTOS, the core is used to control PCIe DMA for PCIe data transfer, thereby realizing the independence of PCIe data transfer control. (3) By using the first application module to continuously poll the flag bit of the PCIe data access module, and the first application module corresponds to a bare metal / RTOS application module, since the bare metal / RTOS has simple functions, a short and fixed operation cycle, it can further ensure that the PCIe DMA transfer status can be identified faster, more real-time, and more stably, so as to further improve the real-time and stability of PCIe communication, that is, to further ensure the real-time of PCIe data transmission. (4) The present invention abandons the RPMSG framework commonly used for inter-core communication and instead adopts the underlying Mailbox interrupt communication. Since the traditional RPMSG framework will perform function encapsulation based on Mailbox, the operation of the RPMSG framework will be relatively time-consuming. Therefore, the present invention can allow the notification of the first application module (bare metal / RTOS application module) to be transmitted to the second core (main core) more quickly through Mailbox interrupt communication, so as to better ensure that the second system reads PCIe data in a timely manner.

[0041] It should be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0042] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A method for real-time transmission of PCIe data by a multi-core processor, characterized in that: The following steps are involved: S1. Isolate a first core and a second core of a multi-core processor to respectively run different systems, wherein the first core is used to run a first system, and the second core is used to run a second system; S2, the first application module of the first system controls the PCIe data access module to transmit the current PCIe data with the external PCIe EP device; S3, the first application module continuously polls the flag bit of the PCIe data access module to determine whether the PCIe data access module has completed the transmission of the PCIe data this time; S4. If it is determined that the PCIe data access module has completed the transmission of the PCIe data this time, the first application module notifies the second system to read the PCIe data transmitted this time, and the first application module controls the PCIe data access module to perform the next PCIe data transmission.

2. The method for real-time transmission of PCIe data by a multi-core processor according to claim 1, characterized in that: The first system is a bare metal or RTOS.

3. The method for real-time transmission of PCIe data by a multi-core processor according to claim 1, characterized in that: The second system is Linux.

4. The method for real-time transmission of PCIe data by a multi-core processor according to claim 1, characterized in that: The PCIe data access module is PCIe DMA.

5. The method for real-time transmission of PCIe data by a multi-core processor according to claim 4, characterized in that: The step S2 is specifically as follows: the first application module sends a data transmission instruction to the PCIe DMA, and after receiving the data transmission instruction, the PCIe DMA further transmits the current PCIe data with the PCIe EP device.

6. The method for real-time transmission of PCIe data by a multi-core processor according to claim 5, characterized in that: The multi-core processor includes a shared memory, and the transmission of the PCIe data includes: transmitting the PCIe data from the PCIe EP device to the shared memory through the PCIe DMA, or transmitting the PCIe data from the shared memory to the PCIe EP device through the PCIe DMA.

7. The method for real-time transmission of PCIe data by a multi-core processor according to claim 6, characterized in that: The method further includes step S5 after step S4: a second application module of the second system reads the PCIe data transmitted to the shared memory this time, and further, the second application module processes the PCIe data.

8. The method for real-time transmission of PCIe data by a multi-core processor according to claim 1, characterized in that: In the step S4, the first application module uses Mailbox to interrupt communication to notify the second system to read the PCIe data transmitted this time.

9. The method for real-time transmission of PCIe data by a multi-core processor according to claim 1, characterized in that: The PCIeEP device is an FPGA acquisition card or a PCIe hard disk.

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