Test acceptance wiring scheme generation method and device, electronic equipment and storage medium

Abstract

The invention discloses a test acceptance wiring scheme generation method and device, electronic equipment and a storage medium. The method comprises the following steps: acquiring a description file including a primary main wiring diagram and a secondary equipment description diagram of a to-be-accepted secondary system; performing graphical information analysis on the primary main wiring diagram to obtain a first type of representation vectors, and performing graphical information analysis on the secondary equipment description diagram to obtain a second type of representation vectors; taking the first type of representation vector as an imitated query feature vector and the second type of representation vector as an imitated key feature vector, and performing query analysis based on local neighborhood optimization on the imitated query feature vector and the imitated key feature vector to capture a deployment relationship between the primary equipment and the secondary equipment and obtain semantic representation of the wiring scheme; and generating a test acceptance wiring scheme diagram of the to-be-accepted secondary system based on the wiring scheme semantic representation. According to the technical scheme, it is ensured that the generated wiring scheme has comprehensiveness and reliability.

Description

Technical Field

[0001] The present invention relates to the technical field of power systems, and in particular to a method, device, electronic equipment and storage medium for generating a test acceptance wiring scheme. Background Art

[0002] With the continuous development and complexity of power systems, the construction and maintenance of substations are facing increasing challenges. In the construction and operation and maintenance of substation secondary systems, the three remote functions (remote signaling, remote measurement, and remote control) are the key links in realizing remote monitoring and control, and correct wiring is the basis for ensuring the normal operation of the three remote functions. Any slight error may lead to secondary system failure or safety hazards.

[0003] However, the traditional test acceptance wiring scheme design often relies on the experience and personal skills of engineers. Different engineers may propose different design schemes based on their own experience and habits, which makes it difficult to ensure the consistency and standardization of the design results. In addition, manually drawing wiring diagrams is a time-consuming task, especially for large substations. It takes a lot of time and effort to complete the design, and it is also very inconvenient to modify and adjust. In addition, due to the high degree of manual participation, the entire design process is prone to problems such as misreading drawings and missing wiring. Even experienced engineers can hardly avoid omissions in complicated work, and inaccurate wiring design may lead to misoperation or even damage of substation secondary equipment, which may cause serious safety accidents and threaten the lives of staff. Summary of the invention

[0004] The present invention provides a test acceptance wiring scheme generation method, device, electronic equipment and storage medium to ensure that the generated wiring scheme is comprehensive and reliable.

[0005] According to one aspect of the present invention, a method for generating a test acceptance wiring scheme is provided, the method comprising:

[0006] Obtain a description file of the secondary system to be accepted, the description file including a primary main wiring diagram and a secondary device description diagram;

[0007] Performing graphical information analysis on the primary main wiring diagram to obtain a first type of representation vector, and performing graphical information analysis on the secondary device description diagram to obtain a second type of representation vector;

[0008] Using the first type of representation vector as a pseudo-query feature vector and the second type of representation vector as a pseudo-key feature vector, performing query parsing based on local neighborhood optimization on the pseudo-query feature vector and the pseudo-key feature vector to capture the deployment relationship between the primary device and the secondary device and obtain a semantic representation of the wiring scheme;

[0009] A test acceptance wiring plan diagram of the secondary system to be accepted is generated based on the wiring plan semantic representation.

[0010] According to another aspect of the present invention, there is provided a device for generating a test acceptance wiring scheme, the device comprising:

[0011] A file acquisition module, used to acquire a description file of the secondary system to be accepted, wherein the description file includes a primary main wiring diagram and a secondary device description diagram;

[0012] A representation vector acquisition module, used for performing graphical information analysis on the primary main wiring diagram to obtain a first type of representation vector, and performing graphical information analysis on the secondary device description diagram to obtain a second type of representation vector;

[0013] A semantic representation acquisition module, configured to use the first type of representation vector as a pseudo-query feature vector and the second type of representation vector as a pseudo-key feature vector, perform query parsing based on local neighborhood optimization on the pseudo-query feature vector and the pseudo-key feature vector to capture the deployment relationship between the primary device and the secondary device and obtain a semantic representation of the wiring scheme;

[0014] A wiring plan diagram generating module is used to generate a test acceptance wiring plan diagram of the secondary system to be accepted based on the wiring plan semantic representation.

[0015] According to another aspect of the present invention, an electronic device is provided, the electronic device comprising:

[0016] at least one processor; and

[0017] a memory communicatively connected to the at least one processor; wherein,

[0018] The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can execute the test acceptance wiring scheme generation method described in any embodiment of the present invention.

[0019] According to another aspect of the present invention, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the test acceptance wiring scheme generation method described in any embodiment of the present invention when executed.

[0020] The technical solution of the embodiment of the present invention is to obtain a description file including a primary main wiring diagram and a secondary device description diagram of a secondary system to be accepted; perform graphical information analysis on the primary main wiring diagram to obtain a first type of representation vector, and perform graphical information analysis on the secondary device description diagram to obtain a second type of representation vector; use the first type of representation vector as a pseudo-query feature vector and the second type of representation vector as a pseudo-key feature vector, perform query analysis based on local neighborhood optimization on the pseudo-query feature vector and the pseudo-key feature vector to capture the deployment relationship between the primary device and the secondary device and obtain a wiring scheme semantic representation; generate a test acceptance wiring scheme diagram of the secondary system to be accepted based on the wiring scheme semantic representation, analyze the graphical information of the primary main wiring diagram and the secondary device description diagram to identify necessary features from the description file of the secondary system to be accepted, understand the functions of the primary device and the secondary device and the connection relationship between them, and thus automatically generate a wiring scheme. The technical means solves the problem that the prior art relies on the experience and personal skills of engineers, resulting in low efficiency, and is prone to inaccurate wiring schemes due to problems such as misreading drawings and missing wiring, reduces the inefficiency and errors caused by human factors, and ensures that the generated wiring scheme is comprehensive and reliable.

[0021] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0023] Figure 1a A flowchart of a method for generating a test acceptance wiring scheme provided in Embodiment 1 of the present invention;

[0024] Figure 1b A flowchart of obtaining a semantic representation of a wiring scheme provided in the first embodiment of the present invention;

[0025] Figure 2 A schematic diagram of the structure of a test acceptance wiring scheme generating device provided in the second embodiment of the present invention;

[0026] Figure 3 The present invention is a schematic diagram of the structure of an electronic device for implementing the test acceptance wiring scheme generation method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0027] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0028] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0029] Embodiment 1

[0030] Figure 1a This is a flow chart of a test acceptance wiring scheme generation method provided in the first embodiment of the present invention. This embodiment is applicable to the case of testing and accepting the three remote functions of the secondary system. The method can be executed by a test acceptance wiring scheme generation device. The test acceptance wiring scheme generation device can be implemented in the form of hardware and / or software. The test acceptance wiring scheme generation device can be configured in a server. Figure 1a As shown, the method includes:

[0031] S110, obtaining a description file of the secondary system to be accepted, the description file including a primary main wiring diagram and a secondary equipment description diagram.

[0032] Among them, the secondary system to be accepted may refer to the secondary system of the substation to be accepted. The description file can be input externally into the server that executes this method. The primary main wiring diagram can be a diagram that describes the physical connection relationship between the electrical equipment in the substation, and can show the connection status of various primary equipment in detail. The primary equipment can refer to the equipment that directly produces, transmits and distributes high-voltage electric energy. The primary equipment may include generators, transformers, circuit breakers, disconnectors, busbars, power cables and transmission lines, etc. The secondary equipment description diagram may refer to all relevant CAD (Computer Aided Design) drawings of the secondary equipment. All relevant CAD drawings of the secondary equipment may contain information such as the specific location, model specifications, interface type and connection method of the secondary equipment with other equipment. The secondary equipment may refer to equipment that measures, controls, monitors and protects the operating status of the primary equipment and system, such as relay protection devices, automatic control systems, measuring meters, etc.

[0033] S120, performing graphical information analysis on the primary main wiring diagram to obtain a first type of representation vector, and performing graphical information analysis on the secondary device description diagram to obtain a second type of representation vector.

[0034] The first type of representation vector may refer to a primary main wiring diagram graphical parsing code representation vector, and the second type of representation vector may refer to a set of secondary equipment graphical parsing code representation vectors.

[0035] In this embodiment, in order to convert the graphical primary main wiring diagram and all related CAD drawings of secondary equipment into a form that can be understood and processed by the computer, that is, to convert visual information into digital information and capture the semantic parsing features in each graphical information, in this embodiment, the machine learning and image processing algorithms based on artificial intelligence and image recognition technology can be used to parse the graphical information of the primary main wiring diagram and the secondary equipment description diagram. Exemplarily, the primary main wiring diagram and each secondary equipment CAD drawing can be parsed by a void convolutional neural network model to extract key features in the graphics, such as the connection between the primary devices and the specific location, model specifications, interface type and feature information of the secondary devices. Of course, other deep neural network models can also be used to perform graphical information parsing, which is not limited by this embodiment.

[0036] S130. Using the first type of representation vector as a pseudo-query feature vector and the second type of representation vector as a pseudo-key feature vector, performing query parsing based on local neighborhood optimization on the pseudo-query feature vector and the pseudo-key feature vector to capture the deployment relationship between the primary equipment and the secondary equipment and obtain a semantic representation of the wiring scheme.

[0037] Among them, the query parsing processing operation based on local neighborhood optimization can capture the complex relationship between primary and secondary devices through a multi-granularity attention mechanism, and extract implicit semantic information that is crucial to the wiring plan.

[0038] In this embodiment, since the graphical parsing code representation vector of the primary main wiring diagram contains basic attributes and connection feature information about the primary device, the graphical parsing code representation vector of each secondary device contains feature information such as the location, function, and implicit relationship with the primary device of each secondary device. The primary device provides a basic electrical connection framework, while the secondary device is responsible for monitoring, controlling, and protecting these primary devices. Therefore, to design and generate a reasonable wiring scheme, it is necessary to understand the correspondence between the primary device and the secondary device. Based on this, in this embodiment, the graphical parsing code representation vector of the primary main wiring diagram is used as a pseudo-query feature vector and the set of graphical parsing code representation vectors of the secondary devices is used as a set of pseudo-key feature vectors, and the set of pseudo-query feature vectors and pseudo-key feature vectors are subjected to query parsing based on local neighborhood optimization to obtain a semantic representation of the wiring scheme.

[0039] In an optional implementation, the S130 operation may include: performing embedded coding on the first type of representation vector to obtain a first type of feature vector; performing one-dimensional convolution coding on the second type of representation vector to obtain a second type of feature vector; using the first type of representation vector as a pseudo-query feature vector, the second type of representation vector and the second type of feature vector as pseudo-key feature vectors, and the first type of feature vector as a value vector, performing feature fusion processing based on query matching on the pseudo-query feature vector, the value vector and the pseudo-key feature vector to obtain a semantic representation of the wiring scheme.

[0040] The first type of feature vector may refer to a primary main wiring diagram graphical analysis value feature vector, and the second type of feature vector may refer to a secondary device graphical analysis local neighborhood semantic association feature vector.

[0041] Optionally, embedding coding is performed on the first type of representation vector to obtain the first type of feature vector. Specifically, the first type of representation vector can be embedded and coded according to a preset value embedding coding matrix to obtain the first type of feature vector. Specifically, the first type of representation vector can be multiplied by the preset value embedding coding matrix to obtain the first type of embedding vector; the first type of embedding vector and the preset value bias vector are added by position to obtain the first type of feature vector. The first type of embedding vector can refer to a graphical parsing embedding vector of a main wiring diagram.

[0042] In this embodiment, the scale of the one-dimensional convolutional coding is equal to an integer multiple of the length of the second type representation vector, in order to ensure that the context information between secondary devices within a specific range can be captured, thereby better reflecting the local neighborhood information in the secondary device.

[0043] Based on the above optional implementation, the first type of representation vector is used as the pseudo-query feature vector, the second type of representation vector and the second type of feature vector are used as the pseudo-key feature vector, and the first type of feature vector is used as the value vector. The pseudo-query feature vector, the value vector and the pseudo-key feature vector are subjected to feature fusion processing based on query matching to obtain the semantic representation of the wiring scheme, which can be as follows: Figure 1b As shown, including:

[0044] S1001, using the first type of representation vector as a pseudo-query feature vector, the first type of feature vector as a value vector, and the second type of representation vector as a pseudo-key feature vector, using a first multi-head attention query module to process the pseudo-query feature vector, the value vector, and the pseudo-key feature vector to obtain a sequence of feature value time series key granularity query matching implicit vectors;

[0045] S1002, using the first type of representation vector as a pseudo-query feature vector, the first type of feature vector as a value vector, and the second type of feature vector as a pseudo-key feature vector, using a second multi-head attention query module to process the pseudo-query feature vector, the value vector, and the pseudo-key feature vector to obtain a sequence of feature value time series key neighborhood granularity query matching implicit vectors;

[0046] S1003, calculating the position mean vector of the sequence of the implicit vector matched by the eigenvalue time series key granularity query to obtain the eigenvalue time series key granularity query matching eigenvector, and calculating the position mean vector of the sequence of the implicit vector matched by the eigenvalue time series key neighborhood granularity query to obtain the eigenvalue time series key neighborhood granularity query matching eigenvector;

[0047] S1004. Fuse the eigenvalue temporal key granularity query matching eigenvector and the eigenvalue temporal key neighborhood granularity query matching eigenvector to obtain a wiring scheme implicit semantic representation vector and use the wiring scheme implicit semantic representation vector as the wiring scheme semantic representation.

[0048] Optionally, the S1001 operation may specifically include: calculating the implicit association matrix between the primary main connection and the secondary device based on the transposed vector of the first type of representation vector and the second type of representation vector; calculating the implicit association modulation matrix between the primary main connection and the secondary device based on the implicit association matrix and the square root of the length of the second type of representation vector; processing the implicit association modulation matrix using a preset activation function to obtain the implicit association activation matrix between the primary main connection and the secondary device; calculating the sequence of eigenvalue timing key granularity query matching implicit vectors based on the implicit association activation matrix and the first type of eigenvector.

[0049] In this embodiment, the product of the transposed vector of the first type of representation vector and the second type of representation vector can be calculated to obtain a graphically analyzed implicit association matrix (i.e., implicit association evidence) between the primary main connection and the secondary device; the graphically analyzed implicit association matrix and the square root of the length of the second type of representation vector are divided by position to obtain a graphically analyzed implicit association modulation matrix (i.e., implicit association modulation matrix) between the primary main connection and the secondary device; the graphically analyzed implicit association modulation matrix is ​​input into a preset activation function (e.g., a softmax function) to obtain a graphically analyzed implicit association activation matrix (i.e., implicit association activation matrix) between the primary main connection and the secondary device; the graphically analyzed implicit association activation matrix is ​​multiplied by the first type of eigenvector to obtain a sequence of eigenvalue time series key granularity query matching implicit vectors.

[0050] Optionally, the S1004 operation may specifically include: calculating the difference vector, dot product vector and sum vector between the primary main connection and the secondary device respectively according to the eigenvalue time key granularity query matching feature vector and the eigenvalue time key neighborhood granularity query matching feature vector; cascading the difference vector, dot product vector and sum vector to obtain the cascade vector of the primary main connection and the secondary device; performing one-dimensional convolution coding on the cascade vector to obtain the convolution coding vector of the primary main connection and the secondary device; performing maximum pooling on the convolution coding vector to obtain the wiring scheme implicit semantic representation vector, and using the wiring scheme implicit semantic representation vector as the wiring scheme semantic representation.

[0051] Among them, the differential vector may refer to the graphically parsed key granularity-key neighborhood granularity differential vector of the primary main wiring and the secondary equipment, and the differential vector may be obtained by subtracting the eigenvalue timing key granularity query matching eigenvalue vector and the eigenvalue timing key neighborhood granularity query matching eigenvalue vector by position. The dot product vector may refer to the graphically parsed key granularity-key neighborhood granularity dot product vector of the secondary main wiring and the secondary equipment, and the dot product vector may be obtained by dot-producting the eigenvalue timing key granularity query matching eigenvalue vector and the eigenvalue timing key neighborhood granularity query matching eigenvalue vector by position. The sum vector may refer to the graphically parsed key granularity-key neighborhood granularity sum vector of the primary main wiring and the secondary equipment, and the sum vector may be obtained by adding the eigenvalue timing key granularity query matching eigenvalue vector and the eigenvalue timing key neighborhood granularity query matching eigenvalue vector by position.

[0052] The cascade vector of the primary main wiring and the secondary device may refer to the graphical parsing key granularity-key neighborhood granularity cascade vector of the primary main wiring and the secondary device. The convolutional coding vector of the primary main wiring and the secondary device may refer to the graphical parsing key granularity-key neighborhood granularity convolutional coding vector of the primary main wiring and the secondary device, and the convolutional coding vector of the primary main wiring and the secondary device may be subjected to the maximum pooling processing based on the local window to obtain the implicit semantic representation vector of the wiring scheme.

[0053] Based on the above content, in this embodiment, the following optimized query parsing formula can be used to perform query parsing based on local neighborhood optimization on the pseudo-query feature vector and pseudo-key feature vector of S130 to capture the deployment relationship between the primary equipment and the secondary equipment and obtain the semantic representation of the wiring plan.

[0054] The optimized query parsing formula may be:

[0055] K={k1,k2,...,k i , ..., k n}; where K represents a set of secondary device graphical parsing coding representation vectors (second type representation vectors), k1, k2, ..., k i , ..., k n Represents the 1st, 2nd, ..., ith, ..., nth secondary device graphical analysis code representation vector in the set of secondary device graphical analysis code representation vectors, and n represents the number of representation vectors in the set of secondary device graphical analysis code representation vectors.

[0056] K′=Conv 1×l ({k1,k2,...,k i , ..., k n}); where Conv 1×l (·) represents one-dimensional convolutional coding, l represents an integer multiple of the length of the secondary device graphical parsing coding representation vector, and K′ represents the set of secondary device graphical parsing local neighborhood semantic association feature vectors (ie, the second type of feature vectors).

[0057] K′={k1′,k2′,...,k i ′,...,k m ′}; where k1′, k′2, ..., k i ′, ..., k m 'surface

[0058] , represents the 1st, 2nd, ..., ith, ..., mth secondary device graphical analysis local neighborhood semantic association feature vectors in the set of secondary device graphical analysis local neighborhood semantic association feature vectors, where m represents the number of feature vectors in the set of secondary device graphical analysis local neighborhood semantic association feature vectors.

[0059] v v =v q W q +b q ; where v q represents the graphical analytical encoding representation vector of a main wiring diagram (i.e., the first type of representation vector), W q represents the preset value embedding encoding matrix, b qRepresents the preset value bias vector, v v Represents the graphical analytical value eigenvector of a main wiring diagram (i.e., the first type of eigenvector).

[0060] Among them, k i T Indicates k i The transposed vector of , d1 represents the length of the vector represented by the graphical parsing code of the secondary device, softmax(·) represents the softmax function, v ki The i-th eigenvalue time series key granularity query matching implicit vector in the sequence representing the eigenvalue time series key granularity query matching implicit vector.

[0061] Among them, k i ' T Indicates k i The transposed vector of , d2 represents the length of the semantic association feature vector of the local neighborhood of the secondary device graphical analysis, v ni The i-th eigenvalue temporal key neighborhood granularity query matching implicit vector in the sequence representing the eigenvalue temporal key neighborhood granularity query matching implicit vector.

[0062] Among them, v k Represents the feature value time series key granularity query matching feature vector. Among them, v n Represents the feature value time series key neighborhood granularity query matching feature vector.

[0063] in, ⊙ and They represent positional subtraction, positional dot multiplication, and positional addition, respectively. [·, ·, ·] represents cascade processing. conv1D(·) represents a one-dimensional convolutional encoding operation. MaxPool(·) represents a maximum pooling operation. v p Represents the implicit semantic representation vector of the wiring scheme.

[0064] In summary, the query parsing process based on local neighborhood optimization in S130 can be generally understood as follows:

[0065] Through the one-dimensional convolution operation, the implicit correlation between the graphical analytical coding representation vectors of each secondary device is extracted, which helps to enhance the ability to understand the relationship between each secondary device. The convolution kernel size of the one-dimensional convolution is set to an integer multiple of the length of the graphical analytical coding representation vector of the secondary device to ensure that the contextual information between secondary devices within a specific range can be captured, thereby better reflecting the local neighborhood information in the secondary device. This means that not only a single secondary device itself is considered, but also how other devices around it are connected, which is very important for understanding the interaction between devices.

[0066] Furthermore, the graphical parsing encoding representation vector of the primary wiring diagram is processed using the value embedding encoding matrix to generate a graphical parsing value feature vector of the primary wiring diagram, so that the query feature vector can be converted into a form that is more suitable as a value vector in the attention mechanism. Through embedding encoding, the graphical parsing encoding representation vector of the primary wiring diagram can be mapped to a higher-dimensional space, so that in the subsequent attention mechanism, these feature vectors can better express the graphical parsing semantics and query intent of the primary wiring diagram, and effectively interact with other secondary device graphical parsing semantics.

[0067] Then, the processed pseudo-query feature vector, value vector and pseudo-key feature vector are input into the multi-head attention query module based on the transformer structure to focus on the relationship between the query vector (primary device) and the key vector (secondary device) from different perspectives through the multi-head attention mechanism. This helps to capture the complex connections and connection relationships between primary devices at different levels and different secondary devices, and provides a basis for the subsequent automatic wiring solution generation.

[0068] Furthermore, the positional mean vector of the sequence of implicit vectors matching the eigenvalue time series key granularity query and the sequence of implicit vectors matching the eigenvalue time series key neighborhood granularity query is calculated, and they are fused into the final wiring scheme implicit semantic representation vector, which can obtain a representation that integrates the features of different granularity levels. The purpose of the fusion is to integrate the graphical analysis features of the primary main wiring diagram and the graphical analysis feature information of each secondary device at two different granularity levels, to ensure that the final wiring scheme semantic representation can fully reflect the multiple relationships between the primary main wiring semantics and the secondary device semantics, and provide a more reliable data basis for the generation of subsequent secondary system three-remote test acceptance wiring schemes.

[0069] S140. Generate a test acceptance wiring plan diagram for the secondary system to be accepted based on the wiring plan semantic representation.

[0070] Optionally, the wiring scheme implicit semantic representation vector is input into a wiring scheme renderer based on a diffusion model to obtain a test acceptance wiring scheme diagram.

[0071] It can be understood that the wiring scheme is rendered using the implicit semantic representation of the wiring scheme containing the complex dependent connection features between the primary and secondary devices, thereby automatically generating the CAD drawing of the wiring scheme. This not only covers all the necessary three-remote signal points, but also takes into account how to arrange the simulation terminals most effectively to facilitate subsequent actual operations. In this way, a more intelligent automatic generation of the three-remote test acceptance wiring scheme for the substation secondary system can be achieved, reducing the inefficiency and errors caused by human factors, so as to ensure that the generated wiring scheme is comprehensive and reliable.

[0072] The technical solution of the embodiment of the present invention is to obtain a description file including a primary main wiring diagram and a secondary device description diagram of a secondary system to be accepted; perform graphical information analysis on the primary main wiring diagram to obtain a first type of representation vector, and perform graphical information analysis on the secondary device description diagram to obtain a second type of representation vector; use the first type of representation vector as a pseudo-query feature vector and the second type of representation vector as a pseudo-key feature vector, perform query analysis based on local neighborhood optimization on the pseudo-query feature vector and the pseudo-key feature vector to capture the deployment relationship between the primary device and the secondary device and obtain a wiring scheme semantic representation; generate a test acceptance wiring scheme diagram of the secondary system to be accepted based on the wiring scheme semantic representation, analyze the graphical information of the primary main wiring diagram and the secondary device description diagram to identify necessary features from the description file of the secondary system to be accepted, understand the functions of the primary device and the secondary device and the connection relationship between them, and thus automatically generate a wiring scheme. The technical means solves the problem that the prior art relies on the experience and personal skills of engineers, resulting in low efficiency, and is prone to inaccurate wiring schemes due to problems such as misreading drawings and missing wiring, reduces the inefficiency and errors caused by human factors, and ensures that the generated wiring scheme is comprehensive and reliable.

[0073] Embodiment 2

[0074] Figure 2 This is a schematic diagram of the structure of a test acceptance wiring scheme generation device provided in the second embodiment of the present invention. Figure 2 As shown, the device includes: a file acquisition module 210, a representation vector acquisition module 220, a semantic representation acquisition module 230 and a wiring diagram generation module 240. Among them:

[0075] The file acquisition module 210 is used to acquire the description file of the secondary system to be accepted, wherein the description file includes a primary main wiring diagram and a secondary device description diagram;

[0076] A representation vector acquisition module 220, configured to perform graphical information analysis on the primary main wiring diagram to obtain a first type of representation vector, and perform graphical information analysis on the secondary device description diagram to obtain a second type of representation vector;

[0077] A semantic representation acquisition module 230, configured to use the first type of representation vector as a pseudo-query feature vector and the second type of representation vector as a pseudo-key feature vector, perform query parsing based on local neighborhood optimization on the pseudo-query feature vector and the pseudo-key feature vector to capture the deployment relationship between the primary device and the secondary device and obtain a semantic representation of the wiring scheme;

[0078] The wiring plan diagram generating module 240 is used to generate a test acceptance wiring plan diagram of the secondary system to be accepted based on the wiring plan semantic representation.

[0079] The technical solution of the embodiment of the present invention is to obtain a description file including a primary main wiring diagram and a secondary device description diagram of a secondary system to be accepted; perform graphical information analysis on the primary main wiring diagram to obtain a first type of representation vector, and perform graphical information analysis on the secondary device description diagram to obtain a second type of representation vector; use the first type of representation vector as a pseudo-query feature vector and the second type of representation vector as a pseudo-key feature vector, perform query analysis based on local neighborhood optimization on the pseudo-query feature vector and the pseudo-key feature vector to capture the deployment relationship between the primary device and the secondary device and obtain a wiring scheme semantic representation; generate a test acceptance wiring scheme diagram of the secondary system to be accepted based on the wiring scheme semantic representation, analyze the graphical information of the primary main wiring diagram and the secondary device description diagram to identify necessary features from the description file of the secondary system to be accepted, understand the functions of the primary device and the secondary device and the connection relationship between them, and thus automatically generate a wiring scheme. The technical means solves the problem that the prior art relies on the experience and personal skills of engineers, resulting in low efficiency, and is prone to inaccurate wiring schemes due to problems such as misreading drawings and missing wiring, reduces the inefficiency and errors caused by human factors, and ensures that the generated wiring scheme is comprehensive and reliable.

[0080] Optionally, the semantic representation acquisition module 230 may include:

[0081] A first-category feature vector acquisition unit, configured to perform embedding coding on the first-category representation vector to obtain a first-category feature vector;

[0082] A second-type feature vector acquisition unit, used for performing one-dimensional convolution coding on the second-type representation vector to obtain a second-type feature vector, wherein a scale of the one-dimensional convolution coding is equal to an integer multiple of a length of the second-type representation vector;

[0083] A semantic representation acquisition unit is used to use the first type of representation vector as the pseudo-query feature vector, the second type of representation vector and the second type of feature vector as the pseudo-key feature vector, and the first type of feature vector as the value vector, perform feature fusion processing based on query matching on the pseudo-query feature vector, the value vector and the pseudo-key feature vector, and obtain the semantic representation of the wiring scheme.

[0084] Optionally, the first type of feature vector acquisition unit can be specifically used for:

[0085] Multiplying the first type of representation vector by a preset value embedding coding matrix to obtain a first type of embedding vector;

[0086] The first type of embedding vector is added to the preset value bias vector by position to obtain the first type of feature vector.

[0087] Optionally, the semantic representation acquisition unit may include:

[0088] A first sequence acquisition subunit is used to use the first type of representation vector as the imitation query feature vector, the first type of feature vector as the value vector, and the second type of representation vector as the imitation key feature vector, and use a first multi-head attention query module to process the imitation query feature vector, the value vector, and the imitation key feature vector to obtain a sequence of feature value time series key granularity query matching implicit vectors;

[0089] A second sequence acquisition subunit is used to use the first type of representation vector as the imitation query feature vector, the first type of feature vector as the value vector, and the second type of feature vector as the imitation key feature vector, and use a second multi-head attention query module to process the imitation query feature vector, the value vector and the imitation key feature vector to obtain a sequence of feature value time series key neighborhood granularity query matching implicit vectors;

[0090] A feature vector acquisition subunit is used to calculate the position mean vector of the sequence of the feature value time series key granularity query matching implicit vectors to obtain the feature value time series key granularity query matching feature vector, and calculate the position mean vector of the sequence of the feature value time series key neighborhood granularity query matching implicit vectors to obtain the feature value time series key neighborhood granularity query matching feature vector;

[0091] The semantic representation acquisition subunit is used to fuse the feature value time key granularity query matching feature vector and the feature value time key neighborhood granularity query matching feature vector to obtain a wiring scheme implicit semantic representation vector and use the wiring scheme implicit semantic representation vector as the wiring scheme semantic representation.

[0092] Optionally, the first sequence acquisition subunit may be specifically used for:

[0093] Calculate the implicit association matrix between the primary main wiring and the secondary equipment according to the transposed vector of the first type of representation vector and the second type of representation vector;

[0094] Calculating an implicit correlation modulation matrix between a primary main connection and a secondary device according to the implicit correlation matrix and a square root of the length of the second type representation vector;

[0095] Processing the implicit correlation modulation matrix using a preset activation function to obtain an implicit correlation activation matrix of a primary main connection and a secondary device;

[0096] The sequence of the eigenvalue time-series key granularity query matching implicit vectors is calculated according to the implicit association activation matrix and the first type of eigenvectors.

[0097] Optional, semantic representation of the acquisition subunit, which can be used for:

[0098] According to the eigenvalue time series key granularity query matching eigenvector and the eigenvalue time series key neighborhood granularity query matching eigenvector, respectively calculate the difference vector, dot product vector and sum vector between the primary main connection and the secondary device;

[0099] Performing cascade processing on the difference vector, the dot product vector and the sum vector to obtain a cascade vector of a primary main connection and a secondary device;

[0100] Performing one-dimensional convolution coding processing on the cascade vector to obtain a convolution coding vector of a primary main connection and a secondary device;

[0101] The convolutional coding vector is subjected to maximum pooling processing to obtain a latent semantic representation vector of the wiring scheme, and the latent semantic representation vector of the wiring scheme is used as the semantic representation of the wiring scheme.

[0102] Optionally, the wiring diagram generating module 240 may be specifically used for:

[0103] The wiring scheme implicit semantic representation vector is input into a wiring scheme renderer based on a diffusion model to obtain the test acceptance wiring scheme diagram.

[0104] The test acceptance wiring scheme generating device provided in the embodiment of the present invention can execute the test acceptance wiring scheme generating method provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the execution method.

[0105] Embodiment 3

[0106] Figure 3 A schematic diagram of an electronic device 300 that can be used to implement an embodiment of the present invention is shown. The electronic device is intended to represent various forms of digital computers or various forms of mobile devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present invention described and / or required herein.

[0107] like Figure 3As shown, the electronic device 300 includes at least one processor 301, and a memory connected to the at least one processor 301, such as a read-only memory (ROM) 302, a random access memory (RAM) 303, etc., wherein the memory stores a computer program that can be executed by at least one processor, and the processor 301 can perform various appropriate actions and processes according to the computer program stored in the read-only memory (ROM) 302 or the computer program loaded from the storage unit 308 to the random access memory (RAM) 303. In the RAM 303, various programs and data required for the operation of the electronic device 300 can also be stored. The processor 301, the ROM 302, and the RAM 303 are connected to each other via a bus 304. An input / output (I / O) interface 305 is also connected to the bus 304.

[0108] A number of components in the electronic device 300 are connected to the I / O interface 305, including: an input unit 306, such as a keyboard, a mouse, etc.; an output unit 307, such as various types of displays, speakers, etc.; a storage unit 308, such as a disk, an optical disk, etc.; and a communication unit 309, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 309 allows the electronic device 300 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0109] The processor 301 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the processor 301 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, digital signal processors (DSPs), and any appropriate processors, controllers, microcontrollers, etc. The processor 301 executes the various methods and processes described above, such as a test acceptance wiring scheme generation method.

[0110] In some embodiments, the test acceptance wiring scheme generation method can be implemented as a computer program, which is tangibly contained in a computer-readable storage medium, such as a storage unit 308. In some embodiments, part or all of the computer program can be loaded and / or installed on the electronic device 300 via the ROM 302 and / or the communication unit 309. When the computer program is loaded into the RAM 303 and executed by the processor 301, one or more steps of the test acceptance wiring scheme generation method described above can be performed. Alternatively, in other embodiments, the processor 301 can be configured to execute the test acceptance wiring scheme generation method in any other appropriate manner (for example, by means of firmware).

[0111] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0112] Computer programs for implementing the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that when the computer program is executed by the processor, the functions / operations specified in the flow chart and / or block diagram are implemented. The computer program may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0113] In the context of the present invention, a computer-readable storage medium may be a tangible medium that may contain or store a computer program for use by or in combination with an instruction execution system, device or equipment. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices or equipment, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0114] To provide interaction with a user, the systems and techniques described herein may be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and a pointing device (e.g., a mouse or trackball) through which the user can provide input to the electronic device. Other types of devices may also be used to provide interaction with the user; for example, the feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form (including acoustic input, voice input, or tactile input).

[0115] The systems and techniques described herein may be implemented in a computing system that includes backend components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes frontend components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such backend components, middleware components, or frontend components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), a blockchain network, and the Internet.

[0116] A computing system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The client and server relationship is generated by computer programs running on the corresponding computers and having a client-server relationship with each other. The server may be a cloud server, also known as a cloud computing server or cloud host, which is a host product in the cloud computing service system to solve the defects of difficult management and weak business scalability in traditional physical hosts and VPS services.

[0117] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0118] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for generating a test acceptance wiring scheme, characterized in that: include: Obtain a description file of the secondary system to be accepted, the description file including a primary main wiring diagram and a secondary device description diagram; Performing graphical information analysis on the primary main wiring diagram to obtain a first type of representation vector, and performing graphical information analysis on the secondary device description diagram to obtain a second type of representation vector; Using the first type of representation vector as a pseudo-query feature vector and the second type of representation vector as a pseudo-key feature vector, performing query parsing based on local neighborhood optimization on the pseudo-query feature vector and the pseudo-key feature vector to capture the deployment relationship between the primary device and the secondary device and obtain a semantic representation of the wiring scheme; A test acceptance wiring plan diagram of the secondary system to be accepted is generated based on the wiring plan semantic representation.

2. The method according to claim 1, characterized in that The first type of representation vector is used as a pseudo-query feature vector and the second type of representation vector is used as a pseudo-key feature vector, and query parsing based on local neighborhood optimization is performed on the pseudo-query feature vector and the pseudo-key feature vector to capture the deployment relationship between the primary device and the secondary device and obtain a semantic representation of the wiring scheme, including: Performing embedding coding on the first type of representation vector to obtain a first type of feature vector; Performing one-dimensional convolution coding on the second type of representation vector to obtain a second type of feature vector, wherein a scale of the one-dimensional convolution coding is equal to an integer multiple of a length of the second type of representation vector; The first type of representation vector is used as the pseudo-query feature vector, the second type of representation vector and the second type of feature vector are used as the pseudo-key feature vector, and the first type of feature vector is used as the value vector. Feature fusion processing based on query matching is performed on the pseudo-query feature vector, the value vector and the pseudo-key feature vector to obtain the semantic representation of the wiring scheme.

3. The method according to claim 2, characterized in that The first type of representation vector is embedded and encoded to obtain a first type of feature vector, including: Multiplying the first type of representation vector by a preset value embedding coding matrix to obtain a first type of embedding vector; The first type of embedding vector is added to the preset value bias vector by position to obtain the first type of feature vector.

4. The method according to claim 2, characterized in that Taking the first type of representation vector as the query-like feature vector, taking the second type of representation vector and the second type of feature vector as the key-like feature vector, and taking the first type of feature vector as the value vector, performing feature fusion processing based on query matching on the query-like feature vector, the value vector, and the key-like feature vector to obtain the wiring scheme semantic representation, including: Using the first type of representation vector as the pseudo-query feature vector, the first type of feature vector as the value vector, and the second type of representation vector as the pseudo-key feature vector, using a first multi-head attention query module to process the pseudo-query feature vector, the value vector, and the pseudo-key feature vector to obtain a sequence of feature value time series key granularity query matching implicit vectors; Using the first type of representation vector as the pseudo-query feature vector, the first type of feature vector as the value vector, and the second type of feature vector as the pseudo-key feature vector, using a second multi-head attention query module to process the pseudo-query feature vector, the value vector, and the pseudo-key feature vector to obtain a sequence of feature value temporal key neighborhood granularity query matching implicit vectors; Calculate the positional mean vector of the sequence of the eigenvalue time series key granularity query matching implicit vectors to obtain the eigenvalue time series key granularity query matching eigenvector, and calculate the positional mean vector of the sequence of the eigenvalue time series key neighborhood granularity query matching implicit vectors to obtain the eigenvalue time series key neighborhood granularity query matching eigenvector; The characteristic value time series key granularity query matching characteristic vector and the characteristic value time series key neighborhood granularity query matching characteristic vector are integrated to obtain a wiring scheme implicit semantic representation vector and use the wiring scheme implicit semantic representation vector as the wiring scheme semantic representation.

5. The method according to claim 4, characterized in that The first type of representation vector is used as the pseudo-query feature vector, the first type of feature vector is used as the value vector, and the second type of representation vector is used as the pseudo-key feature vector, and the pseudo-query feature vector, the value vector and the pseudo-key feature vector are processed by a first multi-head attention query module to obtain a sequence of feature value time series key granularity query matching implicit vectors, including: Calculate the implicit association matrix between the primary main wiring and the secondary equipment according to the transposed vector of the first type of representation vector and the second type of representation vector; Calculating an implicit correlation modulation matrix between a primary main connection and a secondary device according to the implicit correlation matrix and a square root of the length of the second type representation vector; Processing the implicit correlation modulation matrix using a preset activation function to obtain an implicit correlation activation matrix of a primary main connection and a secondary device; The sequence of the eigenvalue time-series key granularity query matching implicit vectors is calculated according to the implicit association activation matrix and the first type of eigenvectors.

6. The method according to claim 5, characterized in that The method comprises: fusing the feature value time sequence key granularity query matching feature vector and the feature value time sequence key neighborhood granularity query matching feature vector to obtain a wiring scheme implicit semantic representation vector and using the wiring scheme implicit semantic representation vector as the wiring scheme semantic representation, including: According to the eigenvalue time series key granularity query matching eigenvector and the eigenvalue time series key neighborhood granularity query matching eigenvector, respectively calculate the difference vector, dot product vector and sum vector between the primary main connection and the secondary device; Performing cascade processing on the difference vector, the dot product vector and the sum vector to obtain a cascade vector of a primary main connection and a secondary device; Performing one-dimensional convolution coding processing on the cascade vector to obtain a convolution coding vector of a primary main connection and a secondary device; The convolutional coding vector is subjected to maximum pooling processing to obtain a latent semantic representation vector of the wiring scheme, and the latent semantic representation vector of the wiring scheme is used as the semantic representation of the wiring scheme.

7. The method according to claim 6, characterized in that Generating a test acceptance wiring scheme diagram of the secondary system to be accepted based on the wiring scheme semantic representation includes: The wiring scheme implicit semantic representation vector is input into a wiring scheme renderer based on a diffusion model to obtain the test acceptance wiring scheme diagram.

8. A test acceptance wiring scheme generating device, characterized in that: include: A file acquisition module, used to acquire a description file of the secondary system to be accepted, wherein the description file includes a primary main wiring diagram and a secondary device description diagram; A representation vector acquisition module, used for performing graphical information analysis on the primary main wiring diagram to obtain a first type of representation vector, and performing graphical information analysis on the secondary device description diagram to obtain a second type of representation vector; A semantic representation acquisition module, configured to use the first type of representation vector as a pseudo-query feature vector and the second type of representation vector as a pseudo-key feature vector, perform query parsing based on local neighborhood optimization on the pseudo-query feature vector and the pseudo-key feature vector to capture the deployment relationship between the primary device and the secondary device and obtain a semantic representation of the wiring scheme; A wiring plan diagram generating module is used to generate a test acceptance wiring plan diagram of the secondary system to be accepted based on the wiring plan semantic representation.

9. An electronic device, characterized in that: The electronic device comprises: at least one processor; and a memory communicatively connected to the at least one processor; wherein, The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can execute the test acceptance wiring scheme generating method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the test acceptance wiring scheme generation method according to any one of claims 1 to 7 when executed.

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