Display panel and driving method

Abstract

The invention discloses a display panel and a driving method, the display panel comprises a plurality of rows of pixels, a data signal output by a data output channel on a data driving chip is received for driving, each row of pixels is divided into a plurality of pixel groups, and each pixel group comprises a first pixel, a second pixel, a third pixel and a fourth pixel; the first pixel and the second pixel are connected with the Nth row of scanning lines, and the third pixel and the fourth pixel are connected with the (N + 1) th row of scanning lines; the Mth column of data lines connected with the first pixel and the (M + 2) th column of data lines connected with the third pixel are connected to the Sth data channel on the data driving chip, and the (M + 1) th column of data lines connected with the second pixel and the (M + 3) th column of data lines connected with the fourth pixel are connected to the (S + 1) th data channel on the data driving chip. Each data channel is connected with two data lines, and the two data lines are respectively connected with two pixels controlled by two rows of scanning lines, so that the cost of a data driving chip is further saved, and head shaking lines caused by polarity overturning are improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a driving method. Background Art

[0002] Liquid Crystal Display (LCD) has many advantages such as thin body, power saving, and no radiation, and has been widely used. In the development process of large-size and high-refresh-rate display panels, dual-line gate technology (DLG) has attracted attention. DLG technology is also called double-frequency refresh technology. Its principle is that the panel GDL circuit opens two rows of scan lines at the same time, and the two rows input the same scan signal. In this mode, the number of pixels displayed vertically is reduced by half, and the refresh rate can be doubled without changing the original hardware and chip computing power.

[0003] In the LCD display industry, DRD (Double Row Driving), or 2G1D design, is now increasingly used because it can save data driver chips and chip on film (COF) and open a complete row of pixels through two rows of gate lines, so that the data lines (source) are halved and the gate lines are doubled, thus saving the source IC cost. However, when VCOM is not in the optimal condition, the display panel will have different brightness of positive and negative polarity pixels due to the asymmetry of the positive and negative polarities of the pixels, resulting in shaking head lines and affecting the display effect. Summary of the invention

[0004] The purpose of the present application is to provide a display panel and a driving method that can reduce the number of data driver chips, reduce the cost of the display panel, and improve the head shake pattern.

[0005] The present application discloses a display panel, the display panel comprising a plurality of rows of pixels, receiving a data signal output by a data output channel on a data driving chip for driving, each row of pixels being divided into a plurality of pixel groups, each pixel group comprising a first pixel, a second pixel, a third pixel and a fourth pixel; the first pixel and the second pixel are connected to an N-th row of scan lines, the third pixel and the fourth pixel are connected to an N+1-th row of scan lines; the M-th column of data lines connected to the first pixel and the M+2-th column of data lines connected to the third pixel are connected to an S-th data channel on the data driving chip, the M+1-th column of data lines connected to the second pixel and the M+3-th column of data lines connected to the fourth pixel are connected to an S+1-th data channel on the data driving chip; Wherein, N, M, and T are natural numbers greater than or equal to 1.

[0006] Optionally, along the extension direction of the scan line, the first pixel, the second pixel, the third pixel and the fourth pixel are arranged in sequence, the first pixel and the third pixel have the same polarity, the second pixel and the fourth pixel have the same polarity, the first pixel and the second pixel have different polarities, the Mth column data line connected to the first pixel and the M+2th column data line connected to the third pixel are arranged on the same layer, the M+1th column data line connected to the second pixel and the M+3th column data line connected to the fourth pixel are arranged on the same layer, and the Mth column data line connected to the first pixel and the M+1th column data line connected to the second pixel are arranged on different layers; the Mth column data line is connected to the Sth data channel through a first fan-out routing, and the M+2th column data line is connected to the S+1th data channel through a second fan-out routing; The length of the first fan-out routing is smaller than the length of the second fan-out routing, the cross-sectional area of ​​the first fan-out routing is smaller than the cross-sectional area of ​​the second fan-out routing, and the resistance of the first fan-out routing is equal to the resistance value of the second fan-out routing.

[0007] Optionally, the Sth data channel and the S+1th data channel are stacked on the data driving chip, and the Sth data channel is arranged on the S+1th data channel; the Sth data channel and the Mth column data line have the same height, and the S+1th data channel and the M+1th column data line have the same height.

[0008] Optionally, between two adjacent rows of scan lines, the first pixel, the second pixel, the third pixel and the fourth pixel are arranged in two rows and two columns, and along the extension direction of the data line, the first pixel and the third pixel are arranged in sequence, and the second pixel and the fourth pixel are arranged in sequence, and along the extension direction of the scan line, the first pixel and the second pixel are arranged in sequence, and the third pixel and the fourth pixel are arranged in sequence, the M+2th column data line is arranged between the Mth column data line and the M+1th column data line, and the M+1th column data line is arranged between the M+2th column data line and the M+3th column data line; the Mth column data line, the M+1th column data line, the M+2th column data line and the M+3th column data line are arranged on the same layer.

[0009] Optionally, the first pixel and the second pixel are main pixels, the third pixel and the fourth pixel are auxiliary pixels, the transmittance of the first pixel is greater than that of the third pixel, the transmittance of the second pixel is greater than that of the fourth pixel, the first common line corresponding to the first pixel and the second pixel receives a first common level, and the second common line corresponding to the third pixel and the fourth pixel receives a second common level, and when the grayscales of the first pixel and the third pixel are the same, the voltages of the first common level and the second common level are different.

[0010] Optionally, the display panel includes a refresh rate adjustment circuit and a gate driving circuit, the gate driving circuit includes a first gate driving unit and a second gate driving unit, the first gate driving unit is connected to the input end of the Nth row of scan lines, and the second gate driving unit is connected to the input end of the N+1th row of scan lines, and the refresh rate adjustment module controls the gate driving signals of the first gate driving unit and the second gate driving unit to be output to the input end of the Nth row of scan lines and the input end of the N+1th row of scan lines simultaneously or in time-sharing to achieve display with different refresh rates.

[0011] Optionally, the display panel further includes a first compensation circuit, a second compensation circuit and a picture detection module, wherein the input end of the first compensation circuit is connected between the first gate driver and the input end of the Nth row of scan lines, and the output end is connected to the picture detection module, the input end of the second compensation circuit is connected between the second gate driver and the input end of the N+1th row of scan lines, and the output end is connected to the picture detection module; The picture detection module generates a first compensation voltage and a second compensation voltage corresponding to the brightness, and inputs the first compensation circuit and the second compensation circuit respectively. The first compensation voltage and the second compensation voltage have different magnitudes.

[0012] The present application also discloses a driving method for driving any of the above display panels, the driving method comprising: Generate corresponding gate drive signals and output them to the first pixel and the second pixel connected to the Nth row of scan lines, and the third pixel and the fourth pixel connected to the N+1th row of scan lines respectively; Generate a corresponding data driving signal, and output it to the Mth column data line connected to the first pixel and the M+2th column data line connected to the third pixel through the corresponding Sth data channel, and output it to the M+1th column data line connected to the second pixel and the M+3th column data line connected to the fourth pixel through the corresponding S+1th data channel; Wherein, N, M, and T are natural numbers greater than or equal to 1.

[0013] Optionally, the first pixel, the second pixel, the third pixel and the fourth pixel are arranged in two rows and two columns, along the extension direction of the data line, the first pixel and the third pixel are arranged in sequence, and the second pixel and the fourth pixel are arranged in sequence, along the extension direction of the scan line, the first pixel and the second pixel are arranged in sequence, and the third pixel and the fourth pixel are arranged in sequence, the first common line corresponding to the first pixel and the second pixel receives a first common level, and the second common line corresponding to the third pixel and the fourth pixel receives a second common level, and the driving method further comprises the steps of: Detect the grayscale values ​​of the first pixel and the third pixel, and determine whether the grayscale values ​​are the same. If they are the same, output the first common level and the second common level with different voltage magnitudes to the first common line and the second common line respectively. If they are different, output the first common level and the second common level with the same voltage magnitudes to the first common line and the second common line respectively.

[0014] Optionally, the display panel includes a refresh rate adjustment circuit, a gate driving circuit, a first compensation circuit, a second compensation circuit and a picture detection module, and the step of generating corresponding gate driving signals to be output to the first pixel and the second pixel to be connected to the Nth row of scan lines, and the step of connecting the third pixel and the fourth pixel to the N+1th row of scan lines respectively includes: Detecting the next frame of the picture, and generating a first compensation voltage and a second compensation voltage according to the brightness to compensate the gate driving signals of the first gate driving unit and the second gate driving unit; The display mode of the next frame is detected. If it is a double frequency display, the gate driving signals of the first gate driving unit and the second gate driving unit are controlled to be output to the input end of the Nth row of scanning lines and the input end of the N+1th row of scanning lines at the same time; if it is a normal display, the gate driving signals of the first gate driving unit and the second gate driving unit are controlled to be output to the input end of the Nth row of scanning lines and the input end of the N+1th row of scanning lines in a time-sharing manner.

[0015] Compared with the display panel solution using the DRD architecture, the present application further improves the DRD architecture. Each row of pixels is divided into multiple pixel groups, each pixel group includes a first pixel, a second pixel, a third pixel and a fourth pixel; the first pixel and the second pixel are connected to the Nth row of scan lines, and the third pixel and the fourth pixel are connected to the N+1th row of scan lines; the Mth column data line connected to the first pixel and the M+2th column data line connected to the third pixel are connected to the Sth data channel on the data driver chip, and the M+1th column data line connected to the second pixel and the M+3th column data line connected to the fourth pixel are connected to the S+1th data channel on the data driver chip. In fact, the gate lines are increased by 6 times, and the data driver chip only needs one-third of the display panel with the DRD architecture. The new pixel architecture not only further reduces the cost of the data driver chip, but also avoids the appearance of head shake lines when the polarity is flipped. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The included drawings are used to provide a further understanding of the embodiments of the present application, which constitute a part of the specification, are used to illustrate the implementation methods of the present application, and together with the text description, explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. In the drawings: Figure 1 is a schematic diagram of an exemplary pixel structure (1G1D) of the present application; Figure 2 is a schematic diagram of an exemplary pixel structure (2G1D) of the present application; Figure 3 is a schematic diagram of an exemplary pixel structure (TRD) of the present application; Figure 4 is a schematic structural diagram of a display panel according to a first embodiment of the present application; Figure 5 is a schematic structural diagram of a display panel according to a second embodiment of the present application; Figure 6 is a schematic structural diagram of another display panel according to the second embodiment of the present application; Figure 7 is a schematic structural diagram of a display panel according to a third embodiment of the present application; Figure 8 is a schematic structural diagram of a display panel according to a fourth embodiment of the present application; Fig. 9 is a schematic flow chart of a driving method according to a fifth embodiment of the present application; Fig.10 is a schematic flow chart of a driving method according to a sixth embodiment of the present application; Fig.11 It is a flowchart of the driving method of the seventh embodiment of the present application.

[0017] Among them, 100, display panel; 110, pixel; 120, pixel group; 121, first pixel; 122, second pixel; 123, third pixel; 124, fourth pixel; 130, scan line; 140, data line; 150, fan-out area; 151, first fan-out routing; 152, second fan-out routing; 161, first common line; 162, second common line; 170, refresh rate adjustment circuit; 180, gate drive circuit; 191, first compensation circuit; 192, second compensation circuit; 200, data drive chip; 210, data channel; 220, picture detection module. DETAILED DESCRIPTION

[0018] It should be understood that the terms used herein, the specific structures and functional details disclosed are only for describing specific embodiments and are representative, but the present application can be implemented in many alternative forms and should not be construed as being limited to only the embodiments described herein.

[0019] The present application is described in detail below with reference to the accompanying drawings and optional embodiments.

[0020] refer to Figures 1 to 3 As shown, the conventional display panel architecture 1G1D (such as Figure 1 ) is improved to 2G1D (such as Figure 2 ) is the DRD (double rate driving) architecture, where G1 is the first row of scan lines, G2 is the second row of scan lines, ..., G6 is the sixth row of scan lines, ..., Gn is the Nth row of scan lines, D1 is the first column of data lines, D2 is the second column of data lines, ..., D7 is the seventh column of data lines, and Dn is the Nth column of data lines. The 1G1D architecture can open a complete row of pixels through two rows of gates, so that the source lines are halved and the gate lines are doubled. The increased gate lines can be realized by designing GOA circuits on the side of the gate less model, thus saving the source IC cost, such as Figure 2 The figure shows the DRD architecture commonly used at present, where sub-pixels are arranged in long and short hands; G represents the scan line and D represents the data line. To further save costs, various panel manufacturers currently have TRD architecture products that are cheaper than 2G1D (tri-gate, such as Figure 3 As shown in the figure); compared with normal 1G1D, TRD has data lines reduced to 1 / 3 of 1G1D and gate lines increased to 3 times of 1G1D. Similarly, the increased gate lines can be realized by designing a gate drive circuit (GOA) on the side of the gate less model, and the cost of the data driver chip (source) is further saved.

[0021] refer to Figure 4 As shown, as a first embodiment of the present application, a display panel 100 is disclosed, the display panel 100 includes a plurality of rows of pixels 110, and receives a data signal output by a data output channel on a data driving chip 200 for driving, characterized in that each row of pixels 110 is divided into a plurality of pixel groups 120, each pixel group 120 includes a first pixel 121, a second pixel 122, a third pixel 123 and a fourth pixel 124; the first pixel 121 and the second pixel 122 are connected to an Nth row of scanning lines 130, the third pixel 123 and the fourth pixel 124 are connected to the ... The four pixels 124 are connected to the N+1th row scan line 130; the Mth column data line 140 connected to the first pixel 121 and the M+2th column data line 140 connected to the third pixel 123 are connected to the Sth data channel 210 on the data driver chip 200, and the M+1th column data line 140 connected to the second pixel 122 and the M+3th column data line 140 connected to the fourth pixel 124 are connected to the S+1th data channel 210 on the data driver chip 200; wherein N, M, and T are natural numbers greater than or equal to 1.

[0022] This application is actually a combination of DRD and TRD architecture, source COF is reduced to 1 / 6, and the gate line is increased to 6 times. A row of pixels 110 is divided into a plurality of pixel groups 120. Each pixel group 120 includes four pixels 110, namely a first pixel 121, a second pixel 122, a third pixel 123 and a fourth pixel 124. The first pixel 121 and the second pixel 122 are connected to the Nth row scan line 130, and the third pixel 123 and the fourth pixel 124 are connected to the N+1th row scan line 130; the Mth column data line 140 connected to the first pixel 121 and the M+2th column data line 140 connected to the third pixel 123 are connected to the Sth data channel 210 on the data driver chip 200, and the M+1th column data line 140 connected to the second pixel 122 and the M+3th column data line 140 connected to the fourth pixel 124 are connected to the S+1th data channel 210 on the data driver chip 200; taking UHD (3840*2160 resolution) as an example, assuming that a 960ch source is used COF, 1G1D architecture requires 3840*3 / 960=12 source COFs, 2G1D architecture requires 3840*3 / 2 / 960=6 source COFs, TRD architecture requires 3840*3 / 3 / 960=4 source COFs; combining DRD and TRD produces Figure 4 The in-plane architecture shown in the figure takes UHD as an example. Only 3840*3 / 3 / 2 / 960=2 source COFs are needed. The new DRD TRD architecture further saves the source COF cost. The data driving signals from the same data channel 210 enter two pixels 110 controlled by different scan lines 130 respectively, avoiding data driving signal disorder and preventing the display panel 100 from having different brightness of positive and negative polarity pixels 110 due to the asymmetry of the positive and negative polarities of the pixels 110 when the common voltage VCOM is in a non-optimal condition, thereby forming shaking head wrinkles.

[0023] like Figure 5 As shown, as the second embodiment of the present application, it is a further refinement and improvement of the above-mentioned first embodiment, referring to Figure 5 and Figure 6As shown, along the extension direction of the scan line 130, the first pixel 121, the second pixel 122, the third pixel 123 and the fourth pixel 124 are arranged in sequence, the M-th column data line 140 connected to the first pixel 121 and the M+2-th column data line 140 connected to the third pixel 123 are arranged in the same layer, the M+1-th column data line 140 connected to the second pixel 122 and the M+3-th column data line 140 connected to the fourth pixel 124 are arranged in the same layer, and the M+2-th column data line 140 connected to the first pixel 121 and the M+3-th column data line 140 connected to the fourth pixel 124 are arranged in the same layer. The M-th column data line 140 and the M+1-th column data line 140 connected to the second pixel 122 are arranged in different layers; the M-th column data line 140 is connected to the S-th data channel 210 through the first fan-out wiring 151, and the M+2-th column data line 140 is connected to the S+1-th data channel 210 through the second fan-out wiring 152; wherein the length of the first fan-out wiring 151 is less than the length of the second fan-out wiring 152, and the cross-sectional area of ​​the first fan-out wiring 151 is less than the cross-sectional area of ​​the first fan-out wiring 151. The cross-sectional area of ​​the second fan-out wiring 152, the resistance of the first fan-out wiring 151 and the resistance value of the second fan-out wiring 152 are equal; taking the first column of pixels 110 to the fourth column of pixels 110 as an example, the first row of pixels 110 is a red pixel 110, the second row of pixels 110 is a green pixel 110, the third row of pixels 110 is a blue pixel 110, the first pixel 121, the second pixel 122, the third pixel 123 and the fourth pixel 124 are all red pixels 110, the first row and the first column of pixels 110 , that is, the first pixel 121 is connected to the first column data line 140D1 and the first row scan line 130G1, the first row second column pixel 110, that is, the second pixel 122 is connected to the second column data line 140D2 and the first row scan line 130G1, the first row third column pixel 110, that is, the third pixel 123 is connected to the third column data line 140D3 and the second row scan line 130G2, the first row fourth column pixel 110, that is, the fourth pixel 124 is connected to the fourth column data line 140D4 and the second row scan line 130G2.

[0024] In this embodiment, the four pixels 110 in the pixel group 120 are arranged in sequence, and the pixels 110 in the odd-numbered columns are connected to the same data channel 210, and the pixels 110 in the even-numbered columns are connected to the same data channel 210. In order to avoid crossing lines, the data lines 140 in the odd-numbered columns and the data lines 140 in the even-numbered columns are arranged in layers, the data line 140 in the Mth column connected to the first pixel 121 and the data line 140 in the M+2nd column connected to the third pixel 123 are arranged in the same layer, the data line 140 in the M+1st column connected to the second pixel 122 and the data line 140 in the M+3rd column connected to the fourth pixel 124 are arranged in the same layer, and the data line 140 in the M+1st column connected to the second pixel 122 and the data line 140 in the M+3rd column connected to the fourth pixel 124 are arranged in the same layer. The data lines 140 are arranged in the same layer, and the data line 140 of the Mth column connected to the first pixel 121 and the data line 140 of the M+1th column connected to the second pixel 122 are arranged in different layers, so as to avoid the need for the routing line coming out of the Sth data channel 210 to bypass the data line 140 connected to the S+1th data channel 210 when they are arranged in the same layer, resulting in an increase in the width of the fan-out area 150; in addition, considering that the routing line of the fan-out area 150 will affect the transmission of the data signal, in order to avoid different values ​​of data signal loss, the resistance of the first fan-out routing line 151 and the resistance value of the second fan-out routing line 152 are equal.

[0025] The polarity of the first pixel 121 and the third pixel 123 is the same, the polarity of the second pixel 122 and the fourth pixel 124 is the same, and the polarity of the first pixel 121 and the second pixel 122 is different. When VCOM is not in the optimal condition, the display panel 100 will also cause the brightness of the positive and negative polarity pixels 110 to be different due to the asymmetry of the positive and negative polarities of the pixels 110. For example, when VCOM is too large, the pixels 110 in the D1D3D5D7 columns are all positive and will be darker, and the pixels 110 in the D2D4D6D8 columns are all negative and will be brighter, but because one column is positive and the other column is negative alternately, the shaking head pattern during column inversion is lighter, so that the shaking head pattern phenomenon is somewhat improved.

[0026] Further, such as Figure 6 As shown, considering that the data lines 140 are arranged in two layers, the thickness of the corresponding display panel 100 will also increase, and the number of data channels 210 is relatively large. If the data channels 210 are arranged horizontally, the length of multiple data chips will increase, which will affect the appearance. Therefore, the data channels 210 are arranged in layers corresponding to the data lines 140 of different layers. Specifically, the Sth data channel 210 and the S+1th data channel 210 are stacked on the data driving chip 200, and the Sth data channel 210 is arranged on the S+1th data channel 210; the Sth data channel 210 and the Mth column data line 140 have the same height, and the S+1th data channel 210 and the M+1th column data line 140 have the same height.

[0027] like Figure 7As shown, as the third embodiment of the present application, different from the above embodiment, as another DRDTRD architecture, between two adjacent rows of scan lines 130, the first pixel 121, the second pixel 122, the third pixel 123 and the fourth pixel 124 are arranged in two rows and two columns, along the extension direction of the data line 140, the first pixel 121 and the third pixel 123 are arranged in sequence, the second pixel 122 and the fourth pixel 124 are arranged in sequence, and along the extension direction of the scan line 130, the first pixel 121, the second pixel 122, the third pixel 123 and the fourth pixel 124 are arranged in sequence. The second pixel 122 is arranged in sequence, the third pixel 123 and the fourth pixel 124 are arranged in sequence, the M+2 column data line 140 is arranged between the M column data line 140 and the M+1 column data line 140, and the M+1 column data line 140 is arranged between the M+2 column data line 140 and the M+3 column data line 140; the M column data line 140, the M+1 column data line 140, the M+2 column data line 140 and the M+3 column data line 140 are arranged in the same layer.

[0028] Furthermore, the DRD TRD architecture in the present embodiment can also improve color deviation. The first pixel 121 and the second pixel 122 are main pixels 110, and the third pixel 123 and the fourth pixel 124 are auxiliary pixels 110. The transmittance of the first pixel 121 is greater than the transmittance of the third pixel 123, and the transmittance of the second pixel 122 is greater than the transmittance of the fourth pixel 124. When the pixel 110 in the pixel group 120 is illuminated, the contrast between the main pixels 110 and the auxiliary pixels 110, which are arranged in an staggered manner and have different brightness levels, is relatively large, which can solve the problem of color deviation of the display panel 100 using the pixel 110 structure at a wide viewing angle, thereby improving its display effect. At the same time, for a pixel 110 unit, the four sub-pixels 110 are arranged in two rows and two columns, so that the sub-pixels 110 driven by the same data voltage can be more concentrated, thereby improving their display effect; in addition, the first common line 161 corresponding to the first pixel 121 and the second pixel 122 receives a first common level, and the second common line 162 corresponding to the third pixel 123 and the fourth pixel 124 receives a second common level. When the grayscales of the first pixel 121 and the third pixel 123 are the same, the voltages of the first common level and the second common level are different; by independently controlling the main pixel 110 and the auxiliary pixel 110, the brightness of the corresponding main / auxiliary pixel 110 can be changed by controlling the high and low switching of the common level of the common line, without processing the data signal. Even if the data signals of the main pixel 110 and the auxiliary pixel 110 are the same and have the same grayscale, the brightness difference between the main pixel 110 and the auxiliary pixel 110 can be automatically achieved through the difference in the common level signal, thereby further improving the color deviation.

[0029] like Figure 8As shown, as the fourth embodiment of the present application, it is a further refinement and improvement of any of the above embodiments. The display panel 100 includes a refresh rate adjustment circuit 170 and a gate driving circuit 180. The gate driving circuit 180 includes a first gate driving unit and a second gate driving unit. The first gate driving unit is connected to the input end of the N-th row of scan lines 130, and the second gate driving unit is connected to the input end of the N+1-th row of scan lines 130. The refresh rate adjustment module controls the gate driving signals of the first gate driving unit and the second gate driving unit to be output to the input end of the N-th row of scan lines 130 and the input end of the N+1-th row of scan lines 130 simultaneously or in time-sharing to achieve display with different refresh rates; the refresh rate adjustment circuit 170 is set before the gate driving circuit 180, and a row of pixels 110 in two rows of scan lines 130 can be displayed simultaneously or in time-sharing. When displayed simultaneously, the scanning time of a frame of the picture is reduced by half, thereby improving the refresh rate.

[0030] Furthermore, the display panel 100 also includes a first compensation circuit 191, a second compensation circuit 192 and a picture detection module 220, wherein the input end of the first compensation circuit 191 is connected between the first gate drive and the input end of the N-th row of scan line 130, and the output end is connected to the picture detection module 220, and the input end of the second compensation circuit 192 is connected between the second gate drive and the input end of the N+1-th row of scan line 130, and the output end is connected to the picture detection module 220; wherein the picture detection module 220 generates a corresponding first compensation voltage and a second compensation voltage according to the brightness, and inputs them into the first compensation circuit 191 and the second compensation circuit 192 respectively, and the first compensation voltage and the second compensation voltage are different in magnitude.

[0031] When the refresh rate is doubled, that is, in the frequency doubling mode, the first compensation circuit 191 and the second compensation circuit 192 are turned on, and the first compensation voltage and the second compensation voltage corresponding to the two scanning lines 130 of the same scanning signal are different. Negative compensation is used by the first compensation voltage and the second compensation voltage, that is, the voltage in the gate drive signal is pulled down, so as to generate different scanning signal waveforms output to the scanning line 130. The two rows of scanning signal waveforms are different, and the turn-on voltages of the thin film crystals of the sub-pixels 110 are different, so that the gate opening degrees of the thin film transistors corresponding to the two adjacent rows of pixels 110 are different, so that the two rows of pixels 110 turned on at the same time have different charging rates, thereby producing different display effects, so as to optimize the jaggedness of the edge of the picture and avoid the obvious and strong jaggedness of the edge of the picture.

[0032] like Fig. 9 As shown, as a fifth embodiment of the present application, a driving method is disclosed, the driving method is used to drive the display panel as described in any of the above embodiments, the driving method comprising: S1: Generate corresponding gate drive signals and output them to the first pixel and the second pixel connected to the Nth row of scan lines, and the third pixel and the fourth pixel connected to the N+1th row of scan lines; S2: Generate corresponding data driving signals, and output them to the Mth column data line connected to the first pixel and the M+2th column data line connected to the third pixel through the corresponding Sth data channel 210, and output the corresponding S+1th data channel to the M+1th column data line connected to the second pixel and the M+3th column data line connected to the fourth pixel at the same time; Wherein, N, M, and T are natural numbers greater than or equal to 1.

[0033] refer to Figure 4 and Fig. 9 As shown, in the pixel 110 architecture of the present embodiment, the first pixel 121 and the second pixel 122 are connected to the Nth row scan line 130, and the third pixel 123 and the fourth pixel 124 are connected to the N+1th row scan line 130; the Mth column data line 140 connected to the first pixel 121 and the M+2th column data line 140 connected to the third pixel 123 are connected to the Sth data channel 210 on the data driver chip 200, and the M+1th column data line 140 connected to the second pixel 122 and the M+3th column data line 140 connected to the fourth pixel 124 are connected to the S+1th data channel 210 on the data driver chip 200, which actually increases the gate lines by 6 times, and the data driver chip 200 only needs one-third of the display panel 100 of the DRD architecture; when the display panel 100 displays normally, each gate driving unit generates a corresponding gate driving signal and outputs it to the corresponding scan line 130 scan line 130, and when the scan line 130 is turned on, the corresponding data driver chip 200 outputs a data driving signal to the corresponding pixel 110 for charging and display.

[0034] like Fig.10 As shown, as the sixth embodiment of the present application, it is a further refinement and improvement of the above fifth embodiment, refer to Figure 7 and Fig.10 As shown, the first pixel 121, the second pixel 122, the third pixel 123 and the fourth pixel 124 are arranged in two rows and two columns. Along the extension direction of the data line 140, the first pixel 121 and the third pixel 123 are arranged in sequence, and the second pixel 122 and the fourth pixel 124 are arranged in sequence. Along the extension direction of the scan line 130, the first pixel 121 and the second pixel 122 are arranged in sequence, and the third pixel 123 and the fourth pixel 124 are arranged in sequence. The first common line 161 corresponding to the first pixel 121 and the second pixel 122 receives a first common level, and the second common line 162 corresponding to the third pixel 123 and the fourth pixel 124 receives a second common level. The driving method further includes the steps of: S3: Detecting the grayscale values ​​of the first pixel and the third pixel, and determining whether the grayscale values ​​are the same. If they are the same, outputting the first common level and the second common level with different voltage magnitudes to the first common line and the second common line respectively. If they are different, outputting the first common level and the second common level with the same voltage magnitudes to the first common line and the second common line respectively.

[0035] In this embodiment, considering that the first pixel 121 and the second pixel 122 in the pixel group 120 are main pixels 110, and the third pixel 123 and the fourth pixel 124 are auxiliary pixels 110, dividing the main pixel 110 and the auxiliary pixel 110 can improve color deviation, but when the common level is not good, there will be a difference in brightness, which will affect the display. Therefore, common level lines are respectively set corresponding to the main pixel 110 and the auxiliary pixel 110, and the same or different common levels can be respectively input to the corresponding common level lines, thereby improving the difference in brightness and improving the display effect.

[0036] like Fig.11 As shown, as the seventh embodiment of the present application, it is a further refinement and improvement of the fifth embodiment or the sixth embodiment mentioned above, and reference is made to Figure 8 and Fig.11 As shown, the display panel includes a refresh rate adjustment circuit 170, a gate driving circuit 180, a first compensation circuit 191, a second compensation circuit 192 and a picture detection module 220, and the step S1 includes: S11: Detecting a picture of the next frame, and generating a first compensation voltage and a second compensation voltage according to the brightness to compensate the gate driving signals of the first gate driving unit and the second gate driving unit; S12: Detect the display mode of the next frame. If it is a double frequency display, control the gate driving signals of the first gate driving unit and the second gate driving unit to be output to the input end of the Nth row of scan lines and the input end of the N+1th row of scan lines at the same time; if it is a normal display, control the gate driving signals of the first gate driving unit and the second gate driving unit to be output to the input end of the Nth row of scan lines and the input end of the N+1th row of scan lines in a time-sharing manner.

[0037] This embodiment is mainly aimed at the improvements made in different display modes of the display panel of the DRD TRD architecture. In the normal mode or the double frequency mode, the brightness of the next frame of the picture will be detected, and the gate drive signal will be compensated according to the brightness. If the brightness is not enough, the voltage of the gate drive signal will be positively compensated. If the brightness needs to be reduced, the voltage of the gate drive signal will be negatively compensated, that is, the voltage of the gate drive signal will be lowered. At the same time, if it is in the double frequency mode, it is necessary to control the waveform and input time of the first gate drive signal and the second gate drive signal, and input two gate drive signals at the same time, so as to achieve double frequency display.

[0038] It should be noted that the limitations of the various steps involved in this scheme, without affecting the implementation of the specific scheme, are not considered to limit the order of the steps, that is, the steps written in front can be executed first, or can be executed later, or even simultaneously. As long as this scheme can be implemented, it should be considered to belong to the scope of protection of this application. The inventive concept of this application can form a lot of embodiments, but the length of the application document is limited and cannot be listed one by one. Therefore, under the premise of no conflict, the various embodiments or technical features described above can be arbitrarily combined to form a new embodiment. After the various embodiments or technical features are combined, the original technical effect will be enhanced.

[0039] The above contents are further detailed descriptions of the present application in combination with specific optional implementation methods, and it cannot be determined that the specific implementation of the present application is limited to these descriptions. For ordinary technicians in the technical field to which the present application belongs, several simple deductions or substitutions can be made without departing from the concept of the present application, which should be deemed to fall within the scope of protection of the present application.

Claims

1. A display panel, comprising a plurality of rows of pixels, receiving a data signal output by a data output channel on a data driver chip for driving, characterized in that: Each row of pixels is divided into a plurality of pixel groups, each pixel group includes a first pixel, a second pixel, a third pixel and a fourth pixel; the first pixel and the second pixel are connected to the Nth row scan line, the third pixel and the fourth pixel are connected to the N+1th row scan line; the Mth column data line connected to the first pixel and the M+2th column data line connected to the third pixel are connected to the Sth data channel on the data driving chip, and the M+1th column data line connected to the second pixel and the M+3th column data line connected to the fourth pixel are connected to the S+1th data channel on the data driving chip; Wherein, N, M, and T are natural numbers greater than or equal to 1.

2. The display panel according to claim 1, wherein: Along the extension direction of the scan line, the first pixel, the second pixel, the third pixel and the fourth pixel are arranged in sequence, the first pixel and the third pixel have the same polarity, the second pixel and the fourth pixel have the same polarity, the first pixel and the second pixel have different polarities, the Mth column data line connected to the first pixel and the M+2th column data line connected to the third pixel are arranged on the same layer, the M+1th column data line connected to the second pixel and the M+3th column data line connected to the fourth pixel are arranged on the same layer, and the Mth column data line connected to the first pixel and the M+1th column data line connected to the second pixel are arranged on different layers; the Mth column data line is connected to the Sth data channel through a first fan-out wiring, and the M+2th column data line is connected to the S+1th data channel through a second fan-out wiring; The length of the first fan-out routing is smaller than the length of the second fan-out routing, the cross-sectional area of ​​the first fan-out routing is smaller than the cross-sectional area of ​​the second fan-out routing, and the resistance of the first fan-out routing is equal to the resistance value of the second fan-out routing.

3. The display panel according to claim 2, wherein: The Sth data channel and the S+1th data channel are stacked on the data driving chip, and the Sth data channel is arranged on the S+1th data channel; the Sth data channel and the Mth column data line have the same height, and the S+1th data channel and the M+1th column data line have the same height.

4. The display panel according to claim 1, wherein: Between two adjacent rows of scan lines, the first pixel, the second pixel, the third pixel and the fourth pixel are arranged in two rows and two columns, and along the extension direction of the data line, the first pixel and the third pixel are arranged in sequence, and the second pixel and the fourth pixel are arranged in sequence; along the extension direction of the scan line, the first pixel and the second pixel are arranged in sequence, and the third pixel and the fourth pixel are arranged in sequence, the M+2th column data line is arranged between the Mth column data line and the M+1th column data line, and the M+1th column data line is arranged between the M+2th column data line and the M+3th column data line; the Mth column data line, the M+1th column data line, the M+2th column data line and the M+3th column data line are arranged on the same layer.

5. The display panel according to claim 4, wherein: The first pixel and the second pixel are main pixels, the third pixel and the fourth pixel are auxiliary pixels, the transmittance of the first pixel is greater than that of the third pixel, the transmittance of the second pixel is greater than that of the fourth pixel, the first common line corresponding to the first pixel and the second pixel receives a first common level, the second common line corresponding to the third pixel and the fourth pixel receives a second common level, and when the grayscales of the first pixel and the third pixel are the same, the voltages of the first common level and the second common level are different.

6. The display panel according to claim 4, wherein: The display panel includes a refresh rate adjustment circuit and a gate driving circuit, the gate driving circuit includes a first gate driving unit and a second gate driving unit, the first gate driving unit is connected to the input end of the Nth row of scan lines, and the second gate driving unit is connected to the input end of the N+1th row of scan lines. The refresh rate adjustment module controls the gate driving signals of the first gate driving unit and the second gate driving unit to be output to the input end of the Nth row of scan lines and the input end of the N+1th row of scan lines simultaneously or in time-sharing to achieve display with different refresh rates.

7. The display panel according to claim 6, wherein: The display panel further includes a first compensation circuit, a second compensation circuit and a picture detection module, wherein the input end of the first compensation circuit is connected between the first gate driver and the input end of the Nth row of scan lines, and the output end is connected to the picture detection module, the input end of the second compensation circuit is connected between the second gate driver and the input end of the N+1th row of scan lines, and the output end is connected to the picture detection module; The picture detection module generates a first compensation voltage and a second compensation voltage corresponding to the brightness, and inputs the first compensation circuit and the second compensation circuit respectively. The first compensation voltage and the second compensation voltage have different magnitudes.

8. A driving method, characterized in that: Used to drive the display panel according to any one of claims 1 to 7, the driving method comprising: Generate corresponding gate drive signals and output them to the first pixel and the second pixel connected to the Nth row of scan lines, and the third pixel and the fourth pixel connected to the N+1th row of scan lines respectively; Generate a corresponding data driving signal, and output it to the Mth column data line connected to the first pixel and the M+2th column data line connected to the third pixel through the corresponding Sth data channel, and output it to the M+1th column data line connected to the second pixel and the M+3th column data line connected to the fourth pixel through the corresponding S+1th data channel; Wherein, N, M, and T are natural numbers greater than or equal to 1.

9. The driving method according to claim 8, characterized in that: The first pixel, the second pixel, the third pixel and the fourth pixel are arranged in two rows and two columns. Along the extension direction of the data line, the first pixel and the third pixel are arranged in sequence, and the second pixel and the fourth pixel are arranged in sequence. Along the extension direction of the scan line, the first pixel and the second pixel are arranged in sequence, and the third pixel and the fourth pixel are arranged in sequence. The first common line corresponding to the first pixel and the second pixel receives a first common level, and the second common line corresponding to the third pixel and the fourth pixel receives a second common level. The driving method further comprises the steps of: Detect the grayscale values ​​of the first pixel and the third pixel, and determine whether the grayscale values ​​are the same. If they are the same, output the first common level and the second common level with different voltage magnitudes to the first common line and the second common line respectively. If they are different, output the first common level and the second common level with the same voltage magnitudes to the first common line and the second common line respectively.

10. The driving method according to claim 8, characterized in that: The display panel includes a refresh rate adjustment circuit, a gate driving circuit, a first compensation circuit, a second compensation circuit and a picture detection module, and the steps of generating corresponding gate driving signals and outputting them to the first pixel and the second pixel to connect to the Nth row of scanning lines, and the third pixel and the fourth pixel to connect to the N+1th row of scanning lines respectively include: Detecting the next frame of the picture, and generating a first compensation voltage and a second compensation voltage according to the brightness to compensate the gate driving signals of the first gate driving unit and the second gate driving unit; The display mode of the next frame is detected. If it is a double frequency display, the gate driving signals of the first gate driving unit and the second gate driving unit are controlled to be output to the input end of the Nth row of scanning lines and the input end of the N+1th row of scanning lines at the same time; if it is a normal display, the gate driving signals of the first gate driving unit and the second gate driving unit are controlled to be output to the input end of the Nth row of scanning lines and the input end of the N+1th row of scanning lines in a time-sharing manner.

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