Dynamically reconfigurable memristor array and preparation method thereof

Abstract

The invention relates to a dynamic reconfigurable memristor array and a preparation method thereof, and belongs to a semiconductor memristor technology and an integration and control circuit technology. According to the dynamic reconfigurable memristor array provided by the invention, through the combination of the memristor chip and the peripheral circuit, the reconfiguration of different array structures can be dynamically realized only by switching the mode of the peripheral circuit, including the adjustment of the row number or the column number of the memristor array; and changing the relative position of a single array point in the memristor array and changing other electrical devices connected in series in the array point, such as a diode, a transistor or a selector. Mutually independent memristor devices are prepared on a single substrate, and then the memristor devices are packaged and then connected into a dynamic reconfigurable peripheral circuit, so that memristor arrays with different structures are realized. The requirement of the memristor array can be met more flexibly under the condition of the same number of memristors, so that the requirement for calculation of various neural forms in an artificial neural network or other storage and calculation integrated systems can be better met.

Description

Technical Field

[0001] The present invention belongs to semiconductor memristor technology and integrated and controlled circuit technology, and more specifically, relates to a dynamically reconfigurable memristor array and a preparation method thereof. Background Art

[0002] With the rapid development of the Internet of Things, big data, and cloud computing, the wave of information and intelligence has swept the world. Research and application in the fields of artificial neural networks, storage and computing integration, and artificial intelligence are becoming more and more in-depth. Due to its unique electrical properties, memristors are important electrical devices for all-hardware artificial intelligence neural network systems. In all-hardware artificial neural network systems, memristor arrays are responsible for scaling and mapping artificial synaptic weights and performing a large number of basic neuromorphic calculations such as vector matrix multiplication (VMM). Therefore, different artificial neural network structures and different neural computing functions usually require different memristor arrays to implement different structures. Traditional static memristor arrays often prepare and connect all memristor devices on the same substrate, so after the static memristor array is prepared, the array structure cannot be changed. If there is a need for a memristor array with other structures in the same system or it is found during testing that the original memristor device does not meet the current requirements, the original memristor array will not be applicable, and new devices must be prepared and a new array structure must be planned. Summary of the invention

[0003] The purpose of the present invention is to propose a dynamically reconfigurable memristor array, wherein the memristor array of the present invention comprises independent memristor devices and peripheral circuits, wherein any one of the memristor devices is used to selectively connect to the peripheral circuit, and the structure of the memristor array is dynamically changed by selecting the peripheral circuit connection mode. The memristor array in the present invention can change the structure of the memristor array without re-preparing new memristor devices to adapt to different neuromorphic computing requirements, thus solving the technical problem in the prior art that the array structure cannot be changed after the static memristor array is prepared.

[0004] According to a first aspect of the present invention, there is provided a dynamically reconfigurable memristor array, the memristor array comprising independent memristor devices and peripheral circuits, any one of the memristor devices comprising, from top to bottom, a top electrode, a resistive layer and a bottom electrode, the top electrode and the bottom electrode of any one of the memristor devices being used to connect to a chip carrier, the pins of the chip carrier being selectively connected to the peripheral circuit via a multi-way switch, the chip carrier being able to dynamically change the structure of the memristor array by switching between different connection modes with the peripheral circuit.

[0005] Preferably, the structure of the memristor array is the number of rows of the array, the number of columns of the array, the relative positions of array points, or whether electrical elements are connected in series at array points of the array.

[0006] Preferably, when the memristor array includes 4 memristor devices, the memristor array is a 4×1 memristor array or a 2×2 memristor array.

[0007] Preferably, when the memristor array includes 9 memristor devices, the memristor array is a 9×1 memristor array or a 3×3 memristor array.

[0008] Preferably, when the memristor array includes 12 memristor devices, the memristor array is a 3×4 memristor array or a 2×6 memristor array.

[0009] Preferably, the electrical element is a transistor, a selector or a diode.

[0010] According to another aspect of the present invention, there is provided a method for preparing any one of the dynamically reconfigurable memristor arrays, comprising the following steps:

[0011] (1) preparing a plurality of independent memristor devices on a substrate and packaging them on a chip carrier, wherein the top electrode and the bottom electrode of each memristor device are respectively connected to the chip carrier;

[0012] (2) selectively connecting the pins of the chip carrier in step (1) to the peripheral circuit through a multi-way switch; and connecting a plurality of memristor devices according to different connection modes between the peripheral circuit and the chip carrier to construct memristor arrays with different structures.

[0013] Preferably, in step (1), the memristor device has a Crossbar architecture.

[0014] Preferably, in step (2), the peripheral circuit is a printed circuit board.

[0015] Preferably, in step (2), the chip carrier and the peripheral circuit are connected by gold wire ball welding, chip mounting or conductive silver glue connection.

[0016] In summary, compared with the prior art, the above technical solution conceived by the present invention can at least achieve the following beneficial effects:

[0017] (1) The present invention proposes a dynamically reconfigurable memristor array, which consists of two parts: a memristor device and a peripheral circuit. It can realize different memristor array structures with a fixed number of memristors by switching the peripheral circuit mode without re-preparing new memristor devices, or more conveniently realize array point replacement when a small number of memristor devices are damaged, thereby effectively adapting to various neuromorphic computing requirements and different artificial neural network models, and improving the compatibility of the memristor array with the undesirable characteristics of the memristor. It is of great significance to the realization and related testing of full hardware artificial neural networks.

[0018] (2) The present invention provides a dynamically reconfigurable memristor array. Compared with the traditional static memristor array, this array has dynamic reconfigurability, and the structure of the array can be changed by switching the peripheral circuit connection mode after preparation.

[0019] (3) The memristor array provided by the present invention can test the functions of different memristor array structures to the greatest extent possible while preparing a limited number of memristor devices, and can use different VMM operations under different artificial neural network models, thereby determining the direction of structural design of large-scale memristor array integration in the future. This enables the array to have the flexibility to adapt to different computing requirements and has a positive effect on the design stage of more complex artificial neural network arrays.

[0020] (4) In a conventional memristor array, if a single device is damaged, the entire array will lose its function. However, the memristor array provided by the present invention can be easily connected to other good and undamaged devices by cooperating with peripheral circuits even if a small number of devices fail, thereby improving the service life and compatibility of the entire array.

[0021] (5) The memristor array provided by the present invention can test and screen the prepared memristor devices, and then select appropriate devices to connect to the peripheral circuit, thereby compatibility with the non-ideal characteristics of the devices to a certain extent and improving the accuracy of neuromorphic computing.

[0022] (6) The memristor array provided by the present invention allows external electronic components with different functions to be connected to each array point, so that the memristor array can have more abundant functions such as suppressing leakage current, threshold excitation, scaling mapping, etc., making the control capability of the array more abundant.

[0023] (7) The memristor array implementation method provided by the present invention is applicable to memristor devices made of various materials and has strong universality. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 Schematic diagram of a traditional fixed memristor array.

[0025] Figure 2 Schematic diagram of the dynamically reconfigurable memristor array of the present invention.

[0026] Figure 3 Schematic diagram of the structure of the memristor chip in Example 1.

[0027] Figure 4 1 is an equivalent circuit diagram after the peripheral circuit and the memristor chip are connected in Example 1.

[0028] Figure 5 4×1 memristor array equivalent circuit diagram in Example 1.

[0029] Figure 6 2×2 memristor array equivalent circuit diagram in Example 1.

[0030] Figure 7 1 is an equivalent circuit diagram of a 2×2 memristor array in which the relative positions of array points are changed in Example 1.

[0031] Figure 8 1 is an equivalent circuit diagram of a 2×2 1S1R memristor array having a selection function by controlling a multi-way switch in Example 1.

[0032] Fig. 9 This is the equivalent circuit diagram of the 9×1 memristor array in Example 2.

[0033] Fig.10 This is the equivalent circuit diagram of the 3×3 memristor array in Example 2.

[0034] Fig.11 This is an equivalent circuit diagram of a 3×3 memristor array in which the relative positions of array points are changed in Example 2.

[0035] Fig.12 3 is an equivalent circuit diagram of a 3×3 1D1R memristor array with a rectifying effect realized by adding diodes at array points in Example 2.

[0036] Fig.13 Schematic diagram of the peripheral circuit in Example 3.

[0037] Fig.14 It is a schematic diagram of 3×4, 4×3, 2×6 and 6×2 memristor arrays implemented by inserting 12 devices as a group in Example 3. DETAILED DESCRIPTION

[0038] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0039] Traditional memristor arrays are integrated on a substrate. Therefore, after the preparation is completed, the structure of the memristor array cannot be changed through subsequent operations. The schematic diagram of the traditional static 2×2 memristor array is shown in Figure 1 shown.

[0040] The memristor array of the present invention is composed of two parts: a mutually independent memristor device and a peripheral circuit with dynamic reconfigurability. By controlling the peripheral circuit, the structure of the original memristor array, the relative positions of array points, and other electrical devices external to the array points can be directly adjusted without rebuilding a new array, thereby facilitating the use of the same memristor device in the same array module to test and apply the performance of different array structures.

[0041] The present invention can switch the connection mode of the peripheral circuit through a switch or other control system, so that each independent device is connected into an array with different structures. Figure 2 As shown. Dynamically reconfigurable memristor array. The specific steps to achieve this are:

[0042] (1) preparing memristor devices on a single substrate, and after electrical testing, packaging memristor devices with good electrical performance and similar electrical behavior onto a chip carrier;

[0043] (2) designing and preparing a dynamically reconfigurable peripheral circuit, and connecting the chip carrier pins in (1) to the peripheral circuit;

[0044] (3) Selecting different connection modes of the peripheral circuits and connecting the memristor devices in different connection modes to realize memristor arrays with different structures.

[0045] The specific method for preparing the memristor in step (1) of the present invention is to use photolithography technology for patterning, and then use magnetron sputtering, pulsed laser deposition, electrochemical anodization and other methods to prepare the bottom electrode, resistive layer and top electrode of the memristor, and finally obtain independent memristor devices that can be connected to a chip carrier.

[0046] Preferably, the structure of the memristor prepared in step (1) is a classic Crossbar structure, or other structures in which TE and BE can be connected to a chip carrier respectively.

[0047] The peripheral circuit in step (2) of the present invention has multiple modes for connecting the memristor device, providing an interface for connecting a single array point to other electrical components, and thus has dynamic reconfigurability. At the same time, the peripheral circuit can be conveniently connected to the chip carrier, and the connection mode can be switched by the control system.

[0048] Preferably, the peripheral circuit designed in step (2) is prepared into a PCB, and an interface is provided to allow the pins of the chip carrier to be directly inserted, while the transition between different connection modes of the peripheral circuit is achieved by switching switches.

[0049] Preferably, the method for connecting the memristor device and the chip carrier in step (2) may include: gold wire ball bonding, chip mounting, conductive silver glue connection or other commonly used connection methods in the semiconductor field.

[0050] Preferably, the reconfigurability of the peripheral circuit of step (2) means that the peripheral circuit has different modes of circuit connection, can switch modes through switches or other control systems, provides an interface for connecting to a memristor chip carrier, and can optionally provide other electrical devices connected to array points, such as transistors, selectors, diodes and other interfaces.

[0051] Preferably, the different memristor array structures in step (3) represent at least one difference among the following three characteristics: the number of rows and columns of the array, the relative positions of array points, and the electrical elements connected in series at each array point.

[0052] The following are specific embodiments

[0053] Example 1

[0054] This embodiment provides a method for implementing a dynamically reconfigurable array based on four oxide memristors, and implements four different memristor array structures by controlling the multi-way switches of the peripheral circuits on a single-layer PCB. The specific steps are as follows:

[0055] (1) Cleaning the silicon wafer substrate: Place the silicon wafer in acetone, ethanol, and deionized water in turn, and ultrasonically clean it for 15 minutes each. After three cycles, use a nitrogen gun to blow dry the wafer and set it aside for later use.

[0056] (2) Preparation of memristor chip: Use photolithography and development technology on the substrate to obtain the bottom electrode pattern, then place the sample on the tray of the magnetron sputtering chamber, install the target material for depositing the bottom electrode on the target source of the chamber, set the parameters, and sputter and deposit the corresponding material layer, then debond to obtain the bottom electrode. Use the same method to prepare the oxide resistive layer and the top electrode, and obtain 32 complete independent memristor devices, and finally prepare the memristor chip. The structure of the memristor chip is as follows: Figure 3 shown.

[0057] (3) Screening available memristor devices: Place the prepared memristor chip in a semiconductor characteristic analysis system, and apply electrical signals by connecting the probes of the probe station to the top and bottom electrodes of the device to perform electrical performance tests. After electrical tests were performed on the 32 individual devices on the memristor chip, four devices with stable resistance behavior, good consistency, and similar pulse response performance were selected for backup;

[0058] (4) Welding and packaging of memristor chip and chip carrier: Use gold wire bonding method to package the memristor chip onto the chip carrier. After initializing the wire bonding machine, use AB glue to bond the memristor array to the chip carrier and place it on the tray. Then place the tray on the input material box and semi-automatically enter the welding workbench. Then clamp the tray, preheat the bottom of the chip, and set the welding parameters. After the gold wire is ignited and burned, enter the welding program, align the interface crosshairs with the metal surface to be welded, and weld the bottom electrode and top electrode of the device screened in step (3) to the chip carrier. After welding, remove the memristor chip carrier.

[0059] (5) Preparation of peripheral circuits: Use Altium Designer software to design peripheral circuits. On a single-layer circuit diagram, each node is connected to a multi-way switch to control different connection modes of the peripheral circuit and provide an interface with the chip carrier. Figure 4 It is an equivalent circuit diagram after the peripheral circuit is connected to the memristor in Example 1. After the peripheral circuit design is completed, a single-layer PCB is prepared according to the drawing.

[0060] (6) Array realization: After the packaged memristor chip is inserted into the designed pins of the peripheral circuit, different arrays can be realized by controlling the connection of multiple switches, including a 4×1 memristor array, a 2×2 memristor array, a 2×2 memristor array with changed relative positions of array points, and a 2×2 one Selector one Resistor (1S1R) memristor array with selection function.

[0061] Figure 5 is an equivalent circuit diagram of a 4×1 memristor array in Example 1; Figure 6 is an equivalent circuit diagram of a 2×2 memristor array in Example 1; Figure 7 is an equivalent circuit diagram of a 2×2 memristor array in which the relative positions of array points are changed in Example 1; Figure 8 1 is an equivalent circuit diagram of a 2×2 1S1R memristor array having a selection function by controlling a multi-way switch in Example 1.

[0062] Example 2

[0063] This embodiment provides a method for implementing a dynamically reconfigurable array based on nine oxide memristors, and implements four different memristor array structures by selecting the connection of peripheral circuits on different multi-layer PCBs. The specific steps are as follows:

[0064] (1) Cleaning the silicon wafer substrate: Same as step (1) in Example 1

[0065] (2) Preparation of memristor chip: same as step (2) in Example 1

[0066] (3) Screening of good quality memristor devices: The same as step (3) in Example 1, but nine devices with stable resistance switching behavior, good consistency and similar pulse response performance need to be selected for standby use.

[0067] (4) Welding and packaging of memristor chip and chip carrier: same as step (4) in Example 1

[0068] (5) Preparation of peripheral circuits: Use Altium Designer software to design a multi-layer peripheral circuit with four connection modes and an interface connected to the chip carrier. Prepare a multi-layer PCB according to the drawing, and the circuit of each layer of the PCB represents a connection mode.

[0069] (6) Array realization: After inserting the packaged memristor chip into the interface designed for the peripheral circuit, by selecting the peripheral circuits on different layers of the PCB, a 9×1 memristor array, a 3×3 memristor array, a 3×3 memristor array with changed relative positions of array points, and a 3×3 one diode one resistor (1D1R) memristor array with a rectifying effect realized by connecting diodes in series with the array points can be realized.

[0070] Fig. 9 is the equivalent circuit diagram of the 9×1 memristor array in Example 1; Fig.10 is the equivalent circuit diagram of the 3×3 memristor array in Example 1; Fig.11 is an equivalent circuit diagram of a 3×3 memristor array in which the relative positions of array points are changed in Example 1; Fig.12 3 is an equivalent circuit diagram of a 3×3 1D1R memristor array with a rectifying effect realized by adding diodes at array points in Example 1.

[0071] Example 3

[0072] This embodiment provides a method for implementing a dynamically reconfigurable memristor array that flexibly selects the number of memristor devices and the array structure. By packaging a single memristor device and inserting it into an interface provided by a peripheral circuit to determine the structure of the memristor array, a memristor array with a maximum number of rows and columns of no more than 10 can be implemented. This embodiment uses 12 packaged memristor devices to implement 3×4, 4×3, 2×6, and 6×2 memristor arrays. The specific steps are as follows:

[0073] (1) Preparation of single memristor devices: Based on the memristor structure and materials, a batch of memristor devices are prepared on each clean substrate.

[0074] (2) Packaging a single memristor device: Packaging the memristor device and connecting the top electrode and the bottom electrode to the DIP pins respectively.

[0075] (3) Preparation of peripheral circuit array: Design a cross peripheral circuit array of ten rows and ten columns, and provide an interface for connecting the packaged memristor device with external electrical components at the intersection of each row and each column of peripheral circuits. Fig.13 It is a circuit diagram of the peripheral circuit in Example 3. The peripheral circuit is prepared on the PCB according to the design drawing.

[0076] (4) Realize a memristor array: insert multiple packaged memristor devices into the interface of the peripheral circuit and form an array with a certain structure. Depending on the number of memristor devices and the position of the memristor devices, any memristor array with a number of rows and columns less than or equal to 10 can be constructed. Fig.14 This is a schematic diagram of 3×4, 4×3, 2×6 and 6×2 arrays implemented by inserting 12 devices in Example 3. The black dot represents a unit composed of a memristor and a gating device (transistor, diode, selector, etc.) connected in series. By selecting the input and output of the corresponding array, different array structures can be selected.

[0077] It will be easily understood by those skilled in the art that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A dynamically reconfigurable memristor array, characterized in that: The memristor array includes independent memristor devices and peripheral circuits. Any memristor device comprises a top electrode, a resistive layer and a bottom electrode from top to bottom. The top electrode and the bottom electrode of any memristor device are used to connect to a chip carrier. The pins of the chip carrier are selectively connected to the peripheral circuit through a multi-way switch. The chip carrier can dynamically change the structure of the memristor array by switching different connection modes with the peripheral circuit.

2. The dynamically reconfigurable memristor array according to claim 1, characterized in that: The structure of the memristor array includes the number of rows of the array, the number of columns of the array, the relative positions of array points, or whether electrical elements are connected in series at array points of the array.

3. The dynamically reconfigurable memristor array according to claim 1, characterized in that: When the memristor array includes 4 memristor devices, the memristor array is a 4×1 memristor array or a 2×2 memristor array.

4. The dynamically reconfigurable memristor array according to claim 1, characterized in that: When the memristor array includes 9 memristor devices, the memristor array is a 9×1 memristor array or a 3×3 memristor array.

5. The dynamically reconfigurable memristor array according to claim 1, characterized in that: When the memristor array includes 12 memristor devices, the memristor array is a 3×4 memristor array or a 2×6 memristor array.

6. The dynamically reconfigurable memristor array according to claim 2, characterized in that: The electrical element is a transistor, a selector or a diode.

7. The method for preparing a dynamically reconfigurable memristor array according to any one of claims 1 to 6, characterized in that: The following steps are involved: (1) preparing a plurality of independent memristor devices on a substrate and packaging them on a chip carrier, wherein the top electrode and the bottom electrode of each memristor device are respectively connected to the chip carrier; (2) selectively connecting the pins of the chip carrier in step (1) to the peripheral circuit through a multi-way switch; and connecting a plurality of memristor devices according to different connection modes between the peripheral circuit and the chip carrier to construct memristor arrays with different structures.

8. The preparation method according to claim 7, characterized in that: In step (1), the memristor device has a Crossbar architecture.

9. The preparation method according to claim 7, characterized in that: In step (2), the peripheral circuit is a printed circuit board.

10. The preparation method according to claim 7, characterized in that: In step (2), the chip carrier and the peripheral circuit are connected by gold wire ball welding, chip mounting or conductive silver glue connection.

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