Chip storage performance detection method and device

Abstract

The invention discloses a chip storage performance detection method and device, and the method comprises the steps: obtaining a detection information set of a chip, the detection information set comprises specification information of chip storage specifications, factor information of chip storage performance influence factors, and type information of data types of chip storage data; generating a plurality of storage performance test strategies of the chip by utilizing the detection information set, and recording test log information corresponding to each storage performance test strategy; and calculating a storage performance change value of the chip by adopting the test log information, and determining a storage performance detection result of the chip based on the storage performance change value. According to the invention, the test strategy is constructed through various information of the chip, and the comprehensive test is carried out in combination with different test strategies, so that the detection accuracy can be improved, the detection error can be reduced, and the existing detection requirements can be met.

Description

Background Art

[0002] With the rapid development of integrated circuit chips, users' requirements for the operating efficiency of integrated circuit chips are increasing day by day. However, in daily use, the actual storage performance of the chip often deviates from its storage specifications due to internal damage or data occupation. Therefore, it is necessary to test the storage performance of the chip.

[0003] In order to detect the storage performance of the chip, the commonly used method is: when other data processing functions of the chip are turned off and only the data storage function of the chip is opened, the identification information of the storage speed of the storage chip is obtained; based on the identification information, a detection scheme is determined; and then based on the detection scheme, a performance test is performed on the storage chip to obtain a performance test result.

[0004] However, the commonly used methods currently have the following technical problems: in the process of storing different data, different data information has different utilization rates of storage space. Therefore, the storage speeds of different data are also different. The accuracy of detection using storage speed is low and the error is large, which makes it difficult to meet existing detection needs. Summary of the invention

[0005] The present invention proposes a method and device for detecting chip storage performance. The method can perform comprehensive detection based on the storage specification information of the chip, storage performance influencing factors and storage data type, thereby improving detection accuracy and reducing detection errors.

[0006] A first aspect of an embodiment of the present invention provides a method for detecting chip storage performance, the method comprising:

[0007] Acquire a detection information set of the chip, wherein the detection information set includes specification information of chip storage specifications, factor information of factors affecting chip storage performance, and type information of a data type of chip storage data;

[0008] Generate multiple storage performance test strategies of the chip using the detection information set, and record the test log information corresponding to each storage performance test strategy;

[0009] The test log information is used to calculate a storage performance change value of the chip, and a storage performance detection result of the chip is determined based on the storage performance change value.

[0010] In combination with the first aspect, in one implementation, the step of generating multiple storage performance test strategies of a chip using the detection information set includes:

[0011] Dividing the type information into a plurality of data groups according to the data type, and arranging each of the data groups according to the amount of data to obtain a data sequence;

[0012] Based on the factor information, the data group and the data sequence, a plurality of storage performance test strategies of the chip are generated.

[0013] In combination with the first aspect, in one implementation, dividing the type information into multiple data groups according to the data type, and arranging each of the data groups according to the size of the data to obtain a data sequence includes:

[0014] Determine a data type of each of the type information, and divide the plurality of type information into different data groups according to the data types to obtain a plurality of data groups, each data group corresponding to a data type;

[0015] Determine target type information of each of the data groups, the target type information being type information of which the difference in data amount between type information of the data groups is equal to the unit data amount of the data type corresponding to the data group;

[0016] According to the data amount of the target type information, a plurality of the data groups are arranged to obtain a data sequence.

[0017] In combination with the first aspect, in one implementation, generating multiple storage performance test strategies for a chip based on the storage performance influencing factor information, the data group, and the data sequence includes:

[0018] Obtaining the influencing factor value range of each of the factor information, and screening the target influencing factor value in each of the influencing factor data ranges;

[0019] According to the single variable strategy, after constructing a storage performance influencing factor group using each target influencing factor value, a corresponding data test group is generated using the data group, the storage performance influencing factor group and the data sequence;

[0020] The test parameters of the chip are generated based on the data test group, and a plurality of storage performance test strategies are generated using the test parameters and a preset storage performance test template.

[0021] In combination with the first aspect, in one implementation, recording the test log information corresponding to each storage performance test strategy includes:

[0022] Sending each of the storage performance test strategies to a test client;

[0023] The test log information fed back by the test client is obtained, wherein the test log information includes a plurality of sub-test log information, and the sub-test log information is a test log obtained by performing distribution sorting processing on the storage performance test strategy in chronological order.

[0024] In combination with the first aspect, in one implementation, the calculating the storage performance change value of the chip by using the test log information includes:

[0025] Determine a test performance evaluation value of the chip according to the test log information, and determine a storage performance type corresponding to each test performance evaluation value;

[0026] The test type corresponding to the storage performance type is searched in the database, and the difference between the theoretical performance evaluation value and the test performance evaluation value corresponding to each test type is calculated to obtain the storage performance change value, wherein the theoretical performance evaluation value is the evaluation value of the chip storage performance obtained after identifying the storage specification information.

[0027] In combination with the first aspect, in one implementation, determining the test performance evaluation value of the chip according to the test log information includes:

[0028] Extracting log distribution information from the test log information, the log distribution information including: state distribution information and energy consumption distribution information;

[0029] After obtaining the test indicators corresponding to the log distribution information, the log distribution information is subjected to performance evaluation processing using the test indicators to obtain the test indicator value of each test type;

[0030] After obtaining the impact weight value of the test type corresponding to the log distribution information, the impact weight value and the corresponding test index value are weighted to obtain a test performance evaluation value corresponding to each test type.

[0031] In combination with the first aspect, in one implementation, extracting log distribution information from the test log information includes:

[0032] Determine the test distribution information corresponding to each sub-test log information in the test log information to obtain log distribution information;

[0033] According to the test type corresponding to the chip storage state, the corresponding test distribution information is extracted from the log distribution information to obtain the state distribution information;

[0034] According to the test type corresponding to the chip storage energy consumption, the corresponding test distribution information is extracted from the log distribution information to obtain the energy consumption distribution information.

[0035] In conjunction with the first aspect, in one implementation, the storage performance test result includes: a first test result, a second test result, and a third test result;

[0036] The step of determining a storage performance test result of a chip based on the storage performance change value includes:

[0037] Randomly select one of the plurality of storage performance test strategies as a target test strategy, and determine a first detection result of the chip in the storage state based on the storage performance change value corresponding to the target test strategy;

[0038] Identify the storage performance change value of the storage performance test strategy corresponding to each of the factor information of the chip, and obtain a second detection result of the chip's resistance to the influence of each storage performance influencing factor;

[0039] The storage performance change value of the storage performance test strategy corresponding to each type information of the chip is identified to obtain a third detection result of the chip for each data type.

[0040] A second aspect of an embodiment of the present invention provides a device for detecting chip storage performance, the device comprising:

[0041] An acquisition module, used for acquiring a detection information set of a chip, wherein the detection information set includes specification information of chip storage specifications, factor information of factors affecting chip storage performance, and type information of a data type of chip storage data;

[0042] An information recording module, used to generate multiple storage performance test strategies of the chip using the detection information set, and record the test log information corresponding to each storage performance test strategy;

[0043] The detection result module is used to calculate the storage performance change value of the chip using the test log information, and determine the storage performance detection result of the chip based on the storage performance change value.

[0044] In conjunction with the second aspect, in one implementation, the step of generating multiple storage performance test strategies for a chip using the detection information set includes:

[0045] Dividing the type information into a plurality of data groups according to the data type, and arranging each of the data groups according to the amount of data to obtain a data sequence;

[0046] Based on the factor information, the data group and the data sequence, a plurality of storage performance test strategies of the chip are generated.

[0047] In conjunction with the second aspect, in one implementation, dividing the type information into multiple data groups according to the data type, and arranging each of the data groups according to the size of the data to obtain a data sequence includes:

[0048] Determine a data type of each of the type information, and divide the plurality of type information into different data groups according to the data types to obtain a plurality of data groups, each data group corresponding to a data type;

[0049] Determine target type information of each of the data groups, the target type information being type information of which the difference in data amount between type information of the data groups is equal to the unit data amount of the data type corresponding to the data group;

[0050] According to the data amount of the target type information, a plurality of the data groups are arranged to obtain a data sequence.

[0051] In conjunction with the second aspect, in one implementation, generating multiple storage performance test strategies for a chip based on the storage performance influencing factor information, the data group, and the data sequence includes:

[0052] Obtaining the influencing factor value range of each of the factor information, and screening the target influencing factor value in each of the influencing factor data ranges;

[0053] According to the single variable strategy, after constructing a storage performance influencing factor group using each target influencing factor value, a corresponding data test group is generated using the data group, the storage performance influencing factor group and the data sequence;

[0054] The test parameters of the chip are generated based on the data test group, and a plurality of storage performance test strategies are generated using the test parameters and a preset storage performance test template.

[0055] In conjunction with the second aspect, in one implementation, recording the test log information corresponding to each storage performance test strategy includes:

[0056] Sending each of the storage performance test strategies to a test client;

[0057] The test log information fed back by the test client is obtained, wherein the test log information includes a plurality of sub-test log information, and the sub-test log information is a test log obtained by performing distribution sorting processing on the storage performance test strategy in chronological order.

[0058] In conjunction with the second aspect, in one implementation, the calculating the storage performance change value of the chip by using the test log information includes:

[0059] Determine a test performance evaluation value of the chip according to the test log information, and determine a storage performance type corresponding to each test performance evaluation value;

[0060] The test type corresponding to the storage performance type is searched in the database, and the difference between the theoretical performance evaluation value and the test performance evaluation value corresponding to each test type is calculated to obtain the storage performance change value, wherein the theoretical performance evaluation value is the evaluation value of the chip storage performance obtained after identifying the storage specification information.

[0061] In conjunction with the second aspect, in one implementation, determining the test performance evaluation value of the chip according to the test log information includes:

[0062] Extracting log distribution information from the test log information, the log distribution information including: state distribution information and energy consumption distribution information;

[0063] After obtaining the test indicators corresponding to the log distribution information, the log distribution information is subjected to performance evaluation processing using the test indicators to obtain the test indicator value of each test type;

[0064] After obtaining the impact weight value of the test type corresponding to the log distribution information, the impact weight value and the corresponding test index value are weighted to obtain a test performance evaluation value corresponding to each test type.

[0065] In conjunction with the second aspect, in one implementation, extracting log distribution information from the test log information includes:

[0066] Determine the test distribution information corresponding to each sub-test log information in the test log information to obtain log distribution information;

[0067] According to the test type corresponding to the chip storage state, the corresponding test distribution information is extracted from the log distribution information to obtain the state distribution information;

[0068] According to the test type corresponding to the chip storage energy consumption, the corresponding test distribution information is extracted from the log distribution information to obtain the energy consumption distribution information.

[0069] In conjunction with the second aspect, in one implementation, the storage performance test result includes: a first test result, a second test result, and a third test result;

[0070] The step of determining a storage performance test result of a chip based on the storage performance change value includes:

[0071] Randomly select one of the plurality of storage performance test strategies as a target test strategy, and determine a first detection result of the chip in the storage state based on the storage performance change value corresponding to the target test strategy;

[0072] Identify the storage performance change value of the storage performance test strategy corresponding to each of the factor information of the chip, and obtain a second detection result of the chip's resistance to the influence of each storage performance influencing factor;

[0073] The storage performance change value of the storage performance test strategy corresponding to each type information of the chip is identified to obtain a third detection result of the chip for each data type.

[0074] Compared with the prior art, the embodiments of the present invention provide a method and device for detecting chip storage performance, which have the following beneficial effects: the present invention obtains a detection information set of a chip; uses the detection information set to generate multiple storage performance test strategies for the chip, and records the test log information corresponding to each storage performance test strategy; uses the test log information to calculate the storage performance change value of the chip, and determines the storage performance test result of the chip based on the storage performance change value; the present invention constructs a test strategy through various information of the chip, and then combines different test strategies for comprehensive testing, thereby improving the accuracy of detection and reducing detection errors to meet existing detection needs. BRIEF DESCRIPTION OF THE DRAWINGS

[0075] Figure 1 It is a flowchart of a method for detecting chip storage performance provided by one embodiment of the present invention;

[0076] Figure 2 It is a structural schematic diagram of a chip storage performance detection device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0077] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0078] With the rapid development of integrated circuit chips, users' requirements for the operating efficiency of integrated circuit chips are increasing day by day. However, in daily use, the actual storage performance of the chip often deviates from its storage specifications due to internal damage or data occupation. Therefore, it is necessary to test the storage performance of the chip.

[0079] In order to detect the storage performance of the chip, the commonly used method is: when other data processing functions of the chip are turned off and only the data storage function of the chip is opened, the identification information of the storage speed of the storage chip is obtained; based on the identification information, a detection scheme is determined; and then based on the detection scheme, a performance test is performed on the storage chip to obtain a performance test result.

[0080] However, the commonly used methods currently have the following technical problems: in the process of storing different data, different data information has different utilization rates of storage space. Therefore, the storage speeds of different data are also different. The accuracy of detection using storage speed is low and the error is large, which makes it difficult to meet existing detection needs.

[0081] In order to solve the above problems, a chip storage performance detection method provided in an embodiment of the present application will be introduced and explained in detail through the following specific embodiments.

[0082] Reference Figure 1 , showing a flow chart of a method for detecting chip storage performance provided by an embodiment of the present invention.

[0083] In one embodiment, the chip storage performance detection method can be applied to a chip detection system, which can be a computer or an intelligent terminal. The chip detection system can be connected to multiple clients for communication, and the client can be a client of a technician who performs the detection work.

[0084] Wherein, as an example, the chip storage performance detection method may include:

[0085] S11. Acquire a detection information set of a chip, wherein the detection information set includes specification information of chip storage specifications, factor information of factors affecting chip storage performance, and type information of data type of chip storage data.

[0086] In this embodiment, the chip detection system can respond to the user's operation of uploading information and obtain a detection information set.

[0087] The detection information set may include: specification information about chip storage specifications, factor information about factors affecting chip storage performance, and type information about the data type of chip storage data.

[0088] In one embodiment, the specification information about the chip storage specifications may be the storage specification introduction information in the chip introduction information of the chip when it leaves the factory. The specification information may include storage rate, storage capacity, service life, resistance to various storage performance influencing factors, etc., which can be specifically found from the historical database.

[0089] Similarly, factor information about factors affecting chip storage performance may also be searched in the historical database, and the factor information may include multiple factors affecting chip storage performance and the value range of each factor. Among them, the factors may include temperature factors, humidity factors, pressure factors, etc. The value range of the factors may be the value range of the factors of each factor in the historical period.

[0090] Similarly, type information about the data type of data stored in the chip can also be found in the historical database. The type information may include the data type of different data obtained by the chip, where the data volume of the type information of each data type is different, and the data type may include text type, picture type, video type, audio type, etc.

[0091] S12. Generate multiple storage performance test strategies for the chip using the detection information set, and record test log information corresponding to each storage performance test strategy.

[0092] After obtaining the detection information set, multiple different storage performance test strategies can be constructed according to the data type of the detection information set, the chip storage specification, and the chip storage performance influencing factors. For example, the first storage performance test strategy can be generated for chip storage specification A, humidity influencing factors, and text type; the second storage performance test strategy can be generated for chip storage specification B, pressure influencing factors, and picture type; and the third storage performance test strategy can be generated for chip storage specification C, temperature influencing factors, and audio type.

[0093] In order to perform detection processing for each storage performance test policy, multiple storage performance test policies can be sent to multiple clients of the technician respectively, so that the technician of each client can perform a detection processing according to the storage performance test policy.

[0094] After completing the inspection according to the storage performance test strategy, the technician can record various test information of the chip and upload the test information to the system through its client terminal, and obtain the test log information corresponding to each storage performance test strategy.

[0095] The test log information may include: chip energy consumption record information, storage capacity record information, storage rate record information, storage duration record information, etc.

[0096] In an optional embodiment, the detection information set includes multiple contents, in order to generate different storage performance test strategies for various information in the detection information set, so as to facilitate technicians to perform test processing for different storage performance test strategies. As an example, the use of the detection information set to generate multiple storage performance test strategies for the chip may include the following sub-steps:

[0097] S121. Divide the type information into multiple data groups according to data types, and arrange each data group according to the size of the data to obtain a data sequence.

[0098] In one embodiment, since there are multiple types of data that can be stored in the chip, in order to distinguish data of different data types, the type information can be divided into multiple data groups according to the data type. Each data group can contain one or more type information, and each type of information can correspond to one or more chip storage specifications. Similarly, each type of information can correspond to one or more chip storage performance influencing factors.

[0099] After multiple data groups are obtained through division, the type information in each data group may be sorted according to the amount of data contained in the type information in the data group, so as to obtain a data sequence corresponding to each data group.

[0100] In an optional embodiment, each data group may include one or more type information, and the data volume of each type information is different. In order to arrange the multiple type information included in each data group according to the size of the data volume, as an example, the type information is divided into multiple data groups according to the data type, and each of the data groups is arranged according to the size of the data volume to obtain a data sequence, which may include the following sub-steps:

[0101] S1211. Determine a data type of each type of information, and divide the multiple types of information into different data groups according to the data types to obtain multiple data groups, each data group corresponding to a data type.

[0102] S1212. Determine target type information for each of the data groups, where the target type information is type information in which the difference in data volume between type information of the data groups is equal to the unit data volume of the data type corresponding to the data group.

[0103] S1213. Arrange the plurality of data groups according to the data volume of the target type information to obtain a data sequence.

[0104] Specifically, after dividing multiple types of information into multiple data groups according to data types, the data groups corresponding to each data type can be obtained, and then the unit data volume of each data type can be obtained. The unit data volume can be the data change volume of each data type of the preset system, for example, the unit data volume of the text type is 100 words / symbols; the unit data volume of the picture type with the same resolution is 100 pixels, the unit data volume of the video type with the same resolution is 10S video segment; the unit data volume of the audio type with the same sound quality is 5S audio segment.

[0105] Then, the data volume of each type of information in each data group can be obtained, wherein the data volume can be directly identified, for example, the data volume in KB or MB.

[0106] Next, the difference in data volume may be calculated, specifically, the difference in data volume between the data information. The difference in data volume between the data information in each data group may be calculated.

[0107] Then, the data amount difference is selected from the multiple data amount differences of each data group as the data amount difference of the unit data amount of the data type corresponding to the data group, which is used as the target difference, and the type information corresponding to the target difference is used as the target type information.

[0108] Next, the data size of each target type information in each data group can be obtained, and then for each data group, the target type information of each data group can be arranged in order from small to large according to the data size of the target type information to obtain the data sequence of each data group.

[0109] Based on the above processing, the present invention can form each data group by screening the target type information of the difference in unit data volume, thereby improving the regularity and comprehensiveness of the data information contained in each data group.

[0110] S122. Generate multiple storage performance test strategies for the chip based on the factor information, the data group and the data sequence.

[0111] After obtaining the data sequence, multiple storage performance test strategies for the chip can be generated based on the factor information, data group and data sequence. Optionally, the above factor information, data group and data sequence can be combined in different ways to generate multiple storage performance test strategies for the chip.

[0112] In an optional embodiment, the generating multiple storage performance test strategies of the chip based on the storage performance influencing factor information, the data group and the data sequence may include the following sub-steps:

[0113] S1221. Obtain a numerical range of influencing factors of each of the factor information, and filter a target influencing factor numerical value in each of the influencing factor data ranges.

[0114] S1222. According to the single variable strategy, after constructing a storage performance influencing factor group using the numerical value of each target influencing factor, generate a corresponding data test group using the data group, the storage performance influencing factor group and the data sequence.

[0115] S1223. Generate chip test parameters based on the data test group, and use the test parameters and a preset storage performance test template to generate multiple storage performance test strategies.

[0116] Specifically, the influencing factor value range of the factor information of each storage performance influencing factor can be obtained, and based on the random screening strategy, a target influencing factor value is screened in the influencing factor data range of each storage performance influencing factor to obtain the target influencing factor value of each storage performance influencing factor.

[0117] Based on the target influencing factor value of each storage performance influencing factor, multiple storage performance influencing factor groups are constructed according to the single variable strategy. Then, based on each data group, each storage performance influencing factor group, and the data sequence of each data group, a data test group corresponding to each storage performance influencing factor group is generated; finally, based on the data test group corresponding to each survival performance influencing factor group, multiple storage performance test strategies for the chip are generated.

[0118] Each storage performance influencing factor group may include individual influencing factor values ​​of different influencing factors. The data test group corresponding to each influencing factor group may include type information of individual data quantities of different data types.

[0119] Specifically, based on each storage performance influencing factor group, the influencing factor values ​​of the storage performance influencing factors of the data content of each type of information in each data group can be adjusted respectively to obtain the data test group corresponding to each storage performance influencing factor group. In generating the data test group corresponding to each storage performance influencing factor group, the test sequence of the data test group is determined after sorting the data sequence of the data group where each type of information in the data test group is located.

[0120] After determining the data test group corresponding to each storage performance influencing factor group, test parameters of multiple storage performance test strategies of the chip can be generated, and then multiple storage performance test strategies can be obtained by replacing the parameters in the preset storage performance test template with the test parameters.

[0121] It should be noted that the preset storage performance test template sets the chip in an environment with different influencing factor values ​​of different influencing factors, repeatedly stores the type information of a single data amount of a single data type in the chip, and after the storage is completed, calls each type of information in the chip until all the test strategy templates corresponding to the type information are called.

[0122] Based on the above scheme, the present invention can construct a corresponding storage performance test strategy through a single variable method to improve the comprehensiveness and precision of constructing the storage performance test strategy.

[0123] In an optional embodiment, after generating multiple storage performance test strategies, it is necessary to perform corresponding test processing for each storage performance test strategy to detect the performance of the chip. In order to record the test records of the test processing corresponding to each storage performance test strategy, as an example, the test log information corresponding to each storage performance test strategy may include the following sub-steps:

[0124] S123: Send each of the storage performance test strategies to a test client.

[0125] S124: Acquire test log information fed back by the test client, wherein the test log information includes a plurality of sub-test log information, and the sub-test log information is a test log obtained by performing distribution sorting processing on the storage performance test strategy in chronological order.

[0126] Specifically, each storage performance test strategy can be sent to the client of each technician, so that each technician can perform the test processing corresponding to the chip storage performance according to the storage performance test strategy displayed by the client.

[0127] After completing the test process, each technician will record various information of the test process and record it in his client, and the client will upload various information of the test process.

[0128] After receiving each test record information of each storage performance test strategy, distribution sorting processing is performed in chronological order to obtain sub-test log information corresponding to each test record information, and all sub-test log information is used as the test log information of the storage performance test strategy.

[0129] Based on the above solution, the present invention can improve the recognizability and distinguishability of the obtained test log information by classifying and aggregating the test record information.

[0130] S13. Calculate the storage performance change value of the chip using the test log information, and determine the storage performance test result of the chip based on the storage performance change value.

[0131] In one embodiment, after obtaining the test log information of the test processing, the test log information can be used to calculate the storage performance change value of the chip. The storage performance change value can be the change value of its parameters when the chip stores different data according to the storage performance test strategy, such as the input rate of storage data, the rate of change of capacity, and the change value of capacity, etc.

[0132] Finally, the storage performance test result of the chip is determined by the size of the storage performance change value. The storage performance test result may include: various storage state test results of the chip, various impact resistance test results of the chip, and various storage type test results of the chip. The storage performance change value may include: different test performance evaluation values, and the deviation value between the theoretical performance evaluation values ​​corresponding to each test performance evaluation value.

[0133] For example, when storing type A data according to the storage performance test strategy, the difference between the input rate of the stored data and the input rate of the chip specification information is 0.5, and the difference between the change rate of the capacity and the change rate of the chip specification information is 0.6. 0.5 is less than the input threshold (for example, 1), and 0.6 is also less than the change threshold (for example, 1). It can be determined that the storage performance test result of the chip is that the storage of type A data is abnormal.

[0134] Similarly, when storing type B data according to the storage performance test strategy, the difference between the input rate of the stored data and the input rate of the chip specification information is 1.5, and the difference between the change rate of the capacity and the change rate of the chip specification information is 1.6. 1.5 is greater than the input threshold (for example, 1), and 1.6 is also greater than the change threshold (for example, 1). It can be determined that the storage performance test result of the chip is normal for storing type B data.

[0135] In one embodiment, in order to accurately calculate the storage performance change value of the chip according to the test log information, as an example, the calculation of the storage performance change value of the chip using the test log information may include the following sub-steps:

[0136] S131. Determine a test performance evaluation value of a chip according to the test log information, and determine a storage performance type corresponding to each test performance evaluation value.

[0137] S132. Search the database for the test type corresponding to the storage performance type, and calculate the difference between the theoretical performance evaluation value and the test performance evaluation value corresponding to each test type to obtain a storage performance change value, wherein the theoretical performance evaluation value is an evaluation value of the chip storage performance obtained after identifying the storage specification information.

[0138] In one embodiment, for each storage performance test strategy, a test performance evaluation value of the chip can be calculated based on the test log information of each storage performance test strategy, and each test performance evaluation value is an evaluation value of the chip storage performance corresponding to each storage performance test strategy.

[0139] Next, the storage performance type corresponding to each test performance evaluation value can be determined. Specifically, the test type corresponding to the storage performance type can be searched in the database, and the difference between the theoretical performance evaluation value and the test performance evaluation value corresponding to each test type can be calculated to obtain the storage performance change value, wherein the theoretical performance evaluation value is the evaluation value of the chip storage performance obtained after identifying the storage specification information.

[0140] Specifically, it is also possible to identify the storage performance type to which each theoretical performance evaluation value belongs, and to query the test type corresponding to each storage performance type in the database; based on the test type corresponding to each storage performance type, calculate the deviation value between the test performance evaluation value corresponding to each test type and the theoretical performance evaluation value of the storage performance type corresponding to the test type, and use the deviation value as the storage performance change value of each storage performance type; the storage performance change value may also be used as the storage performance change value corresponding to the storage performance test strategy.

[0141] In this embodiment, the storage performance type to which each theoretical performance evaluation value belongs is preset in the database. The test type corresponding to each storage performance type is a corresponding relationship pre-stored by the technician and stored in the database.

[0142] Based on the above scheme, the present invention obtains the storage performance change value corresponding to the storage performance test strategy by calculating the deviation value of the storage performance type corresponding to various test types, thereby improving the comprehensiveness and calculation accuracy of the storage performance change value corresponding to the storage performance test strategy.

[0143] In one embodiment, the test log information may record a variety of different test contents and test parameters. In order to extract relevant information that can evaluate the test performance and calculate the test performance evaluation value using the relevant information, as an example, determining the test performance evaluation value of the chip according to the test log information may include the following sub-steps:

[0144] S1311. Extract log distribution information from the test log information, where the log distribution information includes: state distribution information and energy consumption distribution information.

[0145] S1312: After obtaining the test indicators corresponding to the log distribution information, use the test indicators to perform performance evaluation processing on the log distribution information to obtain the test indicator value of each test type.

[0146] S1313. After obtaining the impact weight value of the test type corresponding to the log distribution information, weighted processing is performed using the impact weight value and the corresponding test index value to obtain a test performance evaluation value corresponding to each test type.

[0147] Specifically, log distribution information may be first extracted from the test log information, and the log distribution information may include: state distribution information and energy consumption distribution information.

[0148] The state distribution information may be each test distribution information of the test type corresponding to the chip storage state in the test log information, and the energy consumption distribution information may be each test distribution information of the test type corresponding to the chip storage energy consumption distribution information in the test log information.

[0149] Next, the test indicators corresponding to the test types of each test distribution information in the state distribution information can be identified, that is, the test indicators corresponding to the test types of the state distribution information. Then, the test indicators corresponding to the test types of each test distribution information in the energy consumption distribution information can be identified, that is, the test indicators corresponding to the test types of the energy consumption distribution information. Based on the test indicators corresponding to each test type, the test distribution information corresponding to each test type is subjected to performance evaluation processing to obtain the test indicator value of each test type.

[0150] The weight of each test type in the chip storage status that affects the storage performance is collected, as is the weight of each test type in the chip storage energy consumption that affects the storage performance. Based on the weight of the impact of various test types on the storage performance, the indicator value of each test type is weighted to obtain the test performance evaluation value corresponding to each test type.

[0151] In this embodiment, the sum of the impact weights of all test types is 1. The impact weights of each test type of storage status and the impact weights of each test type of storage energy consumption can be manually adjusted according to the test results or actual needs.

[0152] Based on the above scheme, the present invention performs weighted processing on the index value of each test type by calculating the influence weight of each test type to obtain the test performance evaluation value corresponding to each test type, thereby improving the practicality of the obtained test performance evaluation value.

[0153] Wherein, as an example, the extracting log distribution information from the test log information may include the following sub-steps:

[0154] S13111. Determine the test distribution information corresponding to each sub-test log information in the test log information to obtain log distribution information.

[0155] S13112. Extract corresponding test distribution information from the log distribution information according to the test type corresponding to the chip storage status, and obtain status distribution information.

[0156] S13113. Extract corresponding test distribution information from the log distribution information according to the test type corresponding to the chip storage energy consumption, and obtain energy consumption distribution information.

[0157] Specifically, the test type corresponding to each sub-test log information of the storage performance test strategy and the test distribution information of each sub-test log information can be identified, and then the test type corresponding to the chip storage state and the test type corresponding to the chip storage energy consumption are collected.

[0158] According to the test type corresponding to the chip storage state, the test distribution information is extracted to obtain the chip state distribution information. Similarly, according to the test type corresponding to the chip storage energy consumption, the test distribution information is extracted to obtain the chip energy consumption distribution information.

[0159] In this embodiment, the test type corresponding to each sub-test log information of the storage performance test strategy and the test distribution information of each sub-test log information are identified. The test type may include: storage capacity test type, storage rate test type, chip energy consumption test type, and storage duration test type.

[0160] Based on the above solution, the present invention can improve the recognition accuracy of each test distribution information by dividing different test types into storage states and storage energy consumption.

[0161] In one of the embodiments, the storage performance test strategy is a test strategy constructed based on different storage performance influencing factors and different data types. Different storage performance change values ​​can be obtained for different strategies. In order to determine the detection results of different storage performance influencing factors and different data types, the storage performance detection results include: a first detection result, a second detection result and a third detection result.

[0162] Among them, the first test result is the test result of the storage status of the chip under test; the second test result is the test result of the factors affecting the storage performance of the chip under test; and the third test result is the test result of the data type of the data stored in the chip under test.

[0163] Wherein, as an example, the determining of the storage performance detection result of the chip based on the storage performance change value may include the following sub-steps:

[0164] S133. Randomly select one of the multiple storage performance test strategies as a target test strategy, and determine a first detection result of the chip in the storage state based on the storage performance change value corresponding to the target test strategy.

[0165] S134. Identify the storage performance change value of the storage performance test strategy corresponding to each of the factor information of the chip, and obtain a second detection result of the chip's resistance to the influence of each storage performance influencing factor.

[0166] S135. Identify the storage performance change value of the storage performance test strategy corresponding to each type information of the chip, and obtain a third detection result of the chip for each data type.

[0167] Specifically, one of the storage performance test strategies can be randomly selected as a target storage performance test strategy; then, based on the storage performance change value of the target storage performance test strategy, the detection results of each storage state of the chip are identified to obtain a first detection result. Among them, each storage performance test strategy corresponding to the storage performance influencing factor is a storage performance test strategy with the storage performance influencing factor as a single variable; each storage performance test strategy corresponding to the data type is a storage performance test strategy with the data volume of each data type as a single variable.

[0168] Similarly, based on the storage performance change value of the storage performance test strategy corresponding to each storage performance influencing factor, the chip's impact resistance test result for each storage performance influencing factor can be identified to obtain a second test result. The impact resistance test result is the range of change of each storage performance change information of the chip under the change of the storage performance influencing factor. The storage status test result is the actual capacity value, actual storage rate, actual storage life, and chip energy consumption corresponding to the actual unit data volume of the chip.

[0169] Based on the storage performance change value of the storage performance test strategy corresponding to the data type, the storage type detection result of the chip for each data type is identified to obtain a third detection result. The storage type detection result includes the capacity value change information, storage rate change information, storage life change information, and chip energy consumption change information of each data volume of different data types.

[0170] Based on the above solution, the chip's target storage performance test results are obtained by conducting overall analysis and testing from multiple angles, multiple levels, and fine granularity, thereby improving the accuracy of the chip storage performance tested.

[0171] Based on the above scheme, multiple storage performance test strategies for the chip are generated from the perspectives of data type, data volume, and factors affecting chip storage performance, thereby improving the comprehensiveness and precision of chip testing. Then, by identifying the distribution information corresponding to the test log information of each storage performance test strategy, performance evaluation is performed to obtain the storage performance change value of the chip, thereby improving the accuracy and comprehensiveness of the detection and evaluation. Finally, the target storage performance test results of the chip are generated through the storage performance change values ​​corresponding to different storage performance test strategies, thereby avoiding the problem of poor comprehensiveness of detection caused by too little data, so that this scheme performs overall analysis and detection from multiple angles, multiple levels, and fine granularity to obtain the target storage performance test results of the chip. Thereby improving the accuracy of the detected chip storage performance.

[0172] In this embodiment, the embodiment of the present invention provides a method for detecting chip storage performance, and its beneficial effects are: the present invention obtains a detection information set of a chip; uses the detection information set to generate multiple storage performance test strategies of the chip, and records the test log information corresponding to each storage performance test strategy; uses the test log information to calculate the storage performance change value of the chip, and determines the storage performance detection result of the chip based on the storage performance change value; the present invention constructs a test strategy through various information of the chip, and then combines different test strategies for comprehensive testing, thereby improving the accuracy of detection and reducing detection errors to meet existing detection needs.

[0173] The present invention also provides a device for detecting chip storage performance. Figure 2 , showing a schematic structural diagram of a chip storage performance detection device provided by an embodiment of the present invention.

[0174] Wherein, as an example, the chip storage performance detection device may include:

[0175] An acquisition module 201 is used to acquire a detection information set of a chip, wherein the detection information set includes specification information of chip storage specifications, factor information of factors affecting chip storage performance, and type information of a data type of chip storage data;

[0176] The information recording module 202 is used to generate multiple storage performance test strategies of the chip using the detection information set, and record the test log information corresponding to each storage performance test strategy;

[0177] The detection result module 203 is used to calculate the storage performance change value of the chip using the test log information, and determine the storage performance detection result of the chip based on the storage performance change value.

[0178] Optionally, the generating a plurality of storage performance test strategies of the chip by using the detection information set includes:

[0179] Dividing the type information into a plurality of data groups according to the data type, and arranging each of the data groups according to the amount of data to obtain a data sequence;

[0180] Based on the factor information, the data group and the data sequence, a plurality of storage performance test strategies of the chip are generated.

[0181] Optionally, dividing the type information into a plurality of data groups according to data types, and arranging each of the data groups according to the size of the data to obtain a data sequence includes:

[0182] Determine a data type of each of the type information, and divide the plurality of type information into different data groups according to the data types to obtain a plurality of data groups, each data group corresponding to a data type;

[0183] Determine target type information of each of the data groups, the target type information being type information of which the difference in data amount between type information of the data groups is equal to the unit data amount of the data type corresponding to the data group;

[0184] According to the data amount of the target type information, a plurality of the data groups are arranged to obtain a data sequence.

[0185] Optionally, generating a plurality of storage performance test strategies of a chip based on the storage performance influencing factor information, the data group and the data sequence includes:

[0186] Obtaining the influencing factor value range of each of the factor information, and screening the target influencing factor value in each of the influencing factor data ranges;

[0187] According to the single variable strategy, after constructing a storage performance influencing factor group using each target influencing factor value, a corresponding data test group is generated using the data group, the storage performance influencing factor group and the data sequence;

[0188] The test parameters of the chip are generated based on the data test group, and a plurality of storage performance test strategies are generated using the test parameters and a preset storage performance test template.

[0189] Optionally, recording the test log information corresponding to each storage performance test strategy includes:

[0190] Sending each of the storage performance test strategies to a test client;

[0191] The test log information fed back by the test client is obtained, wherein the test log information includes a plurality of sub-test log information, and the sub-test log information is a test log obtained by performing distribution sorting processing on the storage performance test strategy in chronological order.

[0192] Optionally, the calculating the storage performance change value of the chip by using the test log information includes:

[0193] Determine a test performance evaluation value of the chip according to the test log information, and determine a storage performance type corresponding to each test performance evaluation value;

[0194] The test type corresponding to the storage performance type is searched in the database, and the difference between the theoretical performance evaluation value and the test performance evaluation value corresponding to each test type is calculated to obtain the storage performance change value, wherein the theoretical performance evaluation value is the evaluation value of the chip storage performance obtained after identifying the storage specification information.

[0195] Optionally, determining the test performance evaluation value of the chip according to the test log information includes:

[0196] Extracting log distribution information from the test log information, the log distribution information including: state distribution information and energy consumption distribution information;

[0197] After obtaining the test indicators corresponding to the log distribution information, the log distribution information is subjected to performance evaluation processing using the test indicators to obtain the test indicator value of each test type;

[0198] After obtaining the impact weight value of the test type corresponding to the log distribution information, the impact weight value and the corresponding test index value are weighted to obtain a test performance evaluation value corresponding to each test type.

[0199] Optionally, extracting log distribution information from the test log information includes:

[0200] Determine the test distribution information corresponding to each sub-test log information in the test log information to obtain log distribution information;

[0201] According to the test type corresponding to the chip storage state, the corresponding test distribution information is extracted from the log distribution information to obtain the state distribution information;

[0202] According to the test type corresponding to the chip storage energy consumption, the corresponding test distribution information is extracted from the log distribution information to obtain the energy consumption distribution information.

[0203] Optionally, the storage performance test result includes: a first test result, a second test result and a third test result;

[0204] The step of determining a storage performance test result of a chip based on the storage performance change value includes:

[0205] Randomly select one of the plurality of storage performance test strategies as a target test strategy, and determine a first detection result of the chip in the storage state based on the storage performance change value corresponding to the target test strategy;

[0206] Identify the storage performance change value of the storage performance test strategy corresponding to each of the factor information of the chip, and obtain a second detection result of the chip's resistance to the influence of each storage performance influencing factor;

[0207] The storage performance change value of the storage performance test strategy corresponding to each type information of the chip is identified to obtain a third detection result of the chip for each data type.

[0208] Those skilled in the art can clearly understand that, for the sake of convenience and brevity of description, the specific working process of the device described above can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here.

[0209] Furthermore, an embodiment of the present application also provides an electronic device, comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, the method for detecting chip storage performance as described in the above embodiment is implemented.

[0210] Furthermore, an embodiment of the present application also provides a computer-readable storage medium, which stores a computer-executable program, and the computer-executable program is used to enable a computer to execute the chip storage performance detection method as described in the above embodiment.

[0211] It should be noted that the orientation or positional relationship indicated by the terms "upper", "lower", etc. is based on the orientation or positional relationship shown in the accompanying drawings, which is only for the convenience of describing the embodiments of the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation of the present invention. When an element such as a layer, region or substrate is referred to as being "on" or "above" another element, it can be directly on the other element, or there can also be an intermediate element. On the contrary, when an element is referred to as "directly on" or "above" another element, there is no intermediate element. It should also be understood that when an element is referred to as being "under" or "below" another element, it can be directly under or below the other element, or there can also be an intermediate element. On the contrary, when an element is referred to as being "directly under" or "below" another element, there is no intermediate element. Unless otherwise clearly specified and limited, the terms "installed", "connected" and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0212] Those skilled in the art will appreciate that the embodiments of the present application may also provide computer program products. Therefore, the present application may adopt the form of complete hardware embodiments, complete software embodiments, or embodiments in combination with software and hardware. Moreover, the present application may adopt the form of computer program products implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program codes.

[0213] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), apparatuses, and computer program products according to the embodiments of the present application. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0214] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0215] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0216] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the technical principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A method for detecting chip storage performance, characterized in that: The method comprises: Acquire a detection information set of the chip, wherein the detection information set includes specification information of chip storage specifications, factor information of factors affecting chip storage performance, and type information of a data type of chip storage data; Generate multiple storage performance test strategies of the chip using the detection information set, and record the test log information corresponding to each storage performance test strategy; The test log information is used to calculate a storage performance change value of the chip, and a storage performance detection result of the chip is determined based on the storage performance change value.

2. The method for detecting chip storage performance according to claim 1, characterized in that: The method of using the detection information set to generate multiple storage performance test strategies for the chip includes: Dividing the type information into a plurality of data groups according to the data type, and arranging each of the data groups according to the amount of data to obtain a data sequence; Based on the factor information, the data group and the data sequence, a plurality of storage performance test strategies of the chip are generated.

3. The method for detecting chip storage performance according to claim 2, characterized in that: The step of dividing the type information into a plurality of data groups according to the data type, and arranging each of the data groups according to the amount of data to obtain a data sequence includes: Determine a data type of each of the type information, and divide the plurality of type information into different data groups according to the data types to obtain a plurality of data groups, each data group corresponding to a data type; Determine target type information of each of the data groups, the target type information being type information of which the difference in data amount between type information of the data groups is equal to the unit data amount of the data type corresponding to the data group; According to the data amount of the target type information, a plurality of the data groups are arranged to obtain a data sequence.

4. The method for detecting chip storage performance according to claim 2, characterized in that: The generating a plurality of storage performance test strategies of the chip based on the storage performance influencing factor information, the data group and the data sequence comprises: Obtaining the influencing factor value range of each of the factor information, and screening the target influencing factor value in each of the influencing factor data ranges; According to a single variable strategy, after constructing a storage performance influencing factor group using each target influencing factor value, a corresponding data test group is generated using the data group, the storage performance influencing factor group and the data sequence; The test parameters of the chip are generated based on the data test group, and a plurality of storage performance test strategies are generated using the test parameters and a preset storage performance test template.

5. The method for detecting chip storage performance according to claim 1, characterized in that: The recording of the test log information corresponding to each storage performance test strategy includes: Sending each of the storage performance test strategies to a test client; The test log information fed back by the test client is obtained, wherein the test log information includes a plurality of sub-test log information, and the sub-test log information is a test log obtained by performing distribution sorting processing on the storage performance test strategy in chronological order.

6. The method for detecting chip storage performance according to claim 1, characterized in that: The calculating the storage performance change value of the chip by using the test log information includes: Determine a test performance evaluation value of the chip according to the test log information, and determine a storage performance type corresponding to each test performance evaluation value; The test type corresponding to the storage performance type is searched in the database, and the difference between the theoretical performance evaluation value and the test performance evaluation value corresponding to each test type is calculated to obtain the storage performance change value, wherein the theoretical performance evaluation value is the evaluation value of the chip storage performance obtained after identifying the storage specification information.

7. The method for detecting chip storage performance according to claim 6, characterized in that: The step of determining the test performance evaluation value of the chip according to the test log information includes: Extracting log distribution information from the test log information, the log distribution information including: state distribution information and energy consumption distribution information; After obtaining the test indicators corresponding to the log distribution information, the log distribution information is subjected to performance evaluation processing using the test indicators to obtain the test indicator value of each test type; After obtaining the impact weight value of the test type corresponding to the log distribution information, the impact weight value and the corresponding test index value are weighted to obtain a test performance evaluation value corresponding to each test type.

8. The method for detecting chip storage performance according to claim 7, characterized in that: The extracting log distribution information from the test log information includes: Determine the test distribution information corresponding to each sub-test log information in the test log information to obtain log distribution information; According to the test type corresponding to the chip storage state, the corresponding test distribution information is extracted from the log distribution information to obtain the state distribution information; According to the test type corresponding to the chip storage energy consumption, the corresponding test distribution information is extracted from the log distribution information to obtain the energy consumption distribution information.

9. The method for detecting chip storage performance according to claim 1, characterized in that: The storage performance test results include: a first test result, a second test result and a third test result; The step of determining a storage performance test result of a chip based on the storage performance change value includes: Randomly select one of the plurality of storage performance test strategies as a target test strategy, and determine a first detection result of the chip in the storage state based on the storage performance change value corresponding to the target test strategy; Identify the storage performance change value of the storage performance test strategy corresponding to each of the factor information of the chip, and obtain a second detection result of the chip's resistance to the influence of each storage performance influencing factor; The storage performance change value of the storage performance test strategy corresponding to each type information of the chip is identified to obtain a third detection result of the chip for each data type.

10. A device for detecting chip storage performance, characterized in that: The device comprises: An acquisition module, used for acquiring a detection information set of a chip, wherein the detection information set includes specification information of chip storage specifications, factor information of factors affecting chip storage performance, and type information of a data type of chip storage data; An information recording module, used to generate multiple storage performance test strategies of the chip using the detection information set, and record the test log information corresponding to each storage performance test strategy; The detection result module is used to calculate the storage performance change value of the chip using the test log information, and determine the storage performance detection result of the chip based on the storage performance change value.

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