Method of selective etching with reduced aspect ratio dependency
By adopting a combination of dry and wet etching during the etching process of semiconductor devices, using plasma processing technology and gas formulation optimization, the problem of uneven etching in dense areas and isolation areas is solved, and high aspect ratio and uniform etching are achieved. Improves etch selectivity and uniformity.
Patent Information
- Application Number
- CN202411183451.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2016-10-11
- Filing Date
- 2017-09-27
- Publication Date
- 2025-01-10
AI Technical Summary
In the prior art, when forming semiconductor devices, it is difficult to uniformly etch dense areas and isolation areas during mask selective etching, resulting in uneven depth and aspect ratio, differences in etching rate and uneven depth, making it difficult to achieve high-deep aspect ratio characteristics and uniform etching.
Using a combination of multiple etch cycles, including dry and wet etching, the plasma is formed to control the etching process through the deposition and etching stages in the plasma processing chamber using different gas formulations and RF powers, combining temperature control and biasing Frequency optimization enables selective etching of the silicon oxide etching layer.
Effectively reduce the aspect ratio difference between dense areas and isolation areas, realize high aspect ratio etching characteristics, improve etch selectivity and uniformity, reduce corner losses and joints, and ensure uniform etching of the entire wafer surface.
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Figure CN119297083A_ABST
Abstract
Description
This application is a divisional application of the invention patent application with application number 201780062967.4, application date September 27, 2017, and invention name “Method for selective etching with reduced aspect ratio dependence”. CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application claims priority to U.S. Patent Application No. 15 / 290,800, filed on October 11, 2016, the entire contents of which are incorporated herein by reference. background
[0002] The present disclosure relates to a method for forming a semiconductor device on a semiconductor wafer, and more particularly, to a fin revealing process in forming a semiconductor device.
[0003] In forming a semiconductor device, a thin fin may be formed. The layer may be etched to reveal the fin. Summary of the invention
[0004] To achieve the aforementioned objectives and in accordance with the purpose of the present invention, a method for selectively etching an etching layer having isolated areas and dense areas relative to a mask is provided. The etching layer is placed in a processing chamber. An etching process including a plurality of etching cycles is provided, wherein each etching cycle includes: providing a deposition phase and an etching phase. The deposition phase includes: providing a deposition phase gas flow into the processing chamber, the deposition phase gas comprising a fluorocarbon or hydrofluorocarbon-containing gas and an oxygen-containing gas having a fluorocarbon or hydrofluorocarbon to oxygen ratio; providing RF power, which causes the deposition phase gas to form a plasma; and stopping the deposition phase by stopping the deposition phase gas flow into the processing chamber. The etching phase includes: providing an etching phase gas flow into the processing chamber, the etching phase gas comprising a fluorocarbon or hydrofluorocarbon-containing gas and an oxygen-containing gas having a fluorocarbon or hydrofluorocarbon to oxygen ratio lower than the fluorocarbon or hydrofluorocarbon to oxygen ratio of the deposition phase gas; providing RF power, which causes the etching phase gas to form a plasma; and stopping the etching phase by stopping the etching phase gas flow into the processing chamber.
[0005] In another implementation, a method is provided for selectively etching a silicon oxide-containing layer having isolated areas and dense areas relative to a silicon nitride-containing mask. The etched layer is placed in a processing chamber. An electrostatic chuck is maintained at a temperature between 60°C and 120°C. An etching process is provided that includes multiple etching cycles, wherein each etching cycle includes a deposition phase and an etching phase. The deposition phase includes: providing a deposition phase gas flow into the processing chamber, the deposition phase gas containing a gas containing a fluorocarbon or a hydrofluorocarbon; providing RF power that causes the deposition phase gas to form a plasma; and stopping the deposition phase. The etching phase includes: providing an etching phase gas flow into the processing chamber, the etching phase gas is free of fluorocarbons and hydrofluorocarbons and contains Ar and an oxygen-containing gas; providing RF power that causes the etching phase gas to form a plasma; and stopping the etching phase.
[0006] These and other features of the present invention will be described in more detail below in the detailed description of the invention and in conjunction with the following figures. BRIEF DESCRIPTION OF THE DRAWINGS
[0007] The present disclosure is illustrated by way of example and not limitation in the accompanying figures and in which like reference numerals indicate similar elements and in which:
[0008] Figure 1 is a high-level flow chart of an implementation scheme.
[0009] Figure 2 is a more detailed flow chart of the steps for etching the trenches.
[0010] Figure 3A -E is a schematic cross-sectional view of a stack processed according to one embodiment.
[0011] Figure 4 is a schematic diagram of a plasma processing chamber that may be used in one embodiment.
[0012] Figure 5 is a schematic diagram of a computer system that can be used to implement one embodiment. DETAILED DESCRIPTION
[0013] The present invention will now be described in detail with reference to several preferred embodiments shown in the accompanying drawings. In the following description, many specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention can be implemented without some or all of these specific details. In other cases, known process steps and / or structures are not described in detail to avoid making the present invention unclear unnecessarily.
[0014] Figure 11 is a high-level flow chart of an embodiment. In this embodiment, a fin structure is formed in an etch layer below a mask (step 104). A cyclic wet and dry etching process is provided (step 108). Each cycle of the wet and dry etching process includes a dry etching process (step 112) and a wet etching process (step 116). The fin structure may be further processed. Figure 2 1 is a more detailed flow chart of the steps of providing a dry etching process (step 112). The etch layer is placed in a plasma processing chamber (step 204). A cyclic dry etching process is provided (step 208). Each cycle of the cyclic dry etching process includes a deposition phase (step 212) and an etching phase (step 216). The etch layer is removed from the plasma processing chamber (step 220). Example
[0015] In a preferred embodiment of the present invention, a fin structure is formed in the etch layer below the mask (step 104). Figure 3A 300 is a schematic cross-sectional view of a stack 300 having a substrate 304 and a silicon oxide etch layer 308. A fin structure 312 is formed in the etch layer 308. In this example, the fin structure 312 is made of SiGe. A hard mask 316 surrounds the fin structure 312. In this example, the hard mask 316 is made of silicon nitride (SiN). In this example, one or more layers may be disposed between different layers. For example, a silicon oxide liner may be placed between the fin structure 312 and the hard mask 316. The silicon oxide etch layer 308 has a dense region 320 and an isolation region 324. When etching, the dense region 320 of the silicon oxide etch layer 308 will have a higher aspect ratio than the isolation region 324, which may result in uneven etching. In addition, when forming the silicon oxide etch layer 308, a different silicon oxide material may be used in the dense region 320 compared to the isolation region 324. For example, the isolation region may be formed by a conventional spin-on silicon oxide material. However, the dense regions may use silicon oxide based eHARP oxide, which is specifically formulated for high aspect ratio fill processes. The difference in silicon oxide etch layer material may further allow for a difference in etch rate between the dense regions 320 and the isolated regions 324.
[0016] A cyclic wet and dry etching process is provided (step 108). Each cycle of the wet and dry etching process includes a dry etching process (step 112) and a wet etching process (step 116). Figure 2 is a more detailed flow chart providing the steps of the dry etching process (step 112). The stack is placed in a plasma processing chamber (step 204).
[0017] Figure 44 is a schematic diagram of a plasma processing chamber that can be used in one embodiment. In one or more embodiments, the plasma processing system 400 includes a gas distribution plate 406, which is provided with a gas inlet and an electrostatic chuck (ESC) 408 in a processing chamber 449, and the processing chamber 449 is surrounded by a chamber wall 450. In the processing chamber 449, the substrate 304 is located on the top of the ESC 408. The edge ring 460 is placed around the substrate 304. The ESC 408 can provide a bias from the ESC source 448. The gas source 410 is connected to the plasma processing chamber 449 through the distribution plate 406. In this embodiment, the gas source 410 includes a CF4 gas source 412, a C4F6 gas source 416, and one or more additional gas sources 418. Each gas source can include a plurality of gas sources. The ESC temperature controller 451 is connected to the ESC 408 and provides temperature control of the ESC 408. The ESC temperature controller 451 or another temperature controller can also be used to control the temperature of the edge ring 460. In this example, a first connector 413 is used to power an internal heater 411 to heat an internal region of the ESC 408, and a second connector 414 is used to power an external heater 412 to heat an external region of the ESC 408. The RF source 430 provides RF power to the lower electrode 434 and the upper electrode, which in this embodiment is the gas distribution plate 406. In a preferred embodiment, 2MHz, 60MHz, and optional 27MHz power sources make up the RF source 430 and the ESC source 448. In this embodiment, a generator is provided for each frequency. In other embodiments, the generator can be in a separate RF source, or a separate RF generator can be connected to different electrodes. For example, the upper electrode can have an inner electrode and an outer electrode connected to different RF sources. Other arrangements of RF sources and electrodes can be used in other embodiments, for example, in another embodiment, the upper electrode can be grounded. The controller 435 is controllably connected to the RF source 430, the ESC source 448, the exhaust pump 420, and the etching gas source 410. An example of such a plasma processing chamber is the Exelan Flex TM Etching system. The processing chamber can be a CCP (capacitively coupled plasma) reactor or an ICP (inductively coupled plasma) reactor.
[0018] Figure 55 is a high-level block diagram showing a computer system 500 suitable for implementing a controller 435 used in embodiments of the present invention. Computer systems can have many physical forms from integrated circuits, printed circuit boards, and small handheld devices to supercomputers. Computer system 500 includes one or more processors 502, and may also include an electronic display device 504 (for displaying graphics, text, and other data), a main memory 506 (e.g., a random access memory (RAM)), a storage device 508 (e.g., a hard drive), a removable storage device 510 (e.g., an optical drive), a user interface device 512 (e.g., a keyboard, a touch screen, a keypad, a mouse or other pointing device, etc.) and a communication interface 514 (e.g., a wireless network interface). Communication interface 514 allows software and data to be transmitted between computer system 500 and external devices via a link. The system may also include a communication infrastructure 516 (e.g., a communication bus, a cross-connection bar, or a network) connected to the above-mentioned devices / modules.
[0019] The information transmitted via the communication interface 514 may be in the form of signals such as electronic, electromagnetic, optical or other signals that can be received by the communication interface 514 via a communication link that carries the signals and may be implemented using wires or cables, optical fibers, telephone lines, cellular phone links, radio frequency links and / or other communication channels. Using such a communication interface, it is contemplated that one or more processors 502 may receive information from a network during the execution of the above method steps, or may output information to a network. Furthermore, method embodiments of the present invention may be executed solely on a processor, or may be executed over a network such as the Internet with a remote processor that shares a portion of the processing.
[0020] The term "non-transitory computer-readable medium" is generally used to refer to media such as main memory, secondary memory, removable storage devices, and storage devices such as hard disks, flash memory, disk drive memory, CD-ROMs, and other forms of persistent memory, and should not be interpreted as covering transient subject matter such as carrier waves or signals. Examples of computer code include machine code (such as that produced by a compiler) and files containing higher-level code executed by a computer using an interpreter. Computer-readable media may also be computer code that is transmitted by a computer data signal embodied in a carrier wave and represents a sequence of instructions that can be executed by a processor.
[0021] After the stack 300 has been placed in the plasma processing chamber 449, a dry etching process (step 112) can be provided. The dry etching process includes a plurality of cycles, each of which includes a deposition phase (step 212) and an etching phase (step 216). An example of a deposition phase provides a deposition phase gas, which includes a gas containing a fluorocarbon or a hydrofluorocarbon having a certain fluorine-carbon ratio. In this example, a deposition phase gas of 2sccm C4F6 and 341sccm Ar is flowed into the plasma processing chamber 449 while maintaining a pressure of 15 mTorr. The deposition phase gas is formed into an in-situ plasma. In this example, the deposition phase gas is formed into a plasma by providing a pulsed RF power having an RF frequency of at least 60MHz. In this example, an RF power of 1OO watts with a duty cycle of 10% is provided. After 4 seconds, the deposition phase (step 212) is stopped. In this example, the deposition phase (step 212) is stopped by stopping the flow of the deposition phase gas.
[0022] The example of the etching stage provides an etching stage gas, which contains a gas having a fluorine-carbon ratio higher than the fluorine-carbon ratio of the deposition stage gas. In this example, the recipe for the etching stage gas is 343sccm Ar. The processing chamber pressure is maintained at 15 millitorr. The etching stage gas is formed into an in-situ plasma. In this example, the etching stage gas is formed into a plasma by providing a pulsed RF power with an RF frequency of at least 60MHz. In this example, a 100-watt RF power with a 40% duty cycle is provided. A bias is provided to increase the bombardment of the etching layer. In this example, a bias is provided by providing a 2MHz RF power of 100 watts. After 3 seconds, the etching stage (step 216) is stopped. In this example, the etching stage (step 216) is stopped by stopping the flow of the etching stage gas. After multiple cycles, the etching process is stopped. In this example, the process provides 7 cycles. The silicon oxide etching layer is removed from the plasma processing chamber 449 (step 220).
[0023] Figure 3B 4 is a schematic cross-sectional view of the stack 300 after the stack 300 is removed from the plasma processing chamber 449. The silicon oxide etch layer 308 has been etched back to the same depth "D" in both the dense area 320 and the isolated area 324. Residue 328 may be deposited during the dry etching process. In this example, a residue containing silicon oxide is deposited.
[0024] A wet etching process is provided (step 116). In this example, the wet process is a dilute HF bath with a water to HF molar ratio of at least 300: 1. The stack is exposed to the bath for 5 to 60 seconds. Figure 3C is a schematic cross-sectional view of the stack 300 after residue removal by wet etching.
[0025] A second dry etching process is performed on the stack 300 (step 112). In this example, the second dry etching process uses the same recipe as the first dry etching process. In other embodiments, the second dry etching process can be changed from the first dry etching process to better etch higher aspect ratio features. Figure 3D is a schematic cross-sectional view of the stack 300 after the second dry etching process is completed. A residue 332 is deposited by the second dry etching process.
[0026] A second wet etching process is provided (step 116). In this example, the second wet etching process uses the same recipe as the first wet etching process. In other embodiments, the recipe may be adjusted to be different from the first wet etching process to better remove deposits from higher aspect ratio features. Figure 3E is a schematic cross-sectional view of the stack 300 after removing residues by a second wet etch.
[0027] Without being bound by theory, the combination of wet and dry etching provides improved etching relative to dry etching alone or wet etching alone. Wet etching is isotropic. Dry etching is anisotropic. Using only wet etching only results in isotropic etching, which may result in undercutting. In addition, wet etching may have difficulty etching smaller dimensions, depending on the wetting ability and / or hydrophobicity of the material to be etched and the chemicals used to etch the material. In addition, when etching more than one type of material, this etching process has uneven etching depth. This etching may also have poor etching selectivity. This etching may also result in corner loss. In addition, it is difficult to achieve etching uniformity across the entire wafer surface.
[0028] By using a process with dry etching and wet etching, where additional adjustment control is provided by different etchings, various embodiments can etch dense areas and isolated areas simultaneously with reduced hysteresis. In addition, the embodiments can etch different types of silicon oxide-containing layers at the same rate, so that uniform depths are etched in different silicon oxide-containing layers without using an etch stop layer. Dense areas require high aspect ratio etching with high aspect ratios. Various embodiments can etch high aspect ratio features, where the aspect ratio is greater than 2:1. More preferably, the aspect ratio of depth to width is greater than 5:1, where the CD is less than 20nm. More preferably, the CD is less than 15nm. Various embodiments reduce corner loss. Various embodiments have high etching selectivity and can be uniformly adjusted to etch more than one material at the same time. Various embodiments provide vertical profiles without undercuts and minimal bridging of seams, gaps, and patterns. Various embodiments can provide uniform etching on the surface of the wafer. By providing a combination of dry etching and wet etching, various embodiments can provide the above benefits simultaneously.
[0029] Various embodiments provide dry etching, a deposition phase, and an etching phase. The etching gas used during the etching phase is more dilute than the deposition gas used during the deposition phase. In some embodiments, the dilute gas has a lower carbon-to-fluorine ratio.
[0030] In the above example, polymer is deposited on the silicon nitride mask and the silicon oxide containing etch layer. However, the release of oxygen from etching the silicon oxide containing layer causes the polymer to be removed. The absence of oxygen in the silicon nitride mask prevents the polymer from being removed. This selective removal of polymer from the silicon oxide containing etch layer allows the silicon oxide containing etch layer to be etched more selectively relative to the mask.
[0031] In some embodiments, the etching gas includes C4F6, O2 and Ar. Ar is mainly used to maintain the chamber pressure. C4F6 and O2 are used for etching. In some embodiments, Ar can be replaced by CO.
[0032] In another example, the deposition phase gas may be 2 sccm of C4F6, 2 sccm of O2, 323 sccm of Ar, and 20 sccm of CO. The 60 MHz RF signal provides 100 W of power and is pulsed at a 10% duty cycle. The 2 MHz RF signal provides 50-100 watts and is pulsed at a frequency of 100 Hz and a 10% duty cycle. The chamber pressure is maintained at 15 mTorr. The deposition phase is maintained for 5 seconds. The etch phase gas may be 4 sccm of C4F6, 2.5 sccm of O2, 323 sccm of Ar, and 20 sccm of CO. The 60 MHz RF signal provides 100 W of power and is pulsed at a 10% duty cycle. The 2 MHz RF signal provides 50-100 watts and is pulsed at a frequency of 100 Hz and a 10% duty cycle. The chamber pressure is maintained at 15 mTorr. The etch phase is maintained for 3 seconds. This example is repeated for 5 cycles. In this example, the deposition phase gas includes a fluorocarbon- or hydrofluorocarbon-containing gas. The etching phase gas does not contain fluorocarbons and hydrofluorocarbons, but instead contains Ar and an oxygen-containing gas. The oxygen-containing gas can be O2, CO2, or CO. ESC 408 is maintained at a temperature between 60°C and 120°C. More preferably, edge ring 460 is also maintained at a temperature between 60°C and 120°C. ESC temperature controller 151 and / or another temperature controller can be used to achieve this purpose. A preferred temperature range has been found to control polymer deposition to provide the desired selectivity while avoiding pinch-off. Preferably, more bias is provided during the etching phase than during the deposition phase. More RF power can be provided during the etching phase than during the deposition phase. Such an embodiment enables uniform etching of isolated areas and dense areas without hysteresis. Such areas can be uniformly and partially etched without etching stops. Subsequent wet etching can be used to complete the processing of the stack.
[0033] The fin structure in the specification and claims refers to a structure in the form of a fin. For example, the structure including 312 and 316 can represent a fin structure. In one embodiment, the fin structure can include a SiGe fin, an oxide liner surrounding 312, and a nitride liner and a hard mask (316) surrounding the oxide liner and the fin. In other embodiments, the fin structure can be essentially any material that can be used to manufacture devices, such as Ge or III-V materials.
[0034] In another embodiment, the fin structure may include a replacement contact material, a spacer material adjacent to the replacement contact material, and a silicon-based nitride capping material (hard mask) on top of the replacement contact material.
[0035] In another embodiment of the present invention, the proposed method can be used to perform replacement contact etching to expose the active area of the device (metal contacts of the semiconductor device) by removing the contact replacement material. The contact replacement material here is usually a silicon-based oxide. Contact metal deposition, planarization, interlayer dielectric (ILD) deposition and further processing steps can then be performed.
[0036] Other embodiments may provide other RF frequencies. Preferably, the bias frequency is less than 10 MHz. Preferably, the etching phase has a bias RF power with an RF frequency less than 10 MHz, which is greater than the bias RF power with an RF frequency less than 10 MHz provided during the deposition phase.
[0037] Other embodiments may use dry stripping, such as O2-based stripping or N2 / H2 stripping to remove deposits. Other embodiments may have more than one deposition phase or etching phase for each cycle.
[0038] In various embodiments, etching to a uniform depth between the isolated regions and the dense regions means etching to a depth where the difference between the etch depths does not exceed 10 nm. Thus, the lag between the etch depths of the isolated regions and the dense regions does not exceed 10 nm.
[0039] In some embodiments, the wet etch uses HF or HCl etching chemicals or a combination thereof. In some embodiments, the wet etch can be used to reduce or eliminate the oxide footprint. When following a dry etch process, such a wet etch can be used to provide a straighter profile.
[0040] Although the present invention has been described according to several preferred embodiments, there are changes, modifications, permutations and various alternative equivalents that fall within the scope of the present invention. It should also be noted that there are many alternatives to the method and apparatus of the present invention. Therefore, the following appended claims are intended to be interpreted as including all such changes, modifications, permutations and various alternative equivalents that fall within the true spirit and scope of the present invention.
Claims
1. A method for selectively etching an etch layer having isolated areas and dense areas relative to a mask in a process chamber, comprising: A dry etching process comprising a plurality of etching cycles is provided, wherein the dry etching process partially etches the isolated area and the dense area of the etching layer to the same target depth at the same rate, and wherein each etching cycle of the dry etching process comprises: A deposition phase is provided, comprising: providing a deposition phase gas flow into the processing chamber, the deposition phase gas comprising a fluorocarbon- or hydrofluorocarbon-containing gas and an oxygen-containing gas having a ratio of fluorocarbon- or hydrofluorocarbon- to oxygen; providing RF power, which causes the deposition phase gas to form a plasma; and stopping the deposition phase; and An etching phase is provided, comprising: providing an etch phase gas flow into the process chamber, the etch phase gas comprising a fluorocarbon- or hydrofluorocarbon-containing gas and an oxygen-containing gas having a fluorocarbon- or hydrofluorocarbon-to-oxygen ratio different from the fluorocarbon- or hydrofluorocarbon-to-oxygen ratio of the deposition phase gas; providing RF power, wherein the RF power causes the etching phase gas to form a plasma, and wherein the RF power provided during the etching is greater than the RF power provided during the deposition; and The etching phase is stopped. 2 . The method of claim 1 , wherein a bias is provided during the etching phase, wherein the bias provided during the etching phase is higher than the bias provided during the deposition phase.
3. The method of claim 1, wherein the etching phase gas comprises at least one of CF4, C4F6, O2 or Ar, and wherein the deposition phase gas comprises at least C4F6 and an oxygen-containing gas. The method of claim 1 , wherein the etch layer comprises silicon oxide. The method of claim 4 , wherein the mask is a silicon-containing mask. The method of claim 1 , wherein the etching partially etches the etch layer to a target depth.
7. The method of claim 1, wherein the dry etching process deposits a polymer on the mask selectively to the etch layer.
8. The method of claim 1, wherein the etching phase further comprises providing a bias RF power having an RF frequency less than 10 MHz, wherein the deposition phase does not have an RF bias RF power having an RF frequency less than 10 MHz.
9. The method of claim 1, further comprising providing a wet process to remove residues formed by the dry etching process.
10. The method of claim 1, further comprising providing a wet process to remove a taper formed by the dry etching process.
11. The method of claim 1 wherein the etch phase gas has a lower ratio of fluorocarbon or hydrofluorocarbon to oxygen than the deposition phase gas has a ratio of the fluorocarbon or hydrofluorocarbon to oxygen.
12. The method of claim 1 wherein the mask comprises silicon nitride.
13. The method of claim 1, wherein the RF power provided during the etching phase is pulsed, and the RF power provided during the deposition phase is pulsed.
14. A method for selectively etching a silicon oxide-containing layer having isolated regions and dense regions relative to a mask in a processing chamber, comprising: A dry etching process comprising a plurality of etching cycles is provided, wherein the dry etching process partially etches the isolated area and the dense area of the etching layer to the same target depth at the same rate, and wherein each etching cycle of the dry etching comprises: A deposition phase is provided, comprising: providing a deposition phase gas flow into the processing chamber, wherein the deposition phase gas comprises a fluorocarbon or hydrofluorocarbon containing gas; providing RF power, which causes the deposition phase gas to form a plasma; and stopping the deposition phase; and An etching phase is provided, comprising: providing an etch phase gas flow into the processing chamber, the etch phase gas being free of fluorocarbons and hydrofluorocarbons and comprising an oxygen-containing gas; providing RF power, wherein the RF power causes the etching phase gas to form a plasma, and wherein the RF power provided during the etching is greater than the RF power provided during the deposition and The etching phase is stopped.
15. The method of claim 14, wherein a bias is provided during the etching phase, wherein the bias provided during the etching phase is higher than a bias provided during the deposition phase. The method of claim 14 , wherein the etching partially etches the etch layer to a target depth.
17. The method of claim 14, wherein the etching phase further comprises providing a bias RF power of less than 10 MHz, wherein the deposition phase does not have an RF bias RF power of less than 10 MHz.
18. The method of claim 14, further comprising providing a wet process to remove residues formed by the dry etching process. The method of claim 14 , wherein the mask is a hard mask.
20. The method of claim 14, wherein the mask is a silicon-containing mask.
21. The method of claim 14, further comprising maintaining the electrostatic chuck at a temperature between 60°C and 120°C.
22. The method of claim 14, wherein the etch phase gas further comprises Ar.