MOS Transistor Effective Channel Length Testing Method and Device

Abstract

The present invention provides a method and device for testing the effective channel length of a MOS transistor, belonging to the technical field of semiconductor manufacturing. The method is applied to a MOS transistor test structure, and the MOS transistor test structure includes: a plurality of MOS units, each MOS unit including a substrate, a source electrode, a drain electrode, and a gate electrode, the source electrode and the drain electrode being respectively disposed on the substrate, the gate electrode being located between the source electrode and the drain electrode, and an isolation oxide layer being disposed between the substrate and the gate electrode; wherein, all the MOS units share a common substrate, the gate lengths of the respective MOS units are different, and adjacent two MOS units share a source electrode or a drain electrode. When testing, only one set of test structure units is required to test the effective channel length, greatly improving the test efficiency and reducing the space occupied by the test structure.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a method for testing the effective channel length of a MOS transistor, a device for testing the effective channel length of a MOS transistor, a machine-readable storage medium, and an electronic device. Background Art

[0002] MOS is an abbreviation of MOSFET. MOSFET is a metal-oxide-semiconductor field-effect transistor, also known as a metal-oxide-semiconductor field-effect transistor (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET).

[0003] Testkey (TSK) is a test structure mainly used to monitor whether the chip manufacturing process is healthy, whether the device performance is normal, and to determine whether the test results of each parameter of the device meet the standards.

[0004] The existing Testkey test structure only includes one MOS unit, that is, it includes a substrate, a source electrode, a drain electrode, and a gate electrode. Therefore, when using the existing Testkey test structure to test the effective channel length of a MOS transistor, multiple TSKs of MOS with different sizes are required to complete the test, which requires a large amount of test structure space. Summary of the Invention

[0005] The purpose of the embodiments of the present invention is to provide a method for testing the effective channel length of a MOS transistor, a device for testing the effective channel length of a MOS transistor, a machine-readable storage medium, and an electronic device. The method for testing the effective channel length of a MOS transistor can test the effective channel length with only one set of test structure units, greatly improving the test efficiency. At the same time, each MOS unit shares a substrate, and adjacent two MOS units share a source electrode or a drain electrode, so that the MOS transistor test structure is greatly reduced, and the space occupied by the test structure is reduced.

[0006] To achieve the above purpose, in the first aspect of the present application, a method for testing the effective channel length of a MOS transistor is provided, which is applied to a MOS transistor test structure. The MOS transistor test structure includes: a plurality of MOS units, each MOS unit includes a substrate, a source electrode, a drain electrode, and a gate electrode. The source electrode and the drain electrode are respectively disposed on the substrate, the gate electrode is located between the source electrode and the drain electrode, and an isolation oxide layer is disposed between the substrate and the gate electrode. Among them, each MOS unit shares a substrate, the gate lengths of each MOS unit are different, and adjacent two MOS units share a source electrode or a drain electrode. The method for testing the effective channel length of a MOS transistor includes:

[0007] Apply a voltage signal to the MOS units in the MOS transistor test structure according to a preset voltage application scheme;

[0008] Obtain the parameter information of the MOS units in the MOS transistor test structure under the voltage signal;

[0009] Based on the parameter information, obtain the effective channel length.

[0010] In the embodiment of the present application, the preset voltage application scheme includes a preset first voltage application scheme and a preset second voltage application scheme;

[0011] The preset first voltage application scheme is: apply a first fixed drain voltage to all MOS units in the MOS transistor test structure, and apply different gate voltages to any one MOS unit in the MOS transistor test structure;

[0012] The preset second voltage application scheme is: apply a second fixed drain voltage to all MOS units in the MOS transistor test structure, and apply different gate voltages to all MOS units in the MOS transistor test structure.

[0013] In the embodiment of the present application, the obtaining of the parameter information of the MOS units in the MOS transistor test structure under the voltage signal includes:

[0014] Obtain a first drain current, where the first drain current is the drain current of the corresponding MOS unit under different gate voltages under the preset first voltage application scheme;

[0015] Obtain a second drain current, where the second drain current is the drain current of each MOS unit under different gate voltages under the preset second voltage application scheme.

[0016] In the embodiment of the present application, the obtaining of the effective channel length based on the parameter information includes:

[0017] Based on the first drain current and the first fixed drain voltage, obtain a total resistance, where the total resistance is the sum of the channel resistance, the lightly doped region resistance, and the source-drain region resistance;

[0018] Based on the second drain current, the second fixed drain voltage, and the total resistance, obtain a first linear function, where the first linear function is a linear function of the ratio of the drain voltage to the drain current changing with the gate length;

[0019] Based on the intersection point of the first linear function, determine the channel length error;

[0020] Based on the theoretical channel length and the channel length error, obtain the effective channel length.

[0021] In the embodiment of the present application, the first linear function is:

[0022]

[0023] R sd is the source-drain region resistance, R LDD is the lightly doped region resistance, R channel is the channel resistance, L poly is the gate length, ΔL is the difference between the mask channel length and the effective channel length, W is the channel width, c OX is the gate capacitance, μ n is the electron mobility, V gs is the gate voltage, V t is the threshold voltage, V ds is the second fixed drain voltage, I ds is the second drain current.

[0024] In the embodiment of the present application, it further includes:

[0025] Based on the channel length error, obtain the sum of the source-drain region resistance and the lightly doped region resistance;

[0026] Based on the sum of the source-drain region resistance and the lightly doped region resistance and the total resistance, obtain the channel resistance.

[0027] In the embodiment of the present application, gate electrodes are respectively arranged at both ends of the gate.

[0028] The second aspect of the present application provides a MOS transistor effective channel length testing device for the above MOS transistor testing structure, which is applied to the MOS transistor testing structure. The MOS transistor testing structure includes a plurality of MOS units. Each MOS unit includes a substrate, a source electrode, a drain electrode and a gate. The source electrode and the drain electrode are respectively arranged on the substrate. The gate is located between the source electrode and the drain electrode. An isolation oxide layer is arranged between the substrate and the gate; wherein, all MOS units share a substrate, the gate lengths of all MOS units are different, and adjacent two MOS units share a source electrode or a drain electrode; the MOS transistor effective channel length testing device includes:

[0029] A signal application module, configured to apply a voltage signal to the MOS unit in the MOS transistor testing structure according to a preset voltage application scheme;

[0030] A parameter acquisition module, configured to acquire parameter information of the MOS unit in the MOS transistor testing structure under the voltage signal;

[0031] A testing module, configured to obtain an effective channel length based on the parameter information.

[0032] In an embodiment of the present application, the preset voltage application scheme includes a preset first voltage application scheme and a preset second voltage application scheme; the preset first voltage application scheme is: applying a first fixed drain voltage to all MOS units in the MOS transistor test structure, and applying different gate voltages to any one MOS unit in the MOS transistor test structure; the preset second voltage application scheme is: applying a second fixed drain voltage to all MOS units in the MOS transistor test structure, and applying different gate voltages to all MOS units in the MOS transistor test structure.

[0033] In an embodiment of the present application, the parameter acquisition module includes:

[0034] A first acquisition unit, configured to acquire a first drain current, where the first drain current is the drain current of a corresponding MOS unit at different gate voltages under the preset first voltage application scheme;

[0035] A second acquisition unit, configured to acquire a second drain current, where the second drain current is the drain current of each MOS unit at different gate voltages under the preset second voltage application scheme.

[0036] In an embodiment of the present application, the test module includes:

[0037] A first calculation unit, configured to obtain a total resistance based on the first drain current and the first fixed drain voltage, where the total resistance is the sum of the channel resistance, the lightly doped region resistance, and the source-drain region resistance;

[0038] A second calculation unit, configured to obtain a first linear function based on the second drain current, the second fixed drain voltage, and the total resistance, where the first linear function is a linear function of the ratio of the drain voltage to the drain current varying with the gate length;

[0039] A first determination unit, configured to determine a channel length error based on the intersection point of the first linear function;

[0040] A third calculation unit, configured to obtain an effective channel length based on the theoretical channel length and the channel length error.

[0041] In an embodiment of the present application, it further includes:

[0042] A second determination unit, configured to obtain the sum of the source-drain region resistance and the lightly doped region resistance based on the channel length error;

[0043] A resistance calculation module, configured to obtain the channel resistance based on the sum of the source-drain region resistance and the lightly doped region resistance and the total resistance.

[0044] A third aspect of the present application provides an electronic device, which includes:

[0045] At least one processor;

[0046] A memory connected to the at least one processor;

[0047] Wherein, the memory stores instructions executable by the at least one processor, and the at least one processor implements the above-mentioned MOS transistor effective channel length testing method by executing the instructions stored in the memory.

[0048] A fourth aspect of the present application provides a machine-readable storage medium, on which instructions are stored, and when the instructions are executed by a processor, the processor is configured to execute the above-mentioned MOS transistor effective channel length testing method.

[0049] Through the above technical solution, a voltage signal is applied to the MOS unit in the MOS transistor test structure according to a preset voltage application scheme; parameter information of the MOS unit in the MOS transistor test structure under the voltage signal is obtained; based on the parameter information, an effective channel length is obtained. Since a MOS transistor test structure includes multiple MOS units, therefore, only one set of test structure units is required to test the effective channel length during testing, greatly improving the testing efficiency. At the same time, each MOS unit shares a substrate, and adjacent two MOS units share a source or a drain, so that the MOS transistor test structure is greatly reduced, and the space occupied by the test structure is reduced.

[0050] Other features and advantages of the embodiments of the present invention will be described in detail in the subsequent specific implementation part. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] The drawings are used to provide a further understanding of the embodiments of the present invention, and constitute a part of the specification, and are used to explain the embodiments of the present invention together with the following specific implementation manners, but do not constitute a limitation to the embodiments of the present invention. In the drawings:

[0052] Figure 1 Schematically shows a flowchart of a method for testing a MOS transistor test structure according to an embodiment of the present application;

[0053] Figure 2 Schematically shows a flowchart of a method for testing an effective channel length of a MOS transistor according to an embodiment of the present application;

[0054] Figure 3 Schematically shows a structural diagram of a device for testing an effective channel length of a MOS transistor according to an embodiment of the present application;

[0055] Figure 4Schematically shows the internal structure diagram of a computer device according to an embodiment of the present application.

[0056] Description of Reference Numerals

[0057] 410 - Signal application module; 420 - Parameter acquisition module; 430 - Test module; A01 - Processor; A02 - Network interface; A03 - Internal memory; A04 - Display screen; A05 - Input device; A06 - Non-volatile storage medium; B01 - Operating system; B02 - Computer program. Detailed Embodiment

[0058] The following details the specific embodiments of the embodiments of the present invention in conjunction with the accompanying drawings. It should be understood that the specific embodiments described herein are only for the purpose of illustration and explanation of the embodiments of the present invention, and are not used to limit the embodiments of the present invention.

[0059] It should be noted that if there are directional indications (such as up, down, left, right, front, back,...) involved in the embodiments of the present application, then such directional indications are only used to explain the relative positional relationship and movement conditions between components in a specific posture (as shown in the accompanying drawings). If this specific posture changes, then such directional indications will also change accordingly.

[0060] In addition, if there are descriptions involving "first", "second", etc. in the embodiments of the present application, then such descriptions of "first", "second", etc. are only for descriptive purposes, and cannot be understood as indicating or implying their relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions between various embodiments can be combined with each other, but it must be based on the fact that those skilled in the art can implement it. When the combination of technical solutions results in contradictions or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection required by the present application.

[0061] Please refer to Figure 1 , Figure 1 Schematically shows a flow diagram of a MOS transistor test structure method according to an embodiment of the present application. This embodiment provides a MOS transistor test structure, including: a plurality of MOS units, each MOS unit includes a substrate, a source electrode, a drain electrode, and a gate electrode. The source electrode and the drain electrode are respectively disposed on the substrate, the gate electrode is located between the source electrode and the drain electrode, and an isolation oxide layer is disposed between the substrate and the gate electrode; wherein, all MOS units share a substrate, the gate lengths of all MOS units are different, and adjacent two MOS units share a source electrode or a drain electrode.

[0062] In this embodiment, the gate lengths of the respective MOS units are different, so that MOS units of different sizes can be obtained. The above source, drain, and gate can be fabricated according to the manufacturing process of MOS devices, which will not be elaborated here. The arrangement of the above multiple MOS units can be arranged in sequence according to the gate length from short to long or from long to short, or can be arranged arbitrarily. Two adjacent MOS units can share a source or a drain. As Figure 1 shown, the MOS unit with a gate length of L1 and the MOS unit with a gate length of L2 share a drain, and the MOS unit with a gate length of L2 and the MOS unit with a gate length of L3 share a source. Multiple substrate electrodes can be provided on the substrate.

[0063] When using the MOS transistor test structure in this embodiment to test the effective channel length of a MOS transistor, first fix the drain voltage in the MOS transistor test structure, apply different voltages to the gate of any one MOS unit to measure the source-drain current at different gate voltages, and then obtain the sum of the channel resistance, the lightly doped region resistance, and the source-drain region resistance. Then fix the drain voltage again, and obtain the linear function of the ratio of the drain voltage to the drain current and the gate length by measuring the drain current of different gate lengths at different gate voltages. The above linear function of the ratio of the drain voltage to the drain current and the gate length is multiple linear straight lines, and the multiple linear straight lines intersect at a point. The ratio of the drain voltage to the drain current corresponding to this point is the sum of the source-drain region resistance and the lightly doped region resistance, and the corresponding channel length is the channel length error. Specifically, the gate length corresponding to the sum of the source-drain region resistance and the lightly doped region resistance can be obtained, and this gate length is the channel length error. Then, the corresponding channel length can be calculated through the theoretical channel length and the channel length error. At the same time, after obtaining the sum of the source-drain region resistance and the lightly doped region resistance, the channel resistance can be further obtained according to the channel resistance, the lightly doped region resistance, and the sum of the source-drain region resistance.

[0064] In the above implementation process, since a MOS transistor test structure includes multiple MOS units, only one set of test structure units is required to test the effective channel length during testing, which greatly improves the testing efficiency. At the same time, each MOS unit shares a substrate, and adjacent two MOS units share a source or a drain, which greatly reduces the MOS transistor test structure and decreases the space occupied by the test structure. Meanwhile, by using this MOS transistor test structure, the sum of the source-drain and lightly doped region series resistances, the channel resistance, and the effective channel length can be tested simultaneously on one MOS transistor test structure, further improving the testing efficiency. Different gate length MOS units can also be tested through this test structure to verify the influence of the gate length on MOS. The number of MOS units placed in the test structure can be flexibly adjusted to adjust the calculation accuracy and accuracy, and by adjusting the space of each MOS unit in this test structure, the influence of the dense region and the sparse region on the performance of the MOS device can be verified.

[0065] In some embodiments, gate electrodes are respectively disposed at two ends of the gate.

[0066] In this embodiment, electrodes can be respectively disposed at the upper and lower ends of the gate for testing the gate resistance, so as to perform MOS gate resistance testing on this MOS transistor test structure, thereby testing the gate resistance of the MOS in the actual working state.

[0067] Please refer to Figure 2 , Figure 2 which schematically shows a flowchart of a method for testing the effective channel length of a MOS transistor according to an embodiment of the present application. This embodiment provides a method for testing the effective channel length of a MOS transistor based on the above MOS transistor test structure, including the following steps:

[0068] Step 210: Apply a voltage signal to the MOS units in the MOS transistor test structure according to a preset voltage application scheme;

[0069] In this embodiment, this test method can be to pre-establish a program on a test machine table, and the effective channel length of the MOS transistor is tested by executing the program. The above preset voltage application scheme can be preset, and specifically, the voltage application scheme can be implemented by controlling the voltage on / off of each MOS unit during application.

[0070] Among them, in order to be able to quickly test the effective channel length, the preset voltage application scheme includes a preset first voltage application scheme and a preset second voltage application scheme;

[0071] The preset first voltage application scheme is: applying a first fixed drain voltage to all MOS units in the MOS transistor test structure, and applying different gate voltages to any one MOS unit in the MOS transistor test structure;

[0072] The preset second voltage application scheme is as follows: apply a second fixed drain voltage to all MOS units in the MOS transistor test structure, and apply different gate voltages to all MOS units in the MOS transistor test structure.

[0073] In this embodiment, by applying the first voltage application scheme, the drain current at different gate voltages can be measured, and then the sum of the channel resistance, the lightly doped region resistance, and the source-drain region resistance can be obtained; by applying the second voltage application scheme, the drain current of different gate lengths at different gate voltages can be measured to obtain a linear function of the ratio of the drain voltage to the drain current and the gate length. The above first voltage application scheme and second voltage application scheme can be applied at an interval of a certain time to ensure reliable parameter information can be obtained.

[0074] Step 220: Obtain parameter information of the MOS units in the MOS transistor test structure under the voltage signal;

[0075] In this embodiment, the above parameter information includes the drain current at different gate voltages.

[0076] In some embodiments, obtaining the parameter information of the MOS units in the MOS transistor test structure under the voltage signal includes the following steps:

[0077] First, obtain a first drain current, where the first drain current is the drain current of the corresponding MOS unit at different gate voltages under the preset first voltage application scheme;

[0078] In this embodiment, it can be obtained by measuring the drain current of the corresponding MOS unit after applying the first voltage application scheme.

[0079] Then, obtain a second drain current, where the second drain current is the drain current of each MOS unit at different gate voltages under the preset second voltage application scheme.

[0080] In this embodiment, it can be obtained by measuring the drain current of each MOS unit after applying the second voltage application scheme.

[0081] Step 230: Obtain the effective channel length based on the parameter information.

[0082] In some embodiments, obtaining the effective channel length based on the parameter information includes the following steps:

[0083] First, based on the first drain current and the first fixed drain voltage, obtain a total resistance, where the total resistance is the sum of the channel resistance, the lightly doped region resistance, and the source-drain region resistance;

[0084] In this embodiment, by calculating the ratio of the first fixed drain voltage to the first drain current, the obtained result is actually the sum of the channel resistance, the lightly doped region resistance, and the source-drain region resistance.

[0085] Then, based on the second drain current, the second fixed drain voltage, and the total resistance, a first linear function is obtained. The first linear function is a linear function of the ratio of the drain voltage to the drain current varying with the gate length.

[0086] In this embodiment, the first linear function is multiple linear lines. Each linear line represents a linear line of the ratio of the drain voltage to the drain current varying with the gate length under a voltage difference between a gate voltage and a threshold voltage.

[0087] Among them, the first linear function is:

[0088]

[0089] R sd is the source-drain region resistance, R LDD is the lightly doped region resistance, R channel is the channel resistance, L poly is the mask channel length, that is, the gate length, ΔL is the difference between the mask channel length and the effective channel length, W is the channel width, c OX is the gate capacitance, μ n is the electron mobility, V gs is the gate voltage, V t is the threshold voltage; V ds is the drain voltage, that is, the second fixed drain voltage, I ds is the channel current, that is, the second drain current.

[0090] Then, based on the intersection point of the first linear function, the channel length error is determined.

[0091] In this embodiment, multiple linear lines will intersect at a point. The ratio of the drain voltage to the drain current corresponding to this point is the sum of the lightly doped region resistance and the source-drain region resistance. Then, the channel length corresponding to this point is the channel length error.

[0092] Finally, based on the theoretical channel length and the channel length error, the effective channel length is obtained.

[0093] In this embodiment, by calculating the difference between the theoretical channel length and the channel length error, the corresponding channel length can be calculated.

[0094] In the above implementation process, a voltage signal is applied to the MOS unit in the MOS transistor test structure according to a preset voltage application scheme; parameter information of the MOS unit in the MOS transistor test structure under the voltage signal is obtained; based on the parameter information, an effective channel length is obtained. Since a MOS transistor test structure includes multiple MOS units, therefore, only one set of test structure units is required for testing the effective channel length during testing, which greatly improves the testing efficiency. At the same time, each MOS unit shares a substrate, and adjacent two MOS units share a source or a drain, so that the MOS transistor test structure is greatly reduced, and the space occupied by the test structure is reduced.

[0095] In some embodiments, it further includes:

[0096] First, based on the channel length error, the sum of the source-drain region resistance and the lightly doped region resistance is obtained;

[0097] Then, based on the sum of the source-drain region resistance and the lightly doped region resistance and the total resistance, the channel resistance is obtained.

[0098] In this embodiment, the sum of the source-drain region resistance and the lightly doped region resistance is actually a constant. After obtaining the sum of the source-drain region resistance and the lightly doped region resistance, the total resistance can be used to subtract the sum of the source-drain region resistance and the lightly doped region resistance, and then the channel resistance can be further obtained, so that the channel resistance and the effective channel length can be simultaneously measured on a MOS transistor test structure, further improving the testing efficiency.

[0099] Figure 2 It is a schematic flowchart of a method for testing the effective channel length of a MOS transistor in an embodiment. It should be understood that although Figure 2 the steps in the flowchart are shown in sequence according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise clearly stated in this article, the execution of these steps has no strict order limit, and these steps can be executed in other orders. Moreover, Figure 2 at least a part of the steps in

[0100] This embodiment provides a MOS transistor effective channel length testing device for the above MOS transistor test structure. Please refer to Figure 3 , Figure 3Schematically shown is a schematic structural diagram of a MOS transistor effective channel length testing device according to an embodiment of the present application. The MOS transistor effective channel length testing device includes a signal application module 410, a parameter acquisition module 420, and a testing module 430, where:

[0101] The signal application module 410 is configured to apply a voltage signal to the MOS unit in the MOS transistor test structure according to a preset voltage application scheme;

[0102] The parameter acquisition module 420 is configured to acquire parameter information of the MOS unit in the MOS transistor test structure under the voltage signal;

[0103] The testing module 430 is configured to obtain an effective channel length based on the parameter information.

[0104] Among them, the preset voltage application scheme includes a preset first voltage application scheme and a preset second voltage application scheme; the preset first voltage application scheme is: applying a first fixed drain voltage to all MOS units in the MOS transistor test structure, and applying different gate voltages to any one MOS unit in the MOS transistor test structure; the preset second voltage application scheme is: applying a second fixed drain voltage to all MOS units in the MOS transistor test structure, and applying different gate voltages to all MOS units in the MOS transistor test structure.

[0105] Among them, the parameter acquisition module includes:

[0106] A first acquisition unit configured to acquire a first drain current, where the first drain current is the drain current of the corresponding MOS unit at different gate voltages under the preset first voltage application scheme;

[0107] A second acquisition unit configured to acquire a second drain current, where the second drain current is the drain current of each MOS unit at different gate voltages under the preset second voltage application scheme.

[0108] Among them, the testing module includes:

[0109] A first calculation unit configured to obtain a total resistance based on the first drain current and the first fixed drain voltage, where the total resistance is the sum of the channel resistance, the lightly doped region resistance, and the source-drain region resistance;

[0110] A second calculation unit configured to obtain a first linear function based on the second drain current, the second fixed drain voltage, and the total resistance, where the first linear function is a linear function of the ratio of the drain voltage to the drain current varying with the gate length;

[0111] A first determination unit, configured to determine a channel length error based on the intersection point of the first linear function;

[0112] A third calculation unit, configured to obtain an effective channel length based on a theoretical channel length and the channel length error.

[0113] Wherein, it further includes:

[0114] A second determination unit, configured to obtain the sum of the source-drain region resistance and the lightly doped region resistance based on the channel length error;

[0115] A resistance calculation module, configured to obtain a channel resistance based on the sum of the source-drain region resistance and the lightly doped region resistance and the total resistance.

[0116] The MOS transistor effective channel length testing device includes a processor and a memory. The above signal application module 410, parameter acquisition module 420, test module 430, etc. are all stored in the memory as program units, and the processor executes the above program units stored in the memory to implement the MOS transistor effective channel length test.

[0117] The processor contains a kernel, and the kernel retrieves the corresponding program units from the memory. One or more kernels can be set, and by adjusting the kernel parameters, the coordinated optimization of distributed resources in the power regulation area can be achieved through power regulation.

[0118] The memory may include non-permanent memory in a computer-readable medium, forms such as random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash memory (flash RAM), and the memory includes at least one memory chip.

[0119] An embodiment of the present invention provides a machine-readable storage medium, on which a program is stored, and when the program is executed by a processor, the MOS transistor effective channel length testing method is implemented.

[0120] An embodiment of the present invention provides a processor, and the processor is used to run a program, wherein when the program runs, the MOS transistor effective channel length testing method is executed.

[0121] In one embodiment, a computer device is provided. The computer device can be a terminal, and its internal structure diagram can be as Figure 4As shown in the figure. The computer device includes a processor A01, a network interface A02, a display screen A04, an input device A05, and a memory (not shown in the figure) connected by a system bus. Among them, the processor A01 of the computer device is used to provide computing and control capabilities. The memory of the computer device includes an internal memory A03 and a non-volatile storage medium A06. The non-volatile storage medium A06 stores an operating system B01 and a computer program B02. The internal memory A03 provides an environment for the operation of the operating system B01 and the computer program B02 in the non-volatile storage medium A06. The network interface A02 of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor A01, it realizes a method for testing the effective channel length of a MOS transistor. The display screen A04 of the computer device can be a liquid crystal display screen or an electronic ink display screen. The input device A05 of the computer device can be a touch layer covering the display screen, or a button, a trackball, or a touchpad provided on the computer device housing, or an external keyboard, touchpad, or mouse, etc.

[0122] Those skilled in the art can understand that Figure 4 the structure shown in the figure is only a block diagram of some structures related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine some components, or have different component arrangements.

[0123] In one embodiment, the MOS transistor effective channel length testing device provided by the present application can be implemented in the form of a computer program, and the computer program can run on a computer device such as Figure 4 shown. In the memory of the computer device, each program module constituting the MOS transistor effective channel length testing device can be stored. For example, Figure 3 the signal application module 410, the parameter acquisition module 420, and the testing module 430 shown in the figure. The computer program composed of each program module enables the processor to execute the steps in the method for calling the file system in each embodiment of the present application described in this specification.

[0124] Figure 4 The computer device shown in the figure can execute step 210 through the signal application module 410 in the MOS transistor effective channel length testing device shown in Figure 3 the figure, the parameter acquisition module 420 executes step 220, and the testing module 430 executes step 230.

[0125] An embodiment of the present application provides a device, which includes a processor, a memory, and a program stored on the memory and executable on the processor. It is applied to a MOS transistor test structure. The MOS transistor test structure includes multiple MOS units. Each MOS unit includes a substrate, a source electrode, a drain electrode, and a gate electrode. The source electrode and the drain electrode are respectively disposed on the substrate, the gate electrode is located between the source electrode and the drain electrode, and an isolation oxide layer is provided between the substrate and the gate electrode. Among them, all MOS units share a substrate, the gate lengths of all MOS units are different, and adjacent two MOS units share a source electrode or a drain electrode. When the processor executes the program, the following steps are implemented:

[0126] Apply a voltage signal to the MOS units in the MOS transistor test structure according to a preset voltage application scheme;

[0127] Obtain parameter information of the MOS units in the MOS transistor test structure under the voltage signal;

[0128] Based on the parameter information, obtain the effective channel length.

[0129] In one embodiment, the preset voltage application scheme includes a preset first voltage application scheme and a preset second voltage application scheme;

[0130] The preset first voltage application scheme is: apply a first fixed drain voltage to all MOS units in the MOS transistor test structure, and apply different gate voltages to any one MOS unit in the MOS transistor test structure;

[0131] The preset second voltage application scheme is: apply a second fixed drain voltage to all MOS units in the MOS transistor test structure, and apply different gate voltages to all MOS units in the MOS transistor test structure.

[0132] In one embodiment, the obtaining of the parameter information of the MOS units in the MOS transistor test structure under the voltage signal includes:

[0133] Obtain a first drain current, where the first drain current is the drain current of the corresponding MOS unit at different gate voltages under the preset first voltage application scheme;

[0134] Obtain a second drain current, where the second drain current is the drain current of each MOS unit at different gate voltages under the preset second voltage application scheme.

[0135] In one embodiment, the obtaining of the effective channel length based on the parameter information includes:

[0136] Based on the first drain current and the first fixed drain voltage, a total resistance is obtained, and the total resistance is the sum of the channel resistance, the lightly doped region resistance, and the source / drain region resistance;

[0137] Based on the second drain current, the second fixed drain voltage, and the total resistance, a first linear function is obtained, and the first linear function is a linear function in which the ratio of the drain voltage to the drain current changes with the gate length;

[0138] Based on the intersection point of the first linear function, a channel length error is determined;

[0139] Based on the theoretical channel length and the channel length error, an effective channel length is obtained.

[0140] In one embodiment, the first linear function is:

[0141]

[0142] R sd is the source / drain region resistance, R LDD is the lightly doped region resistance, R channel is the channel resistance, L poly is the gate length, ΔL is the difference between the mask channel length and the effective channel length, W is the channel width, c OX is the gate capacitance, μ n is the electron mobility, V gs is the gate voltage, V t is the threshold voltage, V ds is the second fixed drain voltage, I ds is the second drain current.

[0143] In one embodiment, it further includes:

[0144] Based on the channel length error, the sum of the source / drain region resistance and the lightly doped region resistance is obtained;

[0145] Based on the sum of the source / drain region resistance and the lightly doped region resistance and the total resistance, the channel resistance is obtained.

[0146] In one embodiment, gate electrodes are respectively arranged at both ends of the gate.

[0147] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, a system, or a computer program product. Therefore, the present application can adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application can adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0148] This application is described with reference to the flowcharts and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the present application. It should be understood that each flow and / or block in the flowcharts and / or block diagrams, and combinations of flows and / or blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing device to generate a machine, such that the instructions executed by the processor of the computer or other programmable data processing device produce means for implementing the functions specified in one Figure 1 flow or multiple flows and / or blocks Figure 1 block or multiple blocks.

[0149] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, such that the instructions stored in the computer-readable memory produce a manufacture including instruction means that implement the functions specified in one Figure 1 flow or multiple flows and / or blocks Figure 1 block or multiple blocks.

[0150] These computer program instructions can also be loaded onto a computer or other programmable data processing device, such that a series of operation steps are executed on the computer or other programmable device to generate a computer-implemented process, and thus the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in one Figure 1 flow or multiple flows and / or blocks Figure 1 block or multiple blocks.

[0151] In a typical configuration, a computing device includes one or more processors (CPUs), an input / output interface, a network interface, and memory.

[0152] The memory may include non-permanent memory in the form of computer-readable media, random access memory (RAM), and / or non-volatile memory such as read-only memory (ROM) or flash RAM. The memory is an example of computer-readable media.

[0153] A computer-readable medium includes permanent and non-permanent, removable and non-removable media that can implement information storage by any method or technology. The information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, magnetic cassette tapes, magnetic tape disk storage or other magnetic storage devices, or any other non-transitory medium that can be used to store information accessible by a computing device. As defined herein, a computer-readable medium does not include transitory computer-readable media, such as modulated data signals and carrier waves.

[0154] It should also be noted that the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, such that a process, method, article or apparatus comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or apparatus. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or apparatus comprising the element.

[0155] The above are only embodiments of the present application and are not used to limit the present application. For those skilled in the art, various changes and modifications can be made to the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included within the scope of the claims of the present application.

Claims

1. A method for testing the effective channel length of a MOS tube, characterized in that: Applied to a MOS tube test structure, the MOS tube test structure comprises a plurality of MOS units, each MOS unit comprises a substrate, a source, a drain and a gate, the source and the drain are respectively arranged on the substrate, the gate is located between the source and the drain, and an isolation oxide layer is arranged between the substrate and the gate; wherein each MOS unit shares a substrate, each MOS unit has a different gate length, and two adjacent MOS units share a source or a drain; the MOS tube effective channel length test method comprises: According to a preset voltage application scheme, a voltage signal is applied to the MOS unit in the MOS tube test structure; the preset voltage application scheme includes a preset first voltage application scheme and a preset second voltage application scheme; the preset first voltage application scheme is: applying a first fixed drain voltage to all MOS units in the MOS tube test structure, and applying a different gate voltage to any MOS unit in the MOS tube test structure; the preset second voltage application scheme is: applying a second fixed drain voltage to all MOS units in the MOS tube test structure, and applying a different gate voltage to all MOS units in the MOS tube test structure; Acquiring parameter information of a MOS unit in the MOS tube test structure under the voltage signal; Based on the parameter information, an effective channel length is obtained.

2. The MOS tube effective channel length testing method according to claim 1, characterized in that: The obtaining parameter information of the MOS unit in the MOS tube test structure under the voltage signal includes: Obtaining a first drain current, where the first drain current is a drain current of a corresponding MOS unit at different gate voltages under the preset first voltage application scheme; A second drain current is obtained, where the second drain current is the drain current of each MOS unit at different gate voltages under the preset second voltage application scheme.

3. The MOS tube effective channel length testing method according to claim 2, characterized in that: The obtaining of the effective channel length based on the parameter information comprises: Based on the first drain current and the first fixed drain voltage, a total resistance is obtained, wherein the total resistance is the sum of the channel resistance, the lightly doped region resistance and the source and drain region resistance; Based on the second drain current, the second fixed drain voltage and the total resistance, a first linear function is obtained, wherein the first linear function is a linear function of the ratio of the drain voltage to the drain current as the gate length changes; Determining a channel length error based on an intersection point of the first linear function; Based on the theoretical channel length and the channel length error, an effective channel length is obtained.

4. The MOS tube effective channel length testing method according to claim 3, characterized in that: The first linear function is: R sd is the source-drain resistance, R LDD is the resistance of the lightly doped region, R channel is the channel resistance, L poly is the gate length, ΔL is the difference between the mask channel length and the effective channel length, W is the channel width, C OX is the gate capacitance, μ n is the electron mobility, V gs is the gate voltage, V t is the threshold voltage, V ds is the second fixed drain voltage, I ds is the second drain current.

5. The MOS tube effective channel length testing method according to claim 3, characterized in that: Also includes: Based on the channel length error, a sum of the source and drain region resistance and the lightly doped region resistance is obtained; The channel resistance is obtained based on the sum of the source and drain region resistance and the lightly doped region resistance and the total resistance.

6. The MOS tube effective channel length testing method according to claim 1, characterized in that: Gate electrodes are respectively arranged at two ends of the gate.

7. A MOS tube effective channel length test device, characterized in that: Applied to a MOS tube test structure, the MOS tube test structure includes a plurality of MOS units, each MOS unit includes a substrate, a source, a drain and a gate, the source and the drain are respectively arranged on the substrate, the gate is located between the source and the drain, and an isolation oxide layer is arranged between the substrate and the gate; wherein each MOS unit shares a substrate, each MOS unit has a different gate length, and two adjacent MOS units share a source or a drain; the MOS tube effective channel length test device includes: A signal applying module, used for applying a voltage signal to the MOS unit in the MOS tube test structure according to a preset voltage applying scheme; the preset voltage applying scheme includes a preset first voltage applying scheme and a preset second voltage applying scheme; the preset first voltage applying scheme is: applying a first fixed drain voltage to all MOS units in the MOS tube test structure, and applying a different gate voltage to any MOS unit in the MOS tube test structure; the preset second voltage applying scheme is: applying a second fixed drain voltage to all MOS units in the MOS tube test structure, and applying a different gate voltage to all MOS units in the MOS tube test structure; A parameter acquisition module, used to acquire parameter information of the MOS unit in the MOS tube test structure under the voltage signal; The testing module is used to obtain the effective channel length based on the parameter information.

8. The MOS tube effective channel length testing device according to claim 7, characterized in that: The parameter acquisition module includes: A first acquisition unit, configured to acquire a first drain current, wherein the first drain current is a drain current of a corresponding MOS unit under different gate voltages under the preset first voltage application scheme; The second acquisition unit is used to acquire a second drain current, where the second drain current is the drain current of each MOS unit at different gate voltages under the preset second voltage application scheme.

9. The MOS tube effective channel length testing device according to claim 8, characterized in that: The test module includes: a first calculation unit, configured to obtain a total resistance based on the first drain current and the first fixed drain voltage, wherein the total resistance is the sum of a channel resistance, a lightly doped region resistance, and a source-drain region resistance; a second calculation unit, configured to obtain a first linear function based on the second drain current, the second fixed drain voltage and the total resistance, wherein the first linear function is a linear function of a ratio of a drain voltage to a drain current varying with a gate length; A first determining unit, configured to determine a channel length error based on an intersection point of the first linear function; The third calculation unit is used to obtain an effective channel length based on the theoretical channel length and the channel length error.

10. The MOS tube effective channel length testing device according to claim 9, characterized in that: Also includes: A second determining unit, configured to obtain a sum of a source-drain region resistance and a lightly doped region resistance based on the channel length error; The resistance calculation module is used to obtain the channel resistance based on the sum of the source and drain region resistance and the lightly doped region resistance and the total resistance.

11. An electronic device, characterized in that: The electronic device includes: at least one processor; a memory connected to the at least one processor; The memory stores instructions that can be executed by the at least one processor, and the at least one processor implements the MOS tube effective channel length testing method according to any one of claims 1 to 6 by executing the instructions stored in the memory.

12. A machine-readable storage medium having instructions stored thereon, characterized in that: When the instruction is executed by a processor, the processor is configured to execute the MOS tube effective channel length testing method according to any one of claims 1 to 6.

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