Semiconductor structure and preparation method
By forming a cover layer on the substrate surface of the semiconductor structure and retaining the side protective layer, the problem of oxide consumption in the shallow trough isolation structure during wet cleaning is solved, and the reliability and service life of the device are improved.
Patent Information
- Application Number
- CN202411441534.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-15
- Publication Date
- 2025-01-10
AI Technical Summary
During the manufacturing process of metal oxide semiconductor field effect tube (MOSFET), the corner areas where the shallow trough isolation structure contacts the surface of the active area are prone to oxide consumption during the wet cleaning process, resulting in failure of the isolation structure and affecting the reliability of the device sex.
By forming a cover layer on the substrate surface, covering the side and top surface of the substrate surface and the convex portion, and retaining the cover layer at the connection between the side surface of the convex portion and the substrate as a side protective layer, removing the cover layer of the remaining portion. , to protect the corner area where the shallow trough isolation structure contacts the surface of the active area to prevent oxide defects.
Effectively prevent the isolation medium of shallow trough isolation structure from defects, ensure the isolation effect, improve the yield and reliability of the device, and extend the service life.
Smart Images
Figure CN119297152A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductors, and in particular to a semiconductor structure and a preparation method thereof. Background Art
[0002] In the manufacture of Metal Oxide Semiconductor Field Effect Transistor (MOSFET), the reliability of the gate oxide layer is very important. In the existing process, in the process of generating shallow trench isolation (Shallow Trench Isolation), the silicon nitride layer and the oxide layer on the surface of the active area are directly removed by grinding, and multiple wet cleanings are performed in the subsequent ion implantation process and the gate oxide layer preparation process. Since the solution used for wet cleaning is mixed with weak alkaline substances (such as ammonium hydroxide, the chemical formula is NH4OH), these weak alkaline substances will consume the oxide filled in the shallow trench isolation structure. In particular, in the corner area where the shallow trench isolation structure contacts the surface of the active area, when wet cleaning is performed, the cleaning solution remains in the corner area for a longer time than other planar parts, so the oxide is consumed more, causing the shallow trench isolation structure to be abnormal.
[0003] Figure 1 It is a schematic diagram of a device structure of an abnormal shallow trench isolation structure in the prior art; Figure 2 Schematic diagram of a device structure after a polysilicon layer is deposited on the surface of an abnormal shallow trench isolation structure in the prior art. Figure 1 As shown, a shallow trench isolation structure 01 is formed in the semiconductor structure, and a first gate oxide layer 03 and a second gate oxide layer 04 are formed on the surface of the active area isolated by the shallow trench isolation structure 01; the corner area where the shallow trench isolation structure 01 contacts the surface of the active area has a notch 02. After a polysilicon layer is deposited on the surface of the abnormal shallow trench isolation structure, as shown in FIG. Figure 2 As shown, a polysilicon layer 05 is deposited on the surface of the device, and the corner area 02 of the shallow trench isolation structure 01 is filled with polysilicon 05, which makes the isolation function of the shallow trench isolation structure 01 invalid, affecting the reliability of subsequent devices. Summary of the invention
[0004] The technical problem to be solved by the present invention is to provide a semiconductor structure and a preparation method to ensure that the oxide in the corner area of the shallow trench isolation structure and the active area is not consumed.
[0005] In order to solve the above problems, the present invention provides a method for preparing a semiconductor structure, comprising: providing a substrate, wherein a shallow trench isolation structure is formed in the substrate, wherein the shallow trench isolation structure includes an embedded portion embedded in the substrate and a raised portion higher than the surface of the substrate; forming a covering layer on the surface of the substrate, wherein the covering layer covers the surface of the substrate and the side and top surfaces of the raised portion; retaining the covering layer on the side surfaces of the raised portion and the connection between the side surfaces and the substrate to form a side protection layer, and removing the remaining portion of the covering layer.
[0006] In some embodiments, the material of the capping layer is polysilicon.
[0007] In some embodiments, an etch-back process is used to remove the cover layer except for the side surface of the protrusion and the connection between the side surface and the substrate.
[0008] In some embodiments, the embedded portion includes a liner layer and a filled dielectric material, and the protruding portion is composed of the dielectric material.
[0009] In some embodiments, the dielectric material is silicon oxide.
[0010] In some embodiments, the step of forming the shallow trench isolation structure on the substrate includes: forming a barrier layer and a mask layer in sequence from bottom to top on the surface of the substrate, forming a shallow trench on the substrate using photolithography and etching processes, and obtaining a patterned barrier layer and a patterned mask layer; forming the liner layer on the inner wall of the shallow trench; forming a dielectric material layer that fills the shallow trench and is higher than the surface of the substrate by depositing a dielectric material; grinding the dielectric material layer until the patterned mask layer is exposed; and removing the patterned mask layer and the patterned barrier layer in sequence to form the shallow trench isolation structure on the substrate.
[0011] In some embodiments, the liner layer is formed on the inner wall of the shallow trench by an oxidation process.
[0012] In some embodiments, the dielectric material layer is formed by deposition using a high density plasma process.
[0013] In some embodiments, the dielectric material layer is polished by a chemical mechanical polishing process until the patterned mask layer is exposed.
[0014] In some embodiments, the step of retaining the side of the protrusion and the covering layer at the connection between the side and the substrate to form a side protection layer, and removing the remaining part of the covering layer, further includes: forming a gate oxide layer on the active area defined by the shallow trench isolation structure on the substrate, the upper surface of the gate oxide layer is connected to the bottom of the side protection layer, and the lower surface of the gate oxide layer covers the active area; forming a polysilicon layer on the surface of the gate oxide layer and the surface exposed by the shallow trench isolation structure; patterning the polysilicon layer to form a gate, and retaining the side protection layer inside the gate.
[0015] In some embodiments, in the step of forming a gate oxide layer in the active area defined by the shallow trench isolation structure on the substrate, a dual gate oxide process is used to generate a first gate oxide layer and a second gate oxide layer in the active area.
[0016] In order to solve the above problems, the present invention also provides a semiconductor structure, including: a substrate; a shallow trench isolation structure formed in the substrate, the shallow trench isolation structure including an embedded portion embedded in the substrate and a raised portion higher than the surface of the substrate; a side protection layer, the side protection layer is located on the side of the raised portion and at the connection between the side and the substrate.
[0017] In some embodiments, the side protection layer is made of polysilicon.
[0018] In some embodiments, the embedded portion includes a liner layer and a filled dielectric material, and the protruding portion is composed of the dielectric material.
[0019] In some embodiments, the material of the liner layer is silicon oxide, and the dielectric material is silicon oxide.
[0020] The above technical scheme forms a covering layer on the surface of a substrate formed with a shallow trench isolation structure, wherein the shallow trench isolation structure includes an embedded portion embedded in the substrate and a raised portion higher than the substrate surface, so that the covering layer covers the substrate surface and the side and top surfaces of the raised portion; retains the side surfaces of the raised portion and the covering layer at the connection between the side surfaces and the substrate to form a side protection layer, removes the remaining covering layer, and protects the corner area where the shallow trench isolation structure contacts the active area surface through the side protection layer in subsequent processes, prevents the isolation dielectric of the shallow trench isolation structure from being damaged, ensures the isolation effect of the shallow trench isolation structure, improves the yield and reliability of the device, and extends the service life of the device.
[0021] It should be understood that the above general description and the detailed description below are exemplary and explanatory only and cannot limit the present invention. The techniques, methods and devices known to ordinary technicians in the relevant field may not be discussed in detail, but where appropriate, the techniques, methods and devices should be considered as part of the authorization specification. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments of the present invention are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0023] Figure 1 It is a schematic diagram of a device structure of an abnormal shallow trench isolation structure in the prior art;
[0024] Figure 2 It is a schematic diagram of a device structure after a polysilicon layer is deposited on the surface of an abnormal shallow trench isolation structure in the prior art;
[0025] Figure 3 is a flow chart of a method for preparing a semiconductor structure provided by an embodiment of the present invention;
[0026] Figure 4 is a flowchart of steps for forming the shallow trench isolation structure provided by an embodiment of the present invention;
[0027] Figure 5 is a flowchart of steps for preparing a gate structure using the semiconductor structure provided by an embodiment of the present invention;
[0028] Figure 6 is a schematic diagram of a device structure formed by the step of forming a shallow groove in the substrate provided by an embodiment of the present invention;
[0029] Figure 7 is a schematic diagram of a device structure formed by the step of forming a liner layer on the inner wall of the shallow groove provided by an embodiment of the present invention;
[0030] Figure 8 is a schematic diagram of a device structure formed by the steps of depositing a dielectric material layer provided by an embodiment of the present invention;
[0031] Fig. 9 It is a schematic diagram of a device structure formed by the steps of grinding a medium material layer to expose a patterned mask layer provided by an embodiment of the present invention;
[0032] Fig.10 It is a schematic diagram of a device structure formed by the steps of removing a patterned mask layer and a patterned barrier layer provided in one embodiment of the present invention;
[0033] Fig.11 is a schematic diagram of a device structure formed by the step of forming a covering layer on the surface of the substrate provided by an embodiment of the present invention;
[0034] Fig.12 is a schematic diagram of a device structure formed by the step of forming a side protection layer provided in one embodiment of the present invention;
[0035] Fig.13 It is a schematic diagram of a device structure formed by the step of forming a gate oxide layer in an active area provided by an embodiment of the present invention;
[0036] Fig.14 It is a schematic diagram of a device structure formed by the step of forming a polysilicon layer on the surface of the gate oxide layer and the surface exposed by the shallow trench isolation structure provided by one embodiment of the present invention;
[0037] Fig.15A is a schematic diagram of a device structure formed by the step of patterning the polysilicon layer to form a gate provided by an embodiment of the present invention;
[0038] Fig. 15B It is a schematic diagram of a top view of a device structure formed by the step of patterning the polysilicon layer to form a gate provided by an embodiment of the present invention. DETAILED DESCRIPTION
[0039] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0040] An embodiment of the present invention provides a method for preparing a semiconductor structure.
[0041] Please refer to Figure 3 to Figure 15B .in, Figure 3 is a flow chart of a method for preparing a semiconductor structure provided by an embodiment of the present invention; Figure 4 is a flowchart of steps for forming the shallow trench isolation structure provided by an embodiment of the present invention; Figure 5 is a flowchart of steps for preparing a gate structure using the semiconductor structure provided by an embodiment of the present invention; Figure 6 is a schematic diagram of a device structure formed by the step of forming a shallow groove in the substrate provided by an embodiment of the present invention; Figure 7 is a schematic diagram of a device structure formed by the step of forming a liner layer on the inner wall of the shallow groove provided by an embodiment of the present invention; Figure 8 is a schematic diagram of a device structure formed by the steps of depositing a dielectric material layer provided by an embodiment of the present invention; Fig. 9It is a schematic diagram of a device structure formed by the steps of grinding a medium material layer to expose a patterned mask layer provided by an embodiment of the present invention; Fig.10 It is a schematic diagram of a device structure formed by the steps of removing a patterned mask layer and a patterned barrier layer provided in one embodiment of the present invention; Fig.11 is a schematic diagram of a device structure formed by the step of forming a covering layer on the surface of the substrate provided by an embodiment of the present invention; Fig.12 is a schematic diagram of a device structure formed by the step of forming a side protection layer provided in one embodiment of the present invention; Fig.13 It is a schematic diagram of a device structure formed by the step of forming a gate oxide layer in an active area provided by an embodiment of the present invention; Fig.14 It is a schematic diagram of a device structure formed by the step of forming a polysilicon layer on the surface of the gate oxide layer and the surface exposed by the shallow trench isolation structure provided by one embodiment of the present invention;
[0042] Fig.15A is a schematic diagram of a device structure formed by the step of patterning the polysilicon layer to form a gate provided by an embodiment of the present invention; Fig. 15B It is a schematic diagram of a top view of a device structure formed by the step of patterning the polysilicon layer to form a gate provided by an embodiment of the present invention.
[0043] refer to Figure 3 The method for preparing the semiconductor structure includes: step S11, providing a substrate, wherein a shallow trench isolation structure is formed in the substrate, wherein the shallow trench isolation structure includes an embedded portion embedded in the substrate and a raised portion higher than the surface of the substrate; step S12, forming a covering layer on the surface of the substrate, wherein the covering layer covers the surface of the substrate and the side and top surfaces of the raised portion; step S13, retaining the covering layer on the side surfaces of the raised portion and the connection between the side surfaces and the substrate to form a side protection layer, and removing the remaining covering layer.
[0044] Refer to step S11 and Fig.10 A substrate 10 is provided, wherein a shallow trench isolation structure 11 is formed in the substrate 10, wherein the shallow trench isolation structure 11 comprises an embedded portion 111 embedded in the substrate 10 and a raised portion 112 higher than the surface of the substrate 10. The embedded portion 111 comprises a liner layer 12 and a filled dielectric material, and the raised portion 112 is composed of a dielectric material. The dielectric material is silicon oxide.
[0045] refer to Figure 4In this step, the step of forming the shallow trench isolation structure further includes: step S101, forming a barrier layer and a mask layer in sequence from bottom to top on the surface of the substrate, using photolithography and etching processes to form a shallow trench on the substrate, and obtaining a patterned barrier layer and a patterned mask layer; step S102, forming the liner layer on the inner wall of the shallow trench; step S103, forming a dielectric material layer that fills the shallow trench and is higher than the surface of the substrate by depositing a dielectric material; step S104, grinding the dielectric material layer until the patterned mask layer is exposed; step S105, removing the patterned mask layer and the patterned barrier layer in sequence to form the shallow trench isolation structure on the substrate.
[0046] The steps of forming the shallow trench isolation structure are described in detail below.
[0047] Refer to step S101 and Figure 6 A barrier layer and a mask layer are sequentially formed on the surface of the substrate 10 from bottom to top, a shallow groove 15 is formed on the substrate 10 by photolithography and etching processes, and a patterned barrier layer 13 and a patterned mask layer 14 are obtained.
[0048] In this embodiment, the material of the blocking layer is silicon oxide, and the material of the mask layer is silicon nitride. Accordingly, the material of the patterned blocking layer 13 is silicon oxide, and the material of the patterned mask layer 14 is silicon nitride.
[0049] Refer to step S102 and Figure 7 , the lining layer 12 is formed on the inner wall of the shallow groove 15. Figure 7 As shown, the liner layer 12 covers the bottom wall and side walls of the shallow trench 15 connected to the substrate 10, and the liner layer 12 also covers the side walls of the shallow trench 15 connected to the patterned barrier layer 13 and the patterned mask layer 14. In this embodiment, the liner layer 12 is formed on the inner wall of the shallow trench 15 by an oxidation process, and the material of the liner layer 12 is silicon oxide. In some embodiments, the liner layer 12 does not completely cover the side walls of the shallow trench 15 connected to the patterned barrier layer 13 and the patterned mask layer 14.
[0050] Refer to step S103 and Figure 8 , a dielectric material layer 16 is formed by depositing a dielectric material to fill the shallow groove 15 and to protrude above the surface of the substrate 10. In this embodiment, the dielectric material layer 16 is formed by deposition using a high density plasma (HDP) process. Specifically, the dielectric material is deposited by a high density plasma process to form a dielectric material layer 16 that fills the shallow groove 15 and protrude above the surface of the substrate 10. The dielectric material layer 16 is higher than the surface of the substrate 10, providing a margin for the subsequent grinding process.
[0051] In this embodiment, the dielectric material layer 16 is made of silicon oxide. The silicon oxide in the shallow trench 15 enables the formed shallow trench isolation mechanism to have an isolation function.
[0052] Refer to step S104 and Fig. 9 , grinding the dielectric material layer 16 until the patterned mask layer 14 is exposed. In this step, the dielectric material layer 16 is ground by a chemical mechanical polishing process until the patterned mask layer 14 is exposed.
[0053] Refer to step S105 and Fig.10 , the patterned mask layer 14 and the patterned barrier layer 13 are removed in sequence, and the shallow trench isolation structure 11 is formed on the substrate 10. The shallow trench isolation structure 11 includes an embedded portion 111 embedded in the substrate 10 and a protruding portion 112 higher than the surface of the substrate 10.
[0054] In other embodiments, the shallow trench isolation structure 11 may be formed in other ways.
[0055] form Fig.10 After the shallow trench isolation structure shown in the figure is formed, if subsequent processes are directly performed on the shallow trench isolation structure, a gap may appear in the corner area where the shallow trench isolation structure contacts the surface of the active area.
[0056] Continue to refer Figure 3 The present invention adopts the following steps to solve the gap problem in the corner area where the shallow trench isolation structure contacts the surface of the active area.
[0057] Refer to step S12 and Fig.11 A covering layer 170 is formed on the surface of the substrate 10, and the covering layer 170 covers the surface of the substrate 10 and the side and top surfaces of the protrusion 112. The covering layer 170 is made of polysilicon.
[0058] Refer to step S13 and Fig.12 , retain the side of the protrusion 112 and the cover layer 170 at the connection between the side and the substrate 10 to form a side protection layer 17, and remove the remaining part of the cover layer 170. In this embodiment, a back etching process is used to remove part of the cover layer 170. In other embodiments, part of the cover layer 170 can be removed by other processes.
[0059] After executing step S13, the generated semiconductor structure can be used to prepare a gate structure. Figure 5The step of preparing a gate structure using the semiconductor structure further includes: step S14, forming a gate oxide layer in the active area defined by the shallow trench isolation structure on the substrate, the upper surface of the gate oxide layer is connected to the bottom of the side protection layer, and the lower surface of the gate oxide layer covers the active area; step S15, forming a polysilicon layer on the surface of the gate oxide layer and the surface exposed by the shallow trench isolation structure; step S16, patterning the polysilicon layer to obtain a patterned polysilicon layer, and retaining the side protection layer connected to the patterned polysilicon layer.
[0060] Refer to step S14 and Fig.13 A gate oxide layer 18 is formed on the active area defined by the shallow trench isolation structure 11 on the substrate 10, the upper surface of the gate oxide layer 18 is connected to the bottom of the side protection layer 17, and the lower surface of the gate oxide layer 18 covers the active area. Fig.13 As shown, the shallow trench isolation structure 11 includes an embedded portion 111 embedded in the substrate 10 and a raised portion 112 higher than the surface of the substrate, a pad layer 12 is formed on the surface of the embedded portion 111 in contact with the substrate 10, a side protection layer 17 is formed on the side of the raised portion 112, and the connection between the side and the substrate 10 has the side protection layer 17 and the gate oxide layer 18 from top to bottom, which can ensure that the active area is covered by the gate oxide layer 18 to prevent leakage.
[0061] In this step, a dual gate oxide (DGO) process is used to generate the gate oxide layer 18 in the active area. The generated gate oxide layer 18 includes a first gate oxide layer 181 and a second gate oxide layer 182. The first gate oxide layer 181 and the second gate oxide layer 182 are connected to each other and completely cover the active area.
[0062] In this embodiment, the dielectric material is silicon oxide. In the process of forming the gate oxide layer 18, the dielectric material in the protrusion 112 will be consumed. Fig.13 The top surface of the protrusion 112 is lower than the side protection layer 17 .
[0063] Refer to step S15 and Fig.14 , a polysilicon layer 190 is formed on the surface of the gate oxide layer 18 and the surface exposed by the shallow trench isolation structure. In this step, the side protection layer 17 and the polysilicon layer 190 are made of the same material, that is, polysilicon, and the side protection layer 17 has little effect on the overall device. However, the present invention avoids the problem of gaps in the filling oxide at the corner area where the shallow trench isolation structure contacts the surface of the active area by changing the process steps.
[0064] Refer to step S16 and Figure 15A to Figure 15B , the polysilicon layer 190 is patterned to obtain the gate 19, and the side protection layer 17 inside the gate 19 is retained. Fig.15A As shown, in this step, the redundant polysilicon layer 190 is removed by photolithography and etching processes. Accordingly, in this step, the gate oxide layer 18 in the area corresponding to the removed portion of the polysilicon layer 190 is also removed. Fig. 15B As shown in , this step also removes the side protection layer 17 inside the removed portion of the polysilicon layer 190 , and retains the side protection layer 17 inside the gate 19 .
[0065] Based on the same inventive concept, an embodiment of the present invention further provides a semiconductor structure.
[0066] refer to Fig.12 The semiconductor structure includes: a substrate 10, a shallow trench isolation structure 11 and a side protection layer 17. The shallow trench isolation structure 11 is formed in the substrate 10, and the shallow trench isolation structure 11 includes an embedded portion 111 embedded in the substrate 10 and a protruding portion 112 higher than the surface of the substrate 10; the side protection layer 17 is located on the side of the protruding portion 112 and the connection between the side and the substrate 10.
[0067] In this embodiment, the material of the side protection layer 17 is polysilicon.
[0068] In this embodiment, the embedded portion 112 includes a liner layer 12 and a filled dielectric material, and the protruding portion 112 is composed of a dielectric material. The liner layer is made of silicon oxide, and the dielectric material is silicon oxide.
[0069] In the above-mentioned embodiment, a covering layer is formed on the surface of a substrate having a shallow trench isolation structure, wherein the shallow trench isolation structure includes an embedded portion embedded in the substrate and a raised portion higher than the substrate surface, so that the covering layer covers the substrate surface and the side and top surfaces of the raised portion; the side surfaces of the raised portion and the covering layer at the connection between the side surfaces and the substrate are retained to form a side protection layer, and the remaining covering layer is removed. The side protection layer is used to protect the corner area where the shallow trench isolation structure contacts the surface of the active area in subsequent processes, thereby preventing the isolation dielectric of the shallow trench isolation structure from being damaged, thereby ensuring the isolation effect of the shallow trench isolation structure, improving the yield and reliability of the device, and extending the service life of the device.
[0070] It should be noted that, in this document, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion. The various embodiments in this specification are described in a related manner, and the same and similar parts between the various embodiments can be referenced to each other, and each embodiment focuses on the differences from other embodiments.
[0071] The above is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention. It should be noted that a person skilled in the art can make several improvements and modifications without departing from the principle of the present invention, and these improvements and modifications should also be regarded as the protection scope of the present invention.
Claims
1. A method for preparing a semiconductor structure, characterized in that: include: A substrate is provided, wherein a shallow trench isolation structure is formed in the substrate, wherein the shallow trench isolation structure comprises an embedded portion embedded in the substrate and a protruding portion higher than a surface of the substrate; forming a covering layer on the surface of the substrate, wherein the covering layer covers the surface of the substrate and the side surfaces and the top surface of the protruding portion; The side surface of the protruding portion and the covering layer at the connection between the side surface and the substrate are retained to form a side protection layer, and the remaining portion of the covering layer is removed.
2. The method according to claim 1, characterized in that The material of the cover layer is polysilicon.
3. The method according to claim 1, characterized in that The cover layer other than the side surface of the protrusion and the connection between the side surface and the substrate is removed by an etch-back process.
4. The method according to claim 1, characterized in that The embedded part includes a lining layer and a filled dielectric material, and the protruding part is composed of the dielectric material.
5. The method according to claim 4, characterized in that The dielectric material is silicon oxide.
6. The method according to claim 4, characterized in that The step of forming the shallow trench isolation structure on the substrate comprises: A barrier layer and a mask layer are sequentially formed on the surface of the substrate from bottom to top, a shallow groove is formed on the substrate by photolithography and etching processes, and a patterned barrier layer and a patterned mask layer are obtained; forming the lining layer on the inner wall of the shallow groove; Forming a dielectric material layer filling the shallow groove and protruding above the surface of the substrate by depositing a dielectric material; Grinding the dielectric material layer until the patterned mask layer is exposed; The patterned mask layer and the patterned blocking layer are removed in sequence to form the shallow trench isolation structure on the substrate.
7. The method according to claim 6, characterized in that The liner layer is formed on the inner wall of the shallow groove by an oxidation process.
8. The method according to claim 6, characterized in that The dielectric material layer is formed by deposition through a high-density plasma process.
9. The method according to claim 6, characterized in that The dielectric material layer is polished by a chemical mechanical polishing process until the patterned mask layer is exposed.
10. The method according to claim 1, characterized in that After the step of retaining the side surface of the protruding portion and the covering layer at the connection between the side surface and the substrate to form a side protection layer and removing the remaining portion of the covering layer, the method further comprises: Forming a gate oxide layer in the active area defined by the shallow trench isolation structure on the substrate, wherein the upper surface of the gate oxide layer is connected to the bottom of the side protection layer, and the lower surface of the gate oxide layer covers the active area; forming a polysilicon layer on the surface of the gate oxide layer and the exposed surface of the shallow trench isolation structure; The polysilicon layer is patterned to form a gate, and the side protection layer inside the gate is retained.
11. The method according to claim 10, characterized in that In the step of forming a gate oxide layer in the active area defined by the shallow trench isolation structure on the substrate, a dual gate oxide process is used to generate a first gate oxide layer and a second gate oxide layer in the active area.
12. A semiconductor structure, characterized in that: include: substrate; A shallow trench isolation structure is formed in the substrate, wherein the shallow trench isolation structure includes an embedded portion embedded in the substrate and a raised portion higher than a surface of the substrate; A side protection layer is located on the side of the protruding portion and at the connection between the side and the substrate.
13. The semiconductor structure according to claim 12, characterized in that: The material of the side protection layer is polysilicon.
14. The semiconductor structure according to claim 12, characterized in that: The embedded part includes a lining layer and a filled dielectric material, and the protruding part is composed of the dielectric material.
15. The semiconductor structure according to claim 14, characterized in that: The material of the liner layer is silicon oxide, and the dielectric material is silicon oxide.