Semiconductor packaging structure and preparation method thereof

Abstract

The invention relates to a semiconductor packaging structure and a preparation method thereof, the semiconductor packaging structure comprises a substrate, a substrate-free rewiring layer and an isolation buffer layer, and the substrate comprises an interconnection region and a bonding pad located at the periphery of the interconnection region; the substrate-free rewiring layer is located in the interconnection region, is completely embedded in the substrate and is used for electrically connecting at least two bare chips located on the substrate, and the two bare chips are electrically connected with the substrate through corresponding bonding pads respectively; and the isolation buffer layer is located between the outer side wall of the substrate-free rewiring layer and the substrate, so that the problem of high-density interconnection of multiple chips can be at least solved, the packaging cost is reduced, the size of the packaging structure is reduced, and the input / output bandwidth and the power efficiency of the packaging structure are improved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor packaging technology, and in particular to a semiconductor packaging structure and a preparation method thereof. Background Art

[0002] With the continuous development of semiconductor packaging technology, the number of chips in advanced packaging technology continues to increase, and a silicon interposer (Si interposer) is generally introduced to interconnect multiple chips.

[0003] However, Si interposer is expensive. When applied to multi-chip interconnect packaging structures on organic substrates, it will limit the input / output (I / O) bandwidth and power efficiency of the multi-chip interconnect packaging structures, making it difficult to meet the cost and performance requirements of multi-chip high-density interconnect packaging structures. Summary of the invention

[0004] Based on this, the present disclosure provides a semiconductor packaging structure and a preparation method thereof, which can at least solve the problem of high-density interconnection of multiple chips, reduce packaging costs, reduce the volume of the packaging structure, and improve the input / output bandwidth and power efficiency of the packaging structure.

[0005] According to various embodiments of the present disclosure, on the one hand, a semiconductor packaging structure is provided, including a substrate, a substrateless redistribution layer and an isolation buffer layer, the substrate including an interconnection area and solder pads located on the periphery of the interconnection area; the substrateless redistribution layer is located in the interconnection area and is completely embedded in the substrate, and is used to electrically connect at least two bare chips located on the substrate, and the two bare chips are electrically connected to the substrate via corresponding solder pads respectively; the isolation buffer layer is located between the outer side wall of the substrateless redistribution layer and the substrate.

[0006] In the semiconductor packaging structure in the above-mentioned embodiment, by embedding the entire substrate-free redistribution layer into the substrate, the multi-layer interconnection layer in the substrate-free redistribution layer is directly used to realize high-density interconnection between at least two bare chips. Compared with using Si interposer to realize multi-chip interconnection, it is possible to effectively reduce the packaging cost, reduce the volume of the packaging structure, and improve the chip interconnection density, and avoid the increase in the volume of the semiconductor packaging structure due to the introduction of the substrate-free redistribution layer, thereby effectively improving the input / output bandwidth and power efficiency of the packaging structure; by forming an isolation buffer layer between the outer wall of the substrate-free redistribution layer and the substrate, an airtight connection between the substrate-free redistribution layer and the substrate can be achieved, and external impurity particles or gases can be prevented from entering the groove gap to oxidize or contaminate the bare chips. The isolation buffer layer can buffer the stress between the substrate-free redistribution layer and the substrate, and avoid the formation of gaps and / or voids between the substrate-free redistribution layer and the substrate due to thermal expansion and contraction.

[0007] In some embodiments, the top surface of the substrateless redistribution layer is flush with the top surface of the substrate, thereby avoiding the warping of the die and the occurrence of cold solder joints due to the unevenness between the top surface of the substrateless redistribution layer and the top surface of the substrate; and it is convenient to set the conductive bumps of different die to the same height, thereby simplifying the conductive bump preparation process.

[0008] In some embodiments, the redistribution layer includes an organic isolation layer and at least one interconnection layer for electrically connecting different bare chips; the interconnection layer is completely embedded in the organic isolation layer. The multi-layer interconnection layer in the substrate-free redistribution layer is directly used to realize high-density interconnection between at least two bare chips, and the increase in the volume of the semiconductor packaging structure due to the introduction of the substrate-free redistribution layer is avoided.

[0009] In some embodiments, the redistribution layer also includes a solder pad, which is arranged corresponding to the interconnection layer; wherein the solder pad is electrically connected to the corresponding interconnection layer, and the solder pad of the redistribution layer is flush with the top surface of the solder pad of the substrate, so as to facilitate setting the conductive bumps of different bare chips to the same height, simplify the conductive bump preparation process, and effectively avoid the phenomenon of cold solder joints due to the uneven welding bottom surfaces of different bare chips causing the bare chips to warp.

[0010] In some embodiments, the thermal expansion coefficients of the organic isolation layer, the isolation buffer layer and the substrate are at the same order of magnitude, so as to avoid gaps between the organic isolation layer and the isolation buffer layer due to thermal expansion and contraction, thereby preventing unstable bare chip welding.

[0011] In some embodiments, the semiconductor packaging structure also includes a molding layer, which covers at least two bare chips and is located between different bare chips and between the bare chips and the substrate to achieve airtight packaging of different bare chips and prevent external impurity particles or gases from entering the molding layer and oxidizing or contaminating the bare chips.

[0012] In some embodiments, the thermal expansion coefficients of the molding layer and the isolation buffer layer are at the same order of magnitude to reduce the stress difference between the molding layer and the isolation buffer layer on the substrate or the bare chip; the thermal expansion coefficient of the molding layer is smaller than the thermal expansion coefficient of the isolation buffer layer to reduce the stress of the molding layer on the bare chip.

[0013] In some embodiments, the semiconductor packaging structure also includes an adhesive layer, which is located between the bottom surface of the substrateless redistribution layer and the substrate to prevent the redistribution layer from moving and affecting the reliability and life of the welding; and to avoid an increase in the volume of the semiconductor packaging structure due to the introduction of the adhesive layer.

[0014] Another aspect of the present disclosure further provides a method for manufacturing the semiconductor package structure in the aforementioned embodiment, comprising:

[0015] Providing a substrate, the substrate comprising an interconnection area and a pad located at the periphery of the interconnection area, wherein the interconnection area has a groove;

[0016] At least one substrate-free redistribution layer is completely embedded in the groove; the redistribution layer is used to electrically connect at least two bare chips located on the substrate, and the two bare chips are electrically connected to the substrate via corresponding pads respectively;

[0017] An isolation buffer layer is formed, and the isolation buffer layer is located between the outer side wall of the substrate-free redistribution layer and the substrate.

[0018] In the preparation method of the semiconductor packaging structure in the above-mentioned embodiment, by embedding the entire substrate-free redistribution layer into the groove of the substrate interconnection area, the multi-layer interconnection layer in the substrate-free redistribution layer is directly used to realize high-density interconnection between at least two bare chips. Compared with using Si interposer to realize multi-chip interconnection, it can effectively reduce the packaging cost, improve the chip interconnection density, and avoid the increase in the volume of the semiconductor packaging structure due to the introduction of the substrate-free redistribution layer, thereby effectively improving the input / output bandwidth and power efficiency of the packaging structure; by forming an isolation buffer layer between the outer wall of the substrate-free redistribution layer and the substrate, an airtight connection between the substrate-free redistribution layer and the substrate can be achieved, and external impurity particles or gases can be prevented from entering the groove gap to oxidize or contaminate the bare chips. The isolation buffer layer can buffer the stress between the substrate-free redistribution layer and the substrate, and avoid the formation of gaps and / or voids between the substrate-free redistribution layer and the substrate due to thermal expansion and contraction.

[0019] In some embodiments, the method for preparing a semiconductor package structure further includes the following step of forming a substrate-free redistribution layer:

[0020] Providing a substrate, and sequentially forming a stacked sacrificial layer and an initial redistribution layer on the substrate, wherein the sacrificial layer is located between the substrate and the initial redistribution layer;

[0021] The initial redistribution layer is cut along a direction perpendicular to the substrate to form at least one substrate-free redistribution layer.

[0022] In some embodiments, the method for preparing a semiconductor package structure further includes the following step of forming an initial redistribution layer:

[0023] A patterned mask layer is formed on the top surface of the sacrificial layer; the patterned mask layer has a groove defining at least one interconnection layer;

[0024] forming an interconnection layer in the groove of the patterned mask layer; the interconnection layer is used to electrically connect different bare chips;

[0025] The patterned mask layer is removed to form an organic isolation layer covering the interconnection layer. The organic isolation layer and the interconnection layer are used to jointly constitute an initial redistribution layer.

[0026] In some embodiments, the redistribution layer is connected to the bottom surface of the groove via an adhesive layer; after sequentially forming a stacked sacrificial layer and an initial redistribution layer on the substrate, the method further includes:

[0027] Forming an adhesive structure on the top surface of the initial substrate-free redistribution layer, the adhesive structure comprising a base frame and an adhesive material layer located between the base frame and the initial redistribution layer; the orthographic projection of the adhesive material layer on the top surface of the initial substrate-free redistribution layer at least completely covers the top surface of the initial substrate-free redistribution layer;

[0028] removing the substrate and the sacrificial layer;

[0029] During the process of cutting the initial redistribution layer, the adhesive structure is cut, and the adhesive material layer between the redistribution layer and the corresponding base frame is used to form an adhesive layer.

[0030] In some embodiments, after forming the isolation buffer layer, the method further includes:

[0031] A molding layer is formed, wherein the molding layer covers at least two dies and is located between different dies and between the dies and the substrate.

[0032] In some embodiments, before forming the isolation buffer layer and after forming the substrate-free redistribution layer, the method further includes:

[0033] At least two bare chips are bonded to the substrate and the redistribution layer, so that the bare chips are electrically connected to corresponding pads on the substrate and corresponding interconnection layers in the redistribution layer.

[0034] In some embodiments, the pads of the redistribution layer are flush with the top surfaces of the pads of the substrate; bonding at least two dies to the substrate and the redistribution layer comprises:

[0035] forming a conductive protrusion for bonding at least two dies, wherein top surfaces of the conductive protrusion are flush;

[0036] The input and output interfaces of at least two bare chips are bonded to the corresponding conductive bumps. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0038] Figure 1 A schematic cross-sectional structure diagram of a first semiconductor packaging structure provided in the related art is shown; Figure 2 A schematic cross-sectional structure diagram of a second semiconductor packaging structure provided in the related art is shown; Figure 3 A schematic cross-sectional view of a third semiconductor packaging structure provided in the related art is shown; Figure 4 Shown is a schematic cross-sectional structure diagram of a semiconductor packaging structure provided by the present disclosure; Figure 5 A schematic cross-sectional view of another semiconductor packaging structure provided by the present disclosure is shown; Figure 6 A schematic diagram showing a process of preparing a semiconductor packaging structure provided by the present disclosure; Figure 7 It is a schematic cross-sectional view of a structure obtained after forming a sacrificial layer and a mask layer on a substrate in a method for preparing a semiconductor packaging structure provided by the present disclosure; Figure 8 Displayed as Figure 7 A schematic cross-sectional view of the structure obtained after a patterned mask layer and an interconnect layer are formed on the structure shown; Fig. 9 Displayed as Figure 8 A schematic cross-sectional view of the structure obtained after the patterned mask layer is removed from the structure shown and an organic isolation layer is formed; Fig.10 Displayed as Fig. 9 A schematic cross-sectional view of the structure obtained after forming a bonding structure on the structure shown; Fig.11 Displayed as Fig.10 A schematic cross-sectional view of the structure obtained after removing the substrate and the sacrificial layer from the structure shown; Fig.12 Displayed as Fig.11 A schematic cross-sectional view of the structure obtained after cutting the initial redistribution layer and the bonding material layer on the structure shown; Fig.13 Displayed as based on Fig.12 A schematic cross-sectional view of the structure obtained after the structure shown has obtained a substrate-free redistribution layer; Fig.14 It is a schematic cross-sectional view of a structure obtained after all the substrate-free redistribution layers are embedded in the substrate trenches; Fig.15 Displayed as Fig.14 A schematic cross-sectional view of the structure obtained after an isolation buffer layer and a molding layer are formed on the structure shown.

[0052] Description of reference numerals:

[0053] 100, substrate; 10, first bare chip; 20, second bare chip; 12, wire; 30, silicon interposer; 40, silicon bridge; 101, substrate-free redistribution layer; 102, isolation buffer layer; 1011, organic isolation layer; 1012, interconnect layer; 1013 / 1013', pad; 103, molding layer; 104, bonding layer; 202, mask layer; 203, patterned mask layer; 101', initial redistribution layer; 300, bonding structure; 301, base frame; 302, bonding material layer; 105, substrate; 106, sacrificial layer; 107, groove; 108, conductive protrusion. DETAILED DESCRIPTION

[0054] In order to facilitate understanding of the present disclosure, the present disclosure will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present disclosure are shown in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present disclosure more thorough and comprehensive.

[0055] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0056] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers.

[0057] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0058] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0059] It should be noted that the illustrations provided in this embodiment only illustrate the basic concept of the present disclosure in a schematic manner. Although the illustrations only show components related to the present disclosure and are not drawn according to the number, shape and size of components in actual implementation, the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the component layout type may also be more complicated.

[0060] As an example, see Figure 1 After the first die 10 and the second die 20 to be packaged are soldered to the corresponding positions on the top surface of the substrate 100, the first die 10 and the second die 20 are interconnected via the wires 12 inside the substrate 100. For semiconductor packaging manufacturers, the substrate 100 is generally purchased directly, and there is no ability to form multiple wires 12 in the substrate 100 for connecting the first die 10 and the second die 20. In addition, the multi-chip high-density interconnection packaging structure has high requirements on the number of wires 12 in the substrate 100 and the complexity of wiring, which increases the complexity and cost of the packaging process, and it is difficult to meet the cost and performance requirements of the multi-chip high-density interconnection packaging structure.

[0061] As an example, see Figure 2 The silicon interposer 30 is a silicon substrate, which is a conduit for transmitting electrical signals in a multi-chip module in an advanced package. It can realize interconnection between chips and with the package substrate, and serves as a connecting bridge between multiple bare chips, such as the first bare chip 10 and the second bare chip 20, and between the first bare chip 10, the second bare chip 20 and the substrate 100. The silicon interposer 30 has a high fine pitch wiring capability and a reliable TSV (Through Silicon Via) capability. However, for a multi-chip high-density interconnect packaging structure, the silicon interposer will undoubtedly increase the volume and cost of the interconnect packaging structure.

[0062] As an example, see Figure 3In order to further reduce the volume of the multi-chip interconnect packaging structure, a silicon bridge 40 buried in the substrate 100 is used as a connecting bridge between multiple bare chips, such as the first bare chip 10 and the second bare chip 20, and between the first bare chip 10, the second bare chip 20 and the substrate 100. However, the silicon bridge 40 cannot meet the wiring density requirements of the multi-chip high-density interconnect packaging structure, which limits the input / output bandwidth and power efficiency of the multi-chip interconnect packaging structure.

[0063] Based on the above technical problems, the present disclosure provides a semiconductor packaging structure and a preparation method thereof, which can at least solve the problem of high-density interconnection of multiple chips, reduce packaging costs, reduce the volume of the packaging structure, and improve the input / output bandwidth and power efficiency of the packaging structure.

[0064] As an example, see Figure 4 or Figure 5 A semiconductor packaging structure includes a substrate 100, a substrate-free redistribution layer 101 and an isolation buffer layer 102. The substrate 100 includes an interconnection area and a pad 1013' located at the periphery of the interconnection area; the substrate-free redistribution layer 101 is located in the interconnection area and is completely embedded in the substrate 100, and is used to electrically connect at least two bare chips located on the substrate 100. The two bare chips are electrically connected to the substrate 100 via corresponding pads 1013 respectively; the isolation buffer layer 102 is located between the outer side wall of the substrate-free redistribution layer and the substrate 100.

[0065] As an example, see Figure 4 or Figure 5 By embedding the substrate-free redistribution layer 101 completely into the substrate 100, the multi-layer wiring layer in the substrate-free redistribution layer 101 is directly used to realize high-density interconnection between at least two dies, such as the first die 10 and the second die 20, and between the first die 10, the second die 20 and the substrate 100. Compared with the high-density interconnection between the substrate-free redistribution layer 101 and the substrate 100, the high-density interconnection between the substrate-free redistribution layer 101 and the substrate 100 is realized. The present invention relates to an interposer for interconnecting multiple chips, which can effectively reduce packaging costs, increase chip interconnection density, and avoid the increase in the volume of the semiconductor packaging structure due to the introduction of the substrate-free redistribution layer 101, thereby effectively improving the input / output bandwidth and power efficiency of the packaging structure; by forming an isolation buffer layer 102 between the outer wall of the substrate-free redistribution layer 101 and the substrate 100, an airtight connection between the substrate-free redistribution layer and the substrate 100 can be achieved, and external impurity particles or gases can be prevented from entering the groove gap to oxidize or contaminate the bare chip. The isolation buffer layer 102 can buffer the stress between the substrate-free redistribution layer 101 and the substrate 100, and avoid the formation of gaps and / or voids between the substrate-free redistribution layer 101 and the substrate 100 due to thermal expansion and contraction.

[0066] As an example, see Figure 4 or Figure 5The top surface of the substrate-free redistribution layer 101 is flush with the top surface of the substrate 100, avoiding the warping of the die and the occurrence of cold solder joints due to the unevenness between the top surface of the substrate-free redistribution layer and the top surface of the substrate 100; and it is convenient to set the conductive protrusions of different die to the same height, simplifying the process flow of preparing the conductive protrusions and reducing production costs.

[0067] As an example, see Figure 4 or Figure 5 An isolation buffer layer 102 may be provided circumferentially surrounding the outer wall of the substrate-free redistribution layer 101 to reduce the mechanical coupling effect (coupling effect) and the coefficient of thermal expansion (CTE) mismatch between the isolation buffer layer 102 and the substrate 100, thereby reducing stress concentration or cracking in certain areas of the package and improving the reliability of the package structure.

[0068] As an example, see Figure 4 or Figure 5 The substrate-free redistribution layer 101 includes an organic isolation layer 1011 and at least one interconnection layer 1012 for electrically connecting different dies, such as the first die 10 and the second die 20; the interconnection layer 1012 is completely embedded in the organic isolation layer 1011. The multi-layer interconnection layer 1012 in the substrate-free redistribution layer 101 is directly used to realize high-density interconnection between the first die 10 and the second die 20, and avoid the increase in the volume of the semiconductor package structure due to the introduction of the substrate-free redistribution layer 101.

[0069] As an example, see Figure 5 The substrate-free redistribution layer 101 also includes a pad 1013, and the pad 1013 is correspondingly arranged with the interconnection layer 1012; wherein the pad 1013 is electrically connected with the corresponding interconnection layer 1012, and the pad 1013 of the substrate-free redistribution layer 101 is flush with the top surface of the pad 1013' of the substrate 100, which is convenient for setting the conductive protrusions of different bare chips to the same height, simplifying the preparation process of the conductive protrusions, and reducing the production cost; and can effectively avoid the phenomenon of cold solder joints caused by the uneven welding bottom surfaces of different bare chips, resulting in the warping of the bare chips.

[0070] As an example, see Figure 4 or Figure 5The material of the substrate 100 is a conventional PCB material, usually a resin material, such as phenolic resin, epoxy resin, polyester resin, etc. The organic isolation layer 1011 and the isolation buffer layer 102 can be made of resin materials. Polyimide has been widely concerned and applied due to its unique comprehensive properties such as high temperature resistance, oxidation resistance, radiation resistance, corrosion resistance, moisture resistance, high strength and high modulus. Therefore, the organic isolation layer 1011 and the isolation buffer layer 102 can be made of polyimide. The polyimide material has an extremely low thermal expansion coefficient. The thermal expansion coefficient of polyimide is 2×10 -5 / ℃-3×10 -5 / ℃, the thermal expansion coefficient of thermoplastic polyimide is 3×10 -5 / ℃. The materials of the organic isolation layer 1011, the isolation buffer layer 102 and the substrate 100 are all resin materials. By setting the thermal expansion coefficients of the organic isolation layer 1011, the isolation buffer layer 102 and the substrate 100 to be at the same order of magnitude, it is possible to avoid gaps between the organic isolation layer 1011 and the isolation buffer layer 102 due to thermal expansion and contraction, which may lead to unstable bare chip welding; it is also possible to balance the stress of the organic isolation layer 1011, the isolation buffer layer 102 and the substrate 100 on the first bare chip 10 and the second bare chip 20, thereby avoiding the reduction of the performance and life of the first bare chip 10 and the second bare chip 20 due to the stress imbalance.

[0071] In addition, the prior art uses a silicon interposer, and the thermal expansion coefficient of silicon is about 2.4×10 -6 K -1 The materials of the silicon interposer and the substrate are quite different, that is, the thermal expansion coefficients are quite different, and they are very easy to delaminate in hot and cold environments, thus affecting the performance of the package.

[0072] As an example, see Figure 4 or Figure 5 The semiconductor packaging structure also includes a molding layer 103, which covers at least two dies, such as a first die 10 and a second die 20, and is located between the first die 10 and the second die 20, and between the first die 10, the second die 20 and the substrate 100, so as to achieve airtight packaging of different dies and prevent external impurity particles or gases from entering the molding layer 103 and oxidizing or contaminating the dies.

[0073] As an example, see Figure 4 or Figure 5, the thermal expansion coefficients of the molding layer 103 and the isolation buffer layer 102 are at the same order of magnitude, so as to reduce the stress difference between the molding layer 103 and the isolation buffer layer 102 on the first die 10 and the second die 20; the thermal expansion coefficient of the molding layer 103 can be set to be smaller than the thermal expansion coefficient of the isolation buffer layer 102, for example, the thermal expansion coefficient of the molding layer 103 can be set to be similar to the thermal expansion coefficients of the first die 10 and the second die 20, so as to reduce the stress of the molding layer 103 on the first die 10 and the second die 20. The stress can be tensile stress or compressive stress. For example, if the molding layer 103 decreases in volume due to a decrease in temperature, compressive stress will be generated on the first die 10 and the second die 20; conversely, if the molding layer 103 increases in volume due to an increase in temperature, tensile stress will be generated on the first die 10 and the second die 20. By setting the thermal expansion coefficient of the molding layer 103 to be similar to the thermal expansion coefficients of the first die 10 and the second die 20, the temperature change-volume change of the molding layer 103 and the first die 10 and the second die 20 are similar, thereby reducing the tensile stress or compressive stress of the molding layer 103 on the first die 10 and the second die 20, so as to improve the performance and reliability of the multi-chip interconnect packaging structure.

[0074] As an example, see Figure 4 or Figure 5 The semiconductor packaging structure further includes an adhesive layer 104, which is located between the bottom surface of the substrate-free redistribution layer 101 and the substrate 100, so as to prevent the substrate-free redistribution layer 101 from moving and affecting the reliability and life of welding; and to prevent the introduction of the adhesive layer 104 from causing an increase in the volume of the semiconductor packaging structure. The adhesive layer 104 can be an ultra-thin film adhesive, which can achieve a stable connection between the substrate-free redistribution layer 101 and the substrate 100, while facilitating the lamination and thinning of the semiconductor packaging structure. In addition, by adjusting the thickness of the adhesive layer 104, the embedding depth of the substrate-free redistribution layer 101 in the interconnection area can be further adjusted, so that the top surface of the substrate-free redistribution layer 101 is flush with the top surface of the substrate 100.

[0075] As an example, see Figure 6 A method for preparing a semiconductor packaging structure comprises the following steps:

[0076] Step S2: providing a substrate, the substrate comprising an interconnection region and a pad located at the periphery of the interconnection region, and the interconnection region has a groove;

[0077] Step S4: embedding at least one substrate-free redistribution layer completely into the groove; the redistribution layer is used to electrically connect at least two bare chips located on the substrate, and the two bare chips are electrically connected to the substrate via corresponding pads respectively;

[0078] Step S6: forming an isolation buffer layer, wherein the isolation buffer layer is located between the outer side wall of the substrate-free redistribution layer and the substrate.

[0079] As an example, see Figure 6 By embedding all the substrate-free redistribution layers into the grooves of the substrate interconnection area, the multi-layer interconnection layers in the substrate-free redistribution layer are directly used to realize high-density interconnection between at least two bare chips. Compared with using Si interposer to realize multi-chip interconnection, it can effectively reduce packaging costs, improve chip interconnection density, and avoid the increase in the volume of the semiconductor packaging structure due to the introduction of the substrate-free redistribution layer, thereby effectively improving the input / output bandwidth and power efficiency of the packaging structure; by forming an isolation buffer layer between the outer wall of the substrate-free redistribution layer and the substrate, an airtight connection between the substrate-free redistribution layer and the substrate can be achieved, and external impurity particles or gases are prevented from entering the groove gap to oxidize or contaminate the bare chips. The isolation buffer layer can buffer the stress between the substrate-free redistribution layer and the substrate, and avoid the formation of gaps and / or voids between the substrate-free redistribution layer and the substrate due to thermal expansion and contraction.

[0080] As an example, see Figure 6 , the substrate 100 serves as a packaging substrate, on which various device elements (not shown) may be provided. Examples of device elements formed in or on the packaging substrate may include transistors (e.g., metal oxide semiconductor field effect transistors (MOSFET), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJT), high voltage transistors, high frequency transistors, P-channel and / or N-channel field effect transistors (PFETs / NFETs), etc.), diodes, resistors, capacitors, inductors and / or other applicable device elements. Various processes may be performed to form the device elements, such as deposition, etching, implantation, photolithography, annealing and / or other suitable processes. The packaging substrate may also have one or more circuit layers (not shown) for electrically connecting the device elements and subsequently attached semiconductor devices.

[0081] As an example, the method for preparing a semiconductor package structure further includes the following step of forming a substrate-free redistribution layer:

[0082] Step S31: sequentially forming a stacked sacrificial layer and an initial redistribution layer on a substrate, wherein the sacrificial layer is located between the substrate and the initial redistribution layer;

[0083] Step S33: cutting the initial redistribution layer along a direction perpendicular to the substrate to form at least one substrate-free redistribution layer.

[0084] As an example, see Figure 7-Figure 9 Step S31 further includes the following steps of forming an initial redistribution layer 101':

[0085] Step S311: forming a sacrificial layer 106 on the top surface of the substrate 105;

[0086] Step S312: forming a patterned mask layer 203 on the top surface of the sacrificial layer 106; the patterned mask layer 203 has a groove defining at least one interconnection layer 1012;

[0087] Step S313: forming an interconnection layer 1012 in the groove of the patterned mask layer 203, wherein the interconnection layer 1012 is used to electrically connect different dies;

[0088] Step S314: removing the patterned mask layer 203 to form an organic isolation layer 1011 covering the interconnection layer 1012. The organic isolation layer 1011 and the interconnection layer 1012 are used to jointly constitute the initial redistribution layer 101'.

[0089] As an example, see Figure 7-Figure 9 , the material of the substrate 105 provided in step S311 can be made of semiconductor material, insulating material, conductor material or any combination thereof. In step S312, a deposition process can be used to sequentially stack a sacrificial layer 106 and a mask layer 202 on the top surface of the substrate 105. The material of the sacrificial layer 106 can include but is not limited to silicon oxide and / or silicon oxynitride. The sacrificial layer 106 can facilitate the bonding and separation of the substrate 105 and the interconnection layer 1012, simplify the preparation process flow, and reduce the production cost. A photoresist material layer is coated on the top surface of the mask layer 202, and a series of steps such as exposure, development, photolithography and etching are performed to obtain a patterned mask layer 203, and the patterned mask layer 203 has a groove (not shown) defining at least one interconnection layer 1012; the groove can extend along the thickness direction of the sacrificial substrate 200 and have at least one branch extending along a first direction parallel to the top surface of the sacrificial substrate 200, and the groove can also have at least one branch extending along a second direction parallel to the top surface of the sacrificial substrate 200, and the first direction intersects with the second direction. The deposition process may include but is not limited to at least one of a chemical vapor deposition process (CVD), an atomic layer deposition process (ALD), a high density plasma deposition (HDP), a plasma enhanced deposition process, and a spin-on dielectric layer (SOD).

[0090] It should be noted that Figure 8The grooves for forming the interconnection layer 1012 given as an example may be the final shape obtained after multiple pattern transfers, and the number of pattern transfers depends on the number of layers and / or quantity of the interconnection layers 1012 to be formed, and the number of layers and / or quantity of the interconnection layers 1012 to be formed is related to the density of multi-chip interconnection.

[0091] As an example, see Figure 8 In step S313, a deposition process may be used to form an interconnection layer 1012 in the groove of the patterned mask layer 203. The interconnection layer 1012 may extend along the thickness direction of the sacrificial substrate 200 and have at least one branch extending along a first direction parallel to the top surface of the sacrificial substrate 200. The interconnection layer 1012 may also have at least one branch extending along a second direction parallel to the top surface of the sacrificial substrate 200. The material of the interconnection layer 1012 may be selected from copper (Cu), copper alloy, aluminum (Al), aluminum alloy, tungsten (W), tungsten alloy, titanium (Ti), titanium alloy, tantalum (Ta) or tantalum alloy.

[0092] As an example, see Fig. 9 In step S314, the patterned mask layer 203 can be removed by wet etching process; the organic isolation layer 1011 covering the interconnection layer 1012 can be formed by vacuum forming process, and the organic isolation layer 1011 and the interconnection layer 1012 are used to form the initial redistribution layer 101'. The bottom part of the interconnection layer 1012 can be used as the pad 1013'.

[0093] As an example, see Figure 10-11 , the substrate-free redistribution layer 101 is connected to the bottom surface of the groove of the substrate via the adhesive layer 104; after forming the initial redistribution layer 101' in step S31, and before cutting the initial redistribution layer 101' in a direction perpendicular to the substrate 105 in step S33, it also includes:

[0094] Step S321: forming an adhesive structure 300 on the top surface of the initial redistribution layer 101', the adhesive structure 300 comprising a base frame 301 and an adhesive material layer 302 located between the base frame 301 and the initial redistribution layer 101'; the orthographic projection of the adhesive material layer 302 on the top surface of the initial redistribution layer 101' at least completely covers the top surface of the initial redistribution layer 101';

[0095] Step S322 : removing the substrate 105 and the sacrificial layer 106 .

[0096] As an example, see Figure 10-11In step S321, the top surface of the initial redistribution layer 101' is bonded to the base frame 301 using the bonding material layer 302 to support the subsequent cutting of the initial redistribution layer 101'. The bonding material layer 302 is cut during the process of cutting the initial redistribution layer 101', which can reduce the preparation process flow and reduce production costs. In step S322, the bonding structure 300 can be turned over to the bottom of the initial redistribution layer 101', and the substrate 105 and the sacrificial layer 106 are removed by etching and / or chemical mechanical polishing to expose the bottom surface of the pad 1013' in the initial redistribution layer 101'.

[0097] As an example, see Figure 12-13 In the process of cutting the initial redistribution layer 101' in step S33, the adhesive structure 300 is cut, and the adhesive material layer 302 between the substrate-free redistribution layer 101 and the corresponding base frame 301 is used to form the adhesive layer 104. The adhesive layer 104 can be an ultra-thin film adhesive, which can realize the stable connection between the substrate-free redistribution layer 101 and the substrate 100, and facilitate the lamination and thinning of the semiconductor packaging structure.

[0098] As an example, see Fig.14 , at least one substrate-free redistribution layer 101 is completely embedded in the middle of the groove 107; the substrate-free redistribution layer 101 is used to electrically connect at least two dies located on the substrate 100, and the two dies are electrically connected to the substrate 100 via corresponding pads 1013. For example, the first die 10, the second die 20 are bonded to the substrate 100 and the substrate-free redistribution layer 101, so that the first die 10, the second die 20 are electrically connected to the corresponding pads 1013 on the substrate 100 and the corresponding interconnection layer 1012 in the substrate-free redistribution layer 101. The high-density interconnection between the first die 10 and the second die 20 is achieved by directly using the multi-layer interconnection layer 1012 in the substrate-free redistribution layer 101, and the volume increase of the semiconductor package structure due to the introduction of the substrate-free redistribution layer 101 is avoided.

[0099] As an example, see Fig.15 An isolation buffer layer 102 may be formed in the gap of the groove 107. The isolation buffer layer 102 is located between the outer wall of the substrate-free redistribution layer 101 and the substrate 100, and can buffer the stress between the substrate-free redistribution layer 101 and the substrate 100, and prevent the formation of gaps and / or voids between the substrate-free redistribution layer 101 and the substrate 100 due to thermal expansion and contraction. The isolation buffer layer 102 may include epoxy resin, resin, filler material, stress release agent (SRA), adhesion promoter, other suitable materials or combinations thereof.

[0100] As an example, see Fig.15The isolation buffer layer 102 in the groove 107 can circumferentially surround the outer wall of the substrate-free redistribution layer 101, reducing the mechanical coupling effect (coupling effect) and thermal expansion coefficient (coefficient of thermal expansion, CTE) mismatch between the isolation buffer layer 102 and the substrate 100, thereby reducing stress concentration or cracking in certain areas of the package and improving the reliability of the packaging structure.

[0101] As an example, see Fig.15 The thermal expansion coefficients of the organic isolation layer 1011, the isolation buffer layer 102 and the substrate 100 can be set to be at the same order of magnitude, which can avoid the gap between the organic isolation layer 1011 and the isolation buffer layer 102 due to thermal expansion and contraction, resulting in unstable bare chip welding; the stress of the organic isolation layer 1011, the isolation buffer layer 102 and the substrate 100 on the first bare chip 10 and the second bare chip 20 can also be balanced, thereby avoiding the reduction of the performance and life of the first bare chip 10 and the second bare chip 20 due to stress imbalance.

[0102] As an example, see Fig.15 A molding layer 103 can be formed by a plastic encapsulation process. The molding layer 103 covers the outer surfaces of the first die 10 and the second die 20 and is located between the first die 10 and the second die 20, and between the first die 10, the second die 20 and the substrate 100, so as to achieve airtight packaging of different dies and prevent external impurity particles or gases from entering the molding layer 103 and oxidizing or contaminating the dies.

[0103] As an example, see Fig.15 The thermal expansion coefficient of the molding layer 103 can be set to be close to the thermal expansion coefficients of the first die 10 and the second die 20, so that the temperature change-volume change of the molding layer 103 and the first die 10 and the second die 20 are similar, thereby reducing the tensile stress or compressive stress of the molding layer 103 on the first die 10 and the second die 20, so as to improve the performance and reliability of the multi-chip interconnect packaging structure.

[0104] As an example, see Fig.15, the first die 10 and the second die 20 may be integrated circuit (IC) chips or dies, which may include a semiconductor substrate having a plurality of semiconductor devices (e.g., transistors, diodes, passive devices, etc.) thereon to form a functional integrated circuit. Functional integrated circuits may include processors, logic circuits, memory devices, analog circuits, digital circuits, mixed signal circuits, etc. The top surface (the upper surface shown) of the substrate 100 may be used to receive and engage other packaged components of the package. A plurality of electrical connectors (not shown) may be provided on the top surface of the substrate 100 so that the first die 10 and the second die 20 can be electrically connected to an external electronic device such as a printed circuit board (not shown).

[0105] As an example, see Fig.15 At least one of the first die 10 and the second die 20 may be a system on a chip (SoC) or a system on integrated circuit (SoIC) device or package, including two or more chips / die with integrated functions. Each first die 10 or second die 20 may be obtained, for example, by cutting a semiconductor wafer (on which a plurality of integrated circuit dies are formed) along a cutting path to separate the semiconductor wafer into a plurality of separate semiconductor dies. As an example, please continue to refer to Fig.15 The thermal expansion coefficients of the molding layer 103 and the isolation buffer layer 102 are at the same order of magnitude to reduce the stress difference between the molding layer 103 and the isolation buffer layer 102 on the first die 10 and the second die 20; the thermal expansion coefficient of the molding layer 103 can be set to be smaller than the thermal expansion coefficient of the isolation buffer layer 102, for example, the thermal expansion coefficient of the molding layer 103 can be set to be similar to the thermal expansion coefficients of the first die 10 and the second die 20 to reduce the stress of the molding layer 103 on the first die 10 and the second die 20. The stress can be tensile stress or compressive stress.

[0106] As an example, see Fig.15, the pad 1013' of the substrate-free redistribution layer 101 is flush with the top surface of the pad 1013 of the substrate 100; after at least one substrate-free redistribution layer 101 is completely embedded in the groove 107, at least two bare chips can be bonded to the substrate 100 and the redistribution layer. For example, a conductive protrusion 108 for bonding at least two bare chips can be formed, and the top surface of the conductive protrusion 108 is flush, and then the input and output interfaces of the at least two bare chips are bonded to the corresponding conductive protrusion 108, so as to simplify the bonding process and reduce the production cost; and the phenomenon of cold solder joints caused by the uneven welding bottom surfaces of different bare chips due to the warping of the bare chips can be effectively avoided. The conductive protrusion 108 can be or include a solder ball, such as a tin-containing solder ball. The material of the conductive protrusion 108 may include copper, aluminum, gold, nickel, silver, palladium, etc. or a combination thereof. The conductive protrusion 108 may be formed using at least one of an electroplating process, a chemical plating process, a placement process, a printing process, a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, a photolithography process, etc.

[0107] In the method for preparing the semiconductor packaging structure in the above-mentioned embodiment, by embedding the substrate-free redistribution layer 101 completely into the groove of the interconnection area of ​​the substrate 100, the multi-layer interconnection layer 1012 in the substrate-free redistribution layer 101 is directly used to realize high-density interconnection between at least two bare chips. Compared with using Si interposer to realize multi-chip interconnection, it is possible to effectively reduce the packaging cost, improve the chip interconnection density, and avoid the increase in the volume of the semiconductor packaging structure due to the introduction of the substrate-free redistribution layer 101, thereby effectively improving the input / output bandwidth and power efficiency of the packaging structure; by forming an isolation buffer layer 102 between the outer wall of the substrate-free redistribution layer and the substrate 100, an airtight connection between the substrate-free redistribution layer and the substrate 100 can be achieved, and external impurity particles or gases can be prevented from entering the groove gap to oxidize or contaminate the bare chips. The isolation buffer layer 102 can buffer the stress between the substrate-free redistribution layer 101 and the substrate 100, and avoid the formation of gaps and / or voids between the substrate-free redistribution layer 101 and the substrate 100 due to thermal expansion and contraction.

[0108] It should be understood that, although the steps in the flowchart of the accompanying drawings are shown in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear description in this article, there is no strict order restriction on the execution of these steps, and these steps can be executed in other orders. Moreover, although at least a part of the steps in the flowchart may include multiple steps or multiple stages, these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0109] Please note that the above embodiments are for illustrative purposes only and are not meant to limit the present disclosure.

[0110] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0111] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0112] The above embodiments only express several implementation methods of the present disclosure, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the disclosed patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present disclosure, and these all belong to the protection scope of the present disclosure. Therefore, the protection scope of the disclosed patent shall be subject to the attached claims.

Claims

1. A semiconductor packaging structure, characterized in that: include: A substrate including an interconnection region and a pad located at the periphery of the interconnection region; a substrate-free redistribution layer, located in the interconnection region and completely embedded in the substrate, for electrically connecting at least two bare chips located on the substrate, wherein the two bare chips are electrically connected to the substrate via corresponding pads respectively; and The isolation buffer layer is located between the outer side wall of the substrate-free redistribution layer and the substrate.

2. The semiconductor package structure according to claim 1, wherein: The top surface of the substrate-free redistribution layer is flush with the top surface of the substrate.

3. The semiconductor package structure according to claim 2, characterized in that: The substrate-free redistribution layer includes: an organic isolation layer and at least one interconnection layer for electrically connecting different bare chips; The interconnect layer is entirely embedded in the organic isolation layer.

4. The semiconductor package structure according to claim 3, characterized in that: The substrate-free redistribution layer also includes: A pad, arranged corresponding to the interconnection layer; The pads are electrically connected to the corresponding interconnection layers, and the pads of the substrate-free redistribution layer are flush with the top surfaces of the pads of the substrate.

5. The semiconductor package structure according to claim 3, characterized in that: The thermal expansion coefficients of the organic isolation layer, the isolation buffer layer and the substrate are in the same order of magnitude.

6. The semiconductor packaging structure according to any one of claims 1 to 5, characterized in that: The invention also includes a molding layer, which covers the at least two dies and is located between different dies and between the dies and the substrate.

7. The semiconductor package structure according to claim 6, characterized in that: The thermal expansion coefficients of the molding layer and the isolation buffer layer are in the same order of magnitude, and the thermal expansion coefficient of the molding layer is smaller than the thermal expansion coefficient of the isolation buffer layer.

8. The semiconductor packaging structure according to any one of claims 1 to 5, characterized in that: Also includes: The adhesive layer is located between the bottom surface of the substrate-free redistribution layer and the substrate.

9. A method for preparing a semiconductor packaging structure according to any one of claims 1 to 8, characterized in that: include: Providing a substrate, the substrate comprising an interconnection area and a pad located at the periphery of the interconnection area, wherein the interconnection area has a groove; Embed at least one substrate-free redistribution layer completely in the groove; the substrate-free redistribution layer is used to electrically connect at least two bare chips located on the substrate, and the two bare chips are electrically connected to the substrate via corresponding pads respectively; An isolation buffer layer is formed, wherein the isolation buffer layer is located between the outer side wall of the substrate-free redistribution layer and the substrate.

10. The method for preparing a semiconductor packaging structure according to claim 9, characterized in that: The method further includes the following steps of forming the substrate-free redistribution layer: Providing a substrate, and sequentially forming a stacked sacrificial layer and an initial redistribution layer on the substrate, wherein the sacrificial layer is located between the substrate and the initial redistribution layer; The initial redistribution layer is cut along a direction perpendicular to the substrate to form at least one substrate-free redistribution layer.

11. The method for preparing a semiconductor packaging structure according to claim 10, characterized in that: The step of forming the initial redistribution layer is also included: A patterned mask layer is formed on the top surface of the sacrificial layer; the patterned mask layer has a groove defining at least one interconnection layer; forming an interconnection layer in the groove of the patterned mask layer; the interconnection layer is used to electrically connect different bare chips; The patterned mask layer is removed to form an organic isolation layer covering the interconnection layer, wherein the organic isolation layer and the interconnection layer are used to jointly constitute an initial redistribution layer.

12. The method for preparing a semiconductor packaging structure according to claim 10, characterized in that: The substrate-free redistribution layer is connected to the bottom surface of the groove via an adhesive layer; after the stacked sacrificial layer and the initial redistribution layer are sequentially formed on the substrate, the method further includes: A bonding structure is formed on the top surface of the initial substrate-free redistribution layer, wherein the bonding structure comprises a base frame and a bonding material layer located between the base frame and the initial redistribution layer; the orthographic projection of the bonding material layer on the top surface of the initial substrate-free redistribution layer at least completely covers the top surface of the initial substrate-free redistribution layer; removing the substrate and the sacrificial layer; During the process of cutting the initial redistribution layer, the adhesive structure is cut, and the adhesive material layer between the substrate-free redistribution layer and the corresponding base frame is used to form the adhesive layer.

13. The method for preparing a semiconductor packaging structure according to any one of claims 9 to 12, characterized in that: After the isolation buffer layer is formed, the method further includes: A molding layer is formed, wherein the molding layer covers the at least two dies and is located between different dies and between the dies and the substrate.

14. The method for preparing a semiconductor packaging structure according to claim 13, characterized in that: Before forming the isolation buffer layer and after forming the substrate-free redistribution layer, the method further includes: At least two bare chips are bonded to the substrate and the substrate-free redistribution layer, so that the bare chips are electrically connected to corresponding pads on the substrate and corresponding interconnection layers in the substrate-free redistribution layer.

15. The method for preparing a semiconductor packaging structure according to claim 13, characterized in that: The pads of the substrate-free redistribution layer are flush with the top surfaces of the pads of the substrate; and the step of bonding at least two dies to the substrate and the substrate-free redistribution layer comprises: forming a conductive protrusion for bonding the at least two dies, wherein top surfaces of the conductive protrusion are flush; The input and output interfaces of the at least two bare chips are bonded to the corresponding conductive protrusions.

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