Undervoltage protection circuit and high-voltage integrated circuit using same

Abstract

The invention relates to the technical field of under-voltage protection, in particular to an under-voltage protection circuit and a high-voltage integrated circuit using the same, in the under-voltage protection circuit, when an under-voltage fault judgment module judges that an under-voltage fault occurs, an under-voltage fault signal is generated to drive an under-voltage time adaptation module to correspondingly generate a clock signal according to the duration of the under-voltage fault signal; the under-voltage frequency selection module reduces the frequency of the clock signal in stages according to the under-voltage value of the power supply voltage to generate a filtering clock signal, and the under-voltage value is in direct proportion to the frequency of the filtering clock signal; the under-voltage protection trigger module is used for not acting when the duration of the received filtering clock signal is less than the filtering trigger moment, and starting filtering from the filtering trigger moment and generating an under-voltage protection action signal if the duration is greater than or equal to the filtering trigger moment; therefore, the clock signal is used for replacing the level to trigger undervoltage protection, and filtering is achieved to avoid false triggering. And meanwhile, various under-voltage faults are adapted by changing the duration and frequency of the clock signal, so that the under-voltage protection precision is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of undervoltage protection, in particular to an undervoltage protection circuit and a high-voltage integrated circuit using the same. Background Art

[0002] High voltage integrated circuit, or HVIC, is an integrated circuit product that converts MCU signals into driving IGBT or MOS signals. HVIC integrates PMOS tubes, NMOS tubes, triodes, diodes, voltage regulator tubes, resistors, and capacitors to form Schmitt, low voltage level, high voltage level, pulse generation circuit, delay circuit, filter circuit, overcurrent and overheat protection circuit, undervoltage protection circuit, bootstrap circuit and other circuits; in this integrated environment containing multiple circuits, the power supply voltage (i.e. VCC) is affected by multiple circuits, and there will always be some burr noise (such as switching noise light). For example, when the fluctuation amplitude (i.e. voltage change) and width (i.e. duration) of the power supply voltage are large, when the power supply voltage drops to the triggering threshold of the undervoltage protection circuit or below, the voltage in the undervoltage stage is not filtered, and the undervoltage protection action will be frequently triggered, resulting in instability of the subsequent circuit and reducing the working efficiency of the high voltage integrated circuit.

[0003] More importantly, if conventional filtering methods are used (such as setting filter capacitors), the filtering time is basically constant and cannot be adjusted to match different power supply voltages and undervoltage values, resulting in excessive or insufficient filtering effects, and the impact of glitch noise on subsequent circuits cannot be completely eliminated. Summary of the invention

[0004] In view of the above-mentioned defects, the purpose of the present invention is to propose an undervoltage protection circuit and a high-voltage integrated circuit using the same, which uses a clock signal instead of a level-triggered undervoltage protection to achieve filtering and avoid false triggering; at the same time, by changing the duration and frequency of the clock signal to adapt to various undervoltage faults, the accuracy of the undervoltage protection is improved.

[0005] To achieve this object, the present invention adopts the following technical solutions:

[0006] An undervoltage protection circuit comprises an undervoltage fault judgment module, an undervoltage time adaptation module, an undervoltage frequency selection module and an undervoltage protection triggering module; the input end of the undervoltage fault judgment module is connected to a VCC power supply, the output end of the undervoltage fault judgment module, the first reset end of the undervoltage frequency selection module and the first reset end of the undervoltage protection triggering module are all electrically connected to the input end of the undervoltage time adaptation module, the first input end and the second input end of the undervoltage frequency selection module are both electrically connected to the output end of the undervoltage time adaptation module, the selection end of the undervoltage frequency selection module is connected to a VCC power supply, the first output end and the second output end of the undervoltage frequency selection module are respectively electrically connected to the first input end and the second input end of the undervoltage protection triggering module, the second reset end of the undervoltage frequency selection module is electrically connected to the output end of the undervoltage protection triggering module, the second reset end of the undervoltage protection triggering module is electrically connected to the reset end of the undervoltage time adaptation module, and the output end of the undervoltage protection triggering module is connected to a subsequent undervoltage protection action circuit;

[0007] The undervoltage fault judgment module is used to compare the external power supply voltage with the undervoltage threshold, and generate an undervoltage fault signal when the power supply voltage is less than the undervoltage threshold;

[0008] The undervoltage time adaptation module is used to receive the undervoltage fault signal and generate a clock signal according to the duration of the undervoltage fault signal;

[0009] The undervoltage frequency selection module is used to receive the clock signal and the power supply voltage, reduce the frequency of the clock signal in stages according to the undervoltage value of the power supply voltage, and generate a filtered clock signal; the undervoltage value is proportional to the frequency of the filtered clock signal;

[0010] The undervoltage protection trigger module is used to not act when the duration of the received filtering clock signal is less than the filtering trigger moment; when the duration of the received filtering clock signal is greater than or equal to the filtering trigger moment, start filtering from the filtering trigger moment and generate an undervoltage protection action signal.

[0011] Furthermore, the frequency of the clock signal is F1, the frequency of the filter clock signal is F2, and the undervoltage value is divided into n stages from large to small;

[0012] The relationship between the frequency F1 of the clock signal and the frequency F2 of the filtered clock signal is F2=F1*(1 / 2 N ), where N is any value from 1 to n.

[0013] Further, the undervoltage time adaptation module includes an RS trigger RS1, an oscillating current source, a relaxation oscillator and a startup circuit; the S end of the RS trigger RS1 is used as the input end of the undervoltage time adaptation module, the R end of the RS trigger RS1 is used as the reset end of the undervoltage time adaptation module, and the output end of the relaxation oscillator is used as the output end of the undervoltage time adaptation module;

[0014] The Q terminal of the RS trigger RS1 is electrically connected to the input terminal of the startup circuit, the output terminal of the startup circuit is electrically connected to the input terminal of the relaxation oscillator, and the first output terminal and the second output terminal of the oscillation current source are electrically connected to the first current source terminal and the second current source terminal of the relaxation oscillator respectively;

[0015] The waveform of the oscillating current source is opposite to the waveform of the power supply voltage;

[0016] The RS trigger RS1 is used to start the startup circuit when receiving the undervoltage fault signal;

[0017] When the startup circuit is turned on, the startup circuit drives the relaxation oscillator to generate the clock signal.

[0018] Further, the undervoltage frequency selection module includes a first frequency divider and a second frequency divider; the clock end of the first frequency divider is used as the first input end of the undervoltage frequency selection module, the reset end of the first frequency divider is used as the first reset end of the undervoltage frequency selection module, the output end of the first frequency divider is used as the first output end of the undervoltage frequency selection module, the clock end of the second frequency divider is used as the second input end of the undervoltage frequency selection module, the reset end of the second frequency divider is used as the second reset end of the undervoltage frequency selection module, the output end of the second frequency divider is used as the second output end of the undervoltage frequency selection module, and the selection end of the first frequency divider or the second frequency divider is used as the selection end of the undervoltage frequency selection module;

[0019] The first frequency divider and the second frequency divider are both used to receive the clock signal and the power supply voltage, determine the stage of the undervoltage value, and correspondingly reduce the frequency of the clock signal to generate the filtered clock signal;

[0020] The first frequency divider generates the filtered clock signal earlier than the second frequency divider.

[0021] Furthermore, the first frequency divider and the second frequency divider have the same circuit structure;

[0022] The first frequency divider includes a selection unit and n D flip-flops D3; the input end and the output end of the selection unit are respectively used as the selection end and the output end of the first frequency divider, and the clock end and the reset end of the first D flip-flop D3 are respectively used as the clock end and the reset end of the first frequency divider;

[0023] The Q terminal of the preceding D flip-flop D3 is electrically connected to the clock terminal of the following D flip-flop D3, the reset terminals of all the D flip-flops D3 are electrically connected in common, the D terminal and the / Q terminal of each D flip-flop D3 are electrically connected, and the Q terminals of the first to nth D flip-flops D3 are electrically connected to the first selection terminal to the nth selection terminal of the selection unit respectively;

[0024] The selection unit is used to receive the power supply voltage to determine the stage of the undervoltage value; when the undervoltage value is in any stage from the first to the nth stage, the corresponding selection end from the first to the nth selection end of the selection unit is connected to the output end of the selection unit.

[0025] Further, the undervoltage protection trigger module includes a D trigger D1, a D trigger D2, an RS trigger RS2, a NOT gate U2, a NOT gate U4, a NAND gate U3, a NAND gate U5, a NAND gate U7 and an AND gate U6; the clock end and the reset end of the D trigger D1 are respectively used as the first input end and the first reset end of the undervoltage protection trigger module, the clock end of the D trigger D2 is used as the second input end of the undervoltage protection trigger module, the output end of the AND gate U6 is used as the second reset end of the undervoltage protection trigger module, and the Q end of the RS trigger RS2 is used as the output end of the undervoltage protection trigger module;

[0026] The / Q terminal of the D flip-flop D1 is electrically connected to the first input terminal of the NAND gate U3, the reset terminal of the D flip-flop D1, the input terminal of the NAND gate U2, and the first input terminal of the NAND gate U5 are all electrically connected to the first input terminal of the NAND gate U7, the output terminal of the NAND gate U2 is electrically connected to the second input terminal of the NAND gate U3, the / Q terminal of the D flip-flop D2 is electrically connected to the third input terminal of the NAND gate U5, the reset terminal of the D flip-flop D2, the second input terminal of the NAND gate U7, and the input terminal of the NAND gate U4 are all electrically connected to the R The Q end of the S trigger RS2 is electrically connected, the second input end of the NAND gate U5 is electrically connected to the output end of the NAND gate U4, the output end of the NAND gate U3 is electrically connected to the S end of the RS trigger RS2, the output end of the NAND gate U5 is electrically connected to the first input end of the AND gate U6, the output end of the NAND gate U7 is electrically connected to the second input end of the AND gate U6, the output end of the AND gate U6 is electrically connected to the R end of the RS trigger RS2, and the D end of the D trigger D1 and the D end of the D trigger D2 are both connected to the VCC power supply.

[0027] Furthermore, the undervoltage fault judgment module includes a voltage divider circuit, a reference circuit and a comparator U1; the input end of the voltage divider circuit is used as the input end of the undervoltage fault judgment module, and the output end of the comparator U1 is used as the output end of the undervoltage fault judgment module;

[0028] The input end of the voltage divider circuit is electrically connected to the input end of the reference circuit, the output end of the voltage divider circuit is electrically connected to the negative input end of the comparator U1, and the output end of the reference circuit is electrically connected to the positive input end of the comparator U1;

[0029] The voltage divider circuit is used to collect the power supply voltage;

[0030] The reference circuit is used to generate the undervoltage threshold.

[0031] Further, the relaxation oscillator includes a PNP MOS tube M1, an NPN MOS tube M2, a PNP MOS tube M3, an NPN MOS tube M4, a capacitor C1, a capacitor C2, a comparator CMP1, a comparator CMP2 and an RS trigger RS3;

[0032] The gate of the PNP MOS transistor M1 is used as the input terminal of the relaxation oscillator, the Q terminal of the RS trigger RS3 is used as the output terminal of the relaxation oscillator, the source of the PNP MOS transistor M1 is used as the first current source terminal of the relaxation oscillator, and the source of the PNP MOS transistor M3 is used as the second current source terminal of the relaxation oscillator;

[0033] The Q end of the RS trigger RS3 and the gate of the NPN MOS tube M2 are electrically connected to the gate of the PNP MOS tube M1, the drain of the NPN MOS tube M2, the drain of the PNP MOS tube M1, and one end of the capacitor C1 are electrically connected to the positive input end of the comparator CMP1, the other end of the capacitor C1 and the source of the NPN MOS tube M2 are grounded, the gate of the PNP MOS tube M3 and the gate of the NPN MOS tube M4 are grounded to the positive input end of the RS trigger RS3. / Q terminal is electrically connected, the drain of the NPN MOS tube M4, the drain of the PNP MOS tube M3, and one end of the capacitor C2 are electrically connected to the positive input terminal of the comparator CMP2, the other end of the capacitor C2 and the source of the NPN MOS tube M4 are grounded, the negative input terminals of the comparators CMP1 and CMP2 are electrically connected to the output terminal of the reference circuit 12, and the output terminals of the comparators CMP1 and CMP2 are electrically connected to the S terminal and the R terminal of the RS trigger RS3, respectively.

[0034] A high-voltage integrated circuit comprises the above-mentioned undervoltage protection circuit, a fault logic control circuit and a plurality of fault detection circuits; the input end of the undervoltage protection circuit is used as the VCC end of the high-voltage integrated circuit, and the output end of the undervoltage protection circuit and the output ends of the plurality of fault detection circuits are electrically connected to the input end of the fault logic control circuit respectively;

[0035] The fault logic control circuit is used to shut down the high-voltage integrated circuit when the undervoltage protection circuit or any one of the multiple fault detection circuits feeds back a valid signal.

[0036] The technical solution provided by the present invention may include the following beneficial effects: when an undervoltage fault occurs, the power supply voltage (VCC power supply) is smaller than that during normal operation, so an undervoltage threshold is provided in the undervoltage fault judgment module for comparison with the external power supply voltage of the undervoltage fault judgment module. When the power supply voltage is less than the undervoltage threshold, an undervoltage fault signal is generated; the duration of the undervoltage fault signal represents the duration of the undervoltage fault, so the undervoltage time adaptation module generates a clock signal according to the duration of the undervoltage fault signal, so as to match the duration of the undervoltage fault; therefore, the undervoltage frequency selection module receives the power supply voltage under the premise of being driven by the clock signal to determine the undervoltage value (i.e., the difference) between the power supply voltage and the normal undervoltage value. The larger the undervoltage value, the more serious the undervoltage fault, and the longer the filtering time is required, so the frequency of the clock signal needs to be reduced accordingly. The undervoltage frequency selection module reduces the frequency of the clock signal in stages according to the undervoltage value of the power supply voltage to generate a filtered clock signal, so that the filtered clock signal At the same time, the duration of the undervoltage fault and the undervoltage value of the undervoltage fault are adapted; finally, the high or low level of the conventional undervoltage fault protection circuit is replaced by the filtering clock signal to drive the undervoltage protection trigger module to trigger the undervoltage protection action, so as to achieve the purpose of undervoltage filtering; at the same time, in order to avoid the undervoltage fault duration being too short and to match the filtering time of different undervoltage values, the undervoltage protection trigger module sets a filtering trigger moment. If the duration of the filtering clock signal does not reach the filtering trigger moment, it proves that the duration of the undervoltage fault is too short, and the undervoltage protection and filtering are meaningless. If the duration of the filtering clock signal is greater than the filtering trigger moment, it proves that filtering is required according to the duration of the undervoltage fault and the undervoltage value, that is, the time period after the filtering trigger moment is the filtering time (because different undervoltage values ​​correspond to filtering clock signals of different frequencies, this means that the filtering trigger moment changes with the filtering clock signal, thereby adapting the filtering time, that is, the undervoltage value and the filtering time are proportional), so the filtering time represents the effective time of the undervoltage protection.

[0037] To sum up, the filtering principle of the undervoltage protection circuit is to use the clock signal instead of the high or low level of the conventional undervoltage protection circuit to trigger the undervoltage protection action. The generated clock signal has no glitch noise compared to the high or low level, which can completely eliminate the influence of the power supply voltage glitch noise on the undervoltage protection triggering, avoid frequent undervoltage protection action, and improve the working efficiency of the integrated circuit; at the same time, the duration and frequency of the clock signal can be changed to adapt to various undervoltage fault situations, thereby improving the accuracy of the undervoltage protection. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 The invention discloses an undervoltage protection circuit according to one embodiment of the invention.

[0039] Figure 2 Yes Figure 1 A waveform diagram of an undervoltage protection circuit is shown.

[0040] Figure 3 Yes Figure 1 The circuit schematic diagram of the first frequency divider or the second frequency divider is shown.

[0041] Figure 4 Yes Figure 1 The circuit schematic of the relaxation oscillator is shown in Figure 1.

[0042] Figure 5 It is a partial schematic diagram of a high-voltage integrated circuit according to one embodiment of the present invention.

[0043] Among them: undervoltage fault judgment module 1, undervoltage time adaptation module 2, undervoltage frequency selection module 3, undervoltage protection trigger module 4, RS trigger RS1, oscillation current source 21, relaxation oscillator 22, first frequency divider 31, second frequency divider 32, selection unit 33, D trigger D3, D trigger D1, D trigger D2, RS trigger RS2, NOT gate U2, NOT gate U4, NAND gate U3, NAND gate U5, NAND gate U7, AND gate U6, voltage divider circuit 11, reference circuit 12, comparator U1, PNP MOS tube M1, NPN MOS tube M2, PNP MOS tube M3, NPN MOS tube M4, capacitor C1, capacitor C2, comparator CMP1, comparator CMP2, RS trigger RS3, startup circuit 23, fault logic control circuit 5, fault detection circuit 6. DETAILED DESCRIPTION

[0044] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.

[0045] In the description of the embodiments of the present invention, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0046] In the description of the embodiments of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the embodiments of the present invention can be understood according to specific circumstances.

[0047] Combine the following Figures 1 to 5 , describing an undervoltage protection circuit and a high-voltage integrated circuit using the same according to an embodiment of the present invention.

[0048] Example 1

[0049] An undervoltage protection circuit comprises an undervoltage fault judgment module 1, an undervoltage time adaptation module 2, an undervoltage frequency selection module 3 and an undervoltage protection trigger module 4; the input end of the undervoltage fault judgment module 1 is connected to a VCC power supply, the output end of the undervoltage fault judgment module 1, the first reset end of the undervoltage frequency selection module 3 and the first reset end of the undervoltage protection trigger module 4 are all electrically connected to the input end of the undervoltage time adaptation module 2, the first input end and the second input end of the undervoltage frequency selection module 3 are all electrically connected to the output end of the undervoltage time adaptation module 2, the selection end of the undervoltage frequency selection module 3 is connected to the VCC power supply, the first output end and the second output end of the undervoltage frequency selection module 3 are respectively electrically connected to the first input end and the second input end of the undervoltage protection trigger module 4, the second reset end of the undervoltage frequency selection module 3 is electrically connected to the output end of the undervoltage protection trigger module 4, the second reset end of the undervoltage protection trigger module 4 is electrically connected to the reset end of the undervoltage time adaptation module 2, and the output end of the undervoltage protection trigger module 4 is connected to a subsequent undervoltage protection action circuit;

[0050] The undervoltage fault judgment module 1 is used to compare the external power supply voltage with the undervoltage threshold value, and when the power supply voltage is less than the undervoltage threshold value, an undervoltage fault signal is generated;

[0051] The undervoltage time adaptation module 2 is used to receive the undervoltage fault signal and generate a clock signal according to the duration of the undervoltage fault signal;

[0052] The undervoltage frequency selection module 3 is used to receive the clock signal and the power supply voltage, and reduce the frequency of the clock signal in stages according to the undervoltage value of the power supply voltage to generate a filtered clock signal; the undervoltage value is proportional to the frequency of the filtered clock signal;

[0053] The undervoltage protection trigger module 4 is used to not act when the duration of the received filter clock signal is less than the filter trigger moment; when the duration of the received filter clock signal is greater than or equal to the filter trigger moment, filtering starts from the filter trigger moment and generating an undervoltage protection action signal.

[0054] The present invention proposes a preferred embodiment of an undervoltage protection circuit, such as Figure 1 As shown, when an undervoltage fault occurs, the power supply voltage (VCC power supply) is smaller than that in normal operation, so an undervoltage threshold is provided in the undervoltage fault judgment module 1, which is used to compare the external power supply voltage of the undervoltage fault judgment module 1. When the power supply voltage is less than the undervoltage threshold, an undervoltage fault signal is generated; the duration of the undervoltage fault signal represents the duration of the undervoltage fault, so the undervoltage time adaptation module 2 generates a clock signal according to the duration of the undervoltage fault signal, so as to match the duration of the undervoltage fault; therefore, the undervoltage frequency selection module 3 receives the power supply voltage under the premise of being driven by the clock signal to determine the undervoltage value (i.e., the difference) between the power supply voltage and the normal value. The larger the undervoltage value, the more serious the undervoltage fault, and the longer the filtering time is required, so the frequency of the clock signal needs to be reduced accordingly, then the undervoltage frequency selection module 3 reduces the frequency of the clock signal in stages according to the undervoltage value of the power supply voltage, generates a filtered clock signal, so that the filtered clock signal is adapted to the undervoltage fault at the same time duration and undervoltage value of the undervoltage fault; finally, the filtering clock signal replaces the high or low level of the conventional undervoltage fault protection circuit to drive the undervoltage protection trigger module 4 to trigger the undervoltage protection action, thereby achieving the purpose of undervoltage filtering; at the same time, in order to avoid the undervoltage fault duration being too short and to match the filtering time of different undervoltage values, the undervoltage protection trigger module 4 sets a filtering triggering moment. If the duration of the filtering clock signal does not reach the filtering triggering moment, it proves that the undervoltage fault duration is too short, and the undervoltage protection and filtering are meaningless. If the duration of the filtering clock signal is greater than the filtering triggering moment, it proves that it is necessary to filter according to the duration of the undervoltage fault and the undervoltage value, that is, the time period after the filtering triggering moment is the filtering time (because different undervoltage values ​​correspond to filtering clock signals of different frequencies, this means that the filtering triggering moment changes with the filtering clock signal, thereby adapting the filtering time, that is, the undervoltage value and the filtering time are proportional), so the filtering time represents the effective time of the undervoltage protection, such as Figure 2 shown.

[0055] To sum up, the filtering principle of the undervoltage protection circuit is to use the clock signal instead of the high or low level of the conventional undervoltage protection circuit to trigger the undervoltage protection action. The generated clock signal has no glitch noise compared to the high or low level, which can completely eliminate the influence of the power supply voltage glitch noise on the undervoltage protection triggering, avoid frequent undervoltage protection action, and improve the working efficiency of the integrated circuit; at the same time, the duration and frequency of the clock signal can be changed to adapt to various undervoltage fault situations, thereby improving the accuracy of the undervoltage protection.

[0056] Furthermore, the frequency of the clock signal is F1, the frequency of the filter clock signal is F2, and the undervoltage value is divided into n stages from large to small;

[0057] The relationship between the frequency F1 of the clock signal and the frequency F2 of the filtered clock signal is F2 = F1*(1 / 2 N ), where N is any value from 1 to n.

[0058] In this embodiment, the frequency reduction of the undervoltage value is divided into n stages from large to small according to the size of the undervoltage value. The undervoltage value of each stage corresponds to a frequency, so that the frequency can be proportional to the undervoltage value, which meets the setting requirements of the filter clock signal. The preferred frequency reduction scheme is F2 = F1*(1 / 2 N ), where N is the stage of undervoltage value.

[0059] Further, the undervoltage time adaptation module 2 includes an RS trigger RS1, an oscillating current source 21, a relaxation oscillator 22 and a start-up circuit 23; the S end of the RS trigger RS1 is used as the input end of the undervoltage time adaptation module 2, the R end of the RS trigger RS1 is used as the reset end of the undervoltage time adaptation module 2, and the output end of the relaxation oscillator 22 is used as the output end of the undervoltage time adaptation module 2;

[0060] The Q terminal of the RS trigger RS1 is electrically connected to the input terminal of the start-up circuit 23, the output terminal of the start-up circuit is electrically connected to the input terminal of the relaxation oscillator 22, and the first output terminal and the second output terminal of the oscillation current source 21 are electrically connected to the first current source terminal and the second current source terminal of the relaxation oscillator 22 respectively;

[0061] The waveform of the oscillating current source 21 is opposite to that of the power supply voltage;

[0062] The RS trigger RS1 is used to start the startup circuit 23 when receiving an undervoltage fault signal;

[0063] When the startup circuit 23 is turned on, the startup circuit 23 drives the relaxation oscillator 22 to generate a clock signal.

[0064] In this embodiment, although the undervoltage fault signal (high level is valid) output by the undervoltage fault judgment module 1 triggers the RS trigger RS1, the starting circuit 23 (such as a switching circuit) drives the relaxation oscillator 22 to generate a clock signal for subsequent triggering of the undervoltage protection, thereby achieving a filtering effect. However, in order to further improve the filtering effect, the relaxation oscillator 22 is started by an oscillating current source 21 whose waveform is opposite to that of the power supply voltage, thereby achieving the purpose of positive and negative neutralization of the undervoltage fault.

[0065] Further, the undervoltage frequency selection module 3 includes a first frequency divider 31 and a second frequency divider 32; the clock end of the first frequency divider 31 is used as the first input end of the undervoltage frequency selection module 3, the reset end of the first frequency divider 31 is used as the first reset end of the undervoltage frequency selection module 3, the output end of the first frequency divider 31 is used as the first output end of the undervoltage frequency selection module 3, the clock end of the second frequency divider 32 is used as the second input end of the undervoltage frequency selection module 3, the reset end of the second frequency divider 32 is used as the second reset end of the undervoltage frequency selection module 3, the output end of the second frequency divider 32 is used as the second output end of the undervoltage frequency selection module 3, and the selection end of the first frequency divider 31 or the second frequency divider 32 is used as the selection end of the undervoltage frequency selection module 3;

[0066] The first frequency divider 31 and the second frequency divider 32 are both used to receive the clock signal and the power supply voltage, determine the stage of the undervoltage value, and correspondingly reduce the frequency of the clock signal to generate a filtered clock signal;

[0067] The first frequency divider 31 generates the filtered clock signal earlier than the second frequency divider 32 .

[0068] In this embodiment, the undervoltage frequency selection module 3 implements the function of phased frequency reduction of the clock signal according to different undervoltage values ​​by the first frequency divider 31 and the second frequency divider 32. The filtered clock signal actually includes the filtered clock signal output by the first frequency divider 31 and the filtered clock signal output by the second frequency divider 32. The undervoltage protection trigger module 4 first receives the filtered clock signal output by the first frequency divider 31. After the filtering trigger moment is reached, the undervoltage protection trigger module 4 resets the second frequency divider 32 to make the second frequency divider 32 output the filtered clock signal. At this time, the undervoltage protection trigger module 4 will start filtering from the filtering trigger moment and generate an undervoltage protection action signal to trigger the undervoltage protection, thereby meeting the logic design requirements of the undervoltage protection trigger module 4.

[0069] Furthermore, the circuit structures of the first frequency divider 31 and the second frequency divider 32 are the same;

[0070] The first frequency divider 31 includes a selection unit 33 and n D flip-flops D3; the input end and the output end of the selection unit 33 are respectively used as the selection end and the output end of the first frequency divider 31, and the clock end and the reset end of the first D flip-flop D3 are respectively used as the clock end and the reset end of the first frequency divider 31;

[0071] The Q terminal of the previous D flip-flop D3 is electrically connected to the clock terminal of the next D flip-flop D3, the reset terminals of all the D flip-flops D3 are electrically connected in common, the D terminal and the / Q terminal of each D flip-flop D3 are electrically connected, and the Q terminals of the first to nth D flip-flops D3 are electrically connected to the first selection terminal to the nth selection terminal of the selection unit 33 respectively;

[0072] The selection unit 33 is used to receive the power supply voltage to determine the stage of the undervoltage value; when the undervoltage value is in any stage from the first to the nth stage, the corresponding selection end from the first selection end to the nth selection end of the selection unit 33 is connected to the output end of the selection unit 33.

[0073] In this embodiment, the undervoltage frequency selection module 3 is as follows: Figure 3 As shown, taking four D flip-flops D3 as an example, the first frequency divider 31 and the second frequency divider 32 implement the same frequency reduction principle of the clock signal according to different undervoltage values. The circuit is composed of multiple D flip-flops D3. After the clock signal is input, the output frequency will be reduced by half every time it passes through a D flip-flop D3. Therefore, by setting a selection unit 33 (for example, composed of a switch circuit and an MCU), the stage of the undervoltage value is determined, and then the corresponding selection end (Q1 to Qn) and the output end of the selection unit 33 are turned on, so that the frequency of the filtered clock signal finally output by the undervoltage frequency selection module 3 satisfies F2=F1*(1 / 2 N ) to achieve frequency reduction based on the undervoltage value.

[0074] Further, the undervoltage protection trigger module 4 includes a D trigger D1, a D trigger D2, an RS trigger RS2, a NOT gate U2, a NOT gate U4, a NAND gate U3, a NAND gate U5, a NAND gate U7 and an AND gate U6; the clock end and the reset end of the D trigger D1 are respectively used as the first input end and the first reset end of the undervoltage protection trigger module 4, the clock end of the D trigger D2 is used as the second input end of the undervoltage protection trigger module 4, the output end of the AND gate U6 is used as the second reset end of the undervoltage protection trigger module 4, and the Q end of the RS trigger RS2 is used as the output end of the undervoltage protection trigger module 4;

[0075] The / Q terminal of the D flip-flop D1 is electrically connected to the first input terminal of the NAND gate U3, the reset terminal of the D flip-flop D1, the input terminal of the NAND gate U2, and the first input terminal of the NAND gate U5 are all electrically connected to the first input terminal of the NAND gate U7, the output terminal of the NAND gate U2 is electrically connected to the second input terminal of the NAND gate U3, the / Q terminal of the D flip-flop D2 is electrically connected to the third input terminal of the NAND gate U5, the reset terminal of the D flip-flop D2, the second input terminal of the NAND gate U7, and the input terminal of the NAND gate U4 are all electrically connected to the Q terminal of the RS flip-flop RS2, the second input terminal of the NAND gate U5 and the output terminal of the NAND gate U4 are electrically connected, the output terminal of the NAND gate U3 is electrically connected to the S terminal of the RS flip-flop RS2, the output terminal of the NAND gate U5 is electrically connected to the first input terminal of the AND gate U6, the output terminal of the NAND gate U7 is electrically connected to the second input terminal of the AND gate U6, the output terminal of the AND gate U6 is electrically connected to the R terminal of the RS flip-flop RS2, and the D terminal of the D flip-flop D1 and the D terminal of the D flip-flop D2 are both connected to the VCC power supply.

[0076] In this embodiment, when an undervoltage fault occurs, only the D flip-flop D1 is released and reset by the undervoltage fault judgment module 1 ( Figure 1 The A point is high level), which can be triggered by the filter clock signal. After passing through the logic network composed of logic components, the RS trigger RS2 is triggered. If the D trigger D1 has not triggered the RS trigger RS2, the undervoltage fault disappears, the filter clock signal disappears, the D trigger D1 is reset, and the RS trigger RS2 is not triggered. Figure 1 Points E and F remain unchanged (low level off), so this process is the case where the duration of the filter clock signal is less than the filter triggering moment.

[0077] When the duration of the filter clock signal is greater than or equal to the filter triggering moment, the D flip-flop D1 is released and reset by the undervoltage fault judgment module 1 ( Figure 1 A point high level), can be triggered by the filtered clock signal, D flip-flop D1 continues to output signals, after several cycles of rising edges, it is still in undervoltage fault, then Figure 1 The high level at point D in will trigger the RS trigger RS2. Figure 1 Point F in is at a high level, thereby the D flip-flop D2 is also triggered, so that the D flip-flops D1 and D flip-flops D2 remain in the triggered state, so that the RS flip-flop RS2 remains triggered and sends out an undervoltage protection action signal.

[0078] To sum up, the triggering of the RS trigger RS2 is taken as the filtering triggering moment, and the trigger signal of the RS trigger RS2 is used as the undervoltage protection action signal without any glitch noise, thereby achieving the filtering purpose; more importantly, the undervoltage value and the filtering time (undervoltage protection effective time) are proportional to each other. The larger the undervoltage value, the greater the frequency of the filtering signal, and the faster the filtering triggering moment is reached, and the filtering outputs the undervoltage protection action signal.

[0079] Furthermore, the undervoltage fault judgment module 1 includes a voltage divider circuit 11, a reference circuit 12 and a comparator U1; the input end of the voltage divider circuit 11 is used as the input end of the undervoltage fault judgment module 1, and the output end of the comparator U1 is used as the output end of the undervoltage fault judgment module 1;

[0080] The input end of the voltage divider circuit 11 is electrically connected to the input end of the reference circuit 12, the output end of the voltage divider circuit 11 is electrically connected to the negative input end of the comparator U1, and the output end of the reference circuit 12 is electrically connected to the positive input end of the comparator U1;

[0081] The voltage divider circuit 11 is used to collect the power supply voltage;

[0082] The reference circuit 12 is used to generate an undervoltage threshold.

[0083] In this embodiment, the undervoltage fault judgment module 1 mainly judges whether an undervoltage fault occurs. Therefore, the undervoltage fault judgment module 1 is composed of a voltage divider circuit 11, a reference circuit 12 and a comparator U1. The voltage divider circuit 11 (such as a resistor in series) collects the power supply voltage through voltage division and gives it to the negative input terminal of the comparator U1. The reference circuit 12 (such as a Zener diode) generates a clamping voltage through the power supply voltage as an undervoltage threshold to the positive input terminal of the comparator U1. When the collected power supply voltage is higher than the undervoltage threshold, it is an undervoltage fault, and the comparator U1 outputs an undervoltage fault signal (high level is valid).

[0084] Further, the relaxation oscillator 22 includes a PNP MOS transistor M1, an NPN MOS transistor M2, a PNP MOS transistor M3, an NPN MOS transistor M4, a capacitor C1, a capacitor C2, a comparator CMP1, a comparator CMP2 and an RS trigger RS3;

[0085] The gate of the PNP MOS transistor M1 is used as the input terminal of the relaxation oscillator 22, the Q terminal of the RS trigger RS3 is used as the output terminal of the relaxation oscillator 22, the source of the PNP MOS transistor M1 is used as the first current source terminal of the relaxation oscillator 22, and the source of the PNP MOS transistor M3 is used as the second current source terminal of the relaxation oscillator 22;

[0086] The Q end of the RS trigger RS3 and the gate of the NPN MOS tube M2 are electrically connected to the gate of the PNP MOS tube M1, the drain of the NPN MOS tube M2, the drain of the PNP MOS tube M1, and one end of the capacitor C1 are electrically connected to the positive input end of the comparator CMP1, the other end of the capacitor C1 and the source of the NPN MOS tube M2 are grounded, the gate of the PNP MOS tube M3 and the gate of the NPN MOS tube M4 are electrically connected to the / Q end of the RS trigger RS3, the drain of the NPN MOS tube M4, the drain of the PNP MOS tube M3, and one end of the capacitor C2 are electrically connected to the positive input end of the comparator CMP2, the other end of the capacitor C2 and the source of the NPN MOS tube M4 are grounded, the negative input ends of the comparators CMP1 and CMP2 are electrically connected to the output end of the reference circuit 12, and the output ends of the comparators CMP1 and CMP2 are electrically connected to the S end and the R end of the RS trigger RS3, respectively.

[0087] In this embodiment, the working principle of the relaxation oscillator 22 is as follows: Figure 4 As shown, two currents are drawn from the oscillating current source 21, and two charging and discharging circuits are set to be respectively connected to the S terminal and the R terminal of the RS trigger RS3. The circuit structures of the two charging and discharging circuits are the same. After the RS trigger RS1 triggers the starting circuit 23, the two charging and discharging circuits can be charged alternately to start oscillation; for example, the initial state of the relaxation oscillator 22 after power-on is Q=0, / Q=1, Vc1=0, Vc2=VDD, at this time, M1 and M4 are turned on, while M2 and M3 are turned off, C1 starts to charge, and C2 starts to discharge.

[0088] Example 2

[0089] A high voltage integrated circuit, comprising the above-mentioned undervoltage protection circuit, a fault logic control circuit 5 and a plurality of fault detection circuits 6; the input end of the undervoltage protection circuit is used as the VCC end of the high voltage integrated circuit, and the output end of the undervoltage protection circuit and the output ends of the plurality of fault detection circuits 6 are electrically connected to the input end of the fault logic control circuit 5 respectively;

[0090] The fault logic control circuit 5 is used to shut down the high-voltage integrated circuit when the undervoltage protection circuit or any one of the multiple fault detection circuits 6 feeds back a valid signal.

[0091] In this embodiment, a preferred embodiment of a high voltage integrated circuit is also proposed, such as Figure 5 As shown, the above undervoltage protection circuit can be conveniently integrated into a high-voltage integrated circuit to implement undervoltage protection of the high-voltage integrated circuit.

[0092] Other structures and operations of an undervoltage protection circuit according to an embodiment of the present invention and a high-voltage integrated circuit using the same are well known to those skilled in the art and will not be described in detail here.

[0093] In the description of this specification, the description with reference to the terms "embodiment", "example", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0094] Although the embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.

Claims

1. An undervoltage protection circuit, characterized in that: It includes an undervoltage fault judgment module, an undervoltage time adaptation module, an undervoltage frequency selection module and an undervoltage protection triggering module; the input end of the undervoltage fault judgment module is connected to a VCC power supply, the output end of the undervoltage fault judgment module, the first reset end of the undervoltage frequency selection module, and the first reset end of the undervoltage protection triggering module are all electrically connected to the input end of the undervoltage time adaptation module, the first input end and the second input end of the undervoltage frequency selection module are both electrically connected to the output end of the undervoltage time adaptation module, the selection end of the undervoltage frequency selection module is connected to a VCC power supply, the first output end and the second output end of the undervoltage frequency selection module are respectively electrically connected to the first input end and the second input end of the undervoltage protection triggering module, the second reset end of the undervoltage frequency selection module is electrically connected to the output end of the undervoltage protection triggering module, the second reset end of the undervoltage protection triggering module is electrically connected to the reset end of the undervoltage time adaptation module, and the output end of the undervoltage protection triggering module is connected to a subsequent undervoltage protection action circuit; The undervoltage fault judgment module is used to compare the external power supply voltage with the undervoltage threshold, and generate an undervoltage fault signal when the power supply voltage is less than the undervoltage threshold; The undervoltage time adaptation module is used to receive the undervoltage fault signal and generate a clock signal according to the duration of the undervoltage fault signal; The undervoltage frequency selection module is used to receive the clock signal and the power supply voltage, reduce the frequency of the clock signal in stages according to the undervoltage value of the power supply voltage, and generate a filtered clock signal; the undervoltage value is proportional to the frequency of the filtered clock signal; The undervoltage protection trigger module is used to not act when the duration of the received filtering clock signal is less than the filtering trigger moment; when the duration of the received filtering clock signal is greater than or equal to the filtering trigger moment, start filtering from the filtering trigger moment and generate an undervoltage protection action signal.

2. The undervoltage protection circuit according to claim 1, characterized in that: The frequency of the clock signal is F1, the frequency of the filter clock signal is F2, and the undervoltage value is divided into n stages from large to small; The relationship between the frequency F1 of the clock signal and the frequency F2 of the filtered clock signal is F2=F1*(1 / 2 N ), where N is any value from 1 to n.

3. The undervoltage protection circuit according to claim 1, characterized in that: The undervoltage time adaptation module includes an RS trigger RS1, an oscillating current source, a relaxation oscillator and a startup circuit; the S end of the RS trigger RS1 is used as the input end of the undervoltage time adaptation module, the R end of the RS trigger RS1 is used as the reset end of the undervoltage time adaptation module, and the output end of the relaxation oscillator is used as the output end of the undervoltage time adaptation module; The Q terminal of the RS trigger RS1 is electrically connected to the input terminal of the startup circuit, the output terminal of the startup circuit is electrically connected to the input terminal of the relaxation oscillator, and the first output terminal and the second output terminal of the oscillation current source are electrically connected to the first current source terminal and the second current source terminal of the relaxation oscillator respectively; The waveform of the oscillating current source is opposite to the waveform of the power supply voltage; The RS trigger RS1 is used to start the startup circuit when receiving the undervoltage fault signal; When the startup circuit is turned on, the startup circuit drives the relaxation oscillator to generate the clock signal.

4. The undervoltage protection circuit according to claim 2, characterized in that: The undervoltage frequency selection module includes a first frequency divider and a second frequency divider; the clock end of the first frequency divider is used as the first input end of the undervoltage frequency selection module, the reset end of the first frequency divider is used as the first reset end of the undervoltage frequency selection module, the output end of the first frequency divider is used as the first output end of the undervoltage frequency selection module, the clock end of the second frequency divider is used as the second input end of the undervoltage frequency selection module, the reset end of the second frequency divider is used as the second reset end of the undervoltage frequency selection module, the output end of the second frequency divider is used as the second output end of the undervoltage frequency selection module, and the selection end of the first frequency divider or the second frequency divider is used as the selection end of the undervoltage frequency selection module; The first frequency divider and the second frequency divider are both used to receive the clock signal and the power supply voltage, determine the stage of the undervoltage value, and correspondingly reduce the frequency of the clock signal to generate the filtered clock signal; The first frequency divider generates the filtered clock signal earlier than the second frequency divider.

5. The undervoltage protection circuit according to claim 4, characterized in that: The first frequency divider and the second frequency divider have the same circuit structure; The first frequency divider includes a selection unit and n D flip-flops D3; the input end and the output end of the selection unit are respectively used as the selection end and the output end of the first frequency divider, and the clock end and the reset end of the first D flip-flop D3 are respectively used as the clock end and the reset end of the first frequency divider; The Q terminal of the preceding D flip-flop D3 is electrically connected to the clock terminal of the following D flip-flop D3, the reset terminals of all the D flip-flops D3 are electrically connected in common, the D terminal and the / Q terminal of each D flip-flop D3 are electrically connected, and the Q terminals of the first to nth D flip-flops D3 are electrically connected to the first selection terminal to the nth selection terminal of the selection unit respectively; The selection unit is used to receive the power supply voltage to determine the stage of the undervoltage value; When the undervoltage value is in any stage from the first stage to the nth stage, the corresponding selection end from the first selection end to the nth selection end of the selection unit is connected to the output end of the selection unit.

6. The undervoltage protection circuit according to claim 1, characterized in that: The undervoltage protection trigger module includes a D trigger D1, a D trigger D2, an RS trigger RS2, a NOT gate U2, a NOT gate U4, a NAND gate U3, a NAND gate U5, a NAND gate U7 and an AND gate U6; the clock end and the reset end of the D trigger D1 are respectively used as the first input end and the first reset end of the undervoltage protection trigger module, the clock end of the D trigger D2 is used as the second input end of the undervoltage protection trigger module, the output end of the AND gate U6 is used as the second reset end of the undervoltage protection trigger module, and the Q end of the RS trigger RS2 is used as the output end of the undervoltage protection trigger module; The / Q terminal of the D flip-flop D1 is electrically connected to the first input terminal of the NAND gate U3, the reset terminal of the D flip-flop D1, the input terminal of the NAND gate U2, and the first input terminal of the NAND gate U5 are all electrically connected to the first input terminal of the NAND gate U7, the output terminal of the NAND gate U2 is electrically connected to the second input terminal of the NAND gate U3, the / Q terminal of the D flip-flop D2 is electrically connected to the third input terminal of the NAND gate U5, the reset terminal of the D flip-flop D2, the second input terminal of the NAND gate U7, and the input terminal of the NAND gate U4 are all electrically connected to the R The Q end of the S trigger RS2 is electrically connected, the second input end of the NAND gate U5 is electrically connected to the output end of the NAND gate U4, the output end of the NAND gate U3 is electrically connected to the S end of the RS trigger RS2, the output end of the NAND gate U5 is electrically connected to the first input end of the AND gate U6, the output end of the NAND gate U7 is electrically connected to the second input end of the AND gate U6, the output end of the AND gate U6 is electrically connected to the R end of the RS trigger RS2, and the D end of the D trigger D1 and the D end of the D trigger D2 are both connected to the VCC power supply.

7. An undervoltage protection circuit according to claim 3, characterized in that: The undervoltage fault judgment module includes a voltage divider circuit, a reference circuit and a comparator U1; the input end of the voltage divider circuit is used as the input end of the undervoltage fault judgment module, and the output end of the comparator U1 is used as the output end of the undervoltage fault judgment module; The input end of the voltage divider circuit is electrically connected to the input end of the reference circuit, the output end of the voltage divider circuit is electrically connected to the negative input end of the comparator U1, and the output end of the reference circuit is electrically connected to the positive input end of the comparator U1; The voltage divider circuit is used to collect the power supply voltage; The reference circuit is used to generate the undervoltage threshold.

8. An undervoltage protection circuit according to claim 7, characterized in that: The relaxation oscillator includes a PNP MOS tube M1, an NPN MOS tube M2, a PNP MOS tube M3, an NPN MOS tube M4, a capacitor C1, a capacitor C2, a comparator CMP1, a comparator CMP2 and an RS trigger RS3; The gate of the PNP MOS transistor M1 is used as the input terminal of the relaxation oscillator, the Q terminal of the RS trigger RS3 is used as the output terminal of the relaxation oscillator, the source of the PNP MOS transistor M1 is used as the first current source terminal of the relaxation oscillator, and the source of the PNP MOS transistor M3 is used as the second current source terminal of the relaxation oscillator; The Q end of the RS trigger RS3 and the gate of the NPN MOS tube M2 are electrically connected to the gate of the PNP MOS tube M1, the drain of the NPN MOS tube M2, the drain of the PNP MOS tube M1, and one end of the capacitor C1 are electrically connected to the positive input end of the comparator CMP1, the other end of the capacitor C1 and the source of the NPN MOS tube M2 are grounded, the gate of the PNP MOS tube M3 and the gate of the NPN MOS tube M4 are grounded to the positive input end of the RS trigger RS3. / Q terminal is electrically connected, the drain of the NPN MOS tube M4, the drain of the PNP MOS tube M3, and one end of the capacitor C2 are electrically connected to the positive input terminal of the comparator CMP2, the other end of the capacitor C2 and the source of the NPN MOS tube M4 are grounded, the negative input terminals of the comparators CMP1 and CMP2 are electrically connected to the output terminal of the reference circuit 12, and the output terminals of the comparators CMP1 and CMP2 are electrically connected to the S terminal and the R terminal of the RS trigger RS3, respectively.

9. A high voltage integrated circuit, characterized in that: The invention comprises an undervoltage protection circuit, a fault logic control circuit and a plurality of fault detection circuits according to any one of claims 1 to 8; the input end of the undervoltage protection circuit is used as the VCC end of the high-voltage integrated circuit, and the output end of the undervoltage protection circuit and the output ends of the plurality of fault detection circuits are electrically connected to the input end of the fault logic control circuit respectively; The fault logic control circuit is used to shut down the high-voltage integrated circuit when the undervoltage protection circuit or any one of the multiple fault detection circuits feeds back a valid signal.

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