Three-mode buck-boost converter controlled by peak current and valley current

Abstract

The invention discloses a peak current and valley current controlled three-mode buck-boost converter, which comprises a power level circuit, an error amplifier, a slope compensation module, a current sampling module, a PWM (Pulse Width Modulation) comparator, a mode control module and a switching control module, and is characterized in that the power level circuit obtains an output voltage according to an input voltage and outputs a sampling voltage; the error amplifier outputs a control signal according to a comparison result of the sampling voltage and the reference voltage; the mode control module outputs different enable signals according to the states of the input voltage and the output voltage; the slope compensation module outputs different compensation voltages when the converter is in different modes; the current sampling module collects the voltage of peak current or valley current according to different modes; the PWM comparator generates a PWM control signal; the switching control module generates a driving signal according to the PWM control signal and different enable signals so as to switch different modes. The mode switching efficiency can be improved, the duty ratio can be reduced, and then output voltage ripples are reduced.

Description

Technical Field

[0001] The present invention belongs to the technical field of buck-boost converters, and in particular relates to a three-mode buck-boost converter with peak current and valley current control. Background Art

[0002] A DC-DC converter (direct current-to-direct current converter) converts a DC input voltage into a stable output voltage for use by other circuits. Various types and forms of DC-DC converters have been developed, including buck converters for providing an output voltage lower than the input voltage, boost converters for providing an output voltage higher than the input voltage, and buck-boost converters for providing an output voltage that can be lower or higher than the input voltage. For a four-switch buck-boost converter, if the input voltage is higher than the output voltage, it works in buck mode, and if the input voltage is lower than the output voltage, it works in boost mode. For a traditional four-switch converter, whether it works in buck mode or boost mode, the four switches switch alternately.

[0003] In a conventional four-switch buck-boost converter, since the four switches are switched alternately, i.e., when the BUCK (buck) upper power tube and the BOOST (boost) lower power tube are turned on, the BUCK lower power tube and the BOOST upper power tube are turned off, the switching loss increases during the periodic switching of the switches, causing energy to be lost in the form of heat, resulting in low conversion efficiency of the converter. In addition, since the conventional buck-boost converter uses a single current detection mode, i.e., peak current mode or valley current mode, in a single control mode, when in critical switching conditions, the width of the PWM (pulse width modulation) comparator increases due to the need for a larger slope compensation, thereby generating a larger output voltage ripple. The same problem exists in both peak current mode and valley current mode, for example, when the pulse width modulation duty cycle is greater than 50% and the output of the error amplifier is at a level artificially higher than the peak inductor current, the slope compensation ramp is added to the current sensing signal in the peak current mode control. .

[0004] For single mode control, i.e., peak current mode control or valley current mode control, since the buck-boost converter has three working states, i.e., buck working state (BUCK working state), buck-boost working state (BUCK-BOOST working state), and boost working state (BOOST working state), when the converter is in the critical condition of switching between different working states, such as switching from the buck working state to the buck-boost working state, since the duty cycle corresponding to the buck working state is very large at this time (because it is in the critical condition, the input Vin and the output Vout are relatively close, the duty cycle D: Vout / Vin = D at this time, close to 1), and the buck-boost duty cycle is less than 50% (the buck-boost duty cycle D: Vout / Vin = D / (1-D)). Therefore, for the single control mode, the slope compensation required for the buck working mode in this case is very large, while the slope compensation required for the buck-boost working mode is small, which leads to an excessively long pulse width during the transition, thereby causing output voltage ripple. Therefore, to solve these problems of DC-DC converters, it is necessary to make the slope compensation and duty cycle of the converter smooth during buck and boost conversion. Summary of the invention

[0005] In order to solve the above problems existing in the prior art, the present invention provides a three-mode buck-boost converter with peak current and valley current control. The technical problem to be solved by the present invention is achieved by the following technical solutions:

[0006] The present invention provides a three-mode buck-boost converter with peak current and valley current control, comprising a power stage circuit, an error amplifier, a slope compensation module, a current sampling module, a PWM comparator, a mode control module and a switching control module, wherein:

[0007] The power stage circuit is used to obtain an output voltage Vout according to an input voltage Vin and sample the output voltage Vout through a resistor divider to obtain a sampled voltage;

[0008] The error amplifier obtains a control signal according to a comparison result between the sampled voltage and a preset reference voltage;

[0009] The mode control module is used to selectively output different enable signals according to the states of the input voltage Vin and the output voltage Vout, wherein the enable signals include an EN_BOOST enable signal, an EN_BUCK enable signal or an EN_B-B enable signal;

[0010] The slope compensation module is used to output different compensation voltages when the three-mode buck-boost converter is in different modes, and the different modes include BOOST mode, BUCK mode or BUCK-BOOST mode;

[0011] The input end of the current sampling module is connected to the power stage circuit, and is used to collect the voltage of the peak current or the voltage of the valley current according to different modes of the three-mode buck-boost converter;

[0012] The compensation voltage output by the slope compensation module is superimposed on the control signal output by the error amplifier and then input to the negative input terminal of the PWM comparator, and the output terminal of the current sampling signal is connected to the positive input terminal of the PWM comparator; the PWM comparator is used to generate a PWM control signal;

[0013] The switching control module is used to generate a driving signal according to the PWM control signal output by the PWM comparator and different enable signals output by the mode control module, so as to control the three-mode buck-boost converter to switch to different modes.

[0014] Compared with the prior art, the present invention has the following beneficial effects:

[0015] 1. The present invention proposes a three-mode buck-boost converter with peak current and valley current control, which generates three-mode control, namely buck mode control (BUCK mode), buck-boost mode control (BUCK-BOOST mode) and boost mode control (BOOST mode control) according to the comparison between input voltage and output voltage; the switching efficiency is improved by switching between the three modes. In addition, the duty cycle can be reduced and the output voltage ripple can be reduced by switching between the peak current mode and the valley current mode.

[0016] 2. The present invention proposes a novel circuit of a mode control module, which can effectively control the switching of modes; the present invention unifies the slope compensation circuits (slope compensation modules) of the peak current mode and the valley current mode, and selects the output signal of the slope compensation circuit through mode control, thereby greatly simplifying the slope compensation circuit.

[0017] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a schematic diagram of a three-mode buck-boost converter with peak current and valley current control provided by an embodiment of the present invention;

[0019] Figure 2 is a circuit diagram of a mode control module provided by an embodiment of the present invention;

[0020] Figure 3 is a circuit diagram of a slope compensation module provided by an embodiment of the present invention;

[0021] Figure 4 is a circuit diagram of a current sampling module provided by an embodiment of the present invention;

[0022] Figure 5 is a circuit diagram of a switching control module provided by an embodiment of the present invention;

[0023] Figure 6 These are various waveform diagrams of the device operating in the buck, buck-boost, boost, peak current sampling and valley current sampling modes of the present invention. DETAILED DESCRIPTION

[0024] In order to further explain the technical means and effects adopted by the present invention to achieve the predetermined purpose of the invention, the following is a detailed description of a three-mode buck-boost converter with peak current and valley current control proposed by the present invention in combination with the accompanying drawings and specific implementation methods.

[0025] The above and other technical contents, features and effects of the present invention are clearly presented in the following detailed description of the specific implementation modes in conjunction with the accompanying drawings. Through the description of the specific implementation modes, the technical means and effects adopted by the present invention to achieve the predetermined purpose can be more deeply and specifically understood. However, the attached drawings are only for reference and explanation purposes and are not used to limit the technical solutions of the present invention.

[0026] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants are intended to cover non-exclusive inclusion, so that an article or device including a series of elements includes not only those elements, but also other elements that are not explicitly listed. In the absence of more restrictions, the elements defined by the statement "including one..." do not exclude the existence of other identical elements in the article or device including the elements.

[0027] See also Figure 1 , Figure 1It is a schematic diagram of a three-mode buck-boost converter with peak current and valley current control provided by an embodiment of the present invention. The three-mode buck-boost converter of this embodiment includes a power stage circuit, an error amplifier, a slope compensation module, a current sampling module, a PWM comparator, a mode control module and a switching control module, wherein the power stage circuit is used to obtain an output voltage Vout according to an input voltage Vin and sample the output voltage Vout through a resistor divider to output the sampled voltage; the error amplifier outputs a control signal according to a comparison result between the sampled voltage and a preset reference voltage; the mode control module is used to selectively output different enable signals according to the states of the input voltage Vin and the output voltage Vout, and the enable signals include an EN_BOOST enable signal, an EN_BUCK enable signal or an EN_B-B enable signal; the slope compensation module is used to enable the three-mode buck-boost converter when the three-mode buck-boost converter is not in operation. Different compensation voltages are output in the same mode; the input end of the current sampling module is connected to the power stage circuit, which is used to collect the voltage of the peak current or the voltage of the valley current according to the different modes of the three-mode buck-boost converter; the compensation voltage output by the slope compensation module is superimposed with the control signal output by the error amplifier and then input to the negative input end of the PWM comparator, and the output end of the current sampling signal is connected to the positive input end of the PWM comparator; the PWM comparator is used to generate a PWM control signal; the switching control module is used to generate a driving signal according to the PWM control signal output by the PWM comparator and different enable signals output by the mode control module, so as to control the three-mode buck-boost converter to switch to different modes, and the different modes include BOOST mode, BUCK mode or BUCK-BOOST mode.

[0028] Specifically, the power stage circuit of this embodiment includes a transistor M1 (upper switch tube of BUCK), a transistor M2 (upper switch tube of BOOST), a transistor M3 (lower switch tube of BUCK), a transistor M4 (lower switch tube of BOOST), an input capacitor Cin, an output capacitor Co, an inductor L, a resistor R0, a resistor R1 and a resistor R2, wherein the input capacitor Cin is connected between the access end of the input voltage Vin and the ground end, the drain of the transistor M1 is connected to the access end of the input voltage Vin, the inductor L is connected between the source of the transistor M1 and the drain of the transistor M2, the drain of the transistor M3 is connected to the source of the transistor M1; the source of the transistor M3 and the source of the transistor M4 are both connected to the ground. The drain of transistor M4 is connected to the drain of transistor M2, the source of transistor M2 is connected to the output end of output voltage Vout, the output capacitor Co and the resistor R0 are connected in parallel between the output end of output voltage Vout and the ground end, and the resistors R1 and R2 are connected in series between the output end of output voltage Vout and the ground end; the four output ends of the switching control module are respectively connected to the gate of transistor M1, the gate of transistor M2, the gate of transistor M3 and the gate of transistor M4 to control the on and off of transistor M1, transistor M2, transistor M3 and transistor M4 respectively; the two input ends of the current sampling module are respectively connected to the two ends of inductor L; the first input end of the error amplifier is connected between resistor R1 and resistor R2. The positive input end of the error amplifier inputs the preset reference voltage VREF (fixed voltage).

[0029] That is to say, when the output voltage Vout is divided by the resistors R1 and R2 to provide an input voltage to the negative input terminal of the error amplifier EA, the input terminal of the error amplifier EA is provided by the reference voltage VREF; the error amplifier EA amplifies the difference between the positive input terminal and the negative input terminal and outputs the control signal VEA.

[0030] See also Figure 2 , Figure 2: is a circuit diagram of a mode control module provided by an embodiment of the present invention. The mode control module of this embodiment includes a comparator COMP1, a comparator COMP2, an inverter I1, an inverter 12, an RS latch RS1, an RS latch RS2, an AND gate A1 and a counter, wherein the positive input terminal of the comparator COMP1 is used to input the above-mentioned input voltage Vin, the negative input terminal of the comparator COMP1 is used to input 0.8 times of the output voltage Vout, and the output terminal of the comparator COMP1 is respectively connected to the input terminal of the inverter I1 and the first input terminal of the AND gate A1; the positive input terminal of the comparator COMP2 is used to input 1.2 times of the output voltage Vout, the negative input terminal of the comparator COMP2 is used to input the input voltage Vin, and the output terminal of the comparator COMP2 is respectively connected to the inverter I1. 2 and the second input end of the AND gate A1; the output end of the AND gate A1 is connected to the first input end of the counter, and the second input end of the counter inputs the external clock signal CLK; when the output voltage of the AND gate A1 appears high level four times, the output end of the calculator forms a high level; the output end of the inverter I1 is connected to the S end of the RS latch RS1, the output end of the inverter I2 is connected to the S end of the RS latch RS2, the output end of the counter is connected to the R end of the RS latch RS1 and the R end of the RS latch RS2, and the output signal of the counter is used as the EN_B-B enable signal; the Q end of the RS latch RS1 is used to output the EN_BOOST enable signal, and the Q end of the RS latch RS2 is used to output the EN_BUCK enable signal.

[0031] Specifically, the mode control module determines the control mode required by the loop of the three-mode buck-boost converter according to the input voltage Vin and the output voltage Vout; when the input voltage Vin is greater than 1.2 times the output voltage Vout, the output of the comparator COMP2 is low level, which is high level after passing through the inverter I2, and the EN_BUCK output from the Q end of the RS latch RS2 is high level, and it is in buck mode at this time; when the input voltage Vin is less than 1.2 times the output voltage Vout, and the input voltage Vin is greater than 0.8 times the output voltage Vout At t, the output of comparator COMP2 is high. The output of COMP2 is connected to the second input of AND gate A1 on the one hand, and outputs a low level after passing through inverter I2 on the other hand; the output of comparator COMP1 is high at this time. The output of COMP2 is connected to the first input of AND gate A1 on the one hand, and outputs a low level after passing through the first inverter I1 on the other hand; further, the output of AND gate A1 is high at this time and connected to the input of the counter; when A1 outputs a high level, it outputs a high level again after 4 cycles of the counter; when the counter is in the counting stage, EN _B-B is low, the R terminals of the two RS latches remain low, at this time EN_BUCK remains high, EN_BOOST remains low, and it remains in buck mode (BUCK mode); when the count is completed, EN_B-B outputs high, at this time the reset terminals R of RS latch RS1 and RS latch RS2 are high, and both RS latches are reset, that is, EN_BUCK and EN_BOOST outputs are low, and it is in buck-boost mode (BUCK-BOOST mode); when the input voltage Vin is less than 0. When the output voltage Vout is 8 times, the output of comparator COMP1 is low level. At this time, the first input terminal of AND gate A1 is low level, A1 output is low level, EN_B-B is low level, and the output terminal of comparator COMP1 is connected to inverter I1, and the S terminal input of RS latch is high level; the reset terminal R of RS latch is low level, and S terminal is high level, so the output of RS latch is high level, that is, EN_BOOST output is high level, EN_B-B and EN_BUCK are low level, and it is in boost mode (BOOST mode).

[0032] For further information, see Figure 3 , Figure 3: This is a circuit diagram of a slope compensation module provided by an embodiment of the present invention. The slope compensation module includes a comparator COPM3, a Schmitt trigger S1, an inverter I3 and an inverter I4, a transmission gate T1, a transmission gate T2, an operational amplifier OPA1, a resistor R3, a PMOS tube P1, a PMOS tube P2, a PMOS tube P3, a PMOS tube P4, a PMOS tube P5, a PMOS tube P6, an NMOS tube NM1, an NMOS tube NM2, an NMOS tube NM3, a capacitor C1 and a capacitor C2. The comparator COPM3, the Schmitt trigger S1, the inverter I3 and the inverter I4 are connected in sequence, the positive input terminal of the comparator COPM3 is used to input the above-mentioned input voltage Vin, the negative input terminal is used to input the above-mentioned output voltage Vout, the output terminal of the third inverter I3 is used as the A output terminal, and the output terminal of the fourth inverter I4 is used as the B output terminal.

[0033] The transmission gate T1 and the transmission gate T2 respectively include two PMOS tubes, wherein the source of the first PMOS tube in the transmission gate T1 and the drain of the second PMOS tube are both input with the above-mentioned input voltage Vin, and the drain of the first PMOS tube in the transmission gate T1 and the source of the second PMOS tube are both connected to the positive input terminal of the operational amplifier OPA1; the source of the first PMOS tube in the transmission gate T2 and the drain of the second PMOS tube are both input with the output voltage Vout, and the drain of the first PMOS tube in the transmission gate T2 and the source of the second PMOS tube are both connected to the negative input terminal of the operational amplifier OPA1; the gate of the first PMOS tube in the transmission gate T1 and the gate of the second PMOS tube in the transmission gate T2 are both connected to the B output terminal; the gate of the second PMOS tube in the transmission gate T1 and the gate of the first PMOS tube in the transmission gate T2 are both connected to the A output terminal.

[0034] The output end of the operational amplifier OPA1 is connected to the gate of the NMOS tube NM1, the resistor R3 is connected between the source of the NMOS tube NM1 and the ground end, and the negative input end of the operational amplifier OPA1 is connected to the source of the NMOS tube NM1; the drain of the PMOS tube P6 is connected to the drain of the NMOS tube NM1, and the gate of the PMOS tube P6 is used to input the EN_B-B enable signal; the source of the PMOS tube P6 is connected to the drain of the PMOS tube P1, the gate of the PMOS tube P1, the gate of the PMOS tube P2 and the gate of the PMOS tube P4; the source of the PMOS tube P1, the source of the PMOS tube P2 and the source of the PMOS tube P4 are all connected to the power supply terminal VDD, the drain of the PMOS tube P2 is connected to the source of the PMOS tube P3, the gate of the PMOS tube P3 is connected to the B output terminal, and the capacitor C1 The capacitor C2 is connected between the drain of the PMOS tube P3 and the ground terminal, the drain of the NMOS tube NM2 is connected to the drain of the PMOS tube P3, the source of the NMOS tube NM2 and the source of the NMOS tube NM3 are both connected to the ground terminal, the gate of the NMOS tube NM2 is used to input the external clock signal CLK, and the drain of the PMOS tube P3 is also used as the output end of the slope signal PCM_slope; the gate of the PMOS tube P5 is connected to the A output terminal, the drain of the PMOS tube P4 is connected to the source of the PMOS tube P5, the capacitor C2 is connected between the drain of the PMOS tube P5 and the ground terminal, the drain of the NMOS tube NM3 is connected to the drain of the PMOS tube 53, the gate of the NMOS tube NM3 is used to input the clock signal CLK, and the drain of the PMOS tube P5 is also used as the output end of the slope signal VCM_slope.

[0035] The slope compensation module of this embodiment selects to output the PCM_slope slope voltage or the VCM_slope slope voltage or not output the slope voltage according to the state of the three-mode buck-boost converter loop; when the loop is in the BUCK mode, the slope compensation module outputs the PCM_slope compensation voltage; when it is in the BOOST mode, the slope compensation module selects to output the VCM_slope compensation voltage; when it is in the BUCK-BOOST mode, the slope compensation module does not output the compensation voltage; the output of the slope compensation module is superimposed with the output of the error amplifier and then output to the negative input terminal of the PWM comparator.

[0036] Specifically, the slope compensation module selects to output appropriate slope compensation according to the situation of the input signal Vin and the output signal Vout and the state of the mode control; when Vin is greater than Vout, the comparator COPM3 outputs a high level, and after passing through the Schmitt trigger S1, the output is a low level, and after passing through the inverter I3, the A output terminal outputs a high level, and the B output terminal outputs a low level; the function of the Schmitt trigger S1 is to generate a delay to avoid unnecessary flipping caused by fluctuations; when Vin is less than Vout, the A output terminal outputs a low level, and the B output terminal outputs a high level; when Vin is greater than Vout, A is a high level and B is a low level; through the transmission gates T1 and T2, Vin is selected to be output to the positive input terminal of the operational amplifier OPA1; the negative input terminal of the operational amplifier OPA1 is connected to the upper end of the resistor R3, and the operational amplifier OPA1 is used to clamp so that the voltages of its positive input terminal and negative input terminal are consistent; therefore, the current flowing through the resistor R3 is Vin / R3; when the enable signal EN_B When -B is 0, the current flowing through the PMOS tube P1 is the current of R3; the PMOS tubes P2 and PMOS tubes P4 copy the current of the PMOS tube P1; because A is high level and B is low level, the PMOS tube P3 is turned on and the PMOS tube P5 is turned off. At this time, the current of the PMOS tube P2 flows through the capacitor C1, and the clock signal CLK periodically switches the NMOS tube NM2, thereby generating a slope signal PCM_slope related to Vin. At this time, the PMOS tube P5 is turned off and PCM_slope has an output; when Vin is lower than Vout, the transmission gate selects the output as Vout, and the current flowing through the resistor R3 is Vout / R3; because Vout is greater than Vin, A is low level and B is high level, the PMOS tube P3 is turned off, the PMOS tube P5 is turned on, and the current flowing through the PMOS tube P4 charges the capacitor C2, and the slope signal VCM_slope related to Vout is generated through the periodic switching of the NMOS tube NM3.

[0037] See also Figure 4 , Figure 41 is a circuit diagram of a current sampling module provided by an embodiment of the present invention. The current sampling module includes an operational amplifier OPA2, an operational amplifier OPA3, a resistor R3, a resistor R4, a PMOS tube P7, a PMOS tube P8, a PMOS tube P9, a PMOS tube P10, an NMOS tube NM4 and an NMOS tube NM5. The source of the PMOS tube P7 is used to input the above-mentioned input voltage Vin, the gate of the PMOS tube P7 is connected to the first output terminal TG1 of the switching control module, the drain of the PMOS tube P7 is connected to the source of the PMOS tube P8 and the positive input terminal of the operational amplifier OPA2, the gate of the PMOS tube P8 is connected to the A output terminal, the drain of the PMOS tube P8 is connected to the drain of the NMOS tube NM4, the negative input terminal of the operational amplifier OPA2 is connected to the first terminal SW1 of the inductor L in the power stage circuit, the output terminal of the operational amplifier OPA2 is connected to the gate of the NMOS tube NM4, and the resistor R3 is connected between the source of the NMOS tube NM4 and the ground terminal; the source of the NMOS tube NM4 is also used as the output terminal of the sampling voltage V-PCM of the current sampling module; The source of the MOS tube P9 is used to input the above-mentioned output voltage Vout, the gate of the PMOS tube P9 is connected to the second output terminal TG2 of the switching control module, the drain of the PMOS tube P9 is connected to the source of the PMOS tube P10 and the positive input terminal of the operational amplifier OPA3, the gate of the PMOS tube P9 is connected to the B output terminal, the drain of the PMOS tube P9 is connected to the drain of the NMOS tube NM5, the negative input terminal of the operational amplifier OPA3 is connected to the second terminal SW2 of the inductor L in the power stage circuit, the output terminal of the operational amplifier OPA3 is connected to the gate of the NMOS tube NM5, and the resistor R4 is connected between the source of the NMOS tube NM5 and the ground terminal; the source of the NMOS tube NM5 also serves as the output terminal of the sampling voltage V-VCM of the current sampling module.

[0038] Specifically, the current sampling module clamps the positive input terminal to the negative input terminal SW1 through the operational amplifier OPA2, the positive input terminal is connected to the drain of the PMOS tube P7, the source of the PMOS tube P7 is connected to Vin, and the gate terminal is connected to TG1; therefore, the state of the P7 PMOS tube is consistent with the state of the upper power tube M1 of the BUCK of the power stage circuit, so adjusting the width-to-length ratio of P7 can copy the current of the upper power tube M1 of the BUCK circuit of the power stage, and the upper power tube M1 of the BUCK of the power stage circuit carries the current signal of the inductor L, so the PMOS tube P7 can sample the current information of the inductor current L; when A is at a high level, the PMOS tube P8 is turned on, and the current flowing through the PMOS The peak current of tube P7 flows through resistor R3 and is converted into a sampling voltage V-PCM; similarly, the operational amplifier OPA3 clamps the positive terminal to SW2, and the state of PMOS tube P9 is the same as the state of the upper power tube M2 of the power stage circuit BOOST, so the width-to-length ratio of PMOS tube P9 is adjusted to copy the current of the upper power tube M2 of the power stage circuit BOOST, and when B is high, PMOS tube P10 is turned on, so that the valley current of PMOS tube P9 flows through resistor R4 and is converted into a sampling voltage V-VCM; since the output terminals A and B output opposite signals, the output peak current mode or valley current mode is selected according to the states of Vin and Vout.

[0039] Furthermore, the PWM comparator is specifically used for: when the input voltage Vin is greater than 1.2 times of the output voltage Vout, the PWM comparator compares the sampling signal output by the current sampling module with the EA control signal after slope compensation, and outputs a PWM_BUCK signal; when the input voltage Vin is greater than 0.8 times of the output voltage Vout and less than 1.2 times of the output voltage Vout, the PWM comparator compares the sampling signal output by the current sampling module with the EA control signal after slope compensation, and outputs a PWM_B-B signal; when the input voltage Vin is less than 0.8 times of the output voltage Vout, the PWM comparator compares the sampling signal output by the current sampling module with the EA control signal after slope compensation, and outputs a PWM_BOOST signal.

[0040] For further information, see Figure 5 , Figure 51 is a circuit diagram of a switching control module provided by an embodiment of the present invention. The switching control module of this embodiment includes AND gate A2, AND gate A3, AND gate A4, AND gate A5, transmission gate T3, transmission gate T4, transmission gate T5, transmission gate T6, inverter I5, inverter I6, inverter I7, inverter I8, inverter I9, inverter I10, inverter I11, PMOS tube P11, NMOS tube NM6, buffer B1, buffer B2, buffer B3, buffer B4, buffer B5, buffer B6, buffer B7, buffer B8, NAND gate N1, NAND gate N2, NAND gate N3, NAND gate N4, NAND gate N5, NAND gate N6, NAND gate N7, NAND gate N8, NAND gate N9, NAND gate N10, N ... Gate N4, HL delay HL1, HL delay HL2, LH delay LH1 and LH delay LH2, wherein the two input ends of AND gate A2 respectively input EN_B-B enable signal and PWM_B-B signal, the two input ends of AND gate A3 respectively output EN_BUCK enable signal and PWM_BUCK signal, the two input ends of AND gate A3 respectively input EN_B-B enable signal and PWM_B-B signal, and the two input ends of AND gate A4 respectively input EN_BOOST signal and PWM_BOOST signal.

[0041] The transmission gate T3, the transmission gate T4, the transmission gate T5 and the transmission gate T6 respectively include two PMOS tubes, wherein the source of the first PMOS tube in the transmission gate T3 and the drain of the second PMOS tube are both connected to the output end of the AND gate A2, and the drain of the first PMOS tube in the transmission gate T3 and the source of the second PMOS tube are both connected to the drain of the PMOS tube P11 and the input end of the inverter I6; the source of the first PMOS tube in the transmission gate T4 and the drain of the second PMOS tube are both connected to the output end of the AND gate A3, and the drain of the first PMOS tube in the transmission gate T4 and the source of the second PMOS tube are both connected to the input end of the inverter I6; the gate of the first PMOS tube in the transmission gate T3 and the gate of the second PMOS tube in the transmission gate T4 are both input with the EN_BUCK signal; the gate of the second PMOS tube in the transmission gate T3 and the gate of the first PMOS tube in the transmission gate T4 are both input with the EN_B-B signal.

[0042] The source of the first PMOS tube and the drain of the second PMOS tube in the transmission gate T5 are both connected to the output end of the AND gate A4, and the drain of the first PMOS tube and the source of the second PMOS tube in the transmission gate T5 are both connected to the drain of the NMOS tube NM6 and the input end of the inverter I10; the source of the first PMOS tube and the drain of the second PMOS tube in the transmission gate T6 are both connected to the output end of the AND gate A4, and the drain of the first PMOS tube and the source of the second PMOS tube in the transmission gate T6 are both connected to the input end of the inverter I10; the gate of the first PMOS tube in the transmission gate T5 and the gate of the second PMOS tube in the transmission gate T6 are both input with the EN_BOOST signal; the gate of the second PMOS tube in the transmission gate T5 and the gate of the first PMOS tube in the transmission gate T6 are both input with the EN_B-B signal.

[0043] The source of the PMOS tube P11 is connected to the power supply end, the gate of the PMOS tube P11 is used to input the EN_BOOST signal, the inverter I7 is connected between the output end of the inverter I6 and the first input end of the NAND gate N1, the buffer B1, the buffer B2, and the HL delay HL1 are connected in series between the output end of the NAND gate N1 and the first input end of the NAND gate N2, the inverter I8 is connected between the output end of the buffer B1 and the first output end TG1 of the switching control module; the second input end of the NAND gate N2 is connected to the output end of the inverter I6; the buffer B3, the buffer B4, and the LH delay LH1 are connected in series between the output end of the NAND gate N2 and the second input end of the NAND gate N1, and the inverter I9 is ​​connected between the output end of the buffer B3 and the third output end BG1 of the switching control module.

[0044] The gate of the NMOS tube NM6 is connected to the output end of the EN_BUCK enable signal, the source of the NMOS tube NM6 is connected to the ground end, the inverter I11 is connected between the output end of the inverter I10 and the first input end of the NAND gate N3, the buffer B5, the buffer B6, and the HL delay HL2 are connected in series between the output end of the NAND gate N3 and the first input end of the NAND gate N4, the output end of the buffer B5 serves as the second output end TG2 of the switching control module; the second input end of the NAND gate N4 is connected to the output end of the inverter I10; the buffer B7, the buffer B8, and the LH delay LH2 are connected in series between the output end of the NAND gate N4 and the second input end of the NAND gate N3, and the output end of the buffer B7 also serves as the fourth output end BG2 of the switching control module.

[0045] Specifically, when Vin is much larger than Vout, the EN_BUCK enable signal output by the mode control module is high, EN_BOOST and EN_BB are low, and it is in BUCK mode. At this time, the transmission gates T3 and T4 select to output the PWM_BUCK signal, and the PMOS tube P11 is cut off. When PWM_BUCK is high, it is output as low level through the inverter I6, and the NAND gate N2 outputs as high level through the buffer B3 as high level and then the inverter I9 as low level. After passing through buffer B4, it is at a high level, and then after passing through the LH (low side to high side) delay device LH1, it is connected to the input end of N1 at a high level. The output of N1 is at a low level, and after passing through buffer B1, it is at a low level, and then passing through inverter I8, it is at a high level. On the other hand, the output of buffer B1 is connected to buffer B2 at a low level, and after passing through the HL (high side to low side) delay device HL1, it is at a low level; at this time, the output of TG1 is at a low level, and BG1 is at a low level, that is, the upper tube M1 of the power stage circuit BUCK is turned on, and the lower tube M3 is turned off.

[0046] Further, when PWM_BUCK is at a low level, it is at a high level after passing through the inverter I6, and then at a low level after passing through the inverter I7, and at a high level after passing through the NAND gate, and at a high level after passing through the buffer B1, and at a low level after passing through the inverter I8. On the other hand, the output end of the buffer B1 is connected to the buffer B2 at a high level, and is at a high level after passing through the HL delay HL1, and is then connected to the first input end of the NAND gate N2. The second input end of the NAND gate N2 is connected to the output end of I6. At this time, the output of the NAND gate N2 is at a low level, and the output is at a high level after passing through B3 and I9, that is, at this time TG1 is at a low level, and BG1 is at a high level, that is, the upper tube M1 of the power stage BUCK is turned off, and the lower tube M3 is turned on. Since EN_BUCK is at a high level and N6 is turned on, the input end of I10 remains at a low level, TG2 remains on, and TG1 remains off.

[0047] Furthermore, when in buck-boost mode, that is, EN_B-B is high, EN_BUCK and EN_BOOST are low; T3 and T4 choose to output PWM_B-B signal, T5 and T6 also choose to output PWM_B-B signal; when PWM_B-B signal is low, I6 outputs high, I7 outputs low, and AND gate N1 outputs high, which is high after passing through buffer B1. On the one hand, it is connected to inverter I8, and inverter I8 outputs low, and on the other hand, it is high after passing through buffer B2 and HL1, and N2 outputs low, which is high after passing through buffer B3 and inverter The output after the phase shifter I9 is ​​a high level; further, since the PWM_B-B signal is a low level, it is output as a high level after passing through the inverter I10, and then as a low level after passing through the inverter I11, and then as a high level after passing through the NAND gate N3, and then as a high level after passing through the buffer B5. On the other hand, it is output as a high level after passing through the buffer B6 and the HL delay HL2, and then as a low level after passing through the NAND gate N4, and then as a low level after passing through the buffer B7. Therefore, when the PWM_B-B signal is a low level, TG1 outputs a low level, BG1 outputs a high level, TG2 outputs a high level, and BG2 outputs a low level.

[0048] Further, when the PWM_B-B signal is output at a high level, it is low level after passing through the inverter I6, and then high level after passing through the inverter I7, the NAND gate N2 outputs a high level, and then outputs a high level after passing through the buffer B3, and then outputs a low level after passing through the inverter I9. On the other hand, the output end of B3 is connected to the input end of B4, and the output of B4 is a high level, and then the output is a high level after passing through the LH buffer LH1, and then the output is a low level after passing through the NAND gate N1, and then the output is a high level after passing through the buffer B1 and the inverter I8; ​​due to the PWM_B-B signal The output of the signal is high level, and it is output as low level after passing through inverter I10, and then it is output as high level after passing through inverter I11, and then it is output as high level after passing through NAND gate N4, and then it is output as high level after passing through inverter B7, and then it is output as high level after passing through buffer B8 and LH delay device LH2, and then it is output as low level after passing through NAND gate N3, and then it is output as low level after passing through buffer B5; therefore, when the PWM_B-B signal output is high level, TG1 output is high level, BG1 output is low level, TG2 output is low level, and BG2 output is high level.

[0049] Further, when the EN_BOOST signal output by the mode control module is high, EN_BUCK and EN_B-B outputs are low, T5 and T6 output PWM_BOOST signal, when PWM_BOOST output is high, I10 outputs low, then outputs high through inverter I11, NAND gate N4 outputs high, then outputs high through buffer B7, then outputs high through buffer B8 and LH delay device LH2, then outputs low through NAND gate N3, and then outputs low through buffer B5.

[0050] Furthermore, when EN_BOOST outputs a low level, it outputs a high level through inverter I10, then outputs a low level through inverter I11, outputs a high level through NAND gate N3, then outputs a high level through buffer B5, then outputs a high level through buffer B6 and HL delay HL2, then outputs a low level through NAND gate N4, and then outputs a low level through buffer B7. Since EN_BOOST outputs a high level and then outputs a low level through buffer I5, P1 1 is turned on, the input end of I6 is kept at a high level, then passes through the inverter I6 to a low level, then passes through the inverter I7 to output a high level, the NAND gate N2 outputs a high level, passes through the buffer B3 to output a high level, and then passes through the inverter I9 to output a low level. On the other hand, the output end of B3 passes through the input end of B4, the buffer B4 outputs a high level, then passes through the LH buffer LH1 to output a high level, passes through the NAND gate N1 to output a low level, and then passes through the buffer B1 and the inverter I8 to output a high level.

[0051] Further, when PWM_BOOST outputs a high level, TG2 outputs a low level and BG2 outputs a high level; when PWM_BOOST outputs a low level, TG2 outputs a high level and BG2 outputs a low level; TG1 keeps outputting a high level and BG1 keeps outputting a low level.

[0052] For further information, see Figure 6 , Figure 6These are various waveform diagrams of the device in the buck, buck-boost, boost, peak current sampling and valley current sampling modes of the present invention. When the input signal Vin is greater than 1.2 times the output signal Vout, it is in BUCK mode, which is the peak current mode. When the waveform of the control signal VEA (from the error amplifier) ​​and the PCM_slope compensation voltage (from the slope compensation module) superimposed on the peak current output by the current sampling module, the PWM comparator outputs a high level, and TG1 outputs a low level. Until the rising edge of the clock signal arrives, TG1 flips to a high level again. That is, when the clock signal CLK is high, TG1 is high, and when the PWM signal is high, TG1 is low; when 0.8Vout<Vin<1.2Vout, it is in BUCK-BOOST mode, and slope compensation is not required at this time. When the control signal VEA output by the error amplifier contacts the peak current or valley current output by the current sampling module, the output of the PWM comparator flips; when Vin<0.8Vout, it is in BOOST control mode, and the loop selects the valley current mode. When the valley current is subtracted from the VCM_slope compensation voltage and contacts the control signal VEA output by the error amplifier, the output of the PWM comparator flips; therefore, the output voltage Vout can be accurately controlled according to the input of Vin.

[0053] The present invention proposes a three-mode buck-boost converter with peak current and valley current control, which generates three-mode control, namely buck mode control (BUCK mode), buck-boost mode control (BUCK-BOOST mode) and boost mode control (BOOST mode control) according to the comparison between input voltage and output voltage; the switching efficiency is improved by switching between the three modes. In addition, the duty cycle can be reduced and the output voltage ripple can be reduced by reasonably switching between the peak current mode and the valley current mode. The present invention proposes a new circuit of a mode control module, which can effectively control the switching of modes; the present invention unifies the slope compensation circuits (slope compensation modules) of the peak current mode and the valley current mode, and selects the output signal of the slope compensation circuit through mode control, thereby greatly simplifying the slope compensation circuit.

[0054] In the several embodiments provided by the present invention, it should be understood that the apparatus and method disclosed by the present invention can be implemented in other ways. For example, the apparatus embodiments described above are only illustrative, for example, the division of the modules is only a logical function division, and there may be other division methods in actual implementation, for example, multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed.

[0055] In addition, each functional module in each embodiment of the present invention may be integrated into one processing module, or each module may exist physically separately, or two or more modules may be integrated into one module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of hardware plus software functional modules.

[0056] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A three-mode buck-boost converter with peak current and valley current control, characterized in that: It includes a power stage circuit, an error amplifier, a slope compensation module, a current sampling module, a PWM comparator, a mode control module and a switching control module, wherein: The power stage circuit is used to obtain an output voltage Vout according to an input voltage Vin and sample the output voltage Vout through a resistor divider to obtain a sampled voltage; The error amplifier obtains a control signal according to a comparison result between the sampled voltage and a preset reference voltage; The mode control module is used to selectively output different enable signals according to the states of the input voltage Vin and the output voltage Vout, wherein the enable signals include an EN_BOOST enable signal, an EN_BUCK enable signal or an EN_B-B enable signal; The slope compensation module is used to output different compensation voltages when the three-mode buck-boost converter is in different modes, and the different modes include BOOST mode, BUCK mode or BUCK-BOOST mode; The input end of the current sampling module is connected to the power stage circuit, and is used to collect the voltage of the peak current or the voltage of the valley current according to different modes of the three-mode buck-boost converter; The compensation voltage output by the slope compensation module is superimposed on the control signal output by the error amplifier and then input to the negative input terminal of the PWM comparator, and the output terminal of the current sampling signal is connected to the positive input terminal of the PWM comparator; the PWM comparator is used to generate a PWM control signal; The switching control module is used to generate a driving signal according to the PWM control signal output by the PWM comparator and different enable signals output by the mode control module, so as to control the three-mode buck-boost converter to switch to different modes.

2. The three-mode buck-boost converter with peak current and valley current control according to claim 1, characterized in that: The power stage circuit includes a transistor M1, a transistor M2, a transistor M3, a transistor M4, an input capacitor Cin, an output capacitor Co, an inductor L, a resistor R0, a resistor R1 and a resistor R2, wherein: The input capacitor Cin is connected between the input voltage Vin access terminal and the ground terminal, the drain of the transistor M1 is connected to the input voltage Vin access terminal, the inductor L is connected between the source of the transistor M1 and the drain of the transistor M2, and the drain of the transistor M3 is connected to the source of the transistor M1; The source of the transistor M3 and the source of the transistor M4 are both connected to the ground terminal, the drain of the transistor M4 is connected to the drain of the transistor M2, the source of the transistor M2 is connected to the output terminal of the output voltage Vout, the output capacitor Co and the resistor R0 are connected in parallel between the output terminal of the output voltage Vout and the ground terminal, and the resistor R1 and the resistor R2 are connected in series between the output terminal of the output voltage Vout and the ground terminal; The four output terminals of the switching control module are respectively connected to the gate of the transistor M1, the gate of the transistor M2, the gate of the transistor M3 and the gate of the transistor M4 to respectively control the on and off of the transistor M1, the transistor M2, the transistor M3 and the transistor M4; the two input terminals of the current sampling module are respectively connected to the two ends of the inductor L; A negative input terminal of the error amplifier is connected between the resistor R1 and the resistor R2.

3. The three-mode buck-boost converter with peak current and valley current control according to claim 1, characterized in that: The positive input terminal of the error amplifier is used to input a preset reference voltage VREF.

4. The three-mode buck-boost converter with peak current and valley current control according to claim 1, characterized in that: The mode control module includes a comparator COMP1, a comparator COMP2, an inverter I1, an inverter 12, an RS latch RS1, an RS latch RS2, an AND gate A1 and a counter, wherein: The positive input terminal of the comparator COMP1 is used to input the input voltage Vin, the negative input terminal of the comparator COMP1 is used to input 0.8 times of the output voltage Vout, and the output terminal of the comparator COMP1 is connected to the input terminal of the inverter I1 and the first input terminal of the AND gate A1 respectively; The positive input terminal of the comparator COMP2 is used to input 1.2 times of the output voltage Vout, the negative input terminal of the comparator COMP2 is used to input the input voltage Vin, and the output terminal of the comparator COMP2 is respectively connected to the input terminal of the inverter I2 and the second input terminal of the AND gate A1; The output end of the AND gate A1 is connected to the first input end of the counter, the second input end of the counter inputs the external clock signal CLK, and when the output voltage of the AND gate A1 appears high level four times, the output end of the counter outputs high level; The output end of the inverter I1 is connected to the S end of the RS latch RS1, the output end of the inverter I2 is connected to the S end of the RS latch RS2, the output end of the counter is connected to the R end of the RS latch RS1 and the R end of the RS latch RS2, and the counter outputs an EN_B-B enable signal; the Q end of the RS latch RS1 is used to output an EN_BOOST enable signal, and the Q end of the RS latch RS2 is used to output an EN_BUCK enable signal.

5. The three-mode buck-boost converter with peak current and valley current control according to claim 2, characterized in that: The slope compensation module includes a comparator COPM3, a Schmitt trigger S1, an inverter I3 and an inverter I4, a transmission gate T1, a transmission gate T2, an operational amplifier OPA1, a resistor R3, a PMOS tube P1, a PMOS tube P2, a PMOS tube P3, a PMOS tube P4, a PMOS tube P5, a PMOS tube P6, an NMOS tube NM1, an NMOS tube NM2, an NMOS tube NM3, a capacitor C1 and a capacitor C2, wherein: The comparator COPM3, the Schmitt trigger S1, the inverter I3 and the inverter I4 are connected in sequence, the positive input terminal of the comparator COPM3 is used to input the input voltage Vin, the negative input terminal of the comparator COPM3 is used to input the output voltage Vout, the output terminal of the third inverter I3 is used as the A output terminal, and the output terminal of the fourth inverter I4 is used as the B output terminal; The transmission gate T1 and the transmission gate T2 respectively include two PMOS tubes, wherein the source of the first PMOS tube and the drain of the second PMOS tube in the transmission gate T1 are both input with the input voltage Vin, and the drain of the first PMOS tube and the source of the second PMOS tube in the transmission gate T1 are both connected to the positive input terminal of the operational amplifier OPA1; the source of the first PMOS tube and the drain of the second PMOS tube in the transmission gate T2 are both input with the output voltage Vout, and the drain of the first PMOS tube and the source of the second PMOS tube in the transmission gate T2 are both connected to the negative input terminal of the operational amplifier OPA1; the gate of the first PMOS tube in the transmission gate T1 and the gate of the second PMOS tube in the transmission gate T2 are both connected to the B output terminal; the gate of the second PMOS tube in the transmission gate T1 and the gate of the first PMOS tube in the transmission gate T2 are both connected to the A output terminal; The output end of the operational amplifier OPA1 is connected to the gate of the NMOS tube NM1, the resistor R3 is connected between the source of the NMOS tube NM1 and the ground end, and the negative input end of the operational amplifier OPA1 is connected to the source of the NMOS tube NM1; the drain of the PMOS tube P6 is connected to the drain of the NMOS tube NM1, and the gate of the PMOS tube P6 is used to input the EN_B-B enable signal; the source of the PMOS tube P6 is connected to the drain of the PMOS tube P1, the gate of the PMOS tube P1, the gate of the PMOS tube P2, and the gate of the PMOS tube P4; The source of the PMOS tube P1, the source of the PMOS tube P2 and the source of the PMOS tube P4 are all connected to the power supply terminal VDD, the drain of the PMOS tube P2 is connected to the source of the PMOS tube P3, the gate of the PMOS tube P3 is connected to the B output terminal, and the capacitor C1 is connected between the drain of the PMOS tube P3 and the ground terminal. The drain of the NMOS tube NM2 is connected to the drain of the PMOS tube P3, the source of the NMOS tube NM2 and the source of the NMOS tube NM3 are both connected to the ground terminal, the gate of the NMOS tube NM2 is used to input an external clock signal CLK, and the drain of the PMOS tube P3 is also used to output a slope signal PCM_slope; The gate of the PMOS tube P5 is connected to the A output terminal, the drain of the PMOS tube P4 is connected to the source of the PMOS tube P5, the capacitor C2 is connected between the drain of the PMOS tube P5 and the ground terminal, the drain of the NMOS tube NM3 is connected to the drain of the PMOS tube 53, the gate of the NMOS tube NM3 is used to input the clock signal CLK, and the drain of the PMOS tube P5 is also used to output the slope signal VCM_slope.

6. The three-mode buck-boost converter with peak current and valley current control according to claim 5, characterized in that: The current sampling module includes an operational amplifier OPA2, an operational amplifier OPA3, a resistor R3, a resistor R4, a PMOS tube P7, a PMOS tube P8, a PMOS tube P9, a PMOS tube P10, an NMOS tube NM4 and an NMOS tube NM5, wherein: The source of the PMOS tube P7 is used to input the input voltage Vin, the gate of the PMOS tube P7 is connected to the first output terminal TG1 of the switching control module, the drain of the PMOS tube P7 is connected to the source of the PMOS tube P8 and the positive input terminal of the operational amplifier OPA2, the gate of the PMOS tube P8 is connected to the A output terminal, the drain of the PMOS tube P8 is connected to the drain of the NMOS tube NM4, the negative input terminal of the operational amplifier OPA2 is connected to the first terminal SW1 of the inductor L in the power stage circuit, the output terminal of the operational amplifier OPA2 is connected to the gate of the NMOS tube NM4, and the resistor R3 is connected between the source of the NMOS tube NM4 and the ground terminal; the source of the NMOS tube NM4 is also used to output a sampling voltage V-PCM; The source of the PMOS tube P9 is used to input the output voltage Vout, the gate of the PMOS tube P9 is connected to the second output terminal TG2 of the switching control module, the drain of the PMOS tube P9 is connected to the source of the PMOS tube P10 and the positive input terminal of the operational amplifier OPA3, the gate of the PMOS tube P9 is connected to the B output terminal, the drain of the PMOS tube P9 is connected to the drain of the NMOS tube NM5, the negative input terminal of the operational amplifier OPA3 is connected to the second terminal SW2 of the inductor L in the power stage circuit, the output terminal of the operational amplifier OPA3 is connected to the gate of the NMOS tube NM5, and the resistor R4 is connected between the source of the NMOS tube NM5 and the ground terminal; the source of the NMOS tube NM5 is also used to output the sampling voltage V-VCM.

7. The peak current and valley current controlled three-mode buck-boost converter according to claim 1, characterized in that: The PWM comparator is specifically used for: When the input voltage Vin is greater than 1.2 times the output voltage Vout, the PWM comparator outputs a PWM_BUCK signal by comparing the sampling signal output by the current sampling module with the EA control signal after slope compensation; When the input voltage Vin is greater than 0.8 times the output voltage Vout and less than 1.2 times the output voltage Vout, the PWM comparator outputs a PWM_B-B signal by comparing the sampling signal output by the current sampling module with the EA control signal after slope compensation; When the input voltage Vin is less than 0.8 times the output voltage Vout, the PWM comparator outputs a PWM_BOOST signal by comparing the sampling signal output by the current sampling module with the EA control signal after slope compensation.

8. The three-mode buck-boost converter with peak current and valley current control according to claim 7, characterized in that: The switching control module includes AND gate A2, AND gate A3, AND gate A4, AND gate A5, transmission gate T3, transmission gate T4, transmission gate T5, transmission gate T6, inverter I5, inverter I6, inverter I7, inverter I8, inverter I9, inverter I10, inverter I11, PMOS tube P11, NMOS tube NM6, buffer B1, buffer B2, buffer B3, buffer B4, buffer B5, buffer B6, buffer B7, buffer B8, NAND gate N1, NAND gate N2, NAND gate N3, NAND gate N4, HL delay HL1, HL delay HL2, LH delay LH1 and LH delay LH2, wherein, The two input ends of the AND gate A2 are respectively input with EN_BB enable signal and PWM_BB signal, the two input ends of the AND gate A3 are respectively output with EN_BUCK enable signal and PWM_BUCK signal, the two input ends of the AND gate A3 are respectively input with EN_BB enable signal and PWM_BB signal, and the two input ends of the AND gate A4 are respectively input with EN_BOOST signal and PWM_BOOST signal; The transmission gate T3, the transmission gate T4, the transmission gate T5 and the transmission gate T6 respectively include two PMOS tubes, wherein the source of the first PMOS tube and the drain of the second PMOS tube in the transmission gate T3 are both connected to the output end of the AND gate A2, and the drain of the first PMOS tube and the source of the second PMOS tube in the transmission gate T3 are both connected to the drain of the PMOS tube P11 and the input end of the inverter I6; the source of the first PMOS tube and the drain of the second PMOS tube in the transmission gate T4 are both connected to the output end of the AND gate A3, and the drain of the first PMOS tube and the source of the second PMOS tube in the transmission gate T4 are both connected to the input end of the inverter I6; the gate of the first PMOS tube in the transmission gate T3 and the gate of the second PMOS tube in the transmission gate T4 are both input with EN_BUCK signal; the gate of the second PMOS tube in the transmission gate T3 and the gate of the first PMOS tube in the transmission gate T4 are both input with EN_B-B signal; The source of the first PMOS tube and the drain of the second PMOS tube in the transmission gate T5 are both connected to the output end of the AND gate A4, and the drain of the first PMOS tube and the source of the second PMOS tube in the transmission gate T5 are both connected to the drain of the NMOS tube NM6 and the input end of the inverter I10; the source of the first PMOS tube and the drain of the second PMOS tube in the transmission gate T6 are both connected to the output end of the AND gate A4, and the drain of the first PMOS tube and the source of the second PMOS tube in the transmission gate T6 are both connected to the input end of the inverter I10; the gate of the first PMOS tube in the transmission gate T5 and the gate of the second PMOS tube in the transmission gate T6 are both input with the EN_BOOST signal; the gate of the second PMOS tube in the transmission gate T5 and the gate of the first PMOS tube in the transmission gate T6 are both input with the EN_B-B signal; The source of the PMOS tube P11 is connected to the power supply terminal, the gate of the PMOS tube P11 is used to input the EN_BOOST signal, the inverter I7 is connected between the output end of the inverter I6 and the first input end of the NAND gate N1, the buffer B1, the buffer B2, and the HL delay HL1 are connected in series between the output end of the NAND gate N1 and the first input end of the NAND gate N2, the inverter I8 is connected between the output end of the buffer B1 and the first output end TG1 of the switching control module; the second input end of the NAND gate N2 is connected to the output end of the inverter I6; the buffer B3, the buffer B4 and the LH delay LH1 are connected in series between the output end of the NAND gate N2 and the second input end of the NAND gate N1, and the inverter I9 is ​​connected between the output end of the buffer B3 and the third output end BG1 of the switching control module; The gate of the NMOS tube NM6 is used to input the EN_BUCK enable signal, the source of the NMOS tube NM6 is connected to the ground terminal, the inverter I11 is connected between the output terminal of the inverter I10 and the first input terminal of the NAND gate N3, the buffer B5, the buffer B6, and the HL delay HL2 are connected in series between the output terminal of the NAND gate N3 and the first input terminal of the NAND gate N4, and the output terminal of the buffer B5 serves as the second output terminal TG2 of the switching control module; The second input end of the NAND gate N4 is connected to the output end of the inverter I10; the buffer B7, the buffer B8 and the LH delay device LH2 are connected in series between the output end of the NAND gate N4 and the second input end of the NAND gate N3, and the output end of the buffer B7 also serves as the fourth output end BG2 of the switching control module.

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