Multi-converter parallel carrier synchronization control method, electronic equipment and storage medium

Abstract

The invention discloses a carrier synchronization control method with multiple converters connected in parallel, electronic equipment and a storage medium, each converter corresponds to a control unit, each control unit is integrated with a corresponding accumulation counter, one converter is used as a host, the other converters are used as slaves, the method is applied to any slave, and the control unit is integrated with a corresponding accumulation counter. Comprising the following steps: receiving a preset low-frequency synchronization signal generated and sent by a host; capturing a rising edge or a falling edge of the low-frequency synchronizing signal; when the rising edge or the falling edge of the low-frequency synchronization signal is captured every time, collecting the current carrier value and the maximum carrier value of the carrier signal output by the corresponding control unit; and according to the current carrier value and the maximum carrier value, adjusting the carrier count value of the corresponding accumulation counter, so that the carrier signal of the slave computer and the carrier signal of the host computer are synchronized in phase. According to the invention, a low-frequency signal is used as a synchronization mechanism, so that normal operation and efficient output of the multi-machine parallel system are ensured, and the high-frequency synchronization precision is improved.

Description

Technical Field

[0001] The present invention relates to the field of power electronics technology, and in particular to a carrier synchronization control method for multiple converters connected in parallel, an electronic device and a computer-readable storage medium. Background Art

[0002] In a power system with multiple converters operating in parallel, the existence of high-frequency circulating current is an issue that cannot be ignored. High-frequency circulating current not only reduces the overall efficiency of the system, but also increases the heat loss of the system, seriously affecting the stability and reliability of the system. Realizing high-frequency synchronization is regarded as an effective way to suppress high-frequency circulating current.

[0003] At present, the common way to achieve high-frequency synchronization is to compare the carrier phase of each converter with the power frequency phase of the power grid and make real-time frequency adjustments to achieve carrier phase synchronization. Through such dynamic adjustment, the carrier phase of each converter can be synchronized with the power frequency phase of the power grid, thereby realizing parallel power generation of multiple converters. However, this synchronization method depends on the accuracy of grid-connected phase locking, and requires the carrier frequency to be linked with the power frequency. When the grid frequency changes, the carrier frequency will inevitably be out of sync. Any slight frequency deviation will lead to inconsistency between the carrier frequency and the power frequency, thereby affecting the synchronization accuracy of the entire system. Summary of the invention

[0004] The present invention aims to solve one of the technical problems in the related art at least to a certain extent. To this end, the present invention proposes a carrier synchronization control method for multiple converters in parallel, an electronic device and a computer-readable storage medium, which can improve high-frequency synchronization accuracy.

[0005] In a first aspect, an embodiment of the present invention provides a carrier synchronization control method for multiple converters in parallel, wherein each converter corresponds to a control unit, each control unit is integrated with a corresponding cumulative counter, one of the converters is used as a master, and the remaining converters are used as slaves, and the method is applied to any one of the slaves, including:

[0006] Receiving a preset low-frequency synchronization signal generated and sent by the host;

[0007] Capturing the rising edge or the falling edge of the low-frequency synchronization signal;

[0008] When the rising edge or falling edge of the low-frequency synchronization signal is captured each time, the current carrier value and the maximum carrier value of the corresponding carrier signal output by the control unit are collected;

[0009] According to the current carrier value and the maximum carrier value, the carrier count value of the corresponding accumulative counter is adjusted so that the phase of the carrier signal of the slave is synchronized with the phase of the carrier signal of the host.

[0010] Optionally, in one embodiment of the present invention, adjusting the carrier count value of the corresponding accumulative counter according to the current carrier value and the maximum carrier value includes:

[0011] Determine a target carrier value according to the maximum carrier value, wherein the target carrier value is half of the maximum carrier value;

[0012] Determine the magnitude relationship between the current carrier value and the target carrier value to obtain a comparison result;

[0013] The carrier count value of the corresponding accumulative counter is adjusted according to the comparison result.

[0014] Optionally, in one embodiment of the present invention, adjusting the corresponding carrier count value of the accumulative counter according to the comparison result includes:

[0015] When the current carrier value is greater than or equal to the target carrier value, adjusting the corresponding carrier count value of the accumulative counter to the maximum carrier value;

[0016] or,

[0017] When the current carrier value is less than the target carrier value, the corresponding carrier count value of the accumulative counter is adjusted to zero.

[0018] Optionally, in one embodiment of the present invention, at least the control unit of each of the slaves is correspondingly configured with a microprocessing unit, and the capturing of the rising edge or the falling edge of the low-frequency synchronization signal includes:

[0019] Based on the corresponding micro-processing unit, respectively obtaining a first state of the low-frequency synchronization signal at a current moment and a second state of the low-frequency synchronization signal at a next moment;

[0020] Determine whether the first state and the second state are the same. If different, capture the rising edge or falling edge of the low-frequency synchronization signal between the current moment and the first moment. Otherwise, determine that the rising edge or falling edge of the low-frequency synchronization signal is not generated between the current moment and the first moment.

[0021] Optionally, in one embodiment of the present invention, the method further includes:

[0022] Each time a rising edge or a falling edge of the low-frequency synchronization signal is captured, a current timestamp of the low-frequency synchronization signal is recorded by the corresponding microprocessing unit;

[0023] Control the corresponding microprocessing unit to send the current timestamp of the low-frequency synchronization signal to the corresponding control unit.

[0024] Optionally, in one embodiment of the present invention, the collecting the current carrier value and the maximum carrier value of the carrier signal output by the corresponding control unit includes:

[0025] The current carrier value and the maximum carrier value of the carrier signal corresponding to the current timestamp of the low-frequency synchronization signal are collected by the corresponding control unit.

[0026] Optionally, in one embodiment of the present invention, the frequency of the low-frequency synchronization signal is 25-100 Hz.

[0027] In a second aspect, an embodiment of the present invention provides a carrier synchronization control method for multiple converters in parallel, wherein each converter corresponds to a control unit, each control unit is integrated with a corresponding cumulative counter, one of the converters is used as a host, and the remaining converters are used as slaves, and the method is applied to the host, including:

[0028] When a preset low-frequency synchronization signal is generated, the low-frequency synchronization signal is sent to any one of the slaves, so that any one of the slaves captures the rising edge or the falling edge of the low-frequency synchronization signal, and each time any one of the slaves captures the rising edge or the falling edge of the low-frequency synchronization signal, collects the current carrier value and the maximum carrier value of the carrier signal output by the corresponding control unit, and adjusts the carrier count value of the corresponding cumulative counter according to the current carrier value and the maximum carrier value, so as to synchronize the phase of the carrier signal of the slave with the carrier signal of the host.

[0029] In a third aspect, an embodiment of the present invention provides an electronic device, including:

[0030] at least one processor;

[0031] at least one memory for storing at least one program;

[0032] When at least one of the programs is executed by at least one of the processors, the carrier synchronization control method for multiple parallel converters as described in the first aspect and the second aspect is implemented.

[0033] In a fourth aspect, an embodiment of the present invention provides a computer-readable storage medium, which stores a program executable by a processor, and when the program executable by the processor is executed by the processor, it is used to implement the carrier synchronization control method of multiple parallel converters as described in the first aspect and the second aspect.

[0034] The carrier synchronization control method, electronic device and computer-readable storage medium for parallel connection of multiple converters proposed in the present invention can achieve high-frequency synchronization by providing a low-frequency synchronization signal input for high-frequency circulating current caused by carrier asynchrony, that is, the converter as the host generates and sends a low-frequency synchronization signal to each converter as a slave. For each slave, each time the rising edge or falling edge of the low-frequency synchronization signal is captured, the carrier count value of the corresponding accumulator counter is adjusted according to the collected current carrier value and the maximum carrier value, so that the phases of each carrier signal are synchronized, avoiding the influence of the phase difference on the high-frequency circulating current, and effectively suppressing the high-frequency circulating current generated by the parallel converter in normal operation. Compared with the relevant existing technology, the low-frequency signal is used as the synchronization mechanism, the resource configuration is optimized, the hardware resource consumption is significantly reduced, the dependence on high-speed processors and high-precision sensors is reduced, and the influence on the pulse width modulation signal is small, which can ensure the normal operation and efficient output of the multi-machine parallel system, improve the high-frequency synchronization accuracy of the system, and has important engineering practical value. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 is a flow chart of a carrier synchronization control method for multiple converters in parallel provided by an embodiment of the present invention;

[0036] Figure 2 is a schematic structural diagram of a converter provided by an embodiment of the present invention;

[0037] Figure 3 is a circuit topology diagram of a parallel converter provided by an embodiment of the present invention;

[0038] Figure 4 yes Figure 3 The control block diagram of the parallel converter for suppressing high-frequency circulating current is shown;

[0039] Figure 5 yes Figure 1 Flowchart of step S2000 in FIG.

[0040] Figure 6 is a flow chart of a carrier synchronization control method for multiple converters in parallel provided by another embodiment of the present invention;

[0041] Figure 7 yes Figure 1 Flowchart of step S4000 in FIG.

[0042] FIG8( a ) is a diagram showing simulation results of a synchronous carrier mode of a parallel converter in the related prior art;

[0043] FIG8( b ) is a diagram showing simulation results of a carrier synchronization control method for multiple parallel converters provided in accordance with an embodiment of the present invention;

[0044] Fig. 9is a flow chart of a carrier synchronization control method for multiple converters in parallel provided by another embodiment of the present invention;

[0045] Fig.10 It is a structural schematic diagram of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0046] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0047] It should be noted that although the functional modules are divided in the device schematic and the logical order is shown in the flowchart, in some cases, the steps shown or described may be performed in a different order than the module division in the device or the order in the flowchart.

[0048] Figure 1 A flow chart of a carrier synchronization control method for multiple parallel converters provided by an embodiment of the present invention, wherein each converter corresponds to a control unit, each control unit is integrated with a corresponding cumulative counter, one converter is used as a master, and the remaining converters are used as slaves. The method can be applied to any slave, but is not limited to; Figure 1 As shown, the carrier synchronization control method may include but is not limited to steps S1000 to S4000.

[0049] Step S1000, receiving a preset low-frequency synchronization signal generated and sent by the host, that is, the host will send the generated low-frequency synchronization signal to each slave respectively, and for any slave, steps S1000 to S4000 can be executed to achieve phase synchronization with the carrier signal of the host;

[0050] Step S2000, capturing the rising edge or falling edge of the low-frequency synchronization signal, wherein the frequency of the low-frequency synchronization signal may be, but is not limited to, 25 to 100 Hz;

[0051] Step S3000: when the rising edge or falling edge of the low-frequency synchronization signal is captured each time, the current carrier value and the maximum carrier value of the carrier signal output by the corresponding control unit are collected, wherein the maximum carrier value of the host and any slave is the same;

[0052] Step S4000: According to the current carrier value and the maximum carrier value, the carrier count value of the corresponding accumulative counter is adjusted so that the phase of the carrier signal of the slave is synchronized with that of the host.

[0053] In this step, for the high-frequency circulating current caused by carrier asynchrony, high-frequency synchronization can be achieved by providing a low-frequency synchronization signal input, that is, the converter as the host generates and sends a low-frequency synchronization signal to each converter as a slave. For each slave, each time the rising edge or falling edge of the low-frequency synchronization signal is captured, the carrier count value of the corresponding accumulator counter is adjusted according to the collected current carrier value and the maximum carrier value, so that the phases of each carrier signal are synchronized, avoiding the influence of the phase difference on the high-frequency circulating current, and effectively suppressing the high-frequency circulating current generated by the parallel converter under normal operating conditions. Compared with the relevant existing technology, the use of low-frequency signals as a synchronization mechanism optimizes resource allocation, significantly reduces hardware resource consumption, reduces dependence on high-speed processors and high-precision sensors, and has little impact on pulse width modulation signals, can ensure the normal operation and efficient output of the multi-machine parallel system, improve the high-frequency synchronization accuracy of the system, and has important engineering practical value.

[0054] It should be noted that each converter may correspond to a control unit in a variety of presentation forms, which are not limited here. For example, the control unit may be arranged outside the converter, and external communication is performed between the two, or, Figure 2 As shown, the control unit 1100 is arranged in the converter 1000, and the control unit 1100 also integrates an accumulative counter 1110 and a microprocessor unit 1120. The accumulative counter 1110 can be used to generate a high-frequency carrier signal, wherein the microprocessor unit 1120 may be internally provided with, but not limited to, an enhanced capture module (ECAP), and the ECAP can be used to accurately capture the rising edge and the falling edge of the low-frequency synchronization signal; for the converter 1000 serving as the host, the microprocessor unit 1120 may not be required to be provided in its control unit 1100, that is, at least one microprocessor unit 1120 may be configured correspondingly to the control unit 1100 of each slave, and it is not limited here whether the microprocessor unit 1120 is provided in the control unit 1100 of the host.

[0055] In one embodiment, the specific structure of the multi-machine system formed by connecting multiple converters in parallel can be various, and those skilled in the art can make corresponding settings according to actual application scenarios, such as setting it to a two-level converter, a three-level converter, etc., which is not limited here. For example, a circuit topology diagram of connecting multiple converters in parallel is given below, as shown in Figure 3 As shown, Figure 3 The circuit topology diagram of the parallel two-level converter provided in one embodiment of the present invention mainly realizes the power conversion function from DC to AC, including three-phase inductors L1, L2, resistors R1=R2, and three-phase full-bridge power switches S a,k , S b,k , S c,k , k = 1, 2. The upper and lower switches of the same bridge arm work in complementary mode. The two converters are connected in parallel, that is, the AC side is connected to the three-phase AC bus (grid) and the DC side is connected to the DC bus. The direction of current flowing from the converter into the grid is defined as the positive direction, denoted as i a,1 ~i a,2 、i b,1 ~i b,2 、i c,1 ~i c,2 , two parallel converters are independently controlled by their own control units, that is, each converter corresponds to a control unit, different converters correspond to different control units, and one converter is used as the master. In actual scenarios, the number of converters in parallel can be more, that is, the slaves can be set to more, but no matter how many there are, the basic principle is the same, so this embodiment and subsequent embodiments are only based on Figure 3 The circuit topology shown is for illustration only and should not be construed as a limitation.

[0056] In one embodiment, if Figure 4 As shown, Figure 4 for Figure 3 The control block diagram of the parallel two-level converter for suppressing high-frequency circulating current is shown in FIG. In the control block diagram, the current reference value i is firstly set to * d Subtract the current sampling value i d , the error Δi d =i * d -i d It is sent to the corresponding PI control unit and the feedforward compensation e is introduced at the same time d , and decouple to get V d , the calculation formula is V d =K p Δi d -K i ∫Δi d dt, where K p is the proportional coefficient in the preset PI control unit, K i is the integral coefficient in the preset PI control unit; similarly, by calculating the error Δi q =i * q -i q , and send it to the corresponding PI control unit to introduce feedforward compensation e q , and decouple to get V q , the calculation result is the same as V d Similar, no further description; then V d and V qAfter transformation to abc coordinates, 6 pulse width modulation signals are finally output through the SPWM modulation link. In this control process, the low-frequency synchronization signal generated by the host is introduced to realize the carrier synchronization control of multiple converters in parallel.

[0057] In one embodiment, the counts of the cumulative counters integrated in each control unit are independent of each other, that is, the counts of the cumulative counters between different control units do not affect each other, but no matter which control unit it is, each time the rising edge or falling edge of the low-frequency synchronization signal is captured, the current carrier value and the maximum carrier value of the carrier signal output by the control unit are collected, and then the carrier count value of the corresponding cumulative counter is adjusted according to the current carrier value and the maximum carrier value.

[0058] In one embodiment, there is no special requirement for the rising edge or falling edge of the low-frequency synchronization signal, and the rising edge or falling edge can be regarded as an equivalent state, that is, as long as any one of the rising edge and the falling edge of the low-frequency synchronization signal is captured, the carrier synchronization control method of this embodiment can be triggered.

[0059] like Figure 5 As shown, in one embodiment of the present invention, at least one microprocessing unit is configured corresponding to the control unit of each slave, and step S2000 may include but is not limited to steps S2100 to S2200.

[0060] Step S2100: Based on the corresponding microprocessing unit, respectively obtain a first state of the low-frequency synchronization signal at the current moment and a second state at the next moment;

[0061] Step S2200, determine whether the first state and the second state are the same. If different, capture the rising edge or falling edge of the low-frequency synchronization signal between the current moment and the first moment. Otherwise, determine that the rising edge or falling edge of the low-frequency synchronization signal is not generated between the current moment and the first moment.

[0062] In this step, the status of the low-frequency synchronization signal at different times can be obtained, but is not limited to, based on the on-chip peripherals of the microprocessor unit, and then the status at different times are compared to confirm whether the two states are the same. If different, it means that the rising edge or falling edge of the low-frequency synchronization signal can be captured between the current moment and the first moment. Otherwise, it is determined that the rising edge or falling edge of the low-frequency synchronization signal is not generated between the current moment and the first moment. Through this judgment method, the rising edge or falling edge of the low-frequency synchronization signal can be clearly, conveniently and reliably captured. Among them, the first state and the second state can be specifically presented as voltage values ​​of different states. Of course, they can also be presented as other related parameters. This part of the content is well known to those skilled in the art, so it will not be repeated here.

[0063] It should be noted that for two independent microprocessing units, the carrier frequency is theoretically set to be the same for both, but due to the drift of the clock crystal, the deviation of the initial moment and other factors, the carriers of the two control units cannot be accurately synchronized. In an application scenario, the rising and falling edges of the low-frequency synchronization signal can be accurately captured with the help of ECAP, but not limited to. First, the ECAP is initialized and the clock of the ECAP is enabled to ensure that each operation instruction can be executed on time and accurately; for the configuration of the relevant registers, it is set to CAP mode, and for the setting of the timestamp, it is set to a continuous and absolute timestamp mode. Every time the rising or falling edge of the low-frequency signal is captured, the timestamp can be recorded in a timely, complete and accurate manner, with the aim of providing accurate and detailed timestamp information for subsequent data analysis and research.

[0064] like Figure 6 As shown, in one embodiment of the present invention, the carrier synchronization control method may also include but is not limited to steps S5000 to S6000.

[0065] Step S5000: when a rising edge or a falling edge of a low-frequency synchronization signal is captured each time, a current timestamp of the low-frequency synchronization signal is recorded by a corresponding microprocessing unit;

[0066] Step S6000: Control the corresponding microprocessing unit to send the current timestamp of the low-frequency synchronization signal to the corresponding control unit.

[0067] In this step, each time the rising edge or falling edge of the low-frequency synchronization signal is captured, the current timestamp of the low-frequency synchronization signal is recorded by the microprocessing unit to determine the time corresponding to the rising edge or falling edge of the low-frequency synchronization signal, and then the current timestamp of the low-frequency synchronization signal is sent to the corresponding control unit through the microprocessing unit, so that the control unit can promptly know the corresponding time when the rising edge or falling edge of the low-frequency synchronization signal appears, so as to facilitate the control unit to perform corresponding collection of the real-time carrier value at this time.

[0068] In one embodiment of the present invention, step S3000 may include but is not limited to step S3100.

[0069] Step S3100: The current carrier value and the maximum carrier value of the carrier signal corresponding to the current timestamp of the low-frequency synchronization signal are collected by the corresponding control unit.

[0070] It can be seen that the control unit can timely obtain the current timestamp corresponding to the rising edge or falling edge of the low-frequency synchronization signal, and then collect the current carrier value and maximum carrier value of the carrier signal corresponding to the current timestamp of the low-frequency synchronization signal. Through this collection method, the current carrier value and maximum carrier value of the carrier signal in the relevant scenario can be accurately and reliably determined.

[0071] like Figure 7 As shown, in one embodiment of the present invention, step S4000 may include but is not limited to steps S4100 to S4300.

[0072] Step S4100: determining a target carrier value according to the maximum carrier value, wherein the target carrier value is half of the maximum carrier value;

[0073] Step S4200, determine the magnitude relationship between the current carrier value and the target carrier value, and obtain a comparison result;

[0074] Step S4300: adjust the carrier count value of the corresponding accumulative counter according to the comparison result.

[0075] In this step, the comparison result is obtained by judging the size relationship between the current carrier value and the target carrier value. The comparison result can better characterize the relative size of the current carrier value and the target carrier value, and then adjust the carrier count value of the corresponding cumulative counter according to the comparison result, so that the phase of the carrier signal of the slave is synchronized with the phase of the carrier signal of the host.

[0076] In one embodiment, when the current carrier value is greater than or equal to the target carrier value, the carrier count value of the corresponding cumulative counter is adjusted to the maximum carrier value, or when the current carrier value is less than the target carrier value, the carrier count value of the corresponding cumulative counter is adjusted to zero, that is, whenever the rising edge or falling edge of the low-frequency synchronization signal arrives and is detected, the carrier signal will be immediately set to zero or the maximum value. If C≥C max / 2, then N=C max ; C <C max / 2, then N = 0, where C is the current carrier value, C max is the maximum carrier value, and N is the carrier count value of the accumulative counter.

[0077] It should be noted that, since the two control units are set to the same carrier frequency in theory, the frequency difference between the two is only caused by the drift of the clock crystal oscillator, so the frequency offset between the two is very small, and within the low-frequency synchronization signal period (for example, set to 20ms), the carrier signal only produces a small phase difference. Therefore, the periodic forced synchronization mechanism based on the low-frequency synchronization signal proposed in the present invention can ensure the precise synchronization of the carrier signal and effectively suppress the high-frequency zero-sequence circulating current between the parallel converters.

[0078] In order to verify the effectiveness of the carrier synchronization method proposed in the embodiment of the present invention, the applicant conducted a detailed simulation experiment, and the simulation results are shown in Figures 8(a) and 8(b), wherein the "pulse signal" shown in Figures 8(a) and 8(b) is a low-frequency synchronization signal, and "carrier one" and "carrier two" are carriers corresponding to the two control units respectively, wherein "carrier one" is the carrier corresponding to the host and "carrier two" is the carrier corresponding to the slave; compared with the situation shown in Figure 8(a) where the carrier phase needs to be synchronized with the power frequency phase of the power grid, based on the carrier synchronization method proposed in the embodiment of the present invention, as shown in Figure 8(b), the carrier waveforms of the two groups of DSPs achieve high-frequency synchronization, effectively avoiding the high-frequency circulation problem caused by carrier asynchrony, and significantly improving the system performance.

[0079] Fig. 9 A flow chart of a carrier synchronization control method for multiple parallel converters provided by another embodiment of the present invention, wherein each converter corresponds to a control unit, each control unit is integrated with a corresponding cumulative counter, one converter is used as a master, and the remaining converters are used as slaves. The method can be applied to, but is not limited to, the master; Fig. 9 As shown, the carrier synchronization control method may include but is not limited to step S7000.

[0080] Step S7000, when a preset low-frequency synchronization signal is generated, the low-frequency synchronization signal is sent to any slave machine, so that any slave machine can capture the rising edge or falling edge of the low-frequency synchronization signal, and each time any slave machine captures the rising edge or falling edge of the low-frequency synchronization signal, it collects the current carrier value and the maximum carrier value of the carrier signal output by the corresponding control unit, and adjusts the carrier count value of the corresponding cumulative counter according to the current carrier value and the maximum carrier value to synchronize the phase of the carrier signal of the slave machine with the carrier signal of the host machine.

[0081] In this step, for the high-frequency circulating current caused by carrier asynchrony, high-frequency synchronization can be achieved by providing a low-frequency synchronization signal input, that is, the converter as the host generates and sends a low-frequency synchronization signal to each converter as a slave. For each slave, each time the rising edge or falling edge of the low-frequency synchronization signal is captured, the carrier count value of the corresponding accumulator counter is adjusted according to the collected current carrier value and the maximum carrier value, so that the phases of each carrier signal are synchronized, avoiding the influence of the phase difference on the high-frequency circulating current, and effectively suppressing the high-frequency circulating current generated by the parallel converter under normal operating conditions. Compared with the relevant existing technology, the use of low-frequency signals as a synchronization mechanism optimizes resource allocation, significantly reduces hardware resource consumption, reduces dependence on high-speed processors and high-precision sensors, and has little impact on pulse width modulation signals, can ensure the normal operation and efficient output of the multi-machine parallel system, improve the high-frequency synchronization accuracy of the system, and has important engineering practical value.

[0082] The carrier synchronization control method provided in the embodiment of the present invention is consistent with the basic principle of the carrier synchronization control method provided in the above-mentioned embodiments. Therefore, the carrier synchronization control method provided in the embodiment of the present invention also has similar embodiments and beneficial technical effects. Since the embodiments and beneficial technical effects of the carrier synchronization control method have been described in detail above, the remaining embodiments and beneficial technical effects will not be repeated here.

[0083] Fig.10 FIG. 2 is a schematic diagram of the structure of an electronic device 2000 provided by an embodiment of the present invention. Fig.10 As shown, the electronic device 2000 includes a memory 2100 and a processor 2200. The number of the memory 2100 and the processor 2200 may be one or more. Fig.10 In the embodiment, a memory 2100 and a processor 2200 are taken as an example; the memory 2100 and the processor 2200 in the device may be connected via a bus or other means. Fig.10 The example of connecting through bus is taken in the following.

[0084] The memory 2100, as a computer-readable storage medium, can be used to store software programs, computer executable programs and modules, such as program instructions / modules corresponding to the carrier synchronization control method for multiple converters in parallel provided by any embodiment of the present invention. The processor 2200 implements the carrier synchronization control method for multiple converters in parallel by running the software programs, instructions and modules stored in the memory 2100.

[0085] The memory 2100 may mainly include a program storage area and a data storage area, wherein the program storage area may store an operating system and an application required for at least one function. In addition, the memory 2100 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device or other non-volatile solid-state storage device. In some instances, the memory 2100 may further include a memory remotely arranged relative to the processor 2200, and these remote memories may be connected to the device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0086] An embodiment of the present invention further provides a computer-readable storage medium storing computer-executable instructions for executing the carrier synchronization control method for multiple parallel converters provided in any embodiment of the present invention.

[0087] An embodiment of the present invention further provides a computer program product, including a computer program or computer instructions, wherein the computer program or computer instructions are stored in a computer-readable storage medium, a processor of a computer device reads the computer program or computer instructions from the computer-readable storage medium, and the processor executes the computer program or computer instructions, so that the computer device executes the carrier synchronization control method for multiple parallel converters provided in any embodiment of the present invention.

[0088] The electronic devices and application scenarios described in the embodiments of the present invention are intended to more clearly illustrate the technical solutions of the embodiments of the present invention, and do not constitute a limitation on the technical solutions provided by the embodiments of the present invention. Those skilled in the art will appreciate that with the evolution of electronic devices and the emergence of new application scenarios, the technical solutions provided by the embodiments of the present invention are equally applicable to similar technical problems.

[0089] Those skilled in the art will appreciate that all or some of the steps in the methods disclosed above, and the functional modules / units in the systems and devices may be implemented as software, firmware, hardware, or a suitable combination thereof.

[0090] In hardware implementation, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed by several physical components in cooperation. Some physical components or all physical components may be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessing unit, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or temporary medium). As known to those of ordinary skill in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disk (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically embodies computer readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0091] The terms "component", "module", "system", etc. used in this specification are used to represent computer-related entities, hardware, firmware, a combination of hardware and software, software, or software in execution. For example, a component can be, but is not limited to, a process running on a processor, a processor, an object, an executable file, an execution thread, a program, or a computer. By way of illustration, both applications running on a computing device and a computing device can be components. One or more components may reside in a process or an execution thread, and a component may be located on a computer or distributed between two or more computers. In addition, these components may be executed from various computer-readable media having various data structures stored thereon. Components may communicate, for example, through local or remote processes based on signals having one or more data packets (e.g., data from two components interacting with another component between a local system, a distributed system, or a network, such as the Internet interacting with other systems through signals).

Claims

1. A carrier synchronization control method for multiple converters in parallel, characterized in that: Each of the converters corresponds to a control unit, each of the control units is integrated with a corresponding cumulative counter, one of the converters is used as a master, and the other converters are used as slaves, and the method is applied to any one of the slaves, including: Receiving a preset low-frequency synchronization signal generated and sent by the host; Capturing the rising edge or the falling edge of the low-frequency synchronization signal; When the rising edge or falling edge of the low-frequency synchronization signal is captured each time, the current carrier value and the maximum carrier value of the corresponding carrier signal output by the control unit are collected; According to the current carrier value and the maximum carrier value, the carrier count value of the corresponding accumulative counter is adjusted so that the phase of the carrier signal of the slave is synchronized with the phase of the carrier signal of the host.

2. The carrier synchronization control method for multiple converters in parallel according to claim 1, characterized in that: The step of adjusting the carrier count value of the corresponding accumulative counter according to the current carrier value and the maximum carrier value includes: Determine a target carrier value according to the maximum carrier value, wherein the target carrier value is half of the maximum carrier value; Determine the magnitude relationship between the current carrier value and the target carrier value to obtain a comparison result; The carrier count value of the corresponding accumulative counter is adjusted according to the comparison result.

3. The carrier synchronization control method for multiple converters in parallel according to claim 2, characterized in that: The step of adjusting the carrier count value of the corresponding accumulative counter according to the comparison result includes: When the current carrier value is greater than or equal to the target carrier value, adjusting the corresponding carrier count value of the accumulative counter to the maximum carrier value; or, When the current carrier value is less than the target carrier value, the corresponding carrier count value of the accumulative counter is adjusted to zero.

4. The carrier synchronization control method for multiple parallel converters according to claim 1, characterized in that: At least one microprocessing unit is correspondingly configured for the control unit of each slave, and the capturing of the rising edge or the falling edge of the low-frequency synchronization signal comprises: Based on the corresponding micro-processing unit, respectively obtaining a first state of the low-frequency synchronization signal at a current moment and a second state of the low-frequency synchronization signal at a next moment; Determine whether the first state and the second state are the same. If different, capture the rising edge or falling edge of the low-frequency synchronization signal between the current moment and the first moment. Otherwise, determine that the rising edge or falling edge of the low-frequency synchronization signal is not generated between the current moment and the first moment.

5. The carrier synchronization control method for multiple converters in parallel according to claim 4, characterized in that: The method further comprises: Each time a rising edge or a falling edge of the low-frequency synchronization signal is captured, a current timestamp of the low-frequency synchronization signal is recorded by the corresponding microprocessing unit; Control the corresponding microprocessing unit to send the current timestamp of the low-frequency synchronization signal to the corresponding control unit.

6. The carrier synchronization control method for multiple converters in parallel according to claim 5, characterized in that: The collecting of the current carrier value and the maximum carrier value of the carrier signal output by the control unit corresponding to the acquisition includes: The current carrier value and the maximum carrier value of the carrier signal corresponding to the current timestamp of the low-frequency synchronization signal are collected by the corresponding control unit.

7. The carrier synchronization control method for multiple converters in parallel according to any one of claims 1 to 6, characterized in that: The frequency of the low-frequency synchronization signal is 25-100 Hz.

8. A carrier synchronization control method for multiple converters in parallel, characterized in that: Each of the converters corresponds to a control unit, each of the control units is integrated with a corresponding cumulative counter, one of the converters is used as a host, and the other converters are used as slaves, and the method is applied to the host, including: When a preset low-frequency synchronization signal is generated, the low-frequency synchronization signal is sent to any one of the slaves, so that any one of the slaves captures the rising edge or the falling edge of the low-frequency synchronization signal, and each time any one of the slaves captures the rising edge or the falling edge of the low-frequency synchronization signal, collects the current carrier value and the maximum carrier value of the carrier signal output by the corresponding control unit, and adjusts the carrier count value of the corresponding cumulative counter according to the current carrier value and the maximum carrier value, so as to synchronize the phase of the carrier signal of the slave with the carrier signal of the host.

9. An electronic device, characterized in that: include: at least one processor; at least one memory for storing at least one program; When at least one of the programs is executed by at least one of the processors, the carrier synchronization control method for parallel connection of multiple converters as claimed in any one of claims 1 to 8 is implemented.

10. A computer-readable storage medium, characterized in that: A program executable by a processor is stored therein, and when the program executable by the processor is executed by the processor, it is used to implement the carrier synchronization control method for multiple parallel converters as described in any one of claims 1 to 8.

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