FPGA-based hardware optimization SVPWM modulation method

Abstract

The invention provides a hardware optimization SVPWM (space vector pulse width modulation) method based on an FPGA (field programmable gate array). On the basis of a traditional SVPWM modulation method, complex items and redundant items in the traditional SVPWM modulation method are analyzed and simplified, and optimization of the SVPWM modulation method is completed by combining the advantages of FPGA sequential logic and combinational logic parallel computing. In the process, a large amount of irrational number operation occurring in a traditional SVPWM modulation method is optimized, the defect of irrational number operation of the FPGA is avoided, the sector judgment process and the vector action time calculation process are simplified, and the method can be more suitable for the characteristics of FPGA parallel calculation. According to the SVPWM method after hardware optimization, the calculation process is simpler, the SVPWM method is more suitable for programmable logic devices with parallel operation characteristics such as an FPGA, considerable optimization is achieved on available logic resources, the calculation efficiency is greatly improved, and the specific flow chart is shown in the attached drawing of the abstract of the specification.

Description

Technical Field

[0001] The invention belongs to the application field of permanent magnet synchronous motor vector control technology, and in particular relates to a hardware optimized SVPWM (space vector pulse width modulation) method based on FPGA (Field-Programmable Gate Array). Background Art

[0002] In the current motor control field, space vector pulse width modulation (SVPWM) technology is widely used in permanent magnet synchronous motor vector control due to its advantages of high bus voltage utilization, low switching loss and small output harmonic components. With the development of multi-axis multi-motor synchronous drive technology, higher requirements are placed on the control delay and synchronization of motor control algorithms. Therefore, in order to further improve the switching frequency and motor speed control accuracy, the parallel, high-speed and scalable characteristics of FPGA provide a new solution.

[0003] The core idea of ​​SVPWM modulation technology is to synthesize the space voltage vector and obtain a circular rotating magnetic field by adjusting the on-off time of the switch tube of the three-phase voltage full-bridge inverter, drive the motor rotor to rotate, and make the permanent magnet synchronous motor obtain better control performance under certain switching frequency conditions. This method actually regards the three-phase voltage inverter and the AC motor as a whole, and generates a three-phase sine wave current waveform with a phase difference of 120° electrical angle and less distortion in the stator coil by adjusting the switch trigger sequence and combination, thereby generating a constant electromagnetic torque. The main advantages of SVPWM modulation technology are: improving the inverter voltage utilization rate; optimizing harmonics to a higher degree; fast dynamic response speed of the motor; reducing the motor torque pulsation; more suitable for digital system implementation, etc. At present, with the development of digital control systems with MCU as the core, SVPWM modulation methods are widely used, and corresponding new schemes are constantly emerging.

[0004] The traditional SVPWM modulation method adopts a sequential operation structure, which requires multiple steps such as coordinate change, sector judgment, non-zero vector and zero vector action time calculation, and finally obtains the three-phase central symmetrical PWM wave duty cycle, and then generates a 6-pulse drive power device by the timer. The entire calculation process is suitable for sequential calculation, but not for parallel operation. If FPGA is used to complete the traditional SVPWM modulation process, it will consume a lot of resources, cause control delay, and fail to give full play to the parallel operation characteristics of FPGA. In view of this, designing a parallel SVPWM modulation method suitable for FPGA is very important in optimizing resource consumption and improving computing efficiency. Summary of the invention

[0005] The purpose of the present invention is to provide an efficient, hardware-optimized SVPWM modulation method based on FPGA, which is suitable for programmable logic devices with parallel computing characteristics such as FPGA, and can optimize hardware resources and improve the computing efficiency of the control algorithm.

[0006] The technical solution of the present invention:

[0007] A hardware optimized SVPWM modulation method based on FPGA includes the following steps:

[0008] S1, in FPGA, Park inverse transformation is used to convert the DC component U in the two-phase rotating coordinate system after PID link adjustment d , U q Converted to U in the two-phase stationary coordinate system ɑ , U β , perform an equivalent transformation on the subsequent dead zone compensation time and add it to U in the two-phase stationary coordinate system α , U β In, get U ′ ɑ , U β ′ , realize dead zone pre-compensation;

[0009] S2, U ′ α , U β ′ Perform Clark inverse transform and reduce irrational number calculations in subsequent steps by reversing the coordinate axes;

[0010] S3, mining the redundant contents in the calculation of each sector in the traditional SVPWM modulation algorithm, combining the sequential logic and combinational logic in FPGA, and proposing a "symmetrical three-sector" judgment method, which simplifies the sector judgment conditions while reducing the calculation time and the space occupied by the intermediate variables in FPGA;

[0011] S4, simplify the calculation steps of solving the action time of each basic voltage vector in the traditional SVPWM modulation algorithm, delete and merge the redundant items in the calculation process, and optimize it by using the characteristics of FPGA parallel computing;

[0012] S5, overmodulate the action time of each basic voltage vector; determine the current bridge arm comparator flip time, if it is a positive number, perform subsequent operations normally, if it is a negative value, discard the time, and reassign the time obtained in the previous calculation cycle;

[0013] S6, after the overmodulation process in step S5, the corresponding sector three-phase bridge arm comparator flip time T is finally obtained. CH1 , T CH2 , TCH3 , compared with the triangular carrier with adjustable frequency generated by FPGA, and after adding the dead time, the six-way switch tube PWM wave with the corresponding switching frequency is obtained.

[0014] Further, in step S1, the dead zone pre-compensation is as shown in formula (1);

[0015]

[0016] Where U α , U β is the voltage vector component in the two-phase stationary coordinate system, ΔU α , ΔU β The pre-compensation values ​​corresponding to different current polarities are converted into components in the two-phase stationary coordinate system.

[0017] Furthermore, the specific formula of step S2 is shown in formula (2);

[0018]

[0019] Among them, U a , U b , U c is the intermediate variable, U ′ α , U β ′ is the space vector voltage U after dead zone pre-compensation s Components in the two-phase stationary α-β coordinate system.

[0020] Further, step S3 is specifically as follows:

[0021] In the traditional SVPWM modulation algorithm, the space voltage vector is divided into 6 sectors. The voltage vector in each sector is synthesized by its two adjacent basic voltage vectors and the zero voltage vector. By analyzing the formation conditions of each basic voltage vector, it can be found that the basic voltage vector U 4 With the basic voltage vector U 3 is a complementary state, that is, the modulus length is consistent and the direction is opposite; similarly, the other four non-zero basic voltage vectors also have this complementarity;

[0022] By analyzing the space voltage vector U s The conditions falling in each sector, combined with the judgment conditions of the traditional SVPWM modulation algorithm, can be found that there are similarities between the first sector and the fourth sector, the second sector and the fifth sector, and the third sector and the sixth sector, so the traditional six-sector judgment method can be combined into a symmetrical three-sector judgment;

[0023] The specific judgment conditions for symmetrical three-sector judgment are as follows:

[0024] This judgment method uses the intermediate variable U a , U b , U c When the signed number is represented in binary, the highest bit is its positive or negative. Combined with the bitwise operation of FPGA, the symmetrical three-sector judgment method is simplified to the intermediate variable U a , U b , U c The XOR combination logic operation of the highest bit reduces the occupation of FPGA resources by the traditional SVPWM algorithm sector judgment and improves the judgment efficiency.

[0025] Further, step S4 is specifically as follows:

[0026] For the first sector, the three-phase bridge arm comparator flip time and the intermediate variable U obtained in step 2 can be obtained by the space vector synthesis principle and the SVPWM seven-segment allocation principle in the first sector. a , U b , U c The relationship between is shown in the following formula (3):

[0027]

[0028] Among them, T CH , T CH2 , T CH3 is the three-phase bridge arm comparator flip time, T S is the switching cycle time;

[0029] After obtaining the action time of each basic voltage vector, it is found that the action time expressions of adjacent voltage vectors in the first sector and the fourth sector in the traditional SVPWM only have positive and negative differences. From the analysis of the above steps, it can be seen that the two pairs of basic voltage vectors synthesized in the first sector and the fourth sector also only have differences in direction. After substituting, the three-bridge arm comparator flip time expression that is exactly the same for the first sector and the fourth sector can be obtained.

[0030] Similarly, the flipping time of the three bridge arm comparators of the second sector and the fifth sector, and the third sector and the sixth sector are all the same, which is consistent with the "symmetrical three-sector judgment method" implemented in step three;

[0031] In addition, by utilizing the characteristics of FPGA parallel computing, the sector judgment operation is completed through combinational logic. At the same time, the timing logic directly calculates and selects the flip time of the three-phase bridge arm comparator. The entire calculation process is addition, subtraction and shift operations, which further shortens the execution cycle of the entire algorithm.

[0032] Further, in step S6, a dead time is added between the opening and closing of the upper and lower bridge arms. The specific method of increasing the dead time is: the upper bridge arm switch time is increased by T S-T D In comparison, T D Represents the dead time, that is, directly adding the dead time to the upper bridge arm pulse to realize the early shutdown operation of the upper bridge arm, while the lower bridge arm switch tube pulse is directly connected to the completion clock cycle T S In comparison, fast dead-zone protection is finally achieved, which is done using combinational logic in the FPGA.

[0033] Further, in step S6, after adding the dead zone protection, the vector voltage compensation method is used to directly calculate the U in the two-phase stationary coordinate system. α , U β Dead zone pre-compensation is completed in .

[0034] The present invention has the following beneficial effects:

[0035] The present invention provides an SVPWM modulation method based on FPGA hardware resource optimization. On the basis of the traditional SVPWM modulation method, the complex items and redundant items in the traditional SVPWM modulation method are analyzed and simplified, and the advantages of FPGA sequential logic and combinational logic parallel calculation are combined to complete the optimization of the SVPWM modulation method. In this process, a large number of irrational number operations appearing in the traditional SVPWM modulation method are optimized to avoid the shortcomings of FPGA in irrational number operations, simplify the sector judgment process and the vector action time calculation process, and can better adapt to the characteristics of FPGA parallel calculation. The calculation process of the SVPWM method after hardware optimization is simpler and more suitable for programmable logic devices with parallel computing characteristics such as FPGA, which greatly optimizes the available logic resources and greatly improves the computing efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 This is a simplified SVPWM algorithm execution flow chart in an embodiment of the present invention;

[0037] Figure 2 is a schematic diagram of symmetrical three-sector division in an embodiment of the present invention;

[0038] Figure 3 is a schematic diagram of dead zone pre-compensation in an embodiment of the present invention;

[0039] Figure 4 It is a schematic diagram of a three-phase voltage source inverter circuit driven by six PWM signals in an embodiment of the present invention. DETAILED DESCRIPTION

[0040] The following is a clear and complete description of the technical solutions in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, other embodiments obtained by ordinary technicians in this field without creative work are all within the scope of protection of the present invention.

[0041] The purpose of the present invention is to provide a hardware optimized SVPWM modulation method based on FPGA, which is efficient and fast, suitable for programmable logic devices with parallel computing characteristics such as FPGA, and can effectively optimize resource consumption and further improve computing efficiency.

[0042] A hardware optimized SVPWM modulation algorithm based on FPGA is proposed. The modulation method mainly utilizes the flexibility of the simultaneous use of sequential logic and combinational logic of programmable logic devices such as FPGA to optimize the repeated and redundant steps in the traditional SVPWM algorithm (such as patent CN200810025527.4), optimize the FPGA resources, and give full play to the characteristics of FPGA parallel computing to optimize the overall calculation process of the SVPWM modulation algorithm, saving the overall calculation time of the control algorithm. The whole optimization process specifically includes the following steps:

[0043] S1, in FPGA, Park inverse transformation is used to convert the DC component U in the two-phase rotating coordinate system after PID link adjustment d , U q Converted to U in the two-phase stationary coordinate system ɑ , U β , due to the design of adding dead zone protection to the upper and lower bridge arms of the three-phase voltage inverter, in order to avoid the current waveform distortion and output torque pulsation of the permanent magnet synchronous motor under light load, the dead zone compensation time is equivalently transformed and added to U in the two-phase stationary coordinate system. ɑ , U β Get U ′ α , U β ′ , to achieve dead zone pre-compensation, as shown in formula (4);

[0044]

[0045] Where U α , U β is the voltage vector component in the two-phase stationary coordinate system, ΔU α , ΔU β The components of the pre-compensation values ​​corresponding to different current polarities converted to the two-phase stationary coordinate system;

[0046] S2, in order to solve the problem that FPGA calculation of irrational numbers requires a lot of resources and time, U ′ α , U β ′ The Clark inverse transformation and the inversion of the coordinate axis can reduce the irrational number calculation in the subsequent steps. From formula (1), it can be seen that the calculation process after the transformation only includes This irrational number is magnified 1024 times to further simplify the calculation process. This operation can be quickly implemented by shifting and optimizes the FPGA's calculation defects for decimals.

[0047] S3, mining the redundant contents in the traditional SVPWM modulation algorithm for each sector calculation, combining the sequential logic and combinational logic in FPGA, simplifying the sector judgment conditions while reducing the calculation time and the space occupied by the intermediate variables in FPGA, as follows:

[0048] In the traditional SVPWM modulation algorithm, the space voltage vector is divided into 6 sectors. The voltage vector in each sector is synthesized by its two adjacent basic voltage vectors and the zero voltage vector. By analyzing the formation conditions of each basic voltage vector (the on-off conditions of the six switches in the three bridge arms), it can be found that the basic voltage vector U 4 (bridge arm state corresponds to 100) and the basic voltage vector U 3 (The bridge arm state corresponds to 011) is a complementary state, that is, the module length is consistent and the direction is opposite. Similarly, the other four non-zero basic voltage vectors also have this complementarity.

[0049] By analyzing the space voltage vector U s The conditions falling in each sector, combined with the judgment conditions of the traditional SVPWM modulation algorithm, can be found that there are similarities between the time of the first sector and the fourth sector, the second sector and the fifth sector, and the third sector and the sixth sector. Therefore, the traditional six-sector judgment method can be combined into a symmetrical three-sector judgment, such as Figure 2 shown.

[0050] The specific judgment conditions for symmetrical three-sector judgment are as follows:

[0051] This judgment method uses the intermediate variable U a , U b , U c When the signed number is represented in binary, the highest bit is its positive or negative. Combined with the bitwise operation of FPGA, the symmetrical three-sector judgment method is simplified to the intermediate variable U a , U b , U cThe XOR combination logic operation of the highest bit, as shown in formula (5), reduces the occupation of FPGA resources by the traditional SVPWM algorithm sector judgment and improves the judgment efficiency.

[0052]

[0053] Among them, the matrix Sector[2] is U a , U b , U c Sector information obtained after XORing the highest bit;

[0054] S4, simplify the calculation steps of solving the action time of each basic voltage vector in the traditional SVPWM modulation algorithm, delete and merge the redundant items in the calculation process, and optimize it by using the characteristics of FPGA parallel computing;

[0055] Taking the first sector as an example, according to the space vector synthesis principle and the SVPWM seven-segment allocation principle, the three-phase bridge arm comparator flip time T in the first sector can be obtained. CH1 , T CH2 , T CH and the intermediate variable U obtained in step 2 a , U b , U c The relationship between is shown in formula (2):

[0056] After obtaining the action time of each basic voltage vector, it is found by comparison that the action time expressions of adjacent voltage vectors in the first sector and the fourth sector in the traditional SVPWM only have positive and negative differences. From the above analysis, it can be seen that the two pairs of basic voltage vectors synthesized from the first sector and the fourth sector also only have differences in direction, and the three-arm comparator flip time expression that is exactly the same for the first sector and the fourth sector can be obtained.

[0057] Similarly, the flipping time of the three bridge arm comparators of the second sector and the fifth sector, and the third sector and the sixth sector are all the same, which is consistent with the "symmetrical three-sector judgment method" implemented in step three.

[0058] In addition, by taking advantage of the parallel computing characteristics of FPGA, the sector judgment operation is completed through combinational logic, and Sector[2] is obtained at the same time, and the three-arm comparator flip time T is performed by sequential logic. CH1 , T CH , T CH3 The entire calculation process consists of addition, subtraction and shift operations, and the comparator flipping time is shortened to one FPGA clock cycle.

[0059] S5, overmodulating the action time of each basic voltage vector;

[0060] Since the output voltage vector is synthesized by each basic voltage vector and the zero vector, and the output voltage vector has an amplitude range, such as Figure 2 As shown, the action time of each basic voltage vector is also limited by amplitude. In the SVPWM modulation method, the maximum undistorted circular rotating voltage vector that the inverter can output is the inscribed circle of the regular hexagon formed by each non-zero basic voltage vector, and its amplitude is When the synthetic voltage vector exceeds the amplitude, overmodulation will occur, causing distortion of the output voltage. Therefore, overmodulation processing is required to pull the voltage vector back to the inscribed circle. Since the modulation method of the present invention directly obtains the three-phase bridge arm switching time by table lookup method, it is impossible to use the non-zero vector action time and in the traditional SVPWM modulation method to judge overmodulation, and it is also impossible to use proportional reduction to achieve overmodulation processing. However, combined with the required three-phase bridge arm comparator flip time expression and the fact that time cannot be negative, it can be concluded that when the flip time result of any phase bridge arm comparator is negative, overmodulation processing is performed. In the present invention, the overmodulation voltage is pulled back to the voltage vector closest to it to solve the problem. The specific implementation method is to judge the current bridge arm comparator flip time. If it is a positive number, the subsequent operation is performed normally. If it is a negative value, the time is discarded and the time obtained in the previous calculation cycle is reassigned.

[0061] S6, after the overmodulation process in step S5, the corresponding sector three-phase bridge arm comparator flip time T is finally obtained. CH1 , T CH2 , T CH3 , compared with the triangular carrier with adjustable frequency generated by FPGA and adding dead time, the six-way switch tube PWM wave with corresponding switching frequency is obtained.

[0062] Since there is a delay in the opening and closing of the switch tube, the lower bridge arm may be opened when the upper bridge arm is not closed, which will cause an instantaneous short circuit of the power supply. Therefore, it is necessary to increase the dead time between the opening and closing of the upper and lower bridge arms. In the present invention, when generating the switch tube PWM wave, it is directly compared with the triangular carrier with different count peaks to increase the dead zone protection. The specific method is: compare the upper bridge arm switch tube time with T S -T D In comparison, the dead time is directly added to the upper bridge arm pulse to realize the early shutdown operation of the upper bridge arm, while the lower bridge arm switch tube pulse is directly connected to the completion clock cycle T S In comparison, fast dead zone protection is finally achieved. This operation is completed in FPGA using combinational logic, without increasing the consumption of additional clocks and resources, and the efficiency of SVPWM modulation will not be reduced due to the addition of dead zone protection. After adding the dead zone, the inverter output current waveform distortion, output torque pulsation, etc. will be caused. Therefore, the present invention adopts the vector voltage compensation method to calculate the U in the two-phase stationary coordinate system. α , Uβ Complete dead zone pre-compensation in step 1.

[0063] With the above-mentioned ideal embodiments of the present invention as inspiration, through the above-mentioned description, those skilled in the art can make various changes and modifications without departing from the technical concept of the present invention. The technical scope of the present invention is not limited to the contents of the specification, and its technical scope must be determined according to the scope of the claims.

Claims

1. A hardware optimized SVPWM modulation method based on FPGA, characterized in that: It includes the following steps: S1, in FPGA, Park inverse transformation is used to convert the DC component U in the two-phase rotating coordinate system after PID link adjustment d , U q Converted to U in the two-phase stationary coordinate system α , U β , perform an equivalent transformation on the subsequent dead zone compensation time and add it to U in the two-phase stationary coordinate system a , U β In, get U ′ α , U β ′ , realize dead zone pre-compensation; S2, U ′ α , U β ′ Perform Clark inverse transform and reduce irrational number calculations in subsequent steps by reversing the coordinate axes; S3, excavating the redundant contents in the calculation of each sector in the traditional SVPWM modulation algorithm, combining the sequential logic and combinational logic in FPGA, and proposing a "symmetrical three-sector" judgment method, which simplifies the sector judgment conditions and reduces the calculation time and the space occupied by the intermediate variables in FPGA; S4, simplify the calculation steps of solving the action time of each basic voltage vector in the traditional SVPWM modulation algorithm, delete and merge the redundant items in the calculation process, and optimize it by using the characteristics of FPGA parallel computing; S5, overmodulate the action time of each basic voltage vector; determine the current bridge arm comparator flip time, if it is a positive number, perform subsequent operations normally, if it is a negative value, discard the time, and reassign the time obtained in the previous calculation cycle; S6, after the overmodulation process in step S5, the corresponding sector three-phase bridge arm comparator flip time T is finally obtained. CH1 , T CH , T CH3 , compared with the triangular carrier with adjustable frequency generated by FPGA, and after adding the dead time, the six-way switch tube PWM wave with the corresponding switching frequency is obtained.

2. The hardware optimized SVPWM modulation method based on FPGA according to claim 1, characterized in that: In step S1, the dead zone pre-compensation is as shown in formula (1); Where U α , U β is the voltage vector component in the two-phase stationary coordinate system, ΔU α , ΔU β The pre-compensation values ​​corresponding to different current polarities are converted into components in the two-phase stationary coordinate system.

3. The hardware optimized SVPWM modulation method based on FPGA according to claim 1, characterized in that: The specific formula of step S2 is shown in formula (2); Among them, U a , U b , U c is the intermediate variable, U ′ α , U β ′ is the space vector voltage U after dead zone pre-compensation s Components in the two-phase stationary α-β coordinate system.

4. The hardware optimized SVPWM modulation method based on FPGA according to claim 1, characterized in that: Step S3 is as follows: In the traditional SVPWM modulation algorithm, the space voltage vector is divided into 6 sectors. The voltage vector in each sector is synthesized by its two adjacent basic voltage vectors and the zero voltage vector. By analyzing the formation conditions of each basic voltage vector, it can be found that the basic voltage vector U4 and the basic voltage vector U3 are complementary, that is, the module length is consistent and the direction is opposite; similarly, the other four non-zero basic voltage vectors also have this complementarity; By analyzing the space voltage vector U s The conditions falling in each sector, combined with the judgment conditions of the traditional SVPWM modulation algorithm, can be found that there are similarities between the first sector and the fourth sector, the second sector and the fifth sector, and the third sector and the sixth sector, so the traditional six-sector judgment method can be combined into a symmetrical three-sector judgment; The specific judgment conditions for symmetrical three-sector judgment are as follows: This judgment method uses the intermediate variable U a , U b , U c When the signed number is represented in binary, the highest bit is its positive or negative. Combined with the bitwise operation of FPGA, the symmetrical three-sector judgment method is simplified to the intermediate variable U a , U b , U c The XOR combination logic operation of the highest bit reduces the occupation of FPGA resources by the traditional SVPWM algorithm sector judgment and improves the judgment efficiency.

5. The hardware optimized SVPWM modulation method based on FPGA according to claim 1, characterized in that: Step S4 is specifically as follows: For the first sector, the three-phase bridge arm comparator flip time and the intermediate variable U obtained in step 2 can be obtained by the space vector synthesis principle and the SVPWM seven-segment allocation principle in the first sector. a , U b , U c The relationship between is shown in the following formula (3): Among them, T CH1 、T CH2 、T CH3 is the three-phase bridge arm comparator flip time, T S is the switching cycle time; After obtaining the action time of each basic voltage vector, it is found that the action time expressions of adjacent voltage vectors in the first sector and the fourth sector in the traditional SVPWM only have positive and negative differences. From the analysis of the above steps, it can be seen that the two pairs of basic voltage vectors synthesized in the first sector and the fourth sector also only have differences in direction. After substituting, the three-bridge arm comparator flip time expression that is exactly the same for the first sector and the fourth sector can be obtained. Similarly, the flipping time of the three bridge arm comparators of the second sector and the fifth sector, and the third sector and the sixth sector are all the same, which is consistent with the "symmetrical three-sector judgment method" implemented in step three; In addition, by utilizing the characteristics of FPGA parallel computing, the sector judgment operation is completed through combinational logic. At the same time, the timing logic directly calculates and selects the flip time of the three-phase bridge arm comparator. The entire calculation process is addition, subtraction and shift operations, which further shortens the execution cycle of the entire algorithm.

6. The hardware optimized SVPWM modulation method based on FPGA according to claim 1, characterized in that: In step S6, a dead time is added between the opening and closing of the upper and lower bridge arms. The specific method of adding the dead time is: the upper bridge arm switch time is compared with T S -T D In comparison, T D Represents the dead time, that is, directly adding the dead time to the upper bridge arm pulse to realize the early shutdown operation of the upper bridge arm, while the lower bridge arm switch tube pulse is directly connected to the completion clock cycle T S In comparison, fast dead-zone protection is finally achieved, which is done using combinational logic in the FPGA.

7. The hardware optimized SVPWM modulation method based on FPGA according to claim 6, characterized in that: In step S6, after adding the dead zone protection, the vector voltage compensation method is used to directly calculate the U in the two-phase stationary coordinate system. α , U β Dead zone pre-compensation is completed in .

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