Operational amplification circuit and electronic equipment

Abstract

The invention provides an operational amplifier circuit and electronic equipment, and the circuit comprises a first-stage operational amplifier module which is used for outputting a target signal; the filtering module is connected with the first-stage operational amplifier module and is used for eliminating a high-frequency offset signal in the target signal; the buffer module is connected with the first-stage operational amplifier module and the filtering module and used for adjusting the voltage margin of the output end of the first-stage operational amplifier module and improving the loop gain of the operational amplifier circuit; and the second-stage operational amplifier module is connected with the first-stage operational amplifier module and the buffer module and is used for compensating the phase of the signal which is output by the first-stage operational amplifier module and is processed by the filtering module. According to the invention, the precision and bandwidth can be improved while the mismatch is reduced.

Description

Technical Field

[0001] The present application relates to the technical field of operational amplifiers, and in particular to an operational amplifier circuit and an electronic device. Background Art

[0002] The operational amplifier (abbreviated as op amp in this article) is a common integrated circuit, which is widely used in analog signal operation, amplification, rectification and filtering, and is an indispensable component of signal processing. In many applications, the operational amplifier is required to have high precision, wide bandwidth and good stability.

[0003] When the op amp is trying to achieve high precision and high bandwidth compatibility, the stability of the op amp will deteriorate. The stability of the op amp is usually improved by reducing the bandwidth of the op amp. However, this can easily affect the performance of the op amp.

[0004] Therefore, it is necessary to provide an improved technical solution to overcome the above technical problems existing in the prior art. Summary of the invention

[0005] The embodiments of the present application provide an operational amplifier circuit and an electronic device, which can reduce mismatch while improving accuracy and bandwidth.

[0006] In a first aspect, an embodiment of the present application provides an operational amplifier circuit, comprising: The first-stage operational amplifier module is used to output the target signal; A filtering module, connected to the first-stage operational amplifier module, for eliminating high-frequency offset signals in the target signal; A buffer module, connected to the first-stage operational amplifier module and the filter module, and used to adjust the voltage margin of the output end of the first-stage operational amplifier module and to improve the loop gain of the operational amplifier circuit; The second-stage operational amplifier module is connected to the first-stage operational amplifier module and the buffer module, and is used to compensate the phase of the signal output by the first-stage operational amplifier module and processed by the filter module.

[0007] In a second aspect, an embodiment of the present application further provides an electronic device, wherein the electronic device comprises the operational amplifier circuit as described in the first aspect.

[0008] An operational amplifier circuit and electronic device provided by an embodiment of the present application include a first-stage operational amplifier module for outputting a target signal; a filtering module connected to the first-stage operational amplifier module for eliminating high-frequency offset signals in the target signal; a buffer module connected to the first-stage operational amplifier module and the filtering module for adjusting the voltage margin at the output end of the first-stage operational amplifier module and improving the loop gain of the operational amplifier circuit; a second-stage operational amplifier module connected to the first-stage operational amplifier module and the buffer module for compensating the phase of the signal output by the first-stage operational amplifier module after being processed by the filtering module. The present application can reduce mismatch and improve accuracy and bandwidth. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0010] Figure 1 Some exemplary schematic diagrams of operational amplifier circuits are shown; Figure 2 Some exemplary circuit schematic diagrams of operational amplifier circuits are shown; Figure 3 Some exemplary compensation principle schematic diagrams are shown. DETAILED DESCRIPTION

[0011] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments provided in the present application, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of this application.

[0012] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present application. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0013] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present application, unless otherwise specified, "plurality" means two or more.

[0014] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0015] “At least one of A, B, and C” has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0016] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0017] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0018] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of variation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0019] It should be noted that in the embodiments of the present application, "connection" can be understood as electrical connection, and the connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be either a direct connection between A and B or an indirect connection between A and B through one or more other electrical components.

[0020] The first pole / first end D of each transistor used in the embodiments of the present application is one of the source and the drain, and the second pole / second end S of each transistor is the other of the source and the drain. Since the source and drain of the transistor can be symmetrical in structure, the source and drain thereof can be structurally indistinguishable, that is, the first pole / first end D and the second pole / second end S of the transistor in the embodiments of the present application can be structurally indistinguishable. Exemplarily, in the case where the transistor is a P-type transistor, the first pole / first end D of the transistor is the source, and the second pole / second end S is the drain; Exemplarily, in the case where the transistor is an N-type transistor, the first pole / first end D of the transistor is the drain, and the second pole / second end S is the source.

[0021] In the circuit structure provided in the embodiments of the present application, the first node, the second node and other nodes do not represent actual existing components, but represent the junction points of related couplings in the circuit diagram, that is, these nodes are nodes formed by the equivalent junction points of related couplings in the circuit diagram.

[0022] With the rapid development of automobile and industrial technology, the requirements for signal processing accuracy and speed of automotive and industrial electronic products are increasing. As the core module in signal processing chips, the bandwidth and accuracy of operational amplifiers determine the performance requirements of the overall system. High bandwidth helps the system process information faster and achieve faster response speed, and high accuracy helps the system accurately sample information and achieve better sensitivity. Therefore, high-bandwidth and high-precision operational amplifiers are of great value in high-performance signal processing chips.

[0023] To this end, the present application provides an operational amplifier circuit and an electronic device, which are described in detail below.

[0024] See also Figure 1 , Figure 1 A schematic diagram of a module of an operational amplifier circuit in an embodiment of the present application is shown. Figure 1 As shown, the operational amplifier circuit includes: The first stage operational amplifier module 10 is used to output the target signal; A filter module 20, connected to the first-stage operational amplifier module 10, for eliminating high-frequency imbalance signals in the target signal; A buffer module 30, connected to the first-stage operational amplifier module 10 and the filter module 20, for adjusting the voltage margin of the output end of the first-stage operational amplifier module 10 and improving the loop gain of the operational amplifier circuit; The second stage operational amplifier module 40 is connected to the first stage operational amplifier module 10 and the buffer module 30 , and is used to compensate the phase of the signal output by the first stage operational amplifier module 10 after being processed by the filter module 20 .

[0025] In some embodiments, the second stage operational amplifier module 40 includes: An operational amplifier input unit, used for receiving a differential input signal, wherein the differential input signal includes a first voltage signal and a second voltage signal, wherein the first voltage signal and the second voltage signal have the same amplitude but opposite phases; The operational amplifier processing unit is connected to the control end of the buffer module 30 and is used to generate a zero point to adjust the phase of the high-frequency signal output by the output end of the filter module 20 .

[0026] In some embodiments, Figure 2 As shown, the operational amplifier input unit includes: A first transistor M17, a second transistor M18, a third transistor M19 and a fourth transistor M20; The operational amplifier processing unit includes a fifth transistor P21, a sixth transistor P22, a seventh transistor P23, an eighth transistor P24, a ninth transistor M21, a tenth transistor M22, a first resistor R5 and a second resistor R6; The control end G of the first transistor M17 is connected to the first voltage signal Vinp, the first end D of the first transistor M17 is connected to the first end D of the fifth transistor P21, and the second end S of the first transistor M17 is connected to the second end S of the second transistor M18; The control terminal G of the second transistor M18 is connected to the second voltage signal Vinn, and the first terminal D of the second transistor M18 is connected to the first terminal D of the sixth transistor P22; The first end D of the third transistor M19 is connected to the second end S of the second transistor M18, the second end S of the third transistor M19 is connected to the first end D of the fourth transistor M20, the second end S of the fourth transistor M20 is connected to the first power supply Vssh5vs, and the second end S of the fourth transistor M20 is also connected to the first output end of the first-stage operational amplifier module 10 (i.e., the second ends of R1 and R2 in the figure); The second end S of the fifth transistor P21 is connected to the second power supply Vdd, the second end S of the fifth transistor P21 is connected to the second end S of the sixth transistor P22, the second end S of the fifth transistor P21 is also connected to the second output end of the first-stage operational amplifier module 10 (i.e., the source of P5 and P6 in the figure), and the voltage of the second power supply Vdd is greater than the voltage of the first power supply Vssh5vs; The control terminal G of the fifth transistor P21 is connected to the control terminal G of the sixth transistor P22; The second end S of the seventh transistor P23 is connected to the first end D of the fifth transistor P21, and the control end G of the seventh transistor P23 is connected to the control end G of the eighth transistor P24; The second end S of the eighth transistor P24 is connected to the first end D of the sixth transistor P22; The first end D of the seventh transistor P23 is connected to the control end G of the fifth transistor P21, and the first end D of the eighth transistor P24 is connected to the control end of the buffer module 30 (ie, the control end G of P20); The first end D of the ninth transistor M21 is connected to the first end D of the seventh transistor P23, the second end S of the ninth transistor M21 is connected to one end of the first resistor R5, and the other end of the first resistor R5 is connected to the second end S of the fourth transistor M20; The first end D of the tenth transistor M22 is connected to the first end D of the eighth transistor P24, the second end S of the tenth transistor M22 is connected to one end of the second resistor R6, and the other end of the second resistor R6 is connected to the second end S of the fourth transistor M20.

[0027] In some embodiments, Figure 2 As shown, the buffer module 30 includes: an eleventh transistor P19, a twelfth transistor M16, a thirteenth transistor M15, a fourteenth transistor P20, a third resistor R3, a fourth resistor RL1 and a fifth resistor RL2; The second end S of the eleventh transistor P19 is connected to the second output end of the first-stage operational amplifier module 10 (i.e., the source of P5 and P6 in the figure), the control end G of the eleventh transistor P19 is connected to the output end of the filter module 20, and the first end D of the eleventh transistor P19 is connected to the first end D of the twelfth transistor M16; The second end S of the twelfth transistor M16 is connected to the first end D of the thirteenth transistor M15, the second end S of the thirteenth transistor is connected to one end of the third resistor R3, and the other end of the third resistor R3 is connected to the first output end of the first-stage operational amplifier module 10 (i.e., the second ends of R1 and R2); One end of the fourth resistor RL1 is connected to the second end S of the fifth transistor P21 and the second end S of the eleventh transistor P19 respectively, and the other end of the fourth resistor RL1 is connected to the second end S of the fourteenth transistor P20; The second end S of the fourteenth transistor P20 outputs the second voltage signal Vinn, the control end G of the fourteenth transistor P20 serves as the control end of the buffer module 30, the control end G of the fourteenth transistor P20 is connected to the first end D of the eleventh transistor P19, the first end D of the fourteenth transistor P20 outputs the third voltage signal Vadcin, and the first end D of the fourteenth transistor P20 is connected to the fifth resistor RL2 and then grounded.

[0028] In some embodiments, Figure 2 As shown, the buffer module 30 further includes: a fifth resistor R4 and a first capacitor C1; One end of the first capacitor C1 is connected to the control end G of the fourteenth transistor P20 , the other end of the first capacitor C1 is connected to one end of the fifth resistor R4 , and the other end of the fifth resistor R4 is connected to the filter module 20 .

[0029] In some embodiments, Figure 2 As shown, the filtering module 20 includes: a fifteenth transistor P15, a sixteenth transistor P16, a seventeenth transistor P17 and an eighteenth transistor P18, a second capacitor C2, a third capacitor C3 and a fourth capacitor C4; One end of the fourth capacitor C4 is connected to the second power supply Vdd, and the other end of the fourth capacitor C4 is connected to the third output end of the first-stage operational amplifier module 10 (i.e., the drain of P14 and M14 in the figure); The second end S of the fifteenth transistor P15 is connected to the other end of the fourth capacitor C4, the first end D of the fifteenth transistor P15 is connected to one end of the second capacitor C2, and the other end of the second capacitor C2 is connected to the second power supply Vdd; The second end S of the sixteenth transistor P16 is connected to the first end D of the fifteenth transistor P15, and the first end D of the sixteenth transistor P16 is connected to the other end of the fifth resistor R4; The second end S of the seventeenth transistor P17 is connected to the other end of the fourth capacitor C4, the first end D of the seventeenth transistor P17 is connected to one end of the third capacitor C3, and the other end of the third capacitor C3 is connected to the second power supply Vdd; The second end S of the eighteenth transistor P18 is connected to the first end D of the seventeenth transistor P17, and the first end D of the eighteenth transistor P18 is connected to the other end of the fifth resistor R4; The first end D of the sixteenth transistor P16 and the first end D of the eighteenth transistor P18 serve as output ends of the filter module 20 .

[0030] In some embodiments, the first stage operational amplifier module 10 includes: A differential transconductance unit, used for accessing a differential input signal; A first chopping switch unit, connected to the differential transconductance unit, for modulating the frequency of the differential input signal to a preset switching frequency; A signal output unit connected to the differential transconductance unit; a second chopping switch unit, connected to the signal output unit, for modulating the offset of the differential input signal to the preset switching frequency, and simultaneously lowering the frequency of the differential input signal after the frequency modulation to obtain the target signal; The mismatch adjustment unit is connected to the signal output unit and the second chopping switch unit, and is used to reduce the mismatch introduced by the first-stage operational amplifier module 10 due to periodic switching.

[0031] In some embodiments, Figure 2 As shown, the signal output unit includes: a nineteenth transistor P5, a twentieth transistor P6, a twenty-first transistor P13, a twenty-second transistor P14, a twenty-third transistor M5, a twenty-fourth transistor M6, a twenty-fifth transistor M13 and a twenty-sixth transistor M14, a sixth resistor R1 and a seventh resistor R2; The second chopping switch unit includes a twenty-seventh transistor P9, a twenty-eighth transistor P10, a twenty-ninth transistor P11, a thirtieth transistor P12, a thirty-first transistor M9, a thirty-second transistor M10, a thirty-third transistor M11 and a thirty-fourth transistor M12; The mismatch adjustment unit includes a thirty-fifth transistor P7, a thirty-sixth transistor P8, a thirty-seventh transistor M7 and a thirty-eighth transistor M8; The second end S of the nineteenth transistor P5 and the second end S of the twentieth transistor P6 serve as the second output end of the first-stage operational amplifier module 10; The control terminal G of the nineteenth transistor P5 is connected to the control terminal G of the twentieth transistor P6; The second end S of the thirty-fifth transistor P7 is connected to the first end D of the nineteenth transistor P5, and the first end D of the nineteenth transistor P5 is also connected to the first output end of the differential transconductance unit (i.e., the drain of M1); The second end S of the thirty-sixth transistor P8 is connected to the first end D of the twentieth transistor P6, and the first end D of the twentieth transistor P6 is also connected to the second output end of the differential transconductance unit (that is, the drain of M2); The control terminal G of the thirty-fifth transistor P7 is connected to the control terminal G of the thirty-sixth transistor P8; The second end S of the twenty-seventh transistor P9 and the second end S of the twenty-eighth transistor P10 are both connected to the first end D of the thirty-fifth transistor P7, and the second end S of the twenty-ninth transistor P11 and the second end S of the thirtieth transistor P12 are both connected to the first end D of the thirty-sixth transistor P8; The first end D of the twenty-seventh transistor P9 and the first end D of the twenty-ninth transistor P11 are both connected to the second end S of the twenty-first transistor P13, and the first end D of the twenty-eighth transistor P10 and the first end D of the thirtieth transistor P12 are both connected to the second end S of the twenty-second transistor P14; The control terminal G of the twenty-first transistor P13 is connected to the control terminal G of the twenty-second transistor P14; The first end D of the twenty-first transistor P13 is connected to the control end G of the nineteenth transistor P5 and the first end D of the twenty-fifth transistor M13; The first end D of the 26th transistor M14 is connected to the first end D of the 22nd transistor P14, and the first end D of the 22nd transistor P14 and the first end D of the 26th transistor M14 serve as the third output end of the first-stage operational amplifier module 10 to be connected to the other end of the fourth capacitor C4; The control terminal G of the twenty-fifth transistor M13 is connected to the control terminal G of the twenty-sixth transistor M14; The second end S of the twenty-fifth transistor M13 is connected to the first end D of the thirty-first transistor M9 and the first end D of the thirty-third transistor M11, and the second end S of the twenty-sixth transistor M14 is connected to the first end D of the thirty-second transistor M10 and the first end D of the thirty-fourth transistor M12; The second end S of the thirty-first transistor M9 and the second end S of the thirty-second transistor M10 are both connected to the first end D of the thirty-seventh transistor M7, and the second end S of the thirty-third transistor M11 and the second end S of the thirty-fourth transistor M12 are both connected to the first end D of the thirty-eighth transistor M8; The control terminal G of the thirty-seventh transistor M7 is connected to the control terminal G of the thirty-eighth transistor M8; The second end S of the thirty-seventh transistor M7 is connected to the first end D of the twenty-third transistor M5, the second end S of the twenty-third transistor M5 is connected to one end of the sixth resistor R1, and the other end of the sixth resistor R1 is connected to the third output end of the differential transconductance unit (i.e., the source of M4); The second end S of the thirty-eighth transistor M8 is connected to the first end D of the twenty-fourth transistor M6, the second end S of the twenty-fourth transistor M6 is connected to one end of the seventh resistor R2, and the other end of the seventh resistor R2 is connected to the third output end of the differential transconductance unit (i.e., the source of M4); The other end of the sixth resistor R1 and the other end of the seventh resistor R2 serve as the second output end of the first-stage operational amplifier module 10 .

[0032] In some embodiments, Figure 2 As shown, the differential transconductance unit includes: a thirty-ninth transistor M1, a fortieth transistor M2, a forty-first transistor M3, and a forty-second transistor M4; The first chopping switch unit includes a forty-third transistor P1, a forty-fourth transistor P2, a forty-fifth transistor P3, and a forty-sixth transistor P4; The first end D of the thirty-ninth transistor M1 is connected to the first end D of the nineteenth transistor P5 as the first output end of the differential transconductance unit, and the first end D of the fortieth transistor M2 is connected to the first end D of the twentieth transistor P6 as the second output end of the differential transconductance unit; The second end S of the thirty-ninth transistor M1 is connected to the second end S of the fortieth transistor M2, the first end D of the forty-first transistor M3 is connected to the second end S of the thirty-ninth transistor M1, the second end S of the forty-first transistor M3 is connected to the first end D of the forty-second transistor M4, and the second end S of the forty-second transistor M4 serves as the third output end of the differential transconductance unit; The first end D of the 43rd transistor P1 and the first end D of the 45th transistor P3 are both connected to the control end G of the 39th transistor M1, and the first end D of the 44th transistor P2 and the first end D of the 46th transistor P4 are both connected to the control end G of the 40th transistor M2; The second end S of the forty-third transistor P1 is connected to the second end S of the forty-fourth transistor P2 and is connected to the first voltage signal Vinp. The second end S of the forty-fifth transistor P3 and the second end S of the forty-sixth transistor P4 are connected to the second voltage signal Vinn output by the second end S of the fourteenth transistor P20.

[0033] like Figure 2As shown, P1~P4, P9~P12 and M9~P12 are added to the second ends S of M1, M2, P13, P14, M13 and M14. When the frequency of the differential input signal connected to the first-stage operational amplifier module 10 is high, the parasitic capacitance between the second end S of the chopper switch (i.e., P1~P4, P9~P12 and M9~M12) and the ground causes the impedance to decrease, and the mismatch of P13, P14, M13 and M14 will contribute to the output end of the first-stage operational amplifier module 10. A small-sized common-gate tube (P7, P8, M7, M8) is added between the common-gate tube (P13-P14, M13-M14) at the output end and the load tube (M5-M6, P5-P6), thereby reducing the mismatch contribution of the common-gate tube (P13-P14, M13-M14) at the output end and achieving higher-precision sampling output. The switch capacitor in the filter module 20 can be equivalent to: The resistor forms a pole with the subsequent capacitor, which will introduce additional phase shift, deteriorate loop stability, and limit loop bandwidth. To achieve high bandwidth, a second-stage operational amplifier module 40 is added to introduce a left zero point, such as Figure 2 As shown, by compensating the phase of the high-frequency signal output by the first-stage operational amplifier module 10 and processed by the filter module 20, the loop bandwidth of the operational amplifier circuit can be improved to achieve high-bandwidth sampling output.

[0034] like Figure 2 As shown, the operational amplifier circuit is composed of four parts: a first-stage operational amplifier module 10 , a filter module 20 , a buffer module 30 and a second-stage operational amplifier module 40 .

[0035] like Figure 2 As shown, the control terminals G of M1 and M2 of the first-stage operational amplifier module 10 add P1~P4, modulate the input differential input signal to the preset switching frequency, insert M9~M12 and P9~P12 between M5-M6, P5-P6 and P13-P14, M13-M14, demodulate the high-frequency differential input signal to a low frequency, and modulate the offset caused by the mismatch between M1 and M2 and the mismatch between M5-M6, P5-P6 to the preset switching frequency. The control terminals of P1~P4, P9~P12 and M9~M12 can be connected to pulse signals, and the preset switching frequency can be the frequency of the pulse signal pre-set according to the demand, so that a pair of transistors connected to the second terminal S can be turned on and off alternately. For example, the pulse signal connected to P3 and P4 can make P4 turn off when P3 is turned on, and P4 turn on when P3 is turned off. P1 and P2 can also be used as a pair of transistors with a common second terminal S. P9 and P10 may also be used as a pair of transistors sharing a second terminal S. P11 and P12 may also be used as a pair of transistors sharing a second terminal S. M9 and M10 may also be used as a pair of transistors sharing a second terminal S. M11 and M12 may also be used as a pair of transistors sharing a second terminal S.

[0036] Due to the periodic switching of M9~M12 and P9~P12 in the first-stage operational amplifier module 10, there is a parasitic capacitance between the second end S of M9~M12 and P9~P12 and the ground, and the impedance between the second end S of P13, P14, M13 and M14 and the ground will be reduced, and the mismatch will contribute to the output end. Therefore, by inserting a small-sized common-gate tube (P7, P8, M7, M8), the parasitic capacitance can be reduced, and the mismatch contribution of the common-gate tube (P13-P14, M13-M14) at the output end can be reduced. Finally, the target signal output by the first-stage operational amplifier module 10 includes a low-frequency signal with a high proportion and a high-frequency signal with a low proportion. There may be a high-frequency mismatch signal in the high-frequency signal. The high-frequency mismatch signal is filtered out by the filter module 20 connected to the post-stage to achieve high-precision signal sampling.

[0037] like Figure 2 As shown, the filter module 20 is composed of switch capacitors C2-C4 and P15-P18. In the current cycle, P16 and P17 are turned on, P15 and P18 are turned off, and the input target signal output by the first-stage operational amplifier module 10 is sampled and transmitted to C3. In the next cycle, P16 and P17 are turned off, P15 and P18 are turned on, and the signal stored on C3 is output to the buffer module 30 connected to the next stage, and the input target signal output by the first-stage operational amplifier module 10 is sampled and transmitted to C2. Through the periodic switch P15-P18, the low-frequency amount of the input target signal output by the first-stage operational amplifier module 10 is transferred to the buffer module 30 connected to the next stage, and the high-frequency component at the integer multiple of the preset switching frequency of the low-frequency signal output by the filter module 20 is effectively filtered out. Combined with the first-stage operational amplifier module 10 connected to the previous stage, the offset caused by operational amplifier mismatch can be effectively filtered out.

[0038] Among them, the output node of the first stage operational amplifier module 10 (i.e. Figure 2 The first end D of P14 and M14 is connected to the input node of the filter module 20 (ie Figure 2 The first stage operational amplifier module 10 needs to meet a certain voltage margin to work normally. By adding the buffer module 30 of the following embodiment, the voltage margin of the output end of the first stage operational amplifier module 10 can be increased. Figure 2As shown, the output end of the buffer module 30 adopts a source follower structure, that is, the first signal input end of the first-stage operational amplifier module 10 is connected to the second end S of P20 to access the second voltage signal Vinn output by the second end S of the fourteenth transistor P20. The output of the buffer module 30 is fed back to the first signal input end of the first-stage operational amplifier module 10 to access the second voltage signal Vinn, forming a unit gain amplifier, and the loop gain can be improved by the buffer module 30. When the sampled differential input signal changes, the common mode point of the target signal output by the first-stage operational amplifier module 10 is determined by P19, which is independent of the second voltage signal Vinn in the differential input signal, thereby ensuring the voltage margin of the output end of the first-stage operational amplifier module 10. The secondary point introduced by the cascaded buffer module 30 is compensated by the Miller capacitor, i.e., the second capacitor C2, and the zero adjustment resistor, i.e., the fifth resistor R4. That is, in the two-stage operational amplifier or buffer module 30, there are usually two low-frequency poles, one of which is the main pole and the other is the secondary point. Miller compensation technology changes the positions of these two poles by increasing the compensation capacitor, thereby improving the stability of the system. Specifically, Miller capacitance can move the main pole toward low frequency, while the secondary point may be pushed to a higher frequency. However, Miller compensation may also introduce a right half plane zero, which has an adverse effect on the stability of the system. In order to eliminate this adverse effect, a zero adjustment resistor, namely the fifth resistor R4, is usually added to move the right half plane zero to the left half plane by adjusting its resistance value, or eliminate it to optimize the zero position, so as to ensure the stability and performance of the entire system.

[0039] like Figure 2 As shown, the input end of the second-stage operational amplifier module 40 (i.e., the control end of M17 and the control end of M18) is connected to the differential input signal, and the output end of the second-stage operational amplifier module 40 (i.e., the first end D of P24) is connected to the control end of the buffer module 30, i.e., the control end G of P20. The differential input signal is amplified by the second-stage operational amplifier module 40 and then superimposed with the target signal output by the first-stage operational amplifier module 10, thereby changing the signal phase of the differential input signal to the node Va. Since the switching capacitor of the filter module 20 will introduce additional phase shift, deteriorating the loop phase margin, the phase shift amount is related to the loop bandwidth GBW (Gain-Bandwidth Product, the gain-bandwidth product represents the product of the gain and bandwidth of the operational amplifier in an open-loop configuration, which determines the frequency range within which the operational amplifier can maintain a stable gain), thereby limiting the bandwidth of the first-stage operational amplifier module 10. Therefore, by adding the second-stage operational amplifier module 40, the compensation principle diagram Figure 3 As shown, a left zero point is generated by the second-stage operational amplifier module 40, the phase shift introduced by the filter module 20 is compensated, the phase of the high-frequency signal output by the output end of the filter module 20 is increased, and the loop phase margin is improved, thereby improving the overall bandwidth of the operational amplifier circuit and realizing a high-bandwidth, high-precision operational amplifier.

[0040] The present application also provides an electronic device, the electronic device comprising: Figures 1 to 3 The operational amplifier circuit described in .

[0041] The above specific implementations further describe the purpose, technical solutions and beneficial effects of the present application in detail. It should be understood that the above is only a specific implementation of the present application and is not limited to the protection scope of the present application. Without departing from the purpose of the basic characteristics of the present application, the present application can be embodied in various forms. Therefore, the implementation forms in the present application are used for explanation rather than limitation. Since the scope of the present application is limited by the claims rather than the specification, and all changes within the scope defined by the claims or within the equivalent scope of the scope defined by the claims should be understood to be included in the claims. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims

1. An operational amplifier circuit, characterized in that: include: The first-stage operational amplifier module is used to output the target signal; A filtering module, connected to the first-stage operational amplifier module, for eliminating high-frequency offset signals in the target signal; A buffer module, connected to the first-stage operational amplifier module and the filter module, and used to adjust the voltage margin of the output end of the first-stage operational amplifier module and to improve the loop gain of the operational amplifier circuit; The second-stage operational amplifier module is connected to the first-stage operational amplifier module and the buffer module, and is used to compensate the phase of the signal output by the first-stage operational amplifier module and processed by the filter module.

2. The operational amplifier circuit according to claim 1, characterized in that: The second-stage operational amplifier module includes: An operational amplifier input unit, used for receiving a differential input signal, wherein the differential input signal includes a first voltage signal and a second voltage signal, wherein the first voltage signal and the second voltage signal have the same amplitude but opposite phases; The operational amplifier processing unit is connected to the control end of the buffer module and is used to generate a zero point to adjust the phase of the high-frequency signal output by the output end of the filter module.

3. The operational amplifier circuit according to claim 2, characterized in that: The operational amplifier input unit comprises: a first transistor, a second transistor, a third transistor, and a fourth transistor; The operational amplifier processing unit includes a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, a first resistor and a second resistor; The control end of the first transistor is connected to the first voltage signal, the first end of the first transistor is connected to the first end of the fifth transistor, and the second end of the first transistor is connected to the second end of the second transistor; The control terminal of the second transistor is connected to the second voltage signal, and the first terminal of the second transistor is connected to the first terminal of the sixth transistor; The first end of the third transistor is connected to the second end of the second transistor, the second end of the third transistor is connected to the first end of the fourth transistor, the second end of the fourth transistor is connected to the first power supply, and the second end of the fourth transistor is also connected to the first output end of the first-stage operational amplifier module; The second end of the fifth transistor is connected to a second power supply, the second end of the fifth transistor is connected to the second end of the sixth transistor, the second end of the fifth transistor is also connected to the second output end of the first-stage operational amplifier module, and the voltage of the second power supply is greater than the voltage of the first power supply; The control terminal of the fifth transistor is connected to the control terminal of the sixth transistor; The second end of the seventh transistor is connected to the first end of the fifth transistor, and the control end of the seventh transistor is connected to the control end of the eighth transistor; The second end of the eighth transistor is connected to the first end of the sixth transistor; The first end of the seventh transistor is connected to the control end of the fifth transistor, and the first end of the eighth transistor is connected to the control end of the buffer module; A first end of the ninth transistor is connected to a first end of the seventh transistor, a second end of the ninth transistor is connected to one end of the first resistor, and the other end of the first resistor is connected to a second end of the fourth transistor; A first end of the tenth transistor is connected to a first end of the eighth transistor, a second end of the tenth transistor is connected to one end of the second resistor, and the other end of the second resistor is connected to a second end of the fourth transistor.

4. The operational amplifier circuit according to claim 3, characterized in that: The buffer module comprises: an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a third resistor, a fourth resistor, and a fifth resistor; The second end of the eleventh transistor is connected to the second output end of the first-stage operational amplifier module, the control end of the eleventh transistor is connected to the output end of the filter module, and the first end of the eleventh transistor is connected to the first end of the twelfth transistor; The second end of the twelfth transistor is connected to the first end of the thirteenth transistor, the second end of the thirteenth transistor is connected to one end of the third resistor, and the other end of the third resistor is connected to the first output end of the first-stage operational amplifier module; One end of the fourth resistor is connected to the second end of the fifth transistor and the second end of the eleventh transistor respectively, and the other end of the fourth resistor is connected to the second end of the fourteenth transistor; The second end of the fourteenth transistor outputs the second voltage signal, the control end of the fourteenth transistor serves as the control end of the buffer module, the control end of the fourteenth transistor is connected to the first end of the eleventh transistor, the first end of the fourteenth transistor outputs the third voltage signal, and the first end of the fourteenth transistor is connected to the fifth resistor and then grounded.

5. The operational amplifier circuit according to claim 4, characterized in that: The buffer module further includes: a fifth resistor and a first capacitor; One end of the first capacitor is connected to the control end of the fourteenth transistor, the other end of the first capacitor is connected to one end of the fifth resistor, and the other end of the fifth resistor is connected to the filtering module.

6. The operational amplifier circuit according to claim 5, characterized in that: The filtering module includes: a fifteenth transistor, a sixteenth transistor, a seventeenth transistor and an eighteenth transistor, a second capacitor, a third capacitor and a fourth capacitor; One end of the fourth capacitor is connected to the fourth voltage signal, and the other end of the fourth capacitor is connected to the third output end of the first-stage operational amplifier module; The second end of the fifteenth transistor is connected to the other end of the fourth capacitor, the first end of the fifteenth transistor is connected to one end of the second capacitor, and the other end of the second capacitor is connected to the fourth voltage signal; The second end of the sixteenth transistor is connected to the first end of the fifteenth transistor, and the first end of the sixteenth transistor is connected to the other end of the fifth resistor; The second end of the seventeenth transistor is connected to the other end of the fourth capacitor, the first end of the seventeenth transistor is connected to one end of the third capacitor, and the other end of the third capacitor is connected to the fourth voltage signal; The second end of the eighteenth transistor is connected to the first end of the seventeenth transistor, and the first end of the eighteenth transistor is connected to the other end of the fifth resistor; The first end of the sixteenth transistor and the first end of the eighteenth transistor serve as output ends of the filtering module.

7. The operational amplifier circuit according to claim 6, characterized in that: The first-stage op amp module includes: A differential transconductance unit, used for accessing a differential input signal; A first chopping switch unit, connected to the differential transconductance unit, for modulating the frequency of the differential input signal to a preset switching frequency; A signal output unit connected to the differential transconductance unit; a second chopping switch unit, connected to the signal output unit, for modulating the offset of the differential input signal to the preset switching frequency, and simultaneously lowering the frequency of the differential input signal after the frequency modulation to obtain the target signal; The mismatch adjustment unit is connected to the signal output unit and the second chopping switch unit, and is used to reduce the mismatch introduced by the periodic switching of the first-stage operational amplifier module.

8. The operational amplifier circuit according to claim 7, characterized in that: The signal output unit includes: a nineteenth transistor, a twentieth transistor, a twenty-first transistor, a twenty-second transistor, a twenty-third transistor, a twenty-fourth transistor, a twenty-fifth transistor and a twenty-sixth transistor, a sixth resistor and a seventh resistor; The second chopping switch unit includes a twenty-seventh transistor, a twenty-eighth transistor, a twenty-ninth transistor, a thirtieth transistor, a thirty-first transistor, a thirty-second transistor, a thirty-third transistor and a thirty-fourth transistor; The mismatch adjustment unit includes a thirty-fifth transistor, a thirty-sixth transistor, a thirty-seventh transistor and a thirty-eighth transistor; The second end of the nineteenth transistor and the second end of the twentieth transistor serve as the second output end of the first-stage operational amplifier module; The control terminal of the nineteenth transistor is connected to the control terminal of the twentieth transistor; The second end of the thirty-fifth transistor is connected to the first end of the nineteenth transistor, and the first end of the nineteenth transistor is also connected to the first output end of the differential transconductance unit; The second end of the thirty-sixth transistor is connected to the first end of the twentieth transistor, and the first end of the twentieth transistor is also connected to the second output end of the differential transconductance unit; The control terminal of the thirty-fifth transistor is connected to the control terminal of the thirty-sixth transistor; The second end of the twenty-seventh transistor and the second end of the twenty-eighth transistor are both connected to the first end of the thirty-fifth transistor, and the second end of the twenty-ninth transistor and the second end of the thirtieth transistor are both connected to the first end of the thirty-sixth transistor; The first end of the twenty-seventh transistor and the first end of the twenty-ninth transistor are both connected to the second end of the twenty-first transistor, and the first end of the twenty-eighth transistor and the first end of the thirtieth transistor are both connected to the second end of the twenty-second transistor; The control terminal of the twenty-first transistor is connected to the control terminal of the twenty-second transistor; The first terminal of the twenty-first transistor is connected to the control terminal of the nineteenth transistor and the first terminal of the twenty-fifth transistor; The first end of the 26th transistor is connected to the first end of the 22nd transistor, and the first end of the 22nd transistor and the first end of the 26th transistor serve as the third output end of the first-stage operational amplifier module to be connected to the other end of the fourth capacitor; The control terminal of the twenty-fifth transistor is connected to the control terminal of the twenty-sixth transistor; The second end of the twenty-fifth transistor is connected to the first end of the thirty-first transistor and the first end of the thirty-third transistor, and the second end of the twenty-sixth transistor is connected to the first end of the thirty-second transistor and the first end of the thirty-fourth transistor; The second end of the thirty-first transistor and the second end of the thirty-second transistor are both connected to the first end of the thirty-seventh transistor, and the second end of the thirty-third transistor and the second end of the thirty-fourth transistor are both connected to the first end of the thirty-eighth transistor; The control terminal of the thirty-seventh transistor is connected to the control terminal of the thirty-eighth transistor; The second end of the thirty-seventh transistor is connected to the first end of the twenty-third transistor, the second end of the twenty-third transistor is connected to one end of the sixth resistor, and the other end of the sixth resistor is connected to the third output end of the differential transconductance unit; The second end of the thirty-eighth transistor is connected to the first end of the twenty-fourth transistor, the second end of the twenty-fourth transistor is connected to one end of the seventh resistor, and the other end of the seventh resistor is connected to the third output end of the differential transconductance unit; The other end of the sixth resistor and the other end of the seventh resistor serve as the second output end of the first-stage operational amplifier module.

9. The operational amplifier circuit according to claim 8, characterized in that: The differential transconductance unit includes: a thirty-ninth transistor, a fortieth transistor, a forty-first transistor, and a forty-second transistor; The first chopping switch unit includes a forty-third transistor, a forty-fourth transistor, a forty-fifth transistor, and a forty-sixth transistor; The first end of the thirty-ninth transistor is connected to the first end of the nineteenth transistor as the first output end of the differential transconductance unit, and the first end of the fortieth transistor is connected to the first end of the twentieth transistor as the second output end of the differential transconductance unit; The second end of the thirty-ninth transistor is connected to the second end of the fortieth transistor, the first end of the forty-first transistor is connected to the second end of the thirty-ninth transistor, the second end of the forty-first transistor is connected to the first end of the forty-second transistor, and the second end of the forty-second transistor serves as the third output end of the differential transconductance unit; The first end of the 43rd transistor and the first end of the 45th transistor are both connected to the control end of the 39th transistor, and the first end of the 44th transistor and the first end of the 46th transistor are both connected to the control end of the 40th transistor; The second end of the forty-third transistor is connected to the second end of the forty-fourth transistor and is connected to the first voltage signal. The second end of the forty-fifth transistor and the second end of the forty-sixth transistor are connected to the second voltage signal output by the first end of the fourteenth transistor.

10. An electronic device, characterized in that: The electronic device comprises the operational amplifier circuit according to any one of claims 1 to 9.

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