Redundant feedback latch multi-level anti-single-particle reinforced trigger of FinFET technology

Abstract

The invention relates to a redundant feedback latch multilevel anti-single-particle reinforced trigger of a FinFET (FinFET) process, which comprises a data input structure, a clock input structure, four clock control structures, a delay structure, a data master latch structure, a data slave latch structure and a data output structure, the trigger latches data for both the data master latch structure and the data slave latch structure by using a redundancy feedback circuit, and delays one path of data by using a delay structure to filter external single-particle transient pulses at a data end; through a redundancy feedback latch structure and a delay unit, the circuit realizes multi-dimensional reinforcement of single-particle unit / multi-bit upset and single-particle transient, and the single-particle radiation reinforcement resistance of the trigger is significantly improved. In addition, a design reinforcing method combining a circuit and a layout is preferably adopted, the number of Fins in unit grid spacing is designed to be the maximum, an interdigital structure is used for devices at sensitive nodes, meanwhile, the sensitive nodes are arranged in an isolated mode, and the single-particle multi-bit upset resisting capacity is further enhanced.

Description

Technical Field

[0001] The present invention relates to a redundant feedback latch multi-level anti-single particle reinforcement trigger of FinFET process, and in particular to a redundant feedback latch circuit, belonging to the technical field of anti-space radiation reinforcement integrated circuits. Background Art

[0002] When particles in space interact with semiconductor materials, they will generate charges, thus affecting the functions of integrated circuits. Single-particle effects will have different effects on the combinational logic units and timing units that constitute FinFET process integrated circuits. Single event upset (SEU) and single event transient (SET) are typical manifestations of single-particle radiation. Single-particle upset occurs in sequential circuits, which means that when high-energy particles bombard sensitive nodes, the radiation-induced charge causes a soft error in which the data stored in the integrated circuit is flipped. For the nano-FinFET process, its small-scale three-dimensional structure reduces the critical charge for flipping and enhances the charge sharing effect, resulting in a more serious problem of single-particle multi-bit flipping; single-particle transients appear in combinational logic units, which means that the ionized charge induced by particles entering the semiconductor moves in a directional manner under the action of the electric field and concentration gradient, causing transient pulses in the logic potential. Single-particle radiation seriously affects the reliability of FinFET process integrated circuits in radiation environments, threatening the normal operation of electronic systems.

[0003] The trigger is the basic unit of the integrated circuit, and its own radiation resistance is very critical. With the continuous advancement of technology, the performance of integrated circuits has also improved. In order to deal with the problem that the short channel effect has become more serious due to the reduction in feature size, the FinFET (Fin Field-Effect Transistor) structure has been widely used. The FinFET process adds an additional protrusion on the insulating substrate based on the planar process, and its channel is surrounded by a gate, which expands the device from a two-dimensional to a three-dimensional structure, making the single-particle radiation effect mechanism of the FinFET process different from that of the planar process. Traditional single-particle reinforcement design methods, such as dual interlocked storage cells (DICE) and triple-mode redundant structures, will sacrifice a large layout area and power consumption, thereby offsetting the advantages of high integration and low power consumption of the FinFET process, and are not suitable for the single-particle radiation reinforcement design of FinFET process integrated circuits. Summary of the invention

[0004] The technical problem solved by the present invention is: to overcome the deficiencies of the prior art, to provide a redundant feedback latch multi-level single particle reinforced trigger of FinFET process, to improve the single particle radiation reinforced capability of the trigger, and to strengthen it through circuit and layout design, which is easy to implement.

[0005] The technical solution of the present invention is:

[0006] The present invention proposes a redundant feedback latch multi-level single-particle radiation-resistant reinforcement trigger of FinFET process, including a data input structure formed by a first inverter circuit 101; a clock input structure formed by a third inverter circuit 110; a clock control structure formed by clock control structures 102, 104, 106, and 107; a delay structure formed by a cascade inverter structure 103; a data master latch structure formed by a first redundant feedback latch structure 105; a data slave latch structure formed by a second redundant feedback latch structure 108; and a data output structure formed by a second inverter circuit 109. The trigger uses redundant feedback circuits to latch data for both the data master latch structure and the data slave latch structure, and uses a delay structure to filter out external single-particle transient pulses at the data end, and at the same time performs layout reinforcement, designs the Fin within the unit gate spacing to the maximum number, performs a large drive design of the interdigital structure for the device at the sensitive node, and performs a cross-isolation layout for the sensitive node pair, thereby realizing multi-level single-particle radiation-resistant reinforcement.

[0007] In the redundant feedback latch multi-level anti-single-particle reinforcement trigger of the above-mentioned FinFET process, the data input structure is composed of the first inverter circuit 101, and the first inverter circuit 101 is used to invert the input signal Input of the trigger, and its input terminal In is connected to the trigger input signal Input, and its output signal Out is connected to the input terminal In of the first clock control structure 102 and the input terminal In of the cascade inverter structure 103.

[0008] In the redundant feedback latch multi-level anti-single-particle reinforcement trigger of the FinFET process, a clock input structure is formed by the third inverter circuit 110. The third inverter circuit 110 is used to invert the clock signal CP, and its input terminal In is connected to the clock signal CP, and its output terminal CPN is connected to the input terminals CPN of the first clock control structure 102, the second clock control structure 104, the third clock control structure 106, the fourth clock control structure 107, the first redundant feedback latch structure 105, and the second redundant feedback latch structure 108.

[0009] In the redundant feedback latch multi-level anti-single-particle reinforcement trigger of the FinFET process, the clock control structure is composed of clock control structures 102, 104, 106, and 107. The input terminal In of the first clock control structure 102 is connected to the output terminal Out of the first inverter circuit 101 and the input terminal In of the cascade inverter structure 103 at the same time, the input terminal CP of the first clock control structure 102 is connected to the clock signal CP, the input terminal CPN is connected to the output terminal CPN of the third inverter circuit 110, and the output terminal Out of the first clock control structure 102 is connected to the input terminal In1 of the first redundant feedback latch structure 105; the input terminal In of the second clock control structure 104 is connected to the output terminal Out of the cascade inverter structure 103, the input terminal CP of the second clock control structure 104 is connected to the clock signal CP, the input terminal CPN is connected to the output terminal CPN of the third inverter circuit 110, and the output terminal Out of the second clock control structure 104 is connected to the input terminal In2 of the first redundant feedback latch structure 105. The input terminal In2 of the third clock control structure 106 is connected to the output terminal Out1 of the first redundant feedback latch structure 105, the input terminal CP of the third clock control structure 106 is connected to the clock signal CP, the input terminal CPN is connected to the output terminal CPN of the third inverter circuit 110, and the output terminal Out of the third clock control structure 106 is connected to the input terminal In1 of the second redundant feedback latch structure 108; the input terminal In of the fourth clock control structure 107 is connected to the output terminal Out2 of the first redundant feedback latch structure 105, the input terminal CP of the fourth clock control structure 107 is connected to the clock signal CP, the input terminal CPN is connected to the output terminal CPN of the third inverter circuit 110, and the output terminal Out of the fourth clock control structure 107 is connected to the input terminal In2 of the second redundant feedback latch structure 108.

[0010] In the redundant feedback latch multi-level anti-single-event reinforcement trigger of the FinFET process, a delay structure is formed by a cascade inverter structure 103. The cascade inverter structure 103 is used to delay the transmission of the data signal, and its input terminal In is connected to the output terminal Out of the first inverter 101, and its output signal Out is connected to the input terminal In of the second clock control structure 104.

[0011] In the redundant feedback latch multi-level anti-single-particle reinforcement trigger of the FinFET process, the data master latch structure is composed of the first redundant feedback latch structure 105. The input terminal In1 of the first redundant feedback latch structure 105 is connected to the output terminal Out of the first clock control structure 102, the input terminal In2 of the first redundant feedback latch structure 105 is connected to the output terminal Out of the second clock control structure 104, the input terminal CP of the first redundant feedback latch structure 105 is connected to the clock signal CP, the input terminal CPN of the first redundant feedback latch structure 105 is connected to the output terminal CPN of the third inverter circuit 110, the output terminal Out1 of the first redundant feedback latch structure 105 is connected to the input terminal In of the third clock control structure 106, and the output terminal Out2 of the first redundant feedback latch structure 105 is connected to the input terminal In of the fourth clock control structure 107.

[0012] In the redundant feedback latch multi-level anti-single-particle reinforcement trigger of the FinFET process, the data slave latch structure is composed of the second redundant feedback latch structure 108. The input terminal In1 of the second redundant feedback latch structure 108 is connected to the output terminal Out of the third clock control structure 106, the input terminal In2 of the second redundant feedback latch structure 108 is connected to the output terminal Out of the fourth clock control structure 107, the input terminal CP of the second redundant feedback latch structure 108 is connected to the clock signal CP, the input terminal CPN of the second redundant feedback latch structure 108 is connected to the output terminal CPN of the third inverter circuit 110, and the output terminal Out1 of the second redundant feedback latch structure 108 is connected to the input terminal In of the second inverter circuit 109.

[0013] In the redundant feedback latch multi-level anti-single-event reinforcement trigger of the FinFET process, the data output structure is formed by the second inverter circuit 109. The input terminal In of the second inverter circuit 109 is connected to the output terminal Out1 of the second redundant feedback latch structure 108, and the output terminal Out of the second inverter circuit 109 serves as the output terminal Output of the trigger circuit.

[0014] Preferably, the first redundant feedback latch structure 105 and the second redundant feedback latch structure 108 achieve immunity to single-particle unit flips in the storage structure through the redundant feedback circuit structure, and have the ability to suppress single-particle multi-bit flips, thereby realizing anti-single-particle flip reinforcement of the FinFET process trigger.

[0015] Preferably, the clock control structures 102, 104, the cascade inverter structure 103, and the first redundant feedback latch structure 105 constitute a single-particle transient pulse filtering structure, which can filter out external single-particle transient pulses at the data signal end, as well as single-particle transient pulses occurring in the first inverter circuit 101, the clock control structure 102, 104, and the cascade inverter structure 103 inside the trigger, thereby realizing anti-single-particle transient reinforcement of the FinFET process trigger.

[0016] Preferably, in the layout design, the number of Fins within a unit spacing is designed to be the maximum, the devices at the sensitive nodes are designed to be a forked-finger structure, and the sensitive node pairs are designed to be a cross-isolation layout, so as to achieve single-particle radiation reinforcement of the FinFET process trigger under low-overhead conditions.

[0017] Compared with the prior art, the embodiments of the present invention have at least one of the following beneficial effects:

[0018] (1) The redundant feedback latch multi-level single-particle hardening trigger of the FinFET process proposed in the embodiment of the present invention includes a data input structure, a clock input structure, four clock control structures, a delay structure, a data master latch structure, a data slave latch structure and a data output structure. The trigger uses a redundant feedback circuit to latch data for both the data master latch structure and the data slave latch structure, and combines the delay structure to delay one channel of data to filter out external single-particle transient pulses at the data end. The present invention realizes multi-dimensional reinforcement of the circuit against single-particle unit / multi-bit flips and single-particle transients through redundant feedback latch structures and delay units, thereby significantly improving the single-particle radiation hardening capability of the trigger.

[0019] (2) The redundant feedback latch multi-level anti-single-particle reinforcement trigger of the FinFET process proposed in the embodiment of the present invention is designed to address the problem that single-particle incident FinFET process easily induces simultaneous flipping of multiple nodes in circuit reinforcement. A redundant feedback latch structure is designed to achieve immunity to single-particle unit flipping and suppression of multi-bit flipping, and a delay unit is introduced to filter out external single-particle transient pulses, thereby achieving multi-level anti-single-particle flipping reinforcement and anti-single-particle transient reinforcement.

[0020] (3) In the embodiment of the present invention, a design reinforcement method combining circuit and layout is preferably used. In the layout reinforcement, the number of Fins within the unit gate spacing is designed to be the maximum, and a finger structure is used for the devices at the sensitive nodes to enhance the driving current. At the same time, the sensitive node pairs are isolated and laid out, that is, the number of Fins is increased and the sensitive node pairs are isolated without additional area overhead. The finger structure is not used globally, the reinforcement cost is small, and the ability to resist single-particle multi-bit flips is further enhanced. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1is a schematic diagram of a circuit structure of an embodiment of the present invention;

[0022] Figure 2 is a structural diagram of a redundant feedback latch circuit in a circuit structure of an embodiment of the present invention;

[0023] Figure 3 is a structural diagram of a large drive C unit circuit in a circuit structure of an embodiment of the present invention;

[0024] Figure 4 It is a structural diagram of a large drive clock controlled dual-input inverter circuit in the circuit structure of an embodiment of the present invention;

[0025] Figure 5 A structural diagram of a large driver device with an interdigital structure in a circuit structure of an embodiment of the present invention;

[0026] Figure 6 is a structural diagram of an inverter circuit in a circuit structure of an embodiment of the present invention;

[0027] Figure 7 is a structural diagram of a clock control circuit in a circuit structure of an embodiment of the present invention;

[0028] Figure 8 is a structural diagram of a cascade inverter circuit in a circuit structure of an embodiment of the present invention;

[0029] Fig. 9 Schematic diagram of the three-dimensional structure of FinFET device;

[0030] Fig.10 A schematic diagram of increasing the number of Fins and the interdigital structure in the layout reinforcement design of an embodiment of the present invention;

[0031] Fig.11 A schematic diagram of the sensitive node isolation layout in the layout reinforcement design according to an embodiment of the present invention. DETAILED DESCRIPTION

[0032] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments:

[0033] like Figure 1 As shown, an embodiment of the present invention provides a redundant feedback latch multi-level anti-single-particle reinforcement trigger of a FinFET process, including a data input structure 101, a clock input structure 110, a first clock control structure 102, a second clock control structure 104, a third clock control structure 106, a fourth clock control structure 107, a delay structure 103, a data master latch structure 105, a data slave latch structure 108, a data output structure 109 and a clock input structure 110.

[0034] The data input structure 101 transmits external input data to the first clock control structure 102 and the delay structure 103;

[0035] The first clock control structure 102 transmits the data received from the data input structure 101 to the first input terminal of the data master latch structure 105 when the clock is at a low level;

[0036] The delay structure 103 transmits the data received from the data input structure 101 to the second clock control structure 104 after delay;

[0037] The second clock control structure 104 transmits the data received from the delay structure 103 to the second input end of the data master latch structure 105 when the clock is at a low level;

[0038] The data master latch structure 105 transmits the two-way data received from the first clock control structure 102 and the second clock control structure 104 to the third clock control structure 106 and the fourth clock control structure 107 when the clock is at a low level; and latches the two-way data received from the first clock control structure 102 and the second clock control structure 104 when the clock is at a high level;

[0039] The third clock control structure 106 transmits the data received from the data master latch structure 105 to the first input terminal of the data slave latch structure 108 when the clock is at a high level;

[0040] The fourth clock control structure 107 transmits the data received from the data master latch structure 105 to the second input terminal of the data slave latch structure 108 when the clock is at a high level;

[0041] The data slave latch structure 108 transmits the two-way data received from the third clock control structure 106 and the fourth clock control structure 107 to the data output structure 109 when the clock is at a high level; and latches the two-way data received from the third clock control structure 106 and the fourth clock control structure 107 when the clock is at a low level;

[0042] The data output structure 109 outputs the data received from the data latch structure 108 to the outside;

[0043] The clock input structure 110 inverts the external clock signal and transmits it to the input terminals CPN of the first clock control structure 102, the second clock control structure 104, the data master latch structure 105, the third clock control structure 106, the fourth clock control structure 107, and the data slave latch structure 108.

[0044] like Figure 6As shown, the first inverter circuit 101 constitutes a data input structure 101, and the first inverter circuit 101 includes a PMOS transistor 601 and an NMOS transistor 602, wherein the gates of the PMOS transistor 601 and the NMOS transistor 602 are connected together as the input terminal In of the first inverter circuit 101, the source of the PMOS transistor 601 is connected to the power supply VDD, the drain is connected to the drain of the NMOS transistor 602 and serves as the output terminal Out of the first inverter circuit 101, and the source of the NMOS transistor 602 is connected to the power supply ground VSS. The input terminal In of the first inverter circuit 101 is connected to the input signal Input of the trigger circuit, and the output terminal Out is connected to the input terminal In of the first clock control structure 102 and the input terminal In of the cascade inverter structure 103 at the same time.

[0045] The second inverter circuit 109 constitutes a data output structure 109, and the second inverter circuit 109 includes a PMOS transistor 603 and an NMOS transistor 604; wherein the gates of the PMOS transistor 603 and the NMOS transistor 604 are connected together as the input terminal In of the second inverter circuit 109, the source of the PMOS transistor 603 is connected to the power supply VDD, the drain is connected to the drain of the NMOS transistor 604 and serves as the output terminal Out of the second inverter circuit 109, and the source of the NMOS transistor 604 is connected to the power supply ground VSS. The input terminal In of the second inverter circuit 109 is connected to the output terminal Out1 of the second redundant feedback latch structure 108, and the output terminal Out serves as the output signal Output of the trigger.

[0046] The third inverter circuit 110 constitutes a clock input structure 110, and the third inverter circuit 110 includes a PMOS transistor 605 and an NMOS transistor 606, wherein the gates of the PMOS transistor 605 and the NMOS transistor 606 are connected together as the input terminal In of the third inverter circuit 110, the source of the PMOS transistor 605 is connected to the power supply VDD, the drain is connected to the drain of the NMOS transistor 606 and serves as the output terminal Out of the third inverter circuit 110, and the source of the NMOS transistor 606 is connected to the power ground VSS. The input terminal In of the third inverter circuit 110 is connected to the clock signal CP, and the output terminal CPN is simultaneously connected to the input terminals CPN of the clock control structures 102, 104, 106, 107 and the input terminals CPN of the redundant feedback latch structures 105, 108.

[0047] like Figure 7As shown, the first clock control structure 102 includes PMOS transistors 701, 702, NMOS transistors 703, 704; the gates of the PMOS transistors 701 and NMOS transistors 704 of the first clock control structure 102 are connected together as the input terminal In of the first clock control structure 102, the source of the PMOS transistor 701 is connected to the power supply VDD, and the drain is connected to the source of the PMOS transistor 702, the drain of the PMOS transistor 702 is connected to the drain of the NMOS transistor 703 and serves as the output terminal Out of the first clock control structure 102, the source of the NMOS transistor 703 is connected to the drain of the NMOS transistor 704, and the source of the NMOS transistor 704 is connected to the power ground VSS. The gate of the PMOS transistor 702 in the first clock control structure 102 serves as the input terminal CP of the first clock control structure 102 and receives the clock signal CP, and the gate of the NMOS transistor 703 in the first clock control structure 102 serves as the input terminal CPN of the first clock control structure 102 and receives the output terminal CPN of the third inverter circuit 110. An input terminal In of the first clock control structure 102 is connected to an output terminal Out of the first inverter circuit 101 and an input terminal In of the cascade inverter structure 103 . The output terminal Out of the first clock control structure 102 is connected to an input terminal In1 of the first redundant feedback latch structure 105 .

[0048] The second clock control structure 104 includes PMOS transistors 705, 706, NMOS transistors 707, 708; the gates of the PMOS transistors 705 and the NMOS transistors 708 in the second clock control structure 104 are connected together as the input terminal In of the second clock control structure 104, the source of the PMOS transistor 705 is connected to the power supply VDD, the drain is connected to the source of the PMOS transistor 706, the drain of the PMOS transistor 706 is connected to the drain of the NMOS transistor 707 and serves as the output terminal Out of the second clock control structure 104, the source of the NMOS transistor 707 is connected to the drain of the NMOS transistor 708, and the source of the NMOS transistor 708 is connected to the power supply ground VSS. The gate of the PMOS transistor 706 in the second clock control structure 104 serves as the input terminal CP of the second clock control structure 104 and receives the clock signal CP, and the gate of the NMOS transistor 707 in the second clock control structure 104 serves as the input terminal CPN of the second clock control structure 104 and receives the output terminal CPN of the third inverter circuit 110. An input terminal In of the second clock control structure 104 is connected to an output terminal Out of the cascade inverter structure 103 , and an output terminal Out of the second clock control structure 104 is connected to an input terminal In2 of the first redundant feedback latch structure 105 .

[0049] The third clock control structure 106 includes PMOS transistors 709, 710, NMOS transistors 711, 712; the gates of the PMOS transistors 709 and the NMOS transistors 712 in the third clock control structure 106 are connected together as the input terminal In of the third clock control structure 106, the source of the PMOS transistor 709 is connected to the power supply VDD, the drain is connected to the source of the PMOS transistor 710, the drain of the PMOS transistor 710 is connected to the drain of the NMOS transistor 711 and serves as the output terminal Out of the third clock control structure 106, the source of the NMOS transistor 711 is connected to the drain of the NMOS transistor 712, and the source of the NMOS transistor 712 is connected to the power supply ground VSS. The gate of the PMOS transistor 710 in the third clock control structure 106 serves as the input terminal CPN of the third clock control structure 106, connected to the output terminal CPN of the third inverter circuit 110, and the gate of the NMOS transistor 711 in the third clock control structure 106 serves as the input terminal CP of the third clock control structure 106, connected to the clock signal CP. An input terminal In of the third clock control structure 106 is connected to an output terminal Out1 of the first redundant feedback latch structure 105 , and an output terminal Out of the third clock control structure 106 is connected to an input terminal In1 of the second redundant feedback latch structure 108 .

[0050] The fourth clock control structure 107 includes PMOS transistors 713, 714, NMOS transistors 715, 716; the gates of the PMOS transistors 713 and the NMOS transistors 716 in the fourth clock control structure 107 are connected together as the input terminal In of the fourth clock control structure 107, the source of the PMOS transistor 713 is connected to the power supply VDD, the drain is connected to the source of the PMOS transistor 714, the drain of the PMOS transistor 714 is connected to the drain of the NMOS transistor 715 and serves as the output terminal Out of the fourth clock control structure 107, the source of the NMOS transistor 715 is connected to the drain of the NMOS transistor 716, and the source of the NMOS transistor 716 is connected to the power supply ground VSS. The gate of the PMOS transistor 714 in the fourth clock control structure 107 serves as the input terminal CPN of the fourth clock control structure 107 and is connected to the output terminal CPN of the third inverter circuit 110, and the gate of the NMOS transistor 715 in the fourth clock control structure 107 serves as the input terminal CP of the fourth clock control structure 107 and is connected to the clock signal CP. An input terminal In of the fourth clock control structure 107 is connected to an output terminal Out2 of the first redundant feedback latch structure 105 , and an output terminal Out of the fourth clock control structure 107 is connected to an input terminal In2 of the second redundant feedback latch structure 108 .

[0051] like Figure 2As shown, the first redundant feedback latch structure 105 constitutes a data master latch structure 105; the first redundant feedback latch structure 105 includes a first large drive C unit structure 201, a second large drive C unit structure 203, a first large drive clock controlled dual-input inverter 202, and a second large drive clock controlled dual-input inverter 204; wherein the output terminal Out of the first large drive C unit structure 201 is simultaneously connected to the input terminal In1 of the first large drive clock controlled dual-input inverter 202 and the input terminal In2 of the second large drive clock controlled dual-input inverter 204, and serves as the output terminal Out1 of the first redundant feedback latch structure 105; the output terminal Out of the second large drive C unit structure 203 is simultaneously connected to the input terminal In1 of the first large drive clock controlled dual-input inverter 202 and the input terminal In2 of the second large drive clock controlled dual-input inverter 204 The input terminal In2 of the dual-input inverter 202 and the input terminal In1 of the second large driving clock controlling the dual-input inverter 204 are connected to each other, and serve as the output terminal Out2 of the first redundant feedback latch structure 105; the output terminal Out of the first large driving clock controlling the dual-input inverter 202 is connected to the input terminal In2 of the first large driving C unit structure 201 and the second large driving C unit structure 203 at the same time, and serve as the input terminal In2 of the first redundant feedback latch structure 105; the output terminal Out of the second large driving clock controlling the dual-input inverter 204 is connected to the input terminal In1 of the first large driving C unit structure 201 and the second large driving C unit structure 203 at the same time, and serve as the input terminal In1 of the first redundant feedback latch structure 105. The input terminals CP of the first large driving clock controlled dual input inverter 202 and the second large driving clock controlled dual input inverter 204 are used as the input terminals CP of the first redundant feedback latch structure 105, and are connected to the clock signal CP; the input terminals CPN of the first large driving clock controlled dual input inverter 202 and the second large driving clock controlled dual input inverter 204 are used as the input terminals CPN of the first redundant feedback latch structure 105, and are connected to the output terminals CPN of the third inverter circuit 110. The input terminal In1 of the first redundant feedback latch structure 105 is connected to the output terminal Out of the first clock control structure 102, the input terminal In2 of the first redundant feedback latch structure 105 is connected to the output terminal Out of the second clock control structure 104, the output terminal Out1 of the first redundant feedback latch structure 105 is connected to the input terminal In of the third clock control structure 106, and the output terminal Out2 of the first redundant feedback latch structure 105 is connected to the input terminal In of the fourth clock control structure 107.

[0052] The second redundant feedback latch structure 108 constitutes a data slave latch structure 108; the second redundant feedback latch structure 108 includes a third large drive C unit structure 205, a fourth large drive C unit structure 207, a third large drive clock controlled dual-input inverter 206, and a fourth large drive clock controlled dual-input inverter 208; wherein the output terminal Out of the third large drive C unit structure 205 is simultaneously connected to the input terminal In1 of the third large drive clock controlled dual-input inverter 206 and the input terminal In2 of the fourth large drive clock controlled dual-input inverter 208, and serves as the output terminal Out1 of the second redundant feedback latch structure 108; the output terminal Out of the fourth large drive C unit structure 207 is simultaneously connected to the input terminal In1 of the third large drive clock controlled dual-input inverter 206 and the input terminal In2 of the fourth large drive clock controlled dual-input inverter 208 The input terminal In2 of the dual-input inverter 206 and the input terminal In1 of the fourth largest driving clock controlling the dual-input inverter 208 are used as the output terminal Out2 of the second redundant feedback latch structure 108; the output terminal Out of the third largest driving clock controlling the dual-input inverter 206 is simultaneously connected to the input terminal In2 of the third largest driving C unit structure 205 and the fourth largest driving C unit structure 207, and is used as the input terminal In2 of the second redundant feedback latch structure 108; the output terminal Out of the fourth largest driving clock controlling the dual-input inverter 208 is simultaneously connected to the input terminal In1 of the third largest driving C unit structure 205 and the fourth largest driving C unit structure 207, and is used as the input terminal In1 of the second redundant feedback latch structure 108. The input terminal CP of the third large driving clock controlled dual-input inverter 206 and the fourth large driving clock controlled dual-input inverter 208 is used as the input terminal CP of the second redundant feedback latch structure 108, and is connected to the clock signal CP; the input terminal CPN of the third large driving clock controlled dual-input inverter 206 and the fourth large driving clock controlled dual-input inverter 208 is used as the input terminal CPN of the second redundant feedback latch structure 108, and is connected to the output terminal CPN of the third inverter circuit 110. The input terminal In1 of the second redundant feedback latch structure 108 is connected to the output terminal Out of the third clock control structure 106, the input terminal In2 of the second redundant feedback latch structure 108 is connected to the output terminal Out of the fourth clock control structure 107, and the output terminal Out1 of the second redundant feedback latch structure 108 is connected to the input terminal In of the second inverter circuit 109.

[0053] like Figure 3As shown, the first large driving C unit structure 201 includes a first interdigital structure large driving device 301, a PMOS transistor 302, an NMOS transistor 303 and a second interdigital structure large driving device 304. The gates of the first interdigital structure large driving device 301 and the second interdigital structure large driving device 304 are connected together as the input terminal In1 of the first large driving C unit structure 201, and the gates of the PMOS transistor 302 and the NMOS transistor 303 are connected together as the input terminal In2 of the first large driving C unit structure 201. The source of the first interdigital structure large driving device 301 is connected to the power supply VDD, and the drain is connected to the source of the PMOS transistor 302. The drain of the PMOS transistor 302 is connected to the drain of the NMOS transistor 303 and serves as the output terminal Out of the first large driving C unit structure 201. The source of the NMOS transistor 303 is connected to the drain of the second interdigital structure large driving device 304, and the source of the second interdigital structure large driving device 304 is connected to the power ground VSS. The input terminal In1 of the first large driving C unit structure 201 is simultaneously connected to the input terminal In1 of the second large driving C unit structure 203, the output terminal Out of the second large driving clock-controlled dual-input inverter 204, and the output terminal Out of the first clock control structure 102; the input terminal In2 of the first large driving C unit structure 201 is simultaneously connected to the input terminal In2 of the second large driving C unit structure 203, the output terminal Out of the first large driving clock-controlled dual-input inverter 202, and the output terminal Out of the second clock control structure 104; the output terminal Out of the first large driving C unit structure 201 is simultaneously connected to the input terminal In1 of the first large driving clock-controlled dual-input inverter 202, the input terminal In2 of the second large driving clock-controlled dual-input inverter 204, and the input terminal In of the third clock control structure 106.

[0054] The second large driving C unit structure 203 includes a third interdigital structure large driving device 305, a PMOS transistor 306, an NMOS transistor 307 and a fourth interdigital structure large driving device 308. The gates of the third interdigital structure large driving device 305 and the fourth interdigital structure large driving device 308 are connected together as the input terminal In1 of the second large driving C unit structure 203, and the gates of the PMOS transistor 306 and the NMOS transistor 307 are connected together as the input terminal In2 of the second large driving C unit structure 203. The source of the third interdigital structure large driving device 305 is connected to the power supply VDD, and the drain is connected to the source of the PMOS transistor 306. The drain of the PMOS transistor 306 is connected to the drain of the NMOS transistor 307 and serves as the output terminal Out of the second large driving C unit structure 203. The source of the NMOS transistor 307 is connected to the drain of the fourth interdigital structure large driving device 308, and the source of the fourth interdigital structure large driving device 308 is connected to the power ground VSS. The input terminal In1 of the second large driving C unit structure 203 is simultaneously connected to the input terminal In1 of the first large driving C unit structure 201, the output terminal Out of the second large driving clock-controlled dual-input inverter 204, and the output terminal Out of the first clock control structure 102; the input terminal In2 of the second large driving C unit structure 203 is simultaneously connected to the input terminal In2 of the first large driving C unit structure 201, the output terminal Out of the first large driving clock-controlled dual-input inverter 202, and the output terminal Out of the second clock control structure 104; the output terminal Out of the second large driving C unit structure 203 is simultaneously connected to the input terminal In2 of the first large driving clock-controlled dual-input inverter 202, the input terminal In1 of the second large driving clock-controlled dual-input inverter 204, and the input terminal In of the fourth clock control structure 107.

[0055] The third large driving C unit structure 205 includes a fifth interdigital structure large driving device 309, a PMOS transistor 310, an NMOS transistor 311 and a sixth interdigital structure large driving device 312; wherein the gates of the fifth interdigital structure large driving device 309 and the sixth interdigital structure large driving device 312 are connected together as the input terminal In1 of the third large driving C unit structure 205, and the gates of the PMOS transistor 310 and the NMOS transistor 311 are connected together as the input terminal In2 of the third large driving C unit structure 205. The source of the fifth interdigital structure large driving device 309 is connected to the power supply VDD, and the drain is connected to the source of the PMOS transistor 310, and the drain of the PMOS transistor 310 is connected to the drain of the NMOS transistor 311 and serves as the output terminal Out of the third large driving C unit structure 205, and the source of the NMOS transistor 311 is connected to the drain of the sixth interdigital structure large driving device 312, and the source of the sixth interdigital structure large driving device 312 is connected to the power ground VSS. The input terminal In1 of the third largest driving C unit structure 205 is simultaneously connected to the input terminal In1 of the fourth largest driving C unit structure 207, the output terminal Out of the fourth largest driving clock-controlled dual-input inverter 208, and the output terminal Out of the third clock control structure 106; the input terminal In2 of the third largest driving C unit structure 205 is simultaneously connected to the input terminal In2 of the fourth largest driving C unit structure 207, the output terminal Out of the third largest driving clock-controlled dual-input inverter 206, and the output terminal Out of the fourth clock control structure 107; the output terminal Out of the third largest driving C unit structure 205 is simultaneously connected to the input terminal In1 of the third largest driving clock-controlled dual-input inverter 206, the input terminal In2 of the fourth largest driving clock-controlled dual-input inverter 208, and the input terminal In of the second inverter circuit 109.

[0056] The fourth large driving C unit structure 207 includes a seventh interdigital structure large driving device 313, a PMOS transistor 314, an NMOS transistor 315 and an eighth interdigital structure large driving device 316; wherein the gates of the seventh interdigital structure large driving device 313 and the eighth interdigital structure large driving device 316 are connected together as the input terminal In1 of the fourth large driving C unit structure 207, and the gates of the PMOS transistor 314 and the NMOS transistor 315 are connected together as the input terminal In2 of the fourth large driving C unit structure 207. The source of the seventh interdigital structure large driving device 313 is connected to the power supply VDD, the drain is connected to the source of the PMOS transistor 314, the drain of the PMOS transistor 314 is connected to the drain of the NMOS transistor 315 and serves as the output terminal Out of the fourth large driving C unit structure 207, the source of the NMOS transistor 315 is connected to the drain of the eighth interdigital structure large driving device 316, and the source of the eighth interdigital structure large driving device 316 is connected to the power supply ground VSS. The input terminal In1 of the fourth largest driving C unit structure 207 is simultaneously connected to the input terminal In1 of the third largest driving C unit structure 205, the output terminal Out of the fourth largest driving clock-controlled dual-input inverter 208 and the output terminal Out of the third clock control structure 106. The input terminal In2 of the fourth largest driving C unit structure 207 is simultaneously connected to the input terminal In2 of the third largest driving C unit structure 205, the output terminal Out of the third largest driving clock-controlled dual-input inverter 206 and the output terminal Out of the fourth clock control structure 107. The output terminal Out of the fourth largest driving C unit structure 207 is simultaneously connected to the input terminal In2 of the third largest driving clock-controlled dual-input inverter 206 and the input terminal In1 of the fourth largest driving clock-controlled dual-input inverter 208.

[0057] like Figure 4As shown, the first large drive clock controlled dual-input inverter 202 includes a ninth interdigital structure large drive device 401, a PMOS tube 402, an NMOS tube 403 and a tenth interdigital structure large drive device 404; wherein the gate of the ninth interdigital structure large drive device 401 serves as the input terminal In1 of the first large drive clock controlled dual-input inverter 202, the gate of the PMOS tube 402 serves as the input terminal CPN of the first large drive clock controlled dual-input inverter 202 connected to the output terminal CPN of the third inverter circuit 110, the gate of the NMOS tube 403 serves as the input terminal CP of the first large drive clock controlled dual-input inverter 202 connected to the clock signal CP, and the gate of the tenth interdigital structure large drive device 404 serves as the input terminal In2 of the first large drive clock controlled dual-input inverter 202. The source of the ninth interdigitated structure large driver device 401 is connected to the power supply VDD, and the drain is connected to the source of the PMOS tube 402. The drain of the PMOS tube 402 is connected to the drain of the NMOS tube 403 and serves as the output terminal Out of the first large driving clock control dual-input inverter 202. The source of the NMOS tube 403 is connected to the drain of the tenth interdigitated structure large driver device 404. The source of the tenth interdigitated structure large driver device 404 is connected to the power ground VSS. The input terminal In1 of the first large driving clock-controlled dual-input inverter 202 is simultaneously connected to the input terminal In2 of the second large driving clock-controlled dual-input inverter 204, the output terminal Out of the first large driving C unit structure 201 and the input terminal In of the third clock control structure 106. The input terminal In2 of the first large driving clock-controlled dual-input inverter 202 is simultaneously connected to the input terminal In1 of the second large driving clock-controlled dual-input inverter 204, the output terminal Out of the second large driving C unit structure 203 and the input terminal In of the fourth clock control structure 107. The output terminal Out of the first large driving clock-controlled dual-input inverter 202 is simultaneously connected to the input terminals In2 ​​of the first large driving C unit structure 201 and the second large driving C unit structure 203 and the output terminal Out of the second clock control structure 104.

[0058] The second large driving clock controlled dual-input inverter 204 includes an eleventh interdigitated structure large driving device 405, a PMOS tube 406, an NMOS tube 407 and a twelfth interdigitated structure large driving device 408; wherein the gate of the eleventh interdigitated structure large driving device 405 serves as the input terminal In1 of the second large driving clock controlled dual-input inverter 204, the gate of the PMOS tube 406 serves as the input terminal CPN of the second large driving clock controlled dual-input inverter 204 connected to the output terminal CPN of the third inverter circuit 110, the gate of the NMOS tube 407 serves as the input terminal CP of the second large driving clock controlled dual-input inverter 204 connected to the clock signal CP, and the gate of the twelfth interdigitated structure large driving device 408 serves as the input terminal In2 of the second large driving clock controlled dual-input inverter 204. The source of the eleventh interdigitated structure large driver device 405 is connected to the power supply VDD, and the drain is connected to the source of the PMOS tube 406. The drain of the PMOS tube 406 is connected to the drain of the NMOS tube 407 and serves as the output terminal Out of the second large driving clock control dual-input inverter 204. The source of the NMOS tube 407 is connected to the drain of the twelfth interdigitated structure large driver device 408. The source of the twelfth interdigitated structure large driver device 408 is connected to the power supply ground VSS. The input terminal In1 of the second large driving clock-controlled dual-input inverter 204 is simultaneously connected to the input terminal In2 of the first large driving clock-controlled dual-input inverter 202, the output terminal Out of the second large driving C unit structure 203 and the input terminal In of the fourth clock control structure 107. The input terminal In2 of the second large driving clock-controlled dual-input inverter 204 is simultaneously connected to the input terminal In1 of the first large driving clock-controlled dual-input inverter 202, the output terminal Out of the first large driving C unit structure 201 and the input terminal In of the third clock control structure 106. The output terminal Out of the second large driving clock-controlled dual-input inverter 204 is simultaneously connected to the input terminals In1 of the first large driving C unit structure 201 and the second large driving C unit structure 203 and the output terminal Out of the first clock control structure 102.

[0059] The third large drive clock controlled dual-input inverter 206 includes a thirteenth interdigital structure large drive device 409, a PMOS tube 410, an NMOS tube 411 and a fourteenth interdigital structure large drive device 412; wherein the gate of the thirteenth interdigital structure large drive device 409 serves as the input terminal In1 of the third large drive clock controlled dual-input inverter 206, the gate of the PMOS tube 410 serves as the input terminal CP of the third large drive clock controlled dual-input inverter 206 connected to the clock signal CP, the gate of the NMOS tube 411 serves as the input terminal CPN of the third large drive clock controlled dual-input inverter 206 connected to the output terminal CPN of the third inverter circuit 110, and the gate of the fourteenth interdigital structure large drive device 412 serves as the input terminal In2 of the third large drive clock controlled dual-input inverter 206. The source of the thirteenth-finger structure large driver device 409 is connected to the power supply VDD, and the drain is connected to the source of the PMOS tube 410. The drain of the PMOS tube 410 is connected to the drain of the NMOS tube 411 and serves as the output terminal Out of the third large driving clock control dual-input inverter 206. The source of the NMOS tube 411 is connected to the drain of the fourteenth-finger structure large driver device 412. The source of the fourteenth-finger structure large driver device 412 is connected to the power ground VSS. The input terminal In1 of the third largest driving clock-controlled dual-input inverter 206 is simultaneously connected to the input terminal In2 of the fourth largest driving clock-controlled dual-input inverter 208, the output terminal Out of the third largest driving C unit structure 205, and the input terminal In of the second inverter circuit 109. The input terminal In2 of the third largest driving clock-controlled dual-input inverter 206 is simultaneously connected to the input terminal In1 of the fourth largest driving clock-controlled dual-input inverter 208 and the output terminal Out of the fourth largest driving C unit structure 207. The output terminal Out of the third largest driving clock-controlled dual-input inverter 206 is simultaneously connected to the input terminals In2 ​​of the third largest driving C unit structure 205 and the fourth largest driving C unit structure 207, and the output terminal Out of the fourth clock control structure 107.

[0060] The fourth large drive clock-controlled dual-input inverter 208 includes a fifteenth interdigitated structure large drive device 413, a PMOS tube 414, an NMOS tube 415 and a sixteenth interdigitated structure large drive device 416; wherein the gate of the fifteenth interdigitated structure large drive device 413 serves as the input terminal In1 of the fourth large drive clock-controlled dual-input inverter 208, the gate of the PMOS tube 414 serves as the input terminal CP of the fourth large drive clock-controlled dual-input inverter 208 and is connected to the clock signal CP, the gate of the NMOS tube 415 serves as the input terminal CPN of the fourth large drive clock-controlled dual-input inverter 208 and is connected to the output terminal CPN of the third inverter circuit 110, and the gate of the sixteenth interdigitated structure large drive device 416 serves as the input terminal In2 of the fourth large drive clock-controlled dual-input inverter 208. The source of the fifteenth interdigitated structure large driver device 413 is connected to the power supply VDD, and the drain is connected to the source of the PMOS tube 414. The drain of the PMOS tube 414 is connected to the drain of the NMOS tube 415 and serves as the output terminal Out of the fourth large driving clock control dual-input inverter 208. The source of the NMOS tube 415 is connected to the drain of the sixteenth interdigitated structure large driver device 416. The source of the sixteenth interdigitated structure large driver device 416 is connected to the power ground VSS. The input terminal In1 of the fourth largest driving clock-controlled dual-input inverter 208 is simultaneously connected to the input terminal In2 of the third largest driving clock-controlled dual-input inverter 206 and the output terminal Out of the fourth largest driving C unit structure 207. The input terminal In2 of the fourth largest driving clock-controlled dual-input inverter 208 is simultaneously connected to the input terminal In1 of the third largest driving clock-controlled dual-input inverter 206, the output terminal Out of the third largest driving C unit structure 205 and the input terminal In of the second inverter circuit 109. The output terminal Out of the fourth largest driving clock-controlled dual-input inverter 208 is simultaneously connected to the input terminals In1 of the third largest driving C unit structure 205 and the fourth largest driving C unit structure 207 and the output terminal Out of the third clock control structure 106.

[0061] like Figure 5 As shown, the first interdigitated structure large driver device 301 includes PMOS tubes 501 and 502, wherein the sources of the PMOS tubes 501 and 502 are connected together as the source of the first interdigitated structure large driver device 301, the gates are connected together as the gates of the first interdigitated structure large driver device 301, and the drains are connected together as the drain of the first interdigitated structure large driver device 301.

[0062] The second interdigital structure large driver device 304 includes NMOS tubes 503 and 504, wherein the sources of the NMOS tubes 503 and 504 are connected together as the source of the second interdigital structure large driver device 304, the gates are connected together as the gate of the second interdigital structure large driver device 304, and the drains are connected together as the drain of the second interdigital structure large driver device 304.

[0063] The third interdigital structure large driver device 305 includes PMOS tubes 505 and 506, wherein the sources of the PMOS tubes 505 and 506 are connected together as the source of the third interdigital structure large driver device 305, the gates are connected together as the gates of the third interdigital structure large driver device 305, and the drains are connected together as the drains of the third interdigital structure large driver device 305.

[0064] The fourth interdigital structure large driver device 308 includes NMOS tubes 507 and 508, wherein the sources of NMOS tubes 507 and 508 are connected together as the source of the fourth interdigital structure large driver device 308, the gates are connected together as the gates of the fourth interdigital structure large driver device 308, and the drains are connected together as the drain of the fourth interdigital structure large driver device 308.

[0065] The fifth interdigitated structure large driver device 309 includes PMOS tubes 509 and 510, wherein the sources of the PMOS tubes 509 and 510 are connected together as the source of the fifth interdigitated structure large driver device 309, the gates are connected together as the gates of the fifth interdigitated structure large driver device 309, and the drains are connected together as the drains of the fifth interdigitated structure large driver device 309.

[0066] The sixth interdigital structure large driver device 312 includes NMOS tubes 511 and 512, wherein the sources of the NMOS tubes 511 and 512 are connected together as the source of the sixth interdigital structure large driver device 312, the gates are connected together as the gates of the sixth interdigital structure large driver device 312, and the drains are connected together as the drain of the sixth interdigital structure large driver device 312.

[0067] The seventh interdigital structure large driver device 313 includes PMOS tubes 513 and 514, wherein the sources of the PMOS tubes 513 and 514 are connected together as the source of the seventh interdigital structure large driver device 313, the gates are connected together as the gates of the seventh interdigital structure large driver device 313, and the drains are connected together as the drains of the first interdigital structure large driver device 313.

[0068] The eighth interdigital structure large driver device 316 includes NMOS tubes 515 and 516, wherein the sources of the NMOS tubes 515 and 516 are connected together as the source of the eighth interdigital structure large driver device 316, the gates are connected together as the gates of the eighth interdigital structure large driver device 316, and the drains are connected together as the drain of the eighth interdigital structure large driver device 316.

[0069] The ninth interdigital structure large driver device 401 includes PMOS tubes 517 and 518, wherein the sources of the PMOS tubes 517 and 518 are connected together as the source of the ninth interdigital structure large driver device 401, the gates are connected together as the gates of the ninth interdigital structure large driver device 401, and the drains are connected together as the drain of the ninth interdigital structure large driver device 401.

[0070] The tenth interdigital structure large driver device 404 includes NMOS tubes 519 and 520, wherein the sources of the NMOS tubes 519 and 520 are connected together as the source of the tenth interdigital structure large driver device 404, the gates are connected together as the gates of the tenth interdigital structure large driver device 404, and the drains are connected together as the drain of the tenth interdigital structure large driver device 404.

[0071] The eleventh interdigitated structure large driver device 405 includes PMOS tubes 521 and 522, wherein the sources of the PMOS tubes 521 and 522 are connected together as the source of the eleventh interdigitated structure large driver device 405, the gates are connected together as the gates of the eleventh interdigitated structure large driver device 405, and the drains are connected together as the drains of the eleventh interdigitated structure large driver device 405.

[0072] The twelfth interdigital structure large driver device 408 includes NMOS tubes 523 and 524, wherein the sources of the NMOS tubes 523 and 524 are connected together as the source of the twelfth interdigital structure large driver device 408, the gates are connected together as the gates of the twelfth interdigital structure large driver device 408, and the drains are connected together as the drain of the twelfth interdigital structure large driver device 408.

[0073] The thirteenth interdigital structure large driver device 409 includes PMOS tubes 525 and 526, wherein the sources of the PMOS tubes 525 and 526 are connected together as the source of the thirteenth interdigital structure large driver device 409, the gates are connected together as the gates of the thirteenth interdigital structure large driver device 409, and the drains are connected together as the drain of the thirteenth interdigital structure large driver device 409.

[0074] The fourteenth interdigital structure large driver device 412 includes NMOS tubes 527 and 528, wherein the sources of the NMOS tubes 527 and 528 are connected together as the source of the fourteenth interdigital structure large driver device 412, the gates are connected together as the gates of the fourteenth interdigital structure large driver device 412, and the drains are connected together as the drain of the fourteenth interdigital structure large driver device 412.

[0075] The fifteenth interdigitated structure large driver device 413 includes PMOS tubes 529 and 530, wherein the sources of the PMOS tubes 529 and 530 are connected together as the source of the fifteenth interdigitated structure large driver device 413, the gates are connected together as the gates of the fifteenth interdigitated structure large driver device 413, and the drains are connected together as the drain of the fifteenth interdigitated structure large driver device 413.

[0076] The sixteenth interdigitated structure large driver device 416 includes NMOS tubes 531 and 532, wherein the sources of the NMOS tubes 531 and 532 are connected together as the source of the sixteenth interdigitated structure large driver device 416, the gates are connected together as the gates of the sixteenth interdigitated structure large driver device 416, and the drains are connected together as the drain of the sixteenth interdigitated structure large driver device 416.

[0077] like Figure 8 As shown, the cascade inverter structure 103 constitutes a delay structure 103, and the cascade inverter structure 103 includes PMOS tubes 801, 803, and NMOS tubes 802, 804; wherein the source of the PMOS tube 801 is connected to the power supply VDD, the gates of the PMOS tube 801 and the NMOS tube 802 are connected together as the input terminal In of the cascade inverter structure 103, the drain of the PMOS tube 801 is connected to the drain of the NMOS tube 802 and is connected to the gates of the PMOS tube 803 and the NMOS tube 804, the source of the NMOS tube 802 is connected to the power supply ground VSS, the source of the PMOS tube 803 is connected to the power supply VDD, the source of the NMOS tube 804 is connected to the power supply ground VSS, and the drains of the PMOS tube 803 and the NMOS tube 804 are connected together as the output terminal Out of the cascade inverter structure 103. The input terminal In of the cascade inverter structure 103 is connected to the output terminal Out of the first inverter circuit 101 and the input terminal In of the first clock control structure 102 . The output terminal Out of the cascade inverter structure 103 is connected to the input terminal In of the second clock control structure 104 .

[0078] Example

[0079] like Figure 1 The diagram shows a schematic diagram of a redundant feedback latch multi-level anti-single-event reinforcement trigger of a FinFET process provided in this example, including inverter circuits 101 , 109 , 110 , clock control structures 102 , 104 , 106 , 107 , a cascade inverter structure 103 , and redundant feedback latch structures 105 , 108 .

[0080] like Figure 2The structure diagram of the redundant feedback latch circuit in the redundant feedback latch multi-level anti-single particle reinforcement trigger of a FinFET process provided by this embodiment is shown. This structure is used to achieve interlocking of data signals and at the same time achieve anti-single particle flip-flop reinforcement. Taking the first redundant feedback latch structure 105 as an example, when data is stably transmitted, the inputs of the input terminals In1 and In2 of the first redundant feedback latch structure 105 are the same, and the large drive C unit structures 201 and 203 are both turned on. For example, the input terminals In1 and In2 of the first redundant feedback latch structure 105 are both digital signals 1. Through the inversion of the large drive C unit structures 201 and 203, the output terminals Out1 and Out2 of the first redundant feedback latch structure 105 are both digital signals 0, and are input to the large drive clock controlled dual input inverters 202 and 204. When the large When the input terminal CP of the driving clock-controlled dual-input inverter 202, 204 is a digital signal 1, the large-drive clock-controlled dual-input inverter 202, 204 are both turned on, and the output terminals Out1, Out2 are digital signals 1, and the digital signal 1 will continue to be input to the input terminals In1, In2 of the large-drive C unit structure 201, 203, thereby ensuring that the output terminals Out1, Out2 of the first redundant feedback latch structure 105 are stably maintained in a logic state opposite to the input terminals In1, In2 of the first redundant feedback latch structure 105, and data interlocking is achieved. For the first redundant feedback latch structure 105, when the data at the input terminals In1, In2 are the same, the data signal output by the clock control structure 102, 104 when the clock signal CP is a digital signal 0 is latched and inverted and input to the clock control structure 106, 107 when the clock signal CP is a digital signal 1, forming the main latch structure of the trigger.When data transmission is unstable, the inputs of the input terminals In1 and In2 of the first redundant feedback latch structure 105 are different. For example, when the clock signal CP is a digital signal 0, the NMOS tube 704 of the first clock control structure 102 is turned on by a single particle incident when it is turned off, and the node N3 is turned into a digital signal 0. Then, the input terminals In1 and In2 of the first redundant feedback latch structure 105 are digital signals 0 and 1 respectively, that is, the input terminals In1 and In2 of the large-drive C unit structures 201 and 203 are digital signals 0 and 1 respectively. The different signals at the two input terminals will cause the large-drive C unit structures 201 and 203 to be turned off, and the output terminals Out1 and Out2 will maintain the original Digital signals 0 and 0, when the clock signal CP is digital signal 1, the large-drive clock controls the dual-input inverters 202 and 204 to be turned on, and the digital signals 0 and 0 of the input terminals In1 and In2 are inverted and output. Then, through redundant feedback, the input terminal In1 signal of the large-drive C unit structure 201 and 203 is restored to the correct digital signal 1, that is, the input terminals In1 and In2 of the first redundant feedback latch structure 105 are the same and are both digital signals 1, and the data can continue to be correctly and stably transmitted, realizing resistance to single-particle unit flip. Similarly, when the input terminal In1 data of the first redundant feedback latch structure 105 is correct and the In2 data is flipped, error correction can also be achieved through redundant feedback to ensure that the data is correctly latched. When the first large driving C unit structure 201 is incident by a single particle and causes the internal node N5 to flip, the nodes N5 and N6 are respectively digital signals 1 and 0, then the input terminals In1 and In2 of the large driving clock controlled dual-input inverters 202 and 204 are different, the first large driving clock controlled dual-input inverter 202 is turned off, and the N4 node maintains the original digital signal 1. When the clock signal CP is digital signal 1, the PMOS tubes 405, 406 and NMOS tubes 407 of the second large driving clock controlled dual-input inverter 204 are turned off. 07 and 408 are both turned on. Under the condition of the same pull-up and pull-down capability of the FinFET process circuit design, this state makes the N3 node maintain the original digital signal 1. Then, through the feedback of nodes N3 and N4, the large drive C unit structures 201 and 203 are both turned on to output the digital signals 1 of nodes N3 and N4 inverted, so that node N5 is restored to the correct digital signal 0 that is the same as node N6, realizing the resistance to single-particle unit flip inside the latch structure. Similarly, when the data of the internal node N6 is flipped, error correction can also be achieved through redundant feedback. This structure can restore the flipped node to the correct state through redundant feedback when any node of the storage nodes N3, N4, N5, and N6 is flipped, realizing immunity to single-particle unit flip.When the above two data instability situations occur at the same time, that is, the node N3 and the node N5 flip at the same time, at this time, the node N3 flips to the digital signal 0, and the node N5 flips to the digital signal 1. Since the nodes N3 and N4 are digital signals 0 and 1 respectively, the second large driving C unit structure 203 is turned off, and the node N6 maintains the original correct digital signal 0. Since the nodes N5 and N6 are digital signals 1 and 0 respectively, the first large driving clock control dual-input inverter 202 is turned off, and the node N4 maintains the original correct digital signal 1. For the first redundant feedback latch structure 1 05, the simultaneous flipping of the internal storage nodes N3 and N5 will not affect the correct state of the other two internal storage nodes N4 and N6. The first redundant feedback latch structure 105 will not latch the erroneous data. As the flipped data of the nodes N3 and N5 return to normal, the state of the latch also returns to normal. Except for the simultaneous flipping of the nodes N3 and N4, or the simultaneous flipping of the nodes N5 and N6, the flipping of any other two nodes will not change the correct data stored in the other storage nodes. The redundant feedback latch structure has a significant ability to resist multi-bit flipping.

[0081] like Figure 3The circuit implementation form of the large-drive C unit structure 201, 203, 205, and 207 is shown. This structure is used to achieve that when the logic states of the input terminals In1 and In2 are the same, the input signal is inverted and output, and when the logic states of the input terminal signals In1 and In2 are different, the original output logic function is maintained, and a large-drive design is performed for the PMOS connected to the power supply VDD and the NMOS connected to the power supply ground VSS, and the single-particle resistance of the output node is improved by enhancing the recovery current. Taking the first large driving C unit structure 201 as an example, when the input terminal signals In1 and In2 are the same, such as both are digital signals 1, the gates of the PMOS tubes 301 and 302 are both digital signals 1, then the PMOS tubes 301 and 302 are both cut off, and at the same time, the gates of the NMOS tubes 303 and 304 are both digital signals 1, then the NMOS tubes 303 and 304 are both turned on, and the output terminal Out of the first large driving C unit structure 201 outputs the digital signal 0 through the pull-down effect of the turned-on NMOS tubes 303 and 304, thereby realizing the function of inverting the input signal 1. When the input terminal signals In1 and In2 are different, such as digital signals 0 and 1 respectively, the gates of the PMOS tubes 301 and 302 are connected to the digital signals 0 and 1 respectively, then the PMOS tube 301 is turned on and the PMOS tube 302 is turned off, and at the same time, the gates of the NMOS tubes 303 and 304 are connected to the digital signals 1 and 0 respectively, then the NMOS tube 303 is turned on and the NMOS tube 304 is turned off. Since the pull-up and pull-down networks of the first large driving C unit structure 201 are not turned on, the output terminal Out of the first large driving C unit structure 201 maintains the original data signal. In addition, the PMOS tube 301 connected to the power supply VDD and the NMOS tube 304 connected to the power supply ground VSS are designed as interdigital structure large driving devices, which can enhance the recovery current of the device drain when a single particle is incident, and improve the circuit's single particle resistance capability.

[0082] like Figure 4The circuit implementation form of the large-drive clock-controlled dual-input inverters 202, 204, 206, and 208 is shown. Two of the structures are used to share the connection of the dual-input signals, so that when the clock signal CP controls the structure to be in the on state and the logic potentials of the input terminals In1 and In2 are the same, the two large-drive clock-controlled dual-input inverters will invert the input signals and output them; when the clock signal CP controls the structure to be in the off state, or the logic states of the input terminal signals In1 and In2 are different, the two large-drive clock-controlled dual-input inverters will maintain the original function of outputting data. Taking the large drive clock controlled dual-input inverters 202 and 204 as an example, the input terminal In1 of the first large drive clock controlled dual-input inverter 202 is connected to the input terminal In2 of the second large drive clock controlled dual-input inverter 204, and the input terminal In2 of the first large drive clock controlled dual-input inverter 202 is connected to the input terminal In1 of the second large drive clock controlled dual-input inverter 204. When the clock signal CP is the digital signal 1, the PMOS tube 4 of the first large drive clock controlled dual-input inverter 202 is 02, NMOS tube 403 and PMOS tube 406 and NMOS tube 407 of the second largest driving clock controlled dual-input inverter 204 are all turned on. In this state, when the input terminals In1 and In2 of the first largest driving clock controlled dual-input inverter 202 are both digital signals 1, due to the shared connection of the input signals, the input terminals In1 and In2 of the second largest driving clock controlled dual-input inverter 204 are also digital signals 1, and the PMOS tubes 401 and 405 are both turned off, and the NMOS tubes 404 and 408 are both turned on. When the clock signal CP is a digital signal 1 and the input terminals In1 and In2 of the first large driving clock controlled dual-input inverter 202 are two opposite logic potentials of digital signals 1 and 0, respectively, the PMOS tube 401 and NMOS tube 404 of the first large driving clock controlled dual-input inverter 202 are both turned off, that is, the pull-up and pull-down networks are turned off, and the output node N4 maintains The original logic potential, due to the shared connection of the input signal, the input terminals In1 and In2 of the second largest driving clock controlling the dual-input inverter 204 are digital signals 0 and 1 respectively, and the PMOS tube 405 and NMOS tube 408 of the first largest driving clock controlling the dual-input inverter 202 are both turned on, that is, the pull-up and pull-down networks are both turned on. Under the condition that the pull-up and pull-down capabilities of the FinFET process circuit design are the same, this state enables the node N3 to maintain the original data signal, that is, the output nodes N3 and N4 maintain the original logic level unchanged.Through this structure and the connection method of its shared input terminal, the effect of ensuring that the correct latching of data is not affected when one input signal is flipped is achieved. Combined with the PMOS tube connected to the power supply VDD and the NMOS tube connected to the power ground VSS designed as a large driver device with an interdigitated structure, the circuit's anti-single particle reinforcement capability is improved through a multi-level reinforcement method.

[0083] like Figure 5 The circuit implementation of the interdigital structure large driver device 301, 304, 305, 308, 309, 312, 313, 316, 401, 404, 405, 408, 409, 412, 413, 416 of this embodiment is shown. By using this structure, the transistors are connected in parallel through the interdigital structure, and the drive is increased without increasing the sensitive volume, achieving the effect of anti-single particle reinforcement. Taking the large driver device 301 with an interdigital structure as an example, the source, gate and drain of the PMOS tube 501 are respectively connected to the source, gate and drain of the PMOS tube 502, and the drain regions of the PMOS tubes 501 and 502 are shared in the layout. When the gate of the large driver device 301 with an interdigital structure is connected to the digital signal 0 and the NMOS tubes 303 and 304 are turned on by a single particle incident, the large driver device 301 with an interdigital structure supplements holes through the two sources of the PMOS tubes 501 and 502 without additionally increasing the drain area, thereby enhancing the recovery current of the node N5, thereby achieving anti-single particle reinforcement with low reinforcement cost and high energy efficiency ratio.

[0084] like Figure 6 The circuit implementation form of the inverter circuits 101, 109, and 110 in a redundant feedback latch multi-level anti-single particle reinforcement trigger of a FinFET process provided in this embodiment is shown. This structure is used to achieve the effect of inverting the data signal output. The first inverter circuit 101 inverts the input signal Input of the trigger circuit and inputs it to the first clock control circuit 102 and the cascade inverter structure 103; the second inverter circuit 109 inverts the input signal and uses it as the output of the trigger circuit; the third inverter circuit 110 inverts the clock signal CP, outputs the inverted clock signal CPN, and provides timing control for each part of the trigger structure.

[0085] like Figure 7The circuit implementation form of the clock control structures 102, 104, 106, and 107 in a redundant feedback latch multi-level anti-single particle reinforcement trigger of a FinFET process provided by this embodiment is shown. This structure is used to control the input of the data signal through the level state of the clock signal CP and invert the input signal. Taking the first clock control structure 102 as an example, when the clock signal CP is a digital signal 0, the PMOS tube 702 and the NMOS tube 703 are both turned on, and the first clock control structure 102 implements the function of inverting the input signal In; when the clock signal CP is a digital signal 1, the PMOS tube 702 and the NMOS tube 703 are both turned off, and the pull-up and pull-down networks of the first clock control structure 102 are not connected, and the output terminal Out will maintain the original logic value unchanged and enter the high impedance state, that is, the transmission or retention of data is controlled by the clock signal.

[0086] like Figure 8 The circuit implementation form of the cascade inverter structure 103 in the redundant feedback latch multi-level anti-single-particle reinforcement trigger of the FinFET process provided by this embodiment is shown. This structure is used to realize delayed data transmission, and the input signal of the filter structure is formed together with the undelayed data to realize the filtering function of the single-particle transient pulse. The cascade inverter structure 103 is composed of two cascaded inverter circuits. The output signal is logically consistent with the input signal and has a certain time delay. The data signal output by the cascade inverter structure 103 and the data signal output by the first inverter circuit 101 constitute two signals with a certain phase difference, which are respectively input into the first redundant feedback latch structure 105 through the clock control structures 104 and 102. Since the first redundant feedback latch structure 105 can correctly latch and output the two inconsistent input signals when the logical states are consistent, the cascade inverter structure 103 is introduced on the basis of the first redundant feedback latch structure 105 to realize filtering of external single-particle transient pulses in the data port. The filtering width is the delay of the cascade inverter structure 103. Using the cascade inverter structure 103 as a delay unit can improve the circuit's ability to resist single-particle transients and achieve single-particle reinforcement.

[0087] like Fig. 9 The figure shows a schematic diagram of the three-dimensional structure of the FinFET device of this embodiment. Compared with the planar MOSFET structure, FinFET has an additional protrusion on the original insulating substrate, and its channel is surrounded by a gate. The FinFET device expands the transistor structure from two-dimensional to three-dimensional, and there is a new way to calculate the active area width. The calculation formula for the effective width of the active area of ​​the FinFET device is W Fin-eff =N Fin-eff *(2H Fin +T Fin ), where H Fin Fin high, T Finis the Fin width, N Fin-eff N is the number of effective Fins of the device. Fin-eff =1,2,···n. For H Fin and T Fin , when designing the layout Fin and T Fin All are fixed values ​​and cannot be modified; for N Fin-eff , this value has a further calculation formula N Fin-eff =N Fin / Pit *N Finger , where N Fin / Pit N is the number of Fins per unit gate spacing. Finger is the number of parallel transistors after using the interdigital structure, N Fin / Pit and N Finger =1,2,···n, which are adjustable parameters during layout design.

[0088] like Fig.10 The figure shows a schematic diagram of increasing the number of Fins and the finger structure in the layout reinforcement design of a redundant feedback latch multi-level anti-single-particle reinforcement trigger of a FinFET process provided by this embodiment. For the FinFET process, the structural characteristics of its small-sized three-dimensional Fin significantly reduce the volume of the single-particle sensitive area of ​​the device compared to the planar process, resulting in a decrease in the amount of charge collected at the drain end where the logic flip occurs at the storage node of the digital circuit. Increasing the driving capability can supplement the carriers that maintain the correct logical state by enhancing the recovery current, which is an effective means to suppress the single-particle transient effect of the FinFET device. The effective width of the active area directly affects the driving capability of the device. In the layout, it can be increased by increasing the N Fin / Pit and N Finger Realize the anti-single particle reinforcement. Therefore, this circuit designs the maximum number of Fins within the unit gate spacing in the global layout, and realizes the maximum drive for all FinFET devices in the circuit without increasing the additional area. In addition, for the sensitive nodes N3, N4, N5, N6, N7, N8, N9, and N10, in order to ensure the stability of their logic potential as much as possible, in the large drive C unit structure 201, 203, 205, 207 of the latch structure and the large drive clock control dual-input inverter 202, 204, 206, and 208, the PMOS connected to the power supply VDD and the NMOS connected to the power supply ground VSS use a fork finger structure large drive device. The fork finger structure connects transistors in parallel and shares the drain area. While reducing the sensitive volume, the device realizes a 2-fold drive corresponding to the unit drain area volume, which can further enhance the anti-single particle flip capability of the sensitive nodes N3, N4, N5, N6, N7, N8, N9, and N10. If the N Finger, the drain region of the device no longer meets the condition of being shared by all parallel devices. The increase in the drain area will to a certain extent offset the advantage of the FinFET device in enhancing the recovery current and thus suppressing the single particle effect. Therefore, the forked-finger structure large driver devices 301, 304, 305, 308, 309, 312, 313, 316, 401, 404, 405, 408, 409, 412, 413, 416 are designed as two FinFET devices in parallel to achieve anti-single particle layout reinforcement with high reinforcement energy efficiency ratio.

[0089] like Fig.11 The figure shows a schematic diagram of the sensitive node isolation layout of a FinFET process redundant feedback latch multi-level anti-single particle reinforcement trigger in the layout reinforcement design provided by this embodiment. For nanoscale FinFET process integrated circuits, charge sharing and parasitic bipolar effects lead to a significant increase in the probability of a single particle inducing multiple adjacent nodes to flip simultaneously. This layout method increases the physical spacing of sensitive node pairs without sacrificing the layout area, reduces the probability of simultaneous flipping of sensitive node pairs, and further enhances the anti-single particle multi-bit flip reinforcement capability. Taking the clock control structures 102, 104 and the first redundant feedback latch structure 105 as examples, since the first redundant feedback latch structure 105 cannot realize error correction when the N3 and N4 nodes flip at the same time or the N5 and N6 nodes flip at the same time, for N3 and N4, the first clock control structure 102 and the second large drive clock control dual-input inverter 204 that cause the logic error of N3 and the clock control structure 104 and the first large drive clock control dual-input inverter 202 that cause the logic error of N4 are isolated and laid out; for N5 and N6, the first large drive C unit structure 201 that causes the logic error of N5 and the second large drive C unit structure 203 that causes the logic error of N6 are isolated and laid out. This layout reinforcement layout not only meets the requirements of advanced processes for high integration, but also further enhances the circuit's ability to resist single-particle multi-bit flip reinforcement.

[0090] In this embodiment, a design reinforcement method combining circuit and layout is preferably used. In circuit reinforcement, in view of the problem that single-particle incident FinFET process easily induces simultaneous flipping of multiple nodes, a redundant feedback latch structure is designed to achieve immunity to single-particle unit flipping and suppression of multi-bit flipping, and introduce a delay unit to filter out external single-particle transient pulses; in layout reinforcement, the Fin within the unit gate spacing is designed to be the maximum number, and a fork finger structure is used for the device at the sensitive node to enhance the driving current, and the sensitive node pairs are isolated and laid out to further enhance the ability to resist single-particle multi-bit flipping. This embodiment realizes multi-dimensional reinforcement of the circuit against single-particle unit / multi-bit flipping and single-particle transients through redundant feedback latch structures and delay units, while increasing the number of Fins and isolating sensitive node pairs without additional area overhead, the fork finger structure is not used globally, and the reinforcement cost is low.

[0091] The above description is only the best specific implementation mode of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by any technician familiar with the technical field within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention.

[0092] The contents not described in detail in the specification of the present invention belong to the common knowledge of the professionals in this field.

Claims

1. A FinFET process redundant feedback latch multi-level anti-single event reinforcement trigger, characterized in that: include: A data input structure (101) transmits external input data to a first clock control structure (102) and a delay structure (103); A first clock control structure (102) transmits data received from a data input structure (101) to a first input end of a data master latch structure (105) when the clock is at a low level; The delay structure (103) transmits the data received from the data input structure (101) to the second clock control structure (104) after delay; The second clock control structure (104) transmits the data received from the delay structure (103) to the second input end of the data master latch structure (105) when the clock is at a low level; The data master latch structure (105) transmits two data paths received from the first clock control structure (102) and the second clock control structure (104) to the third clock control structure (106) and the fourth clock control structure (107) when the clock is at a low level; and latches the two data paths received from the first clock control structure (102) and the second clock control structure (104) when the clock is at a high level; A third clock control structure (106) transmits data received from the data master latch structure (105) to a first input terminal of the data slave latch structure (108) when the clock is at a high level; A fourth clock control structure (107) transmits data received from the data master latch structure (105) to a second input end of the data slave latch structure (108) when the clock is at a high level; The data slave latch structure (108) transmits two data paths received from the third clock control structure (106) and the fourth clock control structure (107) to the data output structure (109) when the clock is at a high level; and latches the two data paths received from the third clock control structure (106) and the fourth clock control structure (107) when the clock is at a low level; The data output structure (109) outputs the data received from the data latch structure (108); A clock input structure (110) inverts an external clock signal and transmits the inverted signal to input ends of a first clock control structure (102), a second clock control structure (104), a data master latch structure (105), a third clock control structure (106), a fourth clock control structure (107) and a data slave latch structure (108).

2. The redundant feedback latch multi-level anti-single event hardening trigger of FinFET process according to claim 1, characterized in that: The data input structure (101) is composed of a first inverter circuit, which comprises a PMOS tube (601) and an NMOS tube (602), wherein the gates of the PMOS tube (601) and the NMOS tube (602) are connected together as an input terminal In of the first inverter circuit, the source of the PMOS tube (601) is connected to a power supply VDD, the drain is connected to the drain of the NMOS tube (602) and serves as an output terminal Out of the first inverter circuit, the source of the NMOS tube (602) is connected to a power supply ground VSS, the input terminal In of the first inverter circuit is connected to an input signal Input of a trigger circuit, and the output terminal Out is connected to an input terminal In of the first clock control structure (102) and an input terminal In of a delay structure (103).

3. The redundant feedback latch multi-level anti-single event hardening trigger of FinFET process according to claim 1, characterized in that: The clock input structure (110) is composed of a third inverter circuit, which includes a PMOS transistor (605) and an NMOS transistor (606), wherein the gates of the PMOS transistor (605) and the NMOS transistor (606) are connected together as an input terminal In of the third inverter circuit, the source of the PMOS transistor (605) is connected to a power supply VDD, the drain is connected to the drain of the NMOS transistor (606) and serves as an output terminal Out of the third inverter circuit, the source of the NMOS transistor 606 is connected to a power supply ground VSS, the input terminal In of the third inverter circuit is connected to a clock signal CP, and the output terminal CPN is simultaneously connected to the input terminals CPN of the first clock control structure (102), the second clock control structure (104), the third clock control structure (106) and the fourth clock control structure (107), and the input terminals CPN of the data master latch structure (105) and the data slave latch structure (108).

4. The redundant feedback latch multi-level anti-single event hardening trigger of FinFET process according to claim 1, characterized in that: The first clock control structure (102) comprises a PMOS tube (701), a PMOS tube (702), an NMOS tube (703) and an NMOS tube (704), wherein the gate electrodes of the PMOS tube (701) and the NMOS tube (704) are connected together as an input terminal In of the first clock control structure, the source electrode of the PMOS tube (701) is connected to a power supply VDD, and the drain electrode is connected to the source electrode of the PMOS tube (702), the drain electrode of the PMOS tube (702) is connected to the drain electrode of the NMOS tube (703) and serves as an output terminal Out of the first clock control structure, and the source electrode of the NMOS tube (703) is connected to the NMOS tube (704). The drain of the MOS tube (704) and the source of the NMOS tube (704) are connected to the power ground VSS; the gate of the PMOS tube (702) serves as the input terminal CP of the first clock control structure and is connected to the clock signal CP; the gate of the NMOS tube (703) serves as the input terminal CPN of the first clock control structure and is connected to the output terminal CPN of the clock input structure (110); the input terminal In of the first clock control structure is connected to the output terminal Out of the data input structure (101) and the input terminal In of the delay structure (103); and the output terminal Out of the first clock control structure is connected to the input terminal In1 of the data master latch structure (105).

5. The redundant feedback latch multi-level single event hardening trigger of FinFET process according to claim 1, characterized in that: The second clock control structure (104) comprises a PMOS tube (705), a PMOS tube (706), an NMOS tube (707) and an NMOS tube (708), wherein the gate electrodes of the PMOS tube (705) and the NMOS tube (708) are connected together as an input terminal In of the second clock control structure, the source electrode of the PMOS tube (705) is connected to a power supply VDD, and the drain electrode is connected to the source electrode of the PMOS tube (706), the drain electrode of the PMOS tube (706) is connected to the drain electrode of the NMOS tube (707) and serves as an output terminal Out of the second clock control structure, and the gate electrodes of the NMOS tube (707) and the NMOS tube (708) are connected together as an input terminal In of the second clock control structure, the source electrode of the PMOS tube (705) is connected to a power supply VDD, and the drain electrode is connected to the source electrode of the PMOS tube (706), the drain electrode of the PMOS tube (706) is connected to the drain electrode of the NMOS tube (707) and serves as an output terminal Out of the second clock control structure. The source of the PMOS tube (707) is connected to the drain of the NMOS tube (708), the source of the NMOS tube (708) is connected to the power ground VSS, the gate of the PMOS tube (706) serves as the input terminal CP of the second clock control structure and is connected to the clock signal CP, the gate of the NMOS tube (707) serves as the input terminal CPN of the second clock control structure and is connected to the output terminal CPN of the clock input structure (110), the input terminal In of the second clock control structure is connected to the output terminal Out of the delay structure (103), and the output terminal Out of the second clock control structure is connected to the input terminal In2 of the data master latch structure (105).

6. The redundant feedback latch multi-level single event hardening trigger of FinFET process according to claim 1, characterized in that: The third clock control structure (106) comprises a PMOS tube (709), a PMOS tube (710), an NMOS tube (711) and an NMOS tube (712), wherein the gates of the PMOS tube (709) and the NMOS tube (712) are connected together as an input terminal In of the third clock control structure, the source of the PMOS tube (709) is connected to a power supply VDD, and the drain is connected to the source of the PMOS tube (710), the drain of the PMOS tube (710) is connected to the drain of the NMOS tube (711) and serves as an output terminal Out of the third clock control structure, and the gates of the NMOS tube (71 .... ) is connected to the drain of the NMOS tube (712), the source of the NMOS tube (712) is connected to the power ground VSS, the gate of the PMOS tube (710) serves as the input terminal CPN of the third clock control structure and is connected to the output terminal CPN of the clock input structure (110), the gate of the NMOS tube (711) serves as the input terminal CP of the third clock control structure and is connected to the clock signal CP, the input terminal In of the third clock control structure is connected to the output terminal Out1 of the data master latch structure (105), and the output terminal Out of the third clock control structure is connected to the input terminal In1 of the data slave latch structure (108).

7. The redundant feedback latch multi-level single event hardening trigger of FinFET process according to claim 1, characterized in that: The fourth clock control structure (107) comprises a PMOS tube (713), a PMOS tube (714), an NMOS tube (715) and an NMOS tube (716), wherein the gates of the PMOS tube (713) and the NMOS tube (716) are connected together as an input terminal In of the fourth clock control structure, the source of the PMOS tube (713) is connected to a power supply VDD, the drain is connected to the source of the PMOS tube (714), the drain of the PMOS tube (714) is connected to the drain of the NMOS tube (715) as an output terminal Out of the fourth clock control structure, and the gates of the NMOS tube (715 .... ) is connected to the drain of the NMOS tube (716), the source of the NMOS tube (716) is connected to the power ground VSS, the gate of the PMOS tube (714) serves as the input terminal CPN of the fourth clock control structure and is connected to the output terminal CPN of the clock input structure (110), the gate of the NMOS tube (715) serves as the input terminal CP of the fourth clock control structure and is connected to the clock signal CP, the input terminal In of the fourth clock control structure is connected to the output terminal Out2 of the data master latch structure (105), and the output terminal Out of the fourth clock control structure is connected to the input terminal In2 of the data slave latch structure (108).

8. The redundant feedback latch multi-level single event hardening trigger of FinFET process according to claim 1, characterized in that: The data master latch structure (105) comprises a first large drive C unit structure (201), a second large drive C unit structure (203), a first large drive clock controlled dual-input inverter (202) and a second large drive clock controlled dual-input inverter (204); The output end Out of the first large drive C unit structure (201) is connected to the input end In1 of the first large drive clock controlled dual-input inverter (202) and the input end In2 of the second large drive clock controlled dual-input inverter (204), and serves as the output end Out1 of the data master latch structure; the output end Out of the second large drive C unit structure (203) is connected to the input end In2 of the first large drive clock controlled dual-input inverter (202) and the input end In1 of the second large drive clock controlled dual-input inverter (204), and serves as the output end Out2 of the data master latch structure; the output end Out of the first large drive clock controlled dual-input inverter (202) is simultaneously connected to the input ends In2 ​​of the first large drive C unit structure (201) and the second large drive C unit structure (203), and serves as the input end In2 of the data master latch structure; the output end Out of the second large drive clock controlled dual-input inverter (204) is connected to the first large drive C unit structure (201) and the second large drive C unit structure (204). The input terminal In1 of the element structure (203) is used as the input terminal In1 of the data master latch structure; the input terminals CP of the first large drive clock controlled dual-input inverter (202) and the second large drive clock controlled dual-input inverter (204) are used as the input terminal CP of the data master latch structure and are connected to the clock signal CP; the input terminals CPN of the first large drive clock controlled dual-input inverter (202) and the second large drive clock controlled dual-input inverter (204) are used as the input terminal CPN of the data master latch structure and are connected to the output terminal CPN of the clock input structure (110); the input terminal In1 of the data master latch structure is connected to the output terminal Out of the first clock control structure (102); the input terminal In2 of the data master latch structure is connected to the output terminal Out of the second clock control structure (104); the output terminal Out1 of the data master latch structure is connected to the input terminal In of the third clock control structure (106); and the output terminal Out2 of the data master latch structure is connected to the input terminal In of the fourth clock control structure (107).

9. The redundant feedback latch multi-level anti-single event hardening trigger of FinFET process according to claim 8, characterized in that: The first large driving C unit structure (201) comprises a first interdigital structure large driving device (301), a PMOS tube (302), an NMOS tube (303) and a second interdigital structure large driving device (304); wherein the gate electrodes of the first interdigital structure large driving device (301) and the second interdigital structure large driving device (304) are connected together as an input terminal In1 of the first large driving C unit structure (201), the gate electrodes of the PMOS tube (302) and the NMOS tube (303) are connected together as an input terminal In2 of the first large driving C unit structure (201), the source electrode of the first interdigital structure large driving device (301) is connected to a power supply VDD, the drain electrode is connected to a source electrode of the PMOS tube (302), the drain electrode of the PMOS tube (302) is connected to a drain electrode of the NMOS tube (303) and serves as an output terminal Out of the first large driving C unit structure (201), and the source electrode of the NMOS tube (303) is connected to an output terminal Out of the second interdigital structure large driving device (304). The drain electrode of the second interdigitated structure large driver device (304) is connected to the power ground VSS, the input terminal In1 of the first large driver C unit structure (201) is connected to the input terminal In1 of the second large driver C unit structure (203), the output terminal Out of the second large driver clock-controlled dual-input inverter (204) and the output terminal Out of the first clock control structure (102), the input terminal In2 of the first large driver C unit structure (201) is simultaneously connected to the input terminal In2 of the second large driver C unit structure (203), the output terminal Out of the first large driver clock-controlled dual-input inverter (202) and the output terminal Out of the second clock control structure (104), and the output terminal Out of the first large driver C unit structure (201) is connected to the input terminal In1 of the first large driver clock-controlled dual-input inverter (202), the input terminal In2 of the second large driver clock-controlled dual-input inverter (204) and the input terminal In of the third clock control structure (106). The second large driving C unit structure (203) comprises a third interdigital structure large driving device (305), a PMOS tube (306), an NMOS tube (307) and a fourth interdigital structure large driving device (308); wherein the gates of the third interdigital structure large driving device (305) and the fourth interdigital structure large driving device (308) are connected together as the input terminal In1 of the second large driving C unit structure (203), the gates of the PMOS tube (306) and the NMOS tube (307) are connected together as the input terminal In2 of the second large driving C unit structure (203), the source of the third interdigital structure large driving device (305) is connected to the power supply VDD, the drain is connected to the source of the PMOS tube (306), the drain of the PMOS tube (306) is connected to the drain of the NMOS tube (307) and serves as the output terminal Out of the second large driving C unit structure (203), and the source of the NMOS tube (307) is connected to the fourth interdigital structure large driving device (308). The drain of the fourth interdigital structure large driver device (308) is connected to the power ground VSS, the input terminal In1 of the second large driver C unit structure (203) is connected to the input terminal In1 of the first large driver C unit structure (201), the output terminal Out of the second large driver clock-controlled dual-input inverter (204) and the output terminal Out of the first clock control structure (102), the input terminal In2 of the second large driver C unit structure (203) is connected to the input terminal In2 of the first large driver C unit structure (201), the output terminal Out of the first large driver clock-controlled dual-input inverter (202) and the output terminal Out of the second clock control structure (104), and the output terminal Out of the second large driver C unit structure (203) is connected to the input terminal In2 of the first large driver clock-controlled dual-input inverter (202), the input terminal In1 of the second large driver clock-controlled dual-input inverter (204) and the input terminal In of the fourth clock control structure (107); The first large driving clock controlled dual-input inverter (202) comprises a ninth interdigital structure large driving device (401), a PMOS tube (402), an NMOS tube (403) and a tenth interdigital structure large driving device (404); wherein the gate of the ninth interdigital structure large driving device (401) serves as the input terminal In1 of the first large driving clock controlled dual-input inverter (202), and the gate of the PMOS tube (402) serves as the input terminal CPN of the first large driving clock controlled dual-input inverter (202) and is connected to the clock input structure (110). The gate of the NMOS tube (403) is connected to the output terminal CPN of the first large driving clock control dual-input inverter (202) and is connected to the clock signal CP. The gate of the tenth interdigital structure large driving device (404) is connected to the input terminal In2 of the first large driving clock control dual-input inverter (202). The source of the ninth interdigital structure large driving device (401) is connected to the power supply VDD, and the drain is connected to the source of the PMOS tube (402). The drain of the PMOS tube (402) is connected to the drain of the NMOS tube (403) and is connected to the first large driving clock. The output terminal Out of the first large drive clock controlled dual input inverter (202) is connected, the source of the NMOS tube (403) is connected to the drain of the tenth interdigital structure large drive device (404), the source of the tenth interdigital structure large drive device (404) is connected to the power supply ground VSS, the input terminal In1 of the first large drive clock controlled dual input inverter (202) is connected to the input terminal In2 of the second large drive clock controlled dual input inverter (204), the output terminal Out of the first large drive C unit structure (201) and the input terminal In of the third clock control structure (106), the first large The input terminal In2 of the driving clock controlled dual-input inverter (202) is connected to the input terminal In1 of the second large driving clock controlled dual-input inverter (204), the output terminal Out of the second large driving C unit structure (203) and the input terminal In of the fourth clock control structure (107); the output terminal Out of the first large driving clock controlled dual-input inverter (202) is connected to the input terminals In2 ​​of the first large driving C unit structure (201) and the second large driving C unit structure (203) and the output terminal Out of the second clock control structure (104); The second large drive clock controlled dual-input inverter (204) comprises an eleventh interdigital structure large drive device (405), a PMOS tube (406), an NMOS tube (407) and a twelfth interdigital structure large drive device (408); wherein the gate of the eleventh interdigital structure large drive device (405) serves as the input terminal In1 of the second large drive clock controlled dual-input inverter (204), and the gate of the PMOS tube (406) serves as the input terminal CPN of the second large drive clock controlled dual-input inverter (204) connected to the clock input structure (11 0), the gate of the NMOS tube (407) is used as the input terminal CP of the second large driving clock control dual-input inverter (204) and is connected to the clock signal CP, the gate of the twelfth interdigital structure large driving device (408) is used as the input terminal In2 of the second large driving clock control dual-input inverter (204), the source of the eleventh interdigital structure large driving device (405) is connected to the power supply VDD, the drain is connected to the source of the PMOS tube (406), the drain of the PMOS tube (406) is connected to the drain of the NMOS tube (407) and serves as the second large driving clock control dual-input inverter (204). The output terminal Out of the second large drive clock controlled dual input inverter (204) is connected, the source of the NMOS tube (407) is connected to the drain of the twelfth interdigital structure large drive device (408), the source of the twelfth interdigital structure large drive device (408) is connected to the power supply ground VSS, the input terminal In1 of the second large drive clock controlled dual input inverter (204) is connected to the input terminal In2 of the first large drive clock controlled dual input inverter (202), the output terminal Out of the second large drive C unit structure (203) and the input terminal In of the fourth clock control structure (107), and the The input terminal In2 of the second large drive clock controlled dual-input inverter (204) is connected to the input terminal In1 of the first large drive clock controlled dual-input inverter (202), the output terminal Out of the first large drive C unit structure (201) and the input terminal In of the third clock control structure (106); the output terminal Out of the second large drive clock controlled dual-input inverter (204) is connected to the input terminals In1 of the first large drive C unit structure (201) and the second large drive C unit structure (203) and the output terminal Out of the first clock control structure (102).

10. The redundant feedback latch multi-level anti-single event hardening trigger of FinFET process according to claim 9, characterized in that: The first interdigital structure large driver device (301) comprises a PMOS tube (501) and a PMOS tube (502), wherein the source electrodes of the PMOS tube (501) and the PMOS tube (502) are connected together as the source electrode of the first interdigital structure large driver device, the gate electrodes are connected together as the gate electrode of the first interdigital structure large driver device, and the drain electrodes are connected together as the drain electrode of the first interdigital structure large driver device; The second interdigital structure large driver device (304) comprises an NMOS tube (503) and an NMOS tube (504), wherein the source electrodes of the NMOS tube (503) and the NMOS tube (504) are connected together as the source electrode of the second interdigital structure large driver device, the gate electrodes are connected together as the gate electrode of the second interdigital structure large driver device, and the drain electrodes are connected together as the drain electrode of the second interdigital structure large driver device; The third interdigital structure large driver device (305) comprises a PMOS tube (505) and a PMOS tube (506), wherein the source electrodes of the PMOS tube (505) and the PMOS tube (506) are connected together as the source electrode of the third interdigital structure large driver device, the gate electrodes are connected together as the gate electrode of the third interdigital structure large driver device, and the drain electrodes are connected together as the drain electrode of the third interdigital structure large driver device; The fourth interdigital structure large driver device (308) comprises an NMOS tube (507) and an NMOS tube (508), wherein the source electrodes of the NMOS tube (507) and the NMOS tube (508) are connected together as the source electrode of the fourth interdigital structure large driver device, the gate electrodes are connected together as the gate electrode of the fourth interdigital structure large driver device, and the drain electrodes are connected together as the drain electrode of the fourth interdigital structure large driver device; The ninth interdigital structure large driver device (401) comprises a PMOS tube (517) and a PMOS tube (518), wherein the source electrodes of the PMOS tube (517) and the PMOS tube (518) are connected together as the source electrode of the ninth interdigital structure large driver device, the gate electrodes are connected together as the gate electrode of the ninth interdigital structure large driver device, and the drain electrodes are connected together as the drain electrode of the ninth interdigital structure large driver device; The tenth interdigital structure large driver device (404) comprises an NMOS tube (519) and an NMOS tube (520), wherein the source electrodes of the NMOS tube (519) and the NMOS tube (520) are connected together as the source electrode of the tenth interdigital structure large driver device, the gate electrodes are connected together as the gate electrode of the tenth interdigital structure large driver device, and the drain electrodes are connected together as the drain electrode of the tenth interdigital structure large driver device; The eleventh interdigital structure large driver device (405) comprises a PMOS tube (521) and a PMOS tube (522), wherein the source electrodes of the PMOS tube (521) and the PMOS tube (522) are connected together as the source electrode of the eleven interdigital structure large driver device, the gate electrodes are connected together as the gate electrode of the eleven interdigital structure large driver device, and the drain electrodes are connected together as the drain electrode of the eleven interdigital structure large driver device; The twelfth interdigital structure large driver device (408) comprises an NMOS tube (523) and an NMOS tube (524), wherein the sources of the NMOS tube (523) and the NMOS tube (524) are connected together as the source of the twelfth interdigital structure large driver device, the gates are connected together as the gate of the twelfth interdigital structure large driver device, and the drains are connected together as the drain of the twelfth interdigital structure large driver device.

11. The redundant feedback latch multi-level single event hardening trigger of FinFET process according to claim 1, characterized in that: The data slave latch structure (108) includes a third large drive C unit structure (205), a fourth large drive C unit structure (207), a third large drive clock controlled dual-input inverter (206) and a fourth large drive clock controlled dual-input inverter (208); The output end Out of the third largest driving C unit structure (205) is connected to the input end In1 of the third largest driving clock-controlled dual-input inverter (206) and the input end In2 of the fourth largest driving clock-controlled dual-input inverter (208), and serves as the output end Out1 of the data slave latch structure; the output end Out of the fourth largest driving C unit structure (207) is connected to the input end In2 of the third largest driving clock-controlled dual-input inverter (206) and the input end In1 of the fourth largest driving clock-controlled dual-input inverter (208), and serves as the output end Out2 of the data slave latch structure; the output end Out of the third largest driving clock-controlled dual-input inverter (206) is connected to the input end In2 of the third largest driving C unit structure (205) and the fourth largest driving C unit structure (207), and serves as the input end In2 of the data slave latch structure; the output end Out of the fourth largest driving clock-controlled dual-input inverter (208) is connected to the third largest driving clock-controlled dual-input inverter (206) The input terminals In1 of the C unit structure (205) and the fourth largest driving C unit structure (207) are used as the input terminal In1 of the data slave latch structure; the input terminals CP of the third largest driving clock-controlled dual-input inverter (206) and the fourth largest driving clock-controlled dual-input inverter (208) are used as the input terminal CP of the data slave latch structure and are connected to the clock signal CP; the input terminals CPN of the third largest driving clock-controlled dual-input inverter (206) and the fourth largest driving clock-controlled dual-input inverter (208) are used as the input terminal CPN of the data slave latch structure and are connected to the output terminal CPN of the clock input structure (110); the input terminal In1 of the data slave latch structure is connected to the output terminal Out of the third clock control structure (106); the input terminal In2 of the data slave latch structure is connected to the output terminal Out of the fourth clock control structure (107); and the output terminal Out1 of the data slave latch structure is connected to the input terminal In of the second inverter circuit (109).

12. The redundant feedback latch multi-level single event hardening trigger of FinFET process according to claim 11, characterized in that: The third large drive clock controlled dual-input inverter (206) comprises a thirteenth interdigital structure large drive device (409), a PMOS tube (410), an NMOS tube (411) and a fourteenth interdigital structure large drive device (412); wherein the gate of the thirteenth interdigital structure large drive device (409) serves as the input terminal In1 of the third large drive clock controlled dual-input inverter (206), the gate of the PMOS tube 410 serves as the input terminal CP of the third large drive clock controlled dual-input inverter (206) connected to the clock signal CP, the gate of the NMOS tube 411 serves as the input terminal CPN of the third large drive clock controlled dual-input inverter (206) connected to the output terminal CPN of the third inverter circuit (110), and the gate of the fourteenth interdigital structure large drive device (412) serves as the input terminal In2 of the third large drive clock controlled dual-input inverter (206). The source of the thirteenth interdigital structure large driver device (409) is connected to the power supply VDD, and the drain is connected to the source of the PMOS tube (410). The drain of the PMOS tube (410) is connected to the drain of the NMOS tube (411) and serves as the output terminal Out of the third large driving clock control dual-input inverter (206). The source of the NMOS tube (411) is connected to the drain of the fourteenth interdigital structure large driver device (412). The source of the fourteenth interdigital structure large driver device (412) is connected to the power supply ground VSS. The input terminal In1 of the third largest driving clock controlled dual-input inverter (206) is simultaneously connected to the input terminal In2 of the fourth largest driving clock controlled dual-input inverter (208), the output terminal Out of the third largest driving C unit structure (205) and the input terminal In of the second inverter circuit (109); the input terminal In2 of the third largest driving clock controlled dual-input inverter (206) is simultaneously connected to the input terminal In1 of the fourth largest driving clock controlled dual-input inverter (208) and the output terminal Out of the fourth largest driving C unit structure (207); the output terminal Out of the third largest driving clock controlled dual-input inverter (206) is simultaneously connected to the input terminals In2 ​​of the third largest driving C unit structure (205) and the fourth largest driving C unit structure (207) and the output terminal Out of the fourth clock control structure (107). The fourth large drive clock controlled dual-input inverter (208) comprises a fifteenth large drive device (413) with an interdigital structure, a PMOS tube (414), an NMOS tube (415) and a sixteenth large drive device (416) with an interdigital structure; wherein the gate of the fifteenth large drive device (413) with an interdigital structure serves as the input terminal In1 of the fourth large drive clock controlled dual-input inverter (208); the gate of the PMOS tube (414) serves as the input terminal CP of the fourth large drive clock controlled dual-input inverter (208) connected to the clock signal CP; the gate of the NMOS tube (415) serves as the input terminal CPN of the fourth large drive clock controlled dual-input inverter (208) connected to the output terminal CPN of the third inverter circuit (110); and the gate of the sixteenth large drive device (416) with an interdigital structure serves as the input terminal In2 of the fourth large drive clock controlled dual-input inverter (208). The source of the fifteenth interdigital structure large driver device (413) is connected to the power supply VDD, and the drain is connected to the source of the PMOS tube (414). The drain of the PMOS tube (414) is connected to the drain of the NMOS tube (415) and serves as the output terminal Out of the fourth large driving clock control dual-input inverter (208). The source of the NMOS tube (415) is connected to the drain of the sixteenth interdigital structure large driver device (416). The source of the sixteenth interdigital structure large driver device (416) is connected to the power supply ground VSS. The input terminal In1 of the fourth largest driving clock-controlled dual-input inverter (208) is simultaneously connected to the input terminal In2 of the third largest driving clock-controlled dual-input inverter (206) and the output terminal Out of the fourth largest driving C unit structure (207); the input terminal In2 of the fourth largest driving clock-controlled dual-input inverter (208) is simultaneously connected to the input terminal In1 of the third largest driving clock-controlled dual-input inverter (206), the output terminal Out of the third largest driving C unit structure (205) and the input terminal In of the second inverter circuit (109); the output terminal Out of the fourth largest driving clock-controlled dual-input inverter (208) is simultaneously connected to the input terminals In1 of the third largest driving C unit structure (205) and the fourth largest driving C unit structure (207) and the output terminal Out of the third clock control structure (106); The third large driving C unit structure (205) comprises a fifth interdigital structure large driving device (309), a PMOS tube (310), an NMOS tube (311) and a sixth interdigital structure large driving device (312); wherein the gate electrodes of the fifth interdigital structure large driving device (309) and the sixth interdigital structure large driving device (312) are connected together as an input terminal In1 of the third large driving C unit structure (205), the gate electrodes of the PMOS tube (310) and the NMOS tube (311) are connected together as an input terminal In2 of the third large driving C unit structure (205), the source electrode of the fifth interdigital structure large driving device (309) is connected to a power supply VDD, the drain electrode is connected to a source electrode of the PMOS tube (310), the drain electrode of the PMOS tube (310) is connected to a drain electrode of the NMOS tube (311) and serves as an output terminal Out of the third large driving C unit structure (205), and the source electrode of the NMOS tube (311) is connected to the sixth interdigital structure large driving device (312). The drain of the sixth interdigital structure large driver device (312) is connected to the power ground VSS, the input terminal In1 of the third large driver C unit structure (205) is connected to the input terminal In1 of the fourth large driver C unit structure (207), the output terminal Out of the fourth large driver clock-controlled dual-input inverter (208) and the output terminal Out of the third clock control structure (106), the input terminal In2 of the third large driver C unit structure (205) is connected to the input terminal In2 of the fourth large driver C unit structure (207), the output terminal Out of the third large driver clock-controlled dual-input inverter (206) and the output terminal Out of the fourth clock control structure (107), and the output terminal Out of the third large driver C unit structure (205) is connected to the input terminal In1 of the third large driver clock-controlled dual-input inverter (206), the input terminal In2 of the fourth large driver clock-controlled dual-input inverter (208) and the input terminal In of the second inverter circuit (109); The fourth large driving C unit structure (207) comprises a seventh interdigital structure large driving device (313), a PMOS tube (314), an NMOS tube (315) and an eighth interdigital structure large driving device (316); The gates of the seventh interdigital structure large driver device (313) and the eighth interdigital structure large driver device (316) are connected together as the input terminal In1 of the fourth large driver C unit structure (207); the gates of the PMOS tube (314) and the NMOS tube (315) are connected together as the input terminal In2 of the fourth large driver C unit structure (207); the source of the seventh interdigital structure large driver device (313) is connected to the power supply VDD, the drain is connected to the source of the PMOS tube (314), the drain of the PMOS tube (314) is connected to the drain of the NMOS tube (315) and serves as the output terminal Out of the fourth large driver C unit structure (207); the source of the NMOS tube (315) is connected to the drain of the eighth interdigital structure large driver device (316), and the source of the eighth interdigital structure large driver device (316) is connected to the power supply ground. VSS, the input terminal In1 of the fourth largest driving C unit structure (207) is connected to the input terminal In1 of the third largest driving C unit structure (205), the output terminal Out of the fourth largest driving clock-controlled dual-input inverter (208) and the output terminal Out of the third clock control structure (106), the input terminal In2 of the fourth largest driving C unit structure (207) is connected to the input terminal In2 of the third largest driving C unit structure (205), the output terminal Out of the third largest driving clock-controlled dual-input inverter (206) and the output terminal Out of the fourth clock control structure (107), and the output terminal Out of the fourth largest driving C unit structure (207) is connected to the input terminal In2 of the third largest driving clock-controlled dual-input inverter (206) and the input terminal In1 of the fourth largest driving clock-controlled dual-input inverter (208).

13. The redundant feedback latch multi-level single event hardening trigger of FinFET process according to claim 12, characterized in that: The fifth interdigital structure large driver device (309) comprises a PMOS tube (509) and a PMOS tube (510), wherein the source electrodes of the PMOS tube (509) and the PMOS tube (510) are connected together as the source electrode of the fifth interdigital structure large driver device, the gate electrodes are connected together as the gate electrode of the fifth interdigital structure large driver device, and the drain electrodes are connected together as the drain electrode of the fifth interdigital structure large driver device; The sixth interdigital structure large driver device (312) comprises an NMOS tube (511) and an NMOS tube (512), wherein the source electrodes of the NMOS tube (511) and the NMOS tube (512) are connected together as the source electrode of the sixth interdigital structure large driver device, the gate electrodes are connected together as the gate electrode of the sixth interdigital structure large driver device, and the drain electrodes are connected together as the drain electrode of the sixth interdigital structure large driver device; The seventh interdigital structure large driver device (313) comprises a PMOS tube (513) and a PMOS tube (514), wherein the source electrodes of the PMOS tube (513) and the PMOS tube (514) are connected together as the source electrode of the seventh interdigital structure large driver device, the gate electrodes are connected together as the gate electrode of the seventh interdigital structure large driver device, and the drain electrodes are connected together as the drain electrode of the first interdigital structure large driver device; The eighth interdigital structure large driver device (316) comprises an NMOS tube (515) and an NMOS tube (516), wherein the source electrodes of the NMOS tube (515) and the NMOS tube (516) are connected together as the source electrode of the eighth interdigital structure large driver device, the gate electrodes are connected together as the gate electrode of the eighth interdigital structure large driver device, and the drain electrodes are connected together as the drain electrode of the eighth interdigital structure large driver device; The thirteenth interdigital structure large driver device (409) comprises a PMOS tube (525) and a PMOS tube (526), ​​wherein the source electrodes of the PMOS tube (525) and the PMOS tube (526) are connected together as the source electrode of the thirteenth interdigital structure large driver device, the gate electrodes are connected together as the gate electrode of the thirteenth interdigital structure large driver device, and the drain electrodes are connected together as the drain electrode of the thirteenth interdigital structure large driver device; The fourteenth interdigital structure large driver device (412) comprises an NMOS tube (527) and an NMOS tube (528), wherein the source electrodes of the NMOS tube (527) and the NMOS tube (528) are connected together as the source electrode of the fourteenth interdigital structure large driver device, the gate electrodes are connected together as the gate electrode of the fourteenth interdigital structure large driver device, and the drain electrodes are connected together as the drain electrode of the fourteenth interdigital structure large driver device; The fifteenth interdigital structure large driver device (413) comprises a PMOS tube (529) and a PMOS tube (530), wherein the source electrodes of the PMOS tube (529) and the PMOS tube (530) are connected together as the source electrode of the fifteenth interdigital structure large driver device, the gate electrodes are connected together as the gate electrode of the fifteenth interdigital structure large driver device, and the drain electrodes are connected together as the drain electrode of the fifteenth interdigital structure large driver device; The sixteenth interdigital structure large driver device (416) comprises an NMOS tube (531) and an NMOS tube (532), wherein the sources of the NMOS tube (531) and the NMOS tube (532) are connected together as the source of the sixteenth interdigital structure large driver device, the gates are connected together as the gate of the sixteenth interdigital structure large driver device, and the drains are connected together as the drain of the sixteenth interdigital structure large driver device.

14. The redundant feedback latch multi-level single event hardening trigger of FinFET process according to claim 1, characterized in that: The delay structure (103) comprises a PMOS tube (801), a PMOS tube (803), an NMOS tube (802) and an NMOS tube (804); wherein the source of the PMOS tube (801) is connected to a power supply VDD, the gates of the PMOS tube (801) and the NMOS tube (802) are connected together as an input terminal In of the delay structure, the drain of the PMOS tube (801) is connected to the drain of the NMOS tube (802) and is connected to the gates of the PMOS tube (803) and the NMOS tube (804), and the gates of the NMOS tube (804) are connected together. The source of (802) is connected to the power ground VSS, the source of the PMOS tube (803) is connected to the power supply VDD, the source of the NMOS tube (804) is connected to the power ground VSS, the drains of the PMOS tube (803) and the NMOS tube (804) are connected together as the output end Out of the delay structure, the input end In of the delay structure is connected to the output end Out of the data input structure (101) and the input end In of the first clock control structure (102), and the output end Out of the delay structure is connected to the input end In of the second clock control structure (104).

15. The redundant feedback latch multi-level single event hardened trigger of FinFET process according to claim 1, characterized in that: The data output structure (109) is composed of a second inverter circuit, which includes a PMOS transistor (603) and an NMOS transistor (604), wherein the gates of the PMOS transistor (603) and the NMOS transistor (604) are connected together as an input terminal In of the second inverter circuit, the source of the PMOS transistor (603) is connected to a power supply VDD, the drain is connected to the drain of the NMOS transistor (604) and serves as an output terminal Out of the second inverter circuit, the source of the NMOS transistor (604) is connected to a power supply ground VSS, the input terminal In of the second inverter circuit is connected to an output terminal Out1 of the data slave latch structure (108), and the output terminal Out serves as an output signal Output of the trigger.

16. The redundant feedback latch multi-level single event hardened trigger of FinFET process according to claim 1, characterized in that: FinFET adds a protrusion on the insulating substrate, and its channel is surrounded by a gate. FinFET devices expand the transistor structure from two-dimensional to three-dimensional. The calculation formula for the effective width of the active area is as follows: IN Fin-eff =N Fin-eff *(2H Fin +T Fin ) Among them, H Fin Fin high, T Fin Fin width, N Fin-eff N is the number of effective Fins of the device. Fin-eff =1,2,···n; Where N Fin-eff =N Fin / Pit *N Finger , N Fin / Pit N is the number of Fins per unit gate spacing. Finger is the number of parallel transistors after using the interdigital structure.

17. The redundant feedback latch multi-level single event hardening trigger of FinFET process according to claim 1, characterized in that: include: The number of Fins within a unit pitch is designed to be the maximum, the devices at sensitive nodes are designed to be interdigitated structures, and the sensitive node pairs are designed to be cross-isolated layouts, thus achieving single-particle radiation hardening of FinFET process triggers under low-cost conditions.

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