Single event upset resistant latch circuit structure with fewer sensitive nodes

Abstract

The invention discloses an anti-single event upset latch circuit structure with fewer sensitive nodes. The anti-single event upset latch circuit structure comprises a clock filter circuit, a delay filter circuit, a latch circuit and a stacked inverter circuit. The clock filter circuit is used for filtering single-particle transient pulses at a clock end and providing clock signals for the latch circuit. The delay filter circuit is used for filtering single-particle transient pulses of a data end and providing input signals for the latch circuit. And the latch circuit is used for realizing data transmission and latch, and maintaining a correct signal output state and level correction after single-particle radiation in a latch state. The stacked inverter circuit is used for providing an inversion signal. The designed latch circuit can realize single-particle transient reinforcement and single-particle transient pulse filtering, has few circuit sensitive nodes, is good in reinforcement effect, and is simple and easy to realize.

Description

Technical Field

[0001] The invention relates to a single-particle flip-resistant latch circuit structure with fewer sensitive nodes, belonging to the technical field of circuit-level radiation-resistant reinforcement. Background Art

[0002] With the continuous development of microelectronics technology, more and more electronic devices need to be applied in various space radiation environments. Radiation effects such as single event effect, total dose effect, displacement damage effect, and instantaneous dose rate have become important threats to the reliability of aerospace integrated circuits, among which the severity of single event effect (SEE) is becoming more and more prominent. Single event effect refers to the fact that after high-energy particles bombard semiconductor devices, a large number of electron-hole pairs are ionized inside the semiconductor and captured by the active area, causing circuit data errors or even permanent damage.

[0003] According to the different types of errors caused, single event effects can be divided into two categories: one is manifested as irreversible permanent damage to electronic devices, called hard errors. Such as single particle gate penetration, single particle burnout, single particle latch, etc. The other is manifested as a transient error in the logic state of the circuit, called a soft error. Including single particle transient, single particle flip, etc. Among them, the single event upset (SEU) effect is one of the most common types of soft errors in digital integrated circuits. For sequential logic circuits, when carriers are collected by sensitive nodes under the action of electric field and concentration, it will cause logic level errors and cause flips.

[0004] Latches are the basic units that constitute trigger circuits, and it is crucial to ensure their radiation resistance. At present, the widely used single-particle upset reinforcement methods mainly include triple-mode redundant structure (TMR), dual-terminal interlocked storage cell (DICE), etc. Although these traditional reinforcement methods have certain single-particle upset resistance capabilities, due to the problems of many sensitive nodes and large area overhead in the above structures, as the size of integrated circuit processes continues to shrink, particles are more likely to bombard sensitive nodes, resulting in reduced reinforcement capabilities. Summary of the invention

[0005] The technical problem solved by the present invention is: to overcome the shortcomings of the prior art and provide a single-particle flip-resistant latch circuit structure with fewer sensitive nodes, in which any node flip can pull the erroneous data back to the correct value, thereby achieving the effect of resisting single-node flip.

[0006] The technical solution of the present invention is:

[0007] The present invention discloses a single-particle flip-resistant latch circuit structure with fewer sensitive nodes, comprising: a clock filter circuit, a delay filter circuit, a latch circuit and a stacked inverter circuit; wherein:

[0008] The input end of the clock filter circuit is connected to the clock signal CLK, and the output end signals CLKN and CLKNN of the clock filter circuit are connected to the clock input end of the latch circuit. The clock filter circuit is used to provide the clock signal to the latch circuit and realize single-particle transient pulse filtering at the clock end;

[0009] The input end of the delay filter circuit is connected to the input signal D, and the output end of the delay filter circuit is connected to the input end of the latch circuit; the delay filter circuit includes a delay unit and a C unit, which is used to provide an input signal to the latch circuit and filter the single-particle transient pulse generated by the input signal;

[0010] The output end of the latch circuit is connected to the input end of the stacked inverter circuit; the latch circuit is used to realize data transmission and latching, and realize single-particle upset resistance in the latched state;

[0011] The output end of the stacked inverter circuit is connected to the output signal Q; the stacked inverter circuit is used to achieve the inversion of the logic level and keep the output level consistent with the input.

[0012] Furthermore, in the above circuit structure, the clock filtering circuit includes a first delay unit, a first C unit and a stacked inverter unit; wherein the input end of the first delay unit is connected to the clock input signal CLK; the input end of the first C unit is connected to the clock signal CLK and the output end of the first delay unit, and the output end of the first C unit is connected to the output signal CLKN and the input end of the stacked inverter unit; and the output end of the stacked inverter unit is connected to the output signal CLKNN.

[0013] Further, in the above circuit structure, the first delay unit is an n-stage cascaded stacked inverter unit; the m-th stage stacked inverter unit includes PMOS transistors Pm1, Pm2 and NMOS transistors Nm1, Nm2; the gates of the PMOS transistors Pm1, Pm2 and the NMOS transistors Nm1, Nm2 are connected as the input end of the stacked inverter unit, connected to the output end of the m-1-th stage inverter, the source of the PMOS transistor Pm1 is connected to the power supply signal VDD, and the drain of the PMOS transistor Pm1 is connected to the source of the PMOS transistor Pm2; the drain of the PMOS transistor Pm2 is connected to the drain of Nm1, and as the output end of the m-th stage inverter, connected to the input end of the m+1-th stage inverter; the source of the NMOS transistor Nm1 is connected to the drain of the NMOS transistor Nm2; the source of the NMOS transistor Nm2 is connected to the power ground signal GND; wherein, n≥m≥1.

[0014] Further, in the above circuit structure, the first C unit includes PMOS transistors P101 and P102 and NMOS transistors N101 and N102; the gate of the PMOS transistor P101 is connected to the gate of the NMOS transistor N101 and serves as the first input terminal of the C unit and is connected to the input clock signal CLK, the source of the PMOS transistor P101 is connected to the power supply VDD, and the drain of the PMOS transistor P101 is connected to the source of the PMOS transistor P102; the gate of the PMOS transistor P102 is connected to the gate of N102 and serves as the second input terminal of the C unit and is connected to the output terminal of the first delay unit, the drain of the PMOS transistor P102 is connected to the drain of the NMOS transistor N101 and is connected as the output terminal of the C unit and is connected to the reverse output clock signal CLKN; the source of the NMOS transistor N101 is connected to the drain of the NMOS transistor N102; the source of the NMOS transistor N102 is connected to the power ground GND;

[0015] Further, in the above circuit structure, the stacked inverter unit includes PMOS transistors P103, P104, and NMOS transistors N103, N104; the gates of the PMOS transistors P103, P104 and the NMOS transistors N103, N104 are connected and serve as the input end of the stacked inverter unit, connected to the output end of the first C unit, the source of the PMOS transistor P103 is connected to the power supply VDD, and the drain of the PMOS transistor P103 is connected to the source of the PMOS transistor P104; the drain of the PMOS transistor P104 is connected to the drain of the NMOS transistor N103, and serves as the output end of the stacked inverter unit, connected to the output clock signal CLKNN; the source of the NMOS transistor N103 is connected to the drain of the NMOS transistor N104; the source of the NMOS transistor N104 is connected to the power ground GND.

[0016] Further, in the above circuit structure, the delay filter circuit includes a second delay unit and a second C unit; wherein the input end of the second delay unit is connected to the input signal D; the input end of the second C unit is connected to the input signal D and the output end of the second delay unit, and the output end of the second C unit is connected to the input end of the latch circuit;

[0017] The second C unit includes PMOS transistors P201, P202 and NMOS transistors N201, N202; the gate of the PMOS transistor P201 is connected to the gate of the NMOS transistor N201 and serves as the first input terminal of the second C unit and is connected to the input signal D, the source of the PMOS transistor P201 is connected to the power supply VDD, and the drain of the PMOS transistor P201 is connected to the source of the PMOS transistor P202; the gate of the PMOS transistor P202 is connected to the gate of N202 and serves as the second input terminal of the second C unit and is connected to the output terminal of the second delay unit, the drain of the PMOS transistor P202 is connected to the drain of the NMOS transistor N201 and serves as the output terminal of the second C unit and is connected to the input terminal of the latch circuit; the source of the NMOS transistor N201 is connected to the drain of the NMOS transistor N202; the source of the NMOS transistor N202 is connected to the power ground GND.

[0018] Further, in the above circuit structure, the latch circuit includes a first-stage clocked inverter unit, a second-stage clocked inverter unit, a first-stage clocked stacked inverter unit, a second-stage clocked stacked inverter unit and a third C unit; wherein the data input end of the first-stage clocked inverter is connected to the data input end of the second-stage clocked inverter, and is connected to the output end of the delay filter unit as the input end of the latch circuit; the first and second clock input ends of the first-stage clocked inverter are respectively connected to the output signals CLKN and CLKNN of the clock filter; the output end of the first-stage clocked inverter is connected to the second data input end of the first-stage clocked stacked inverter unit, the second input end of the third C unit, and the output end of the second-stage clocked stacked inverter unit;

[0019] The first and second clock input terminals of the second-stage clocked inverter are connected to the output signals CLKN and CLKNN of the clock filter; the output terminal of the second-stage clocked inverter is connected to the second data input terminal of the second-stage clocked stacked inverter unit, the first input terminal of the third C unit and the output terminal of the first-stage clocked stacked inverter unit;

[0020] The first and second clock input terminals of the first-stage clock-controlled stacked inverter unit are respectively connected to the output signals CLKNN and CLKN of the clock filter; the first data input terminal of the first-stage clock-controlled stacked inverter unit is connected to the output terminal of the third C unit and the first data input terminal of the second-stage clock-controlled stacked inverter unit, and is used as the output terminal of the latch circuit and connected to the input terminal of the stacked inverter circuit; the first and second clock input terminals of the second-stage clock-controlled stacked inverter unit are respectively connected to the output signals CLKNN and CLKN of the clock filter circuit;

[0021] Furthermore, in the above circuit structure, the first-stage clocked inverter circuit includes PMOS transistors P311 and P312 and NMOS transistors N311 and N312. The gate of the PMOS transistor P311 is connected to the gate of the NMOS transistor N312 and is connected to the output of the delay filter circuit as the data input of the first-stage clocked inverter circuit. The source of the PMOS transistor P311 is connected to the power supply VDD, and the drain of the PMOS transistor P311 is connected to the source of the PMOS transistor P312. The gate of the S transistor P312 is connected to the output signal CLKN of the clock filter circuit as a first clock input terminal, the drain of the PMOS transistor P312 is connected to the drain of the NMOS transistor N311 and serves as the output terminal of the first-stage clock-controlled inverter circuit; the gate of the NMOS transistor N311 is connected to the output signal CLKNN of the clock filter circuit as a second clock input terminal, the source of the NMOS transistor N311 is connected to the drain of the NMOS transistor N312; the source of the NMOS transistor N312 is connected to the power ground GND;

[0022] The second-stage clocked inverter circuit includes PMOS transistors P321 and P322 and NMOS transistors N321 and N322. The gate of the PMOS transistor P321 is connected to the gate of N322 and is connected to the output of the delay filter circuit as a data input of the second-stage clocked inverter circuit. The source of the PMOS transistor P321 is connected to the power supply VDD, and the drain of the PMOS transistor P321 is connected to the source of P322. The gate of the PMOS transistor P322 is connected to the output signal CLKN of the clock filter circuit as a first clock input, and the drain of the PMOS transistor P322 is connected to the drain of the NMOS transistor N321 and is used as the output of the second-stage clocked inverter circuit. The gate of the NMOS transistor N321 is connected to the output signal CLKNN of the clock filter circuit as a second clock input, and the source of the NMOS transistor N321 is connected to the drain of the NMOS transistor N322. The source of the NMOS transistor N322 is connected to the power ground GND.

[0023] Further, in the above circuit structure, the first-stage clocked stacked inverter circuit includes PMOS transistors P331, P332, P333 and NMOS transistors N331, N332, N333; the gate of the PMOS transistor P331 is connected to the gate of the NMOS transistor N333 and serves as the first data input terminal of the clocked stacked inverter circuit, connected to the output terminal of the third C unit; the source of the PMOS transistor P331 is connected to the power supply signal VDD, and the drain of the PMOS transistor P331 is connected to the source of the PMOS transistor P332; the gate of the PMOS transistor P332 serves as the first clock input terminal of the clocked stacked inverter circuit, connected to the output signal CLKNN of the clock delay circuit, and the drain of the PMOS transistor P332 is connected to the NMOS transistor N331 The source of the NMOS transistor N331; the gate of the NMOS transistor N331 is connected to the gate of the PMOS transistor P333, and serves as the second data input terminal of the clocked stack inverter circuit, connected to the output terminal of the first-stage clocked inverter; the drain of the NMOS transistor N331 is connected to the drain of the PMOS transistor P333, and serves as the output terminal of the clocked stack inverter circuit, connected to the output terminal of the second-stage clocked inverter; the source of the PMOS transistor P333 is connected to the drain of the NMOS transistor N332; the gate of the NMOS transistor N332 serves as the second clock input terminal of the clocked stack inverter circuit, connected to the output signal CLKN of the clock delay circuit, the source of the NMOS transistor N332 is connected to the drain of the NMOS transistor N333; the source of the NMOS transistor N333 is connected to the power ground GND;

[0024] The second-stage clocked stacked inverter circuit includes PMOS transistors P341, P342, P343 and NMOS transistors N341, N342, N343; the gate of the PMOS transistor P341 is connected to the gate of the NMOS transistor N343 and serves as the first data input terminal of the clocked stacked inverter circuit and is connected to the output terminal of the third C unit; the source of the PMOS transistor P341 is connected to the power supply signal VDD, and the drain of the PMOS transistor P341 is connected to the source of the PMOS transistor P342; the gate of the PMOS transistor P342 serves as the first clock input terminal of the clocked stacked inverter circuit and is connected to the output signal CLKNN of the clock delay circuit, and the drain of the PMOS transistor P342 is connected to the source of the NMOS transistor N341; The gate of the MOS transistor N341 is connected to the gate of the PMOS transistor P343 and serves as the second data input terminal of the clocked stack inverter circuit, connected to the output terminal of the second-stage clocked inverter; the drain of the NMOS transistor N341 is connected to the drain of the PMOS transistor P343 and serves as the output terminal of the clocked stack inverter circuit, connected to the output terminal of the first-stage clocked inverter; the source of the PMOS transistor P343 is connected to the drain of the NMOS transistor N342; the gate of the NMOS transistor N342 serves as the second clock input terminal of the clocked stack inverter circuit, connected to the output signal CLKN of the clock delay circuit, the source of the NMOS transistor N342 is connected to the drain of the NMOS transistor N343; the source of the NMOS transistor N343 is connected to the power ground GND;

[0025] The third C unit includes PMOS transistors P351, P352 and NMOS transistors N351, N352; the gate of the PMOS transistor P351 is connected to the gate of the NMOS transistor N351, and serves as the first input terminal of the C unit, connected to the output terminal of the second-stage clocked inverter circuit, the source of the PMOS transistor P351 is connected to the power supply VDD, and the drain of the PMOS transistor P351 is connected to the source of the PMOS transistor P352; the gate of the PMOS transistor P352 is connected to the gate of N352, and serves as the second input terminal of the C unit, connected to the output terminal of the first-stage clocked inverter circuit, the drain of the PMOS transistor P352 is connected to the drain of the NMOS transistor N351, and serves as the output terminal of the third C unit, connected to the input terminal of the stacked transistor circuit; the source of the NMOS transistor N351 is connected to the drain of the NMOS transistor N352; the source of the NMOS transistor N352 is connected to the power ground GND.

[0026] Furthermore, in the above circuit structure, the transistor stacking circuit includes PMOS transistors P401, P402 and NMOS transistors N401, N402; wherein, the gates of the PMOS transistors P401, P402, NMOS transistors N401 and N402 are connected and serve as the input of the stacked inverter unit, connected to the output of the latch circuit, the source of the PMOS transistor P401 is connected to the power supply VDD, and the drain of the PMOS transistor P401 is connected to the source of the PMOS transistor P402; the drain of the PMOS transistor P402 is connected to the drain of the NMOS transistor N401, and serves as the output of the transistor stacking circuit, connected to the output signal Q; the source of the NMOS transistor N401 is connected to the drain of the NMOS transistor N402; and the source of the NMOS transistor N402 is connected to the power ground GND.

[0027] The beneficial effects of the present invention and the prior art are:

[0028] (1) The present invention provides a single-particle upset-resistant latch circuit structure with fewer sensitive nodes, which uses a delay filter structure to filter out SET pulses at the clock and data input terminals, uses a C unit structure to implement single-particle upset reinforcement in a latched state, and implements internal node level correction in a latched state based on a redundant interlocking structure.

[0029] (2) The circuit structure provided by the present invention has good single particle resistance performance, fewer sensitive nodes, low overhead and is easy to implement. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 It is a circuit structure principle diagram of the present invention;

[0031] Figure 2 is a structural diagram of a clock delay circuit in the circuit structure of the present invention;

[0032] Figure 3 It is a structural diagram of a clock delay module in the circuit structure of the present invention;

[0033] Figure 4 is a structural diagram of a time delay filter circuit in the circuit structure of the present invention;

[0034] Figure 5 It is a principle diagram and a structure diagram of a latch circuit in the circuit structure of the present invention;

[0035] Figure 6 A schematic diagram of a clocked inverter unit in a latch circuit structure of the present invention;

[0036] Figure 7 A schematic diagram of a clocked stacked inverter unit in a latch circuit structure of the present invention;

[0037] Figure 8 A schematic diagram of a C unit in a latch circuit structure of the present invention;

[0038] Fig. 9 It is a circuit structure diagram of stacked inverters in the circuit structure of the present invention. DETAILED DESCRIPTION

[0039] The present invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0040] The present invention will be further described below in conjunction with the accompanying drawings.

[0041] All features disclosed in this specification, or steps in all methods or processes disclosed, except mutually exclusive features and / or steps, can be combined in any manner.

[0042] Any feature disclosed in this specification, unless otherwise stated, may be replaced by other alternative features that are equivalent or have similar purposes.

[0043] The present invention utilizes a clock filter circuit 001 and a delay filter circuit 002 composed of a delay circuit and a C unit to implement single-particle transient pulse filtering at the clock and input signal ends; and utilizes a latch circuit unit 003 with fewer sensitive nodes composed of a redundant feedback network and C units to implement single-particle upset reinforcement in a latched state and correction of the internal storage node level.

[0044] Figure 1 The figure shows a schematic diagram of a circuit structure of a single-particle upset-resistant latch with fewer sensitive nodes provided by an example of the present invention. It includes a clock filter circuit 001, a delay filter circuit 002, a latch circuit 003 and a stacked inverter circuit 004. The delay filter structure composed of the delay unit and the C unit filters out the SET pulses at the clock end and the input data port; the feedback structure designed inside the latch circuit realizes SEU reinforcement and level recovery.

[0045] Figure 2 The figure shows the implementation form of the clock filter circuit 001, which is composed of a delay unit, a C unit and a stacked inverter unit. The delay unit and the C unit are used to filter the SET pulse, and the stacked inverter is used to provide a reverse clock signal. The input end of the clock filter circuit 001 is connected to the clock signal CLK, and the output end signals CLKN and CLKNN of the clock filter circuit 001 are connected to the input end of the latch circuit 003.

[0046] The first C unit 102 is composed of PMOS transistors P101 and P102 and NMOS transistors N101 and N102; the gate of P101 is connected to the gate of NMOS transistor N101 and serves as the first input terminal of the C unit and is connected to the input clock signal CLK; the source of P101 is connected to the power supply VDD; the drain of P101 is connected to the source of PMOS transistor P102; the gate of P102 is connected to the gate of N102 and serves as the second input terminal of the C unit; the drain of P102 is connected to the drain of NMOS transistor N101 and is connected as the output terminal of the C unit and is connected to the reverse output clock signal CLKN; the source of N101 is connected to the gate of NMOS transistor N101 and is connected to the reverse output clock signal CLKN. The drain of the body tube N102; the source of N102 is connected to the power supply ground GND; the stacked inverter unit 103 is composed of PMOS transistors P103, P104, and NMOS transistors N103 and N104; the gates of P103, P104, N103 and N104 are connected and serve as the input end of the stacked inverter unit 103, the source of P103 is connected to the power supply VDD, and the drain of P103 is connected to the source of P104; the drain of P104 is connected to the drain of N103 and serves as the output end of the stacked circuit and is connected to CLKNN; the source of N103 is connected to the drain of the NMOS transistor N104; the source of the NMOS transistor N104 is connected to the power supply ground GND;

[0047] The principle of clock filtering circuit to achieve SET reinforcement is as follows: CLK and the signal CN output through the delay unit are respectively used as the two inputs of the C unit, where the delay value is determined by the SET pulse width. For the C unit, the C unit outputs an inverted signal when and only when the signals at the first input end and the second input end are the same. When the level states of the two input ends are inconsistent, the output level of the C unit is in a hold state. Therefore, when the clock input signal CLK generates a SET pulse, under the effect of the delay, the logic levels of the CLK and CN ends are inconsistent, and the C unit is in a hold state, maintaining the correct level before the SET is generated until the delay pulse at the CN end ends, and the C unit is in an inverted output state. Therefore, the SET pulse does not affect the output of the C unit, thereby realizing SET pulse filtering at the clock end.

[0048] Figure 3 The figure shows the implementation form of the delay filter unit 002. It is composed of a delay unit and a C unit. The input end of the delay unit 202 is connected to the input signal D; the input end of the second C unit 202 is connected to the input signal D and the output end of the second delay unit 201, and the output end of the second C unit 202 is connected to the input end of the latch circuit 003. The circuit can realize SET pulse filtering at the input data end, and its implementation principle is similar to that of the clock filter circuit.

[0049] The second C unit 202 is composed of PMOS transistors P201, P202 and NMOS transistors N201, N202; the gate of P201 is connected to the gate of NMOS transistor N201 and serves as the first input terminal of the C unit, connected to the input signal D, the source of P201 is connected to the power supply VDD, and the drain of P201 is connected to the source of the PMOS transistor P202; the gate of P202 is connected to the gate of N202 and serves as the second input terminal of the C unit, connected to the output terminal of the second delay unit 201, the drain of P202 is connected to the drain of the NMOS transistor N201, and serves as the output terminal of the C unit, connected to the input terminal of the latch circuit 003; the source of N201 is connected to the drain of the NMOS transistor N202; the source of N202 is connected to the power ground GND.

[0050] Figure 4 The figure shows the implementation of the delay units 101 and 102 inside the clock filter circuit 001 and the delay filter circuit 002. The delay unit is an n-stage cascaded stacked inverter unit, which is composed of PMOS transistors P11, P12, P21, P22...Pm1, Pm2...Pn1, Pn2 and NMOS transistors N11, N12, N21, N22...Nm1, Nm2...Nn1, Nn2, where m and n represent the number of inverter stages, m<n; taking the mth stage stacked inverter as an example, the gates of the PMOS transistors Pm1, Pm2, Nm1, Nm2 are connected as the mth stage stacked inverter. The input end of the inverter is connected to the output end of the m-1th inverter, the source of the PMOS transistor Pm1 is connected to the power supply signal VDD, and the drain of Pm1 is connected to the source of the PMOS transistor Pm2; the drain of the PMOS transistor Pm2 is connected to the drain of Nm1 and serves as the output end of the mth inverter, connected to the input end of the m+1th inverter; the source of the NMOS transistor Nm1 is connected to the drain of the NMOS transistor Nm2; the source of the NMOS transistor Nm2 is connected to the power ground signal GND.

[0051] The delay unit uses a multi-stage cascade structure to achieve SET pulse delay based on the delay characteristics of the inverter. The number of cascaded inverters in series is determined by the SET pulse width. In circuit design, the delay unit uses a stacked inverter structure, which can save layout area while keeping the number of transistors the same.

[0052] Figure 5The structure and circuit implementation form of the latch circuit in the circuit structure of the present invention; the latch circuit 003 is composed of a first-stage clocked inverter unit 301, a second-stage clocked inverter unit 302, a first-stage clocked stacked inverter unit 303, a second-stage clocked stacked inverter unit 304 and a third C unit 305; the data input end of the first-stage clocked inverter 301 is connected to the data input end of the second-stage clocked inverter 302, and is connected to the output end of the delay filter unit 002 as the input end of the latch circuit; the first and second clock input ends of the first-stage clocked inverter 301 are respectively connected to the output signals CLKN and CLKNN of the clock filter 001; the output end of the first-stage clocked inverter 301 is connected to the second data input end of the first-stage clocked stacked inverter unit 303, the second input end of the third C unit 305, and the output end of the second-stage clocked stacked inverter unit 304;

[0053] The first and second clock input terminals of the second-stage clocked inverter 302 are connected to the output signals CLKN and CLKNN of the clock filter 001; the output terminal of the second-stage clocked inverter 302 is connected to the second data input terminal of the second-stage clocked stacked inverter unit 304, the first input terminal of the third C unit 305 and the output terminal of the first-stage clocked stacked inverter unit 303;

[0054] The first and second clock input terminals of the first-stage clock-controlled stacked inverter unit 303 are respectively connected to the output signals CLKNN and CLKN of the clock filter 001; the first data input terminal of the first-stage clock-controlled stacked inverter unit 303 is connected to the output terminal of the third C unit 305 and the first data input terminal of the second-stage clock-controlled stacked inverter unit 304, and is connected to the input terminal of the stacked inverter circuit 004 as the output terminal of the latch circuit; the first and second clock input terminals of the second-stage clock-controlled stacked inverter unit 304 are respectively connected to the output signals CLKNN and CLKN of the clock filter circuit 001;

[0055] The latch circuit structure adopts a redundant feedback network circuit structure combined with a C unit to prevent the output level flip caused by a single particle flip at the node; and a pair of pull-up NMOS and pull-down PMOS are added inside the circuit to effectively avoid the propagation of single particle flips and promote the recovery of logic levels. Compared with the traditional DICE structure, the latch part of this circuit has only three sensitive nodes N1, N2 and N3. When any sensitive node flips, the erroneous data can be pulled back to the correct value through the feedback mechanism or the C unit structure, realizing anti-single node flip reinforcement.

[0056] Since N1 and N2 are symmetrical in the circuit structure, only the flipping of N1 and N3 nodes is described below. When node N1 flips 1-0, N2 is in a high level state. Under the action of the C unit, the output terminal N3 maintains the low level state before the flip, and the output Q state does not change, thereby achieving SEU reinforcement. The clocked stacked inverter 303 is in the off state due to the pull-up NMOS transistor N331, so the error of N1 will not propagate to N2 via the clocked stacked inverter 303, and the clocked stacked inverter 304 is still in the on state and outputs a high level. Since its output terminal is connected to the node N1, it can promote the correction of the N1 level state.

[0057] When N1 flips from 0 to 1, N2 is in a low level state. Under the action of the third C unit 305, the level state of node N3 remains high, and the Q terminal is in a correct low level state. The clocked stack circuit 303 is in an off state due to the pull-down network PMOS transistor P333, so the flip of N1 does not affect the logic state of N2. The clocked stack inverter 304 is still in the on state and outputs a low level, which can promote the recovery of the level of the N1 node.

[0058] When N3 flips from 0 to 1, under the clamping effect of the pull-up NMOS transistor and the pull-down PMOS on the output level of the clocked stacked inverter circuit, the clocked stacked circuits 303 and 304 are both in the off state, so the flip of N3 will not affect N1 and N2, and N1 and N2 both remain in the correct high level state. And N1 and N2 output the correct low level logic through the C unit, which can realize the self-recovery of the N3 node state.

[0059] Figure 6 The first clocked inverter 301 and the second clocked inverter 302 in the latch circuit structure of the present invention are implemented in the form; the two circuit structures are the same and the electrical connections are complementary. Taking the first-stage clocked inverter circuit 301 as an example, it is composed of PMOS transistors P311, P312 and NMOS transistors N311, N312, the gate of P311 is connected to the gate of N312, and is connected to DIN as the data input terminal of the first-stage clocked inverter circuit, the source of P311 is connected to the power supply VDD, and the drain of P311 is connected to the source of P312; the gate of PMOS transistor P312 is connected to CLKN as the first clock input terminal, the drain of P312 is connected to the drain of NMOS transistor N311, and is used as the output terminal of the clocked inverter circuit; the gate of N311 is connected to CLKNN as the second clock input terminal, the source of N311 is connected to the drain of N312; the source of N312 is connected to the power ground GND.

[0060] Compared with the traditional inverter unit, the clock-controlled inverter circuit adds a clock control terminal to achieve data transmission with low power consumption. In the latch transparent state, CLKN is in a low level state and CLKNN is in a high level state. In this case, the clock-controlled inverter unit is turned on and data transmission is achieved through the C unit; in the latched state, the clock-controlled inverter unit is in a turned-off state and will not affect the latch circuit.

[0061] Figure 7 It is an implementation method of the first-stage clocked stacked inverter circuit 303 and the second-stage clocked stacked inverter circuit 304 in the latch circuit structure of the present invention; the two circuit structures are the same, and the electrical connection is a complementary relationship. Taking the first-stage clocked stacked inverter circuit 303 as an example, it is composed of PMOS transistors P331, P332, P333 and NMOS transistors N331, N332, N333; the gate of P331 is connected to the gate of NMOS transistor N333, and is connected to N3 as the first data input terminal of the clocked stacked inverter circuit; the source of P331 is connected to the power supply signal VDD, and the drain of P331 is connected to the source of PMOS transistor P332; the gate of P332 is connected to CLKNN as the first clock input terminal of the clocked stacked inverter circuit, and the drain of P332 is connected to NMOS transistor N3 The gate of N331 is connected to the gate of PMOS transistor P333, and is connected to N1 as the second data input terminal of the clocked stacked inverter circuit; the drain of N331 is connected to the drain of PMOS transistor P333, and is connected to N2 as the output terminal of the clocked stacked inverter circuit 303; the source of PMOS transistor P333 is connected to the drain of NMOS transistor N332; the gate of NMOS transistor N332 is connected to the signal CLKN as the second clock input terminal of the clocked stacked inverter circuit, the source of N332 is connected to the drain of N333; the source of N333 is connected to the power ground GND.

[0062] The implementation principle is explained by taking the clocked stacked inverter circuit 303 as an example: compared with the traditional inverter structure, the stacked inverter structure adds a pair of complementary clock control signals. The inverter circuit is in a working state only when the latch is in a latched state; when the latch is in a transparent state, since the clock-controlled P NMOS are all turned on, the circuit is always in an off state.

[0063] In addition, the clocked stacked inverter also inserts an NMOS transistor N331 in the pull-up PMOS network and a PMOS transistor P333 in the pull-down NMOS network, and serves as the second data input terminal of the inverter circuit. This structure enhances the level clamping effect of the inverter. In the latched state, when and only when the first data input terminal N3 is at a high level. When the second data input terminal N1 is at a low level, the pull-down network is turned on, and the clocked stacked inverter output terminal N2 outputs a low level; and when and only when the first data input terminal N3 is at a low level and the second data input terminal N1 is at a high level, the pull-up network is turned on, and the clocked stacked inverter output terminal N2 outputs a high level. When the inverter input terminal N1 or N3 is flipped, since both the pull-up network and the pull-down network are not turned on, the circuit is still in the off state, and the error will not propagate along the inverter to the output terminal N2.

[0064] Figure 8 The third C unit 305 in the latch circuit structure of the present invention is realized by PMOS transistors P351 and P352 and NMOS transistors N351 and N352; the gate of P351 is connected to the gate of N351 and serves as the first input terminal of the C unit, connected to the output terminal N2 of the second-stage clocked inverter circuit 302; the source of P351 is connected to the power supply VDD; the drain of P351 is connected to the source of the PMOS transistor P352; the gate of P352 is connected to the gate of N352 and serves as the second input terminal of the C unit, connected to the output terminal N1 of the first-stage clocked inverter circuit 301; the drain of P352 is connected to the drain of the NMOS transistor N351 and serves as the output terminal of the C unit and connected to N3; the source of N351 is connected to the drain of the NMOS transistor N352; the source of N352 is connected to the power ground GND;

[0065] The implementation principle is as follows: when the input signals N1 and N2 are the same, the C unit circuit N3 outputs a reverse signal; when the N1 and N2 signals are different, the C unit output N3 output maintains the current state. Therefore, when a single-particle flip occurs in one of the two inputs, the error number will not be transmitted to the output end, thus playing the role of single-particle reinforcement.

[0066] Fig. 9This is an implementation method of the stacked inverter circuit 004 in the circuit structure of the present invention, wherein the gates of the PMOS transistors P401, P402, N401 and N402 are connected and serve as the input end of the stacked inverter unit 004, connected to the output end N3 of the latch circuit 003, the source of the PMOS transistor P401 is connected to the power supply VDD, and the drain is connected to the source of the PMOS transistor P402; the drain of the PMOS transistor P402 is connected to the drain of the NMOS transistor N401, and serves as the output end of the stacked circuit to connect the output signal Q; the source of the NMOS transistor N401 is connected to the drain of the NMOS transistor N402; the source of the NMOS transistor N402 is connected to the power ground GND.

[0067] The function of the stacked inverter circuit is to output the inverted signal of N3 to achieve the correct signal output Q, and the stacked inverter unit has a certain ability to resist single particles. Taking the state of high input as an example, the pull-up PMOS network is turned off and the pull-down NMOS network is turned on. If any of the PMOS transistors is bombarded by a single particle and becomes turned on, since the other series PMOS is not turned on, the pull-up network will not be turned on, and the output level is still not in the correct low level state.

[0068] Contents not described in detail in the specification of the present invention belong to the well-known technologies of professionals in the field. Although the embodiments of the present invention are described in conjunction with the drawings, ordinary technicians in the field can make various modifications or changes within the scope of the attached claims.

[0069] Although the content of the present invention has been described in detail through the above preferred embodiments, it should be appreciated that the above description should not be considered as a limitation of the present invention. After reading the above content, it will be apparent to those skilled in the art that various modifications and substitutions of the present invention will occur. Therefore, the protection scope of the present invention should be limited by the appended claims.

[0070] The contents not described in detail in the specification of the present invention belong to the common knowledge of the professionals in this field.

Claims

1. A single event upset latch circuit structure with fewer sensitive nodes, characterized in that: include: A clock filter circuit (001), a delay filter circuit (002), a latch circuit (003) and a stacked inverter circuit (004); wherein, The input end of the clock filter circuit (001) is connected to the clock signal CLK, and the output end signals CLKN and CLKNN of the clock filter circuit (001) are connected to the clock input end of the latch circuit (003). The clock filter circuit (001) is used to provide the clock signal to the latch circuit (003) and realize single-particle transient pulse filtering at the clock end; The input end of the delay filter circuit (002) is connected to the input signal D, and the output end of the delay filter circuit (002) is connected to the input end of the latch circuit (003); the delay filter circuit (002) comprises a delay unit and a C unit, which are used to provide an input signal to the latch circuit (003) and filter the single particle transient pulse generated by the input signal; The output end of the latch circuit (003) is connected to the input end of the stacked inverter circuit (004); the latch circuit (003) is used to realize data transmission and latching, and to realize single-particle upset resistance in the latched state; The output end of the stacked inverter circuit (004) is connected to the output signal Q; the stacked inverter circuit (004) is used to achieve the inversion of the logic level and keep the output level consistent with the input.

2. The latch circuit structure according to claim 1, characterized in that: The clock filter circuit (001) comprises a first delay unit (101), a first C unit (102) and a stacked inverter unit (103); wherein the input end of the first delay unit (101) is connected to a clock input signal CLK; the input end of the first C unit (102) is connected to the clock signal CLK and the output end of the first delay unit (101); the output end of the first C unit (102) is connected to the output signal CLKN and the input end of the stacked inverter unit (103); and the output end of the stacked inverter unit (103) is connected to the output signal CLKNN.

3. The latch circuit structure according to claim 2, characterized in that: The first delay unit (101) is an n-stage cascaded stacked inverter unit; the m-th stage stacked inverter unit includes PMOS transistors Pm1, Pm2 and NMOS transistors Nm1, Nm2; the gates of the PMOS transistors Pm1, Pm2 and the NMOS transistors Nm1, Nm2 are connected, serving as the input end of the stacked inverter unit, connected to the output end of the m-1-th stage inverter, the source of the PMOS transistor Pm1 is connected to the power supply signal VDD, the drain of the PMOS transistor Pm1 is connected to the source of the PMOS transistor Pm2; the drain of the PMOS transistor Pm2 is connected to the drain of Nm1, and serves as the output end of the m-th stage inverter, connected to the input end of the m+1-th stage inverter; the source of the NMOS transistor Nm1 is connected to the drain of the NMOS transistor Nm2; the source of the NMOS transistor Nm2 is connected to the power ground signal GND; wherein n≥m≥1.

4. The latch circuit structure according to claim 2, characterized in that: The first C unit (102) comprises PMOS transistors P101 and P102 and NMOS transistors N101 and N102; the gate of the PMOS transistor P101 is connected to the gate of the NMOS transistor N101 and serves as a first input terminal of the C unit and is connected to an input clock signal CLK; the source of the PMOS transistor P101 is connected to a power supply VDD; the drain of the PMOS transistor P101 is connected to a source of the PMOS transistor P102; the gate of the PMOS transistor P102 is connected to the gate of N102 and serves as a second input terminal of the C unit and is connected to an output terminal of the first delay unit (101); the drain of the PMOS transistor P102 is connected to the drain of the NMOS transistor N101 and is connected as an output terminal of the C unit and is connected to a reverse output clock signal CLKN; the source of the NMOS transistor N101 is connected to the drain of the NMOS transistor N102; the source of the NMOS transistor N102 is connected to a power ground GND.

5. The latch circuit structure according to claim 2, characterized in that: The stacked inverter unit (103) comprises PMOS transistors P103 and P104 and NMOS transistors N103 and N104; the gates of the PMOS transistors P103 and P104 and the NMOS transistors N103 and N104 are connected and serve as the input end of the stacked inverter unit (103) and are connected to the output end of the first C unit (102); the source of the PMOS transistor P103 is connected to a power supply VDD, and the drain of the PMOS transistor P103 is connected to the source of the PMOS transistor P104; the drain of the PMOS transistor P104 is connected to the drain of the NMOS transistor N103 and serves as the output end of the stacked inverter unit (103) and is connected to the output clock signal CLKNN; the source of the NMOS transistor N103 is connected to the drain of the NMOS transistor N104; and the source of the NMOS transistor N104 is connected to a power ground GND.

6. The latch circuit structure according to claim 1, characterized in that: The delay filter circuit (002) comprises a second delay unit (201) and a second C unit (202); wherein the input end of the second delay unit (201) is connected to an input signal D; the input end of the second C unit (202) is connected to the input signal D and the output end of the second delay unit (201), and the output end of the second C unit (202) is connected to the input end of the latch circuit (003); The second C unit (202) includes PMOS transistors P201 and P202 and NMOS transistors N201 and N202; the gate of the PMOS transistor P201 is connected to the gate of the NMOS transistor N201 and serves as a first input terminal of the second C unit (202) and is connected to an input signal D; the source of the PMOS transistor P201 is connected to a power supply VDD; the drain of the PMOS transistor P201 is connected to the source of the PMOS transistor P202; the PMOS transistor P20 The gate of the PMOS transistor P202 is connected to the gate of N202 and serves as the second input terminal of the second C unit (202) and is connected to the output terminal of the second delay unit (201); the drain of the PMOS transistor P202 is connected to the drain of the NMOS transistor N201 and serves as the output terminal of the second C unit (202) and is connected to the input terminal of the latch circuit (003); the source of the NMOS transistor N201 is connected to the drain of the NMOS transistor N202; and the source of the NMOS transistor N202 is connected to the power ground GND.

7. The latch circuit structure according to claim 1, characterized in that: The latch circuit (003) comprises a first-stage clocked inverter unit (301), a second-stage clocked inverter unit (302), a first-stage clocked stacked inverter unit (303), a second-stage clocked stacked inverter unit (304) and a third C unit (305); wherein the data input end of the first-stage clocked inverter (301) is connected to the data input end of the second-stage clocked inverter (302), and is connected to the output end of the delay filter unit (002) as the input end of the latch circuit (003); the first and second clock input ends of the first-stage clocked inverter (301) are respectively connected to the output signals CLKN and CLKNN of the clock filter (001); the output end of the first-stage clocked inverter (301) is connected to the second data input end of the first-stage clocked stacked inverter unit (303), the second input end of the third C unit (305) and the output end of the second-stage clocked stacked inverter unit (304); The first and second clock input terminals of the second-stage clock-controlled inverter (302) are connected to the output signals CLKN and CLKNN of the clock filter (001); the output terminal of the second-stage clock-controlled inverter (302) is connected to the second data input terminal of the second-stage clock-controlled stacked inverter unit (304), the first input terminal of the third C unit (305) and the output terminal of the first-stage clock-controlled stacked inverter unit (303); The first and second clock input terminals of the first-stage clock-controlled stacked inverter unit (303) are respectively connected to the output signals CLKNN and CLKN of the clock filter (001); the first data input terminal of the first-stage clock-controlled stacked inverter unit (303) is connected to the output terminal of the third C unit (305) and the first data input terminal of the second-stage clock-controlled stacked inverter unit (304), and serves as the output terminal of the latch circuit (003) and is connected to the input terminal of the stacked inverter circuit (004); the first and second clock input terminals of the second-stage clock-controlled stacked inverter unit (304) are respectively connected to the output signals CLKNN and CLKN of the clock filter circuit (001).

8. The latch circuit structure according to claim 7, characterized in that: The first-stage clocked inverter circuit (301) comprises PMOS transistors P311 and P312 and NMOS transistors N311 and N312. The gate of the PMOS transistor P311 is connected to the gate of the NMOS transistor N312 and is connected to the output of the delay filter circuit (002) as the data input of the first-stage clocked inverter circuit (301). The source of the PMOS transistor P311 is connected to a power supply VDD, and the drain of the PMOS transistor P311 is connected to the source of the PMOS transistor P312. The gate of the PMOS transistor P312 is connected to the output signal CLKN of the clock filter circuit (001) as a first clock input terminal, the drain of the PMOS transistor P312 is connected to the drain of the NMOS transistor N311 and serves as the output terminal of the first-stage clock-controlled inverter circuit (301); the gate of the NMOS transistor N311 is connected to the output signal CLKNN of the clock filter circuit (001) as a second clock input terminal, and the source of the NMOS transistor N311 is connected to the drain of the NMOS transistor N312; the source of the NMOS transistor N312 is connected to the power ground GND; The second-stage clocked inverter circuit (302) comprises PMOS transistors P321 and P322 and NMOS transistors N321 and N322. The gate of the PMOS transistor P321 is connected to the gate of N322 and is connected to the output of the delay filter circuit (002) as the data input of the second-stage clocked inverter circuit (302). The source of the PMOS transistor P321 is connected to the power supply VDD, and the drain of the PMOS transistor P321 is connected to the source of P322. The gate of the PMOS transistor P322 is connected to the gate of the first The clock input terminal is connected to the output signal CLKN of the clock filter circuit (001); the drain of the PMOS transistor P322 is connected to the drain of the NMOS transistor N321 and serves as the output terminal of the second-stage clocked inverter circuit (302); the gate of the NMOS transistor N321 serves as the second clock input terminal and is connected to the output signal CLKNN of the clock filter circuit (001); the source of the NMOS transistor N321 is connected to the drain of the NMOS transistor N322; and the source of the NMOS transistor N322 is connected to the power ground GND.

9. The latch circuit structure according to claim 7, characterized in that: The first-stage clocked stacked inverter circuit (303) comprises PMOS transistors P331, P332, P333 and NMOS transistors N331, N332, N333; the gate of the PMOS transistor P331 is connected to the gate of the NMOS transistor N333 and serves as the first data input terminal of the clocked stacked inverter circuit (303) and is connected to the output terminal of the third C unit (305); the source of the PMOS transistor P331 is connected to the power supply signal VDD, and the drain of the PMOS transistor P331 is connected to the source of the PMOS transistor P332; The gate of the PMOS transistor P332 serves as the first clock input terminal of the clock-controlled stacked inverter circuit (303) and is connected to the output signal CLKNN of the clock delay circuit (001); the drain of the PMOS transistor P332 is connected to the source of the NMOS transistor N331; the gate of the NMOS transistor N331 is connected to the gate of the PMOS transistor P333 and serves as the second data input terminal of the clock-controlled stacked inverter circuit (303) and is connected to the output terminal of the first-stage clocked inverter (301); the drain of the NMOS transistor N331 is connected to the gate of the PMOS transistor P333 and serves as the second data input terminal of the clock-controlled stacked inverter circuit (303) and is connected to the output terminal of the first-stage clocked inverter (301); The drain of the PMOS transistor P333 is connected to the output terminal of the clocked stacked inverter circuit (303) and is connected to the output terminal of the second-stage clocked inverter (302); the source of the PMOS transistor P333 is connected to the drain of the NMOS transistor N332; the gate of the NMOS transistor N332 serves as the second clock input terminal of the clocked stacked inverter circuit (303) and is connected to the output signal CLKN of the clock delay circuit (001); the source of the NMOS transistor N332 is connected to the drain of the NMOS transistor N333; the source of the NMOS transistor N333 is connected to the power ground GND; The second-stage clocked stacked inverter circuit (304) comprises PMOS transistors P341, P342, P343 and NMOS transistors N341, N342, N343; the gate of the PMOS transistor P341 is connected to the gate of the NMOS transistor N343 and serves as a first data input terminal of the clocked stacked inverter circuit (304) and is connected to the output terminal of the third C unit (305); the source of the PMOS transistor P341 is connected to a power supply signal VDD, and the drain of the PMOS transistor P341 is connected to the source of the PMOS transistor P342; the gate of the PMOS transistor P342 serves as a first clock input terminal of the clocked stacked inverter circuit (304) and is connected to the output signal CLKNN of the clock delay circuit (001), and the drain of the PMOS transistor P342 is connected to the source of the NMOS transistor N341; The gate of the transistor N341 is connected to the gate of the PMOS transistor P343 and serves as the second data input terminal of the clocked stacked inverter circuit (304) and is connected to the output terminal of the second-stage clocked inverter (302); the drain of the NMOS transistor N341 is connected to the drain of the PMOS transistor P343 and serves as the output terminal of the clocked stacked inverter circuit (304) and is connected to the output terminal of the first-stage clocked inverter (301); the source of the PMOS transistor P343 is connected to the drain of the NMOS transistor N342; the gate of the NMOS transistor N342 serves as the second clock input terminal of the clocked stacked inverter circuit (304) and is connected to the output signal CLKN of the clock delay circuit (001); the source of the NMOS transistor N342 is connected to the drain of the NMOS transistor N343; the source of the NMOS transistor N343 is connected to the power ground GND; The third C unit (305) comprises PMOS transistors P351 and P352 and NMOS transistors N351 and N352; the gate of the PMOS transistor P351 is connected to the gate of the NMOS transistor N351 and serves as the first input terminal of the C unit and is connected to the output terminal of the second-stage clocked inverter circuit (302); the source of the PMOS transistor P351 is connected to the power supply VDD, and the drain of the PMOS transistor P351 is connected to the source of the PMOS transistor P352; the PMOS transistor The gate of the transistor P352 is connected to the gate of N352 and serves as the second input terminal of the C unit, connected to the output terminal of the first-stage clocked inverter circuit (301); the drain of the PMOS transistor P352 is connected to the drain of the NMOS transistor N351 and serves as the output terminal of the third C unit (305), connected to the input terminal of the stacked transistor circuit (004); the source of the NMOS transistor N351 is connected to the drain of the NMOS transistor N352; and the source of the NMOS transistor N352 is connected to the power ground GND.

10. The latch circuit structure according to claim 1, characterized in that: The transistor stack circuit (004) comprises PMOS transistors P401 and P402 and NMOS transistors N401 and N402; wherein the gates of the PMOS transistors P401 and P402 and the NMOS transistors N401 and N402 are connected and serve as the input of the stack inverter unit (004) and are connected to the output of the latch circuit (003); the source of the PMOS transistor P401 is connected to the power supply VDD, and the drain of the PMOS transistor P401 is connected to the source of the PMOS transistor P402; the drain of the PMOS transistor P402 is connected to the drain of the NMOS transistor N401 and serves as the output of the transistor stack circuit (004) and is connected to the output signal Q; The source of the NMOS transistor N401 is connected to the drain of the NMOS transistor N402; the source of the NMOS transistor N402 is connected to the power ground GND.

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