A single event upset resistant latch circuit structure with fewer sensitive nodes

Abstract

The present invention discloses a single-particle flip-resistant latch circuit structure with fewer sensitive nodes, comprising: a clock filter circuit, a delay filter circuit, a latch circuit, and a stacked inverter circuit. The clock filter circuit is used to filter single-particle transient pulses at the clock end and provide a clock signal to the latch circuit. The delay filter circuit is used to filter single-particle transient pulses at the data end and provide an input signal to the latch circuit. The latch circuit is used to realize data transmission and latching, and maintain the correct state and level correction of the output signal after single-particle radiation in the latched state. The stacked inverter circuit is used to provide an inverted signal. The designed latch circuit can realize single-particle transient reinforcement and single-particle transient pulse filtering, has fewer sensitive nodes in the circuit, has a good reinforcement effect, and is simple and easy to implement.

Description

Technical Field

[0001] The invention relates to a single-particle upset resistant latch circuit structure with fewer sensitive nodes, belonging to the technical field of circuit-level radiation-resistant reinforcement. Background Art

[0002] With the continuous advancement of microelectronics technology, an increasing number of electronic devices are required to operate in various space radiation environments. Radiation effects such as single event effects, total dose effects, displacement damage effects, and transient dose rate have become significant threats to the reliability of aerospace integrated circuits. Among these, single event effects (SEEs) are becoming increasingly serious. A SEE occurs when high-energy particles bombard a semiconductor device, ionizing a large number of electron-hole pairs within the semiconductor. These pairs are captured in the active region, causing circuit data errors or even permanent damage.

[0003] Single event effects (SEEs) can be divided into two categories based on the type of error they trigger. One type manifests as irreversible, permanent damage to electronic devices, known as hard errors. Examples include single event gate breakdown, single event burnout, and single event latchup. The other type manifests as transient errors in the circuit's logic state, known as soft errors. These include single event transients and single event upsets. Single event upsets (SEUs) are one of the most common types of soft errors in digital integrated circuits. In sequential logic circuits, when carriers are collected at sensitive nodes under the influence of electric fields and concentrations, they can cause logic level errors, resulting in upsets.

[0004] Latches are the fundamental building blocks of flip-flop circuits, and ensuring their radiation resistance is crucial. Currently, widely used SUP hardening methods include triple-module redundancy (TMR) and dual-interlocked storage cells (DICE). While these traditional hardening methods offer some SUP resistance, they suffer from numerous sensitive nodes and high area overhead. As integrated circuit process sizes continue to shrink, particles are more likely to strike sensitive nodes, reducing the hardening capability. Summary of the Invention

[0005] The technical problem solved by the present invention is: to overcome the shortcomings of the existing technology and provide a single-particle upset resistant latch circuit structure with fewer sensitive nodes, in which any node upset can pull the erroneous data back to the correct value, achieving the effect of resisting single-node upset.

[0006] The technical solution of the present invention is:

[0007] The present invention discloses a single event upset resistant latch circuit structure with fewer sensitive nodes, comprising: a clock filter circuit, a delay filter circuit, a latch circuit and a stacked inverter circuit; wherein,

[0008] The input end of the clock filter circuit is connected to the clock signal CLK, and the output end signals CLKN and CLKNN of the clock filter circuit are connected to the clock input end of the latch circuit. The clock filter circuit is used to provide the clock signal to the latch circuit and realize single-event transient pulse filtering at the clock end;

[0009] The input end of the delay filter circuit is connected to the input signal D, and the output end of the delay filter circuit is connected to the input end of the latch circuit; the delay filter circuit includes a delay unit and a C unit, which is used to provide the input signal to the latch circuit and filter the single-particle transient pulse generated by the input signal;

[0010] The output end of the latch circuit is connected to the input end of the stacked inverter circuit; the latch circuit is used to realize data transmission and latching, and realize single event upset resistance in the latched state;

[0011] The output end of the stacked inverter circuit is connected to the output signal Q; the stacked inverter circuit is used to achieve inversion of the logic level and keep the output level consistent with the input.

[0012] Furthermore, in the above circuit structure, the clock filtering circuit includes a first delay unit, a first C unit and a stacked inverter unit; wherein, the input end of the first delay unit is connected to the clock input signal CLK; the input end of the first C unit is connected to the clock signal CLK and the output end of the first delay unit, and the output end of the first C unit is connected to the output signal CLKN and the input end of the stacked inverter unit; the output end of the stacked inverter unit is connected to the output signal CLKNN.

[0013] Furthermore, in the above circuit structure, the first delay unit is an n-stage cascaded stacked inverter unit; the m-th stage stacked inverter unit includes PMOS transistors Pm1, Pm2 and NMOS transistors Nm1, Nm2; the gates of the PMOS transistors Pm1, Pm2 and the NMOS transistors Nm1, Nm2 are connected as the input end of the stacked inverter unit, connected to the output end of the m-1-th stage inverter, the source of the PMOS transistor Pm1 is connected to the power supply signal VDD, and the drain of the PMOS transistor Pm1 is connected to the source of the PMOS transistor Pm2; the drain of the PMOS transistor Pm2 is connected to the drain of Nm1, and serves as the output end of the m-th stage inverter, connected to the input end of the m+1-th stage inverter; the source of the NMOS transistor Nm1 is connected to the drain of the NMOS transistor Nm2; the source of the NMOS transistor Nm2 is connected to the power ground signal GND; wherein, n≥m≥1.

[0014] Furthermore, in the above circuit structure, the first C unit includes PMOS transistors P101 and P102 and NMOS transistors N101 and N102; the gate of the PMOS transistor P101 is connected to the gate of the NMOS transistor N101 and serves as a first input terminal of the C unit, connected to the input clock signal CLK, the source of the PMOS transistor P101 is connected to the power supply VDD, and the drain of the PMOS transistor P101 is connected to the source of the PMOS transistor P102; the gate of the PMOS transistor P102 is connected to the gate of N102 and serves as a second input terminal of the C unit, connected to the output terminal of the first delay unit, the drain of the PMOS transistor P102 is connected to the drain of the NMOS transistor N101 and serves as the output terminal of the C unit, connected to the inverted output clock signal CLKN; the source of the NMOS transistor N101 is connected to the drain of the NMOS transistor N102; and the source of the NMOS transistor N102 is connected to the power ground GND;

[0015] Furthermore, in the above circuit structure, the stacked inverter unit includes PMOS transistors P103 and P104, and NMOS transistors N103 and N104; the gates of the PMOS transistors P103 and P104 and the NMOS transistors N103 and N104 are connected and serve as the input of the stacked inverter unit and are connected to the output of the first C unit; the source of the PMOS transistor P103 is connected to the power supply VDD, and the drain of the PMOS transistor P103 is connected to the source of the PMOS transistor P104; the drain of the PMOS transistor P104 is connected to the drain of the NMOS transistor N103 and serves as the output of the stacked inverter unit and is connected to the output clock signal CLKNN; the source of the NMOS transistor N103 is connected to the drain of the NMOS transistor N104; and the source of the NMOS transistor N104 is connected to the power ground GND.

[0016] Furthermore, in the above circuit structure, the delay filter circuit includes a second delay unit and a second C unit; wherein the input end of the second delay unit is connected to the input signal D; the input end of the second C unit is connected to the input signal D and the output end of the second delay unit, and the output end of the second C unit is connected to the input end of the latch circuit;

[0017] The second C unit includes PMOS transistors P201 and P202 and NMOS transistors N201 and N202; the gate of the PMOS transistor P201 is connected to the gate of the NMOS transistor N201 and serves as the first input terminal of the second C unit and is connected to the input signal D. The source of the PMOS transistor P201 is connected to the power supply VDD, and the drain of the PMOS transistor P201 is connected to the source of the PMOS transistor P202; the gate of the PMOS transistor P202 is connected to the gate of N202 and serves as the second input terminal of the second C unit and is connected to the output terminal of the second delay unit. The drain of the PMOS transistor P202 is connected to the drain of the NMOS transistor N201 and serves as the output terminal of the second C unit and is connected to the input terminal of the latch circuit; the source of the NMOS transistor N201 is connected to the drain of the NMOS transistor N202; and the source of the NMOS transistor N202 is connected to the power ground GND.

[0018] Furthermore, in the above circuit structure, the latch circuit includes a first-stage clocked inverter unit, a second-stage clocked inverter unit, a first-stage clocked stacked inverter unit, a second-stage clocked stacked inverter unit, and a third C unit; wherein the data input terminal of the first-stage clocked inverter is connected to the data input terminal of the second-stage clocked inverter, and is connected to the output terminal of the delay filter circuit as the input terminal of the latch circuit; the first and second clock input terminals of the first-stage clocked inverter are respectively connected to the output signals CLKN and CLKNN of the clock filter circuit; the output terminal of the first-stage clocked inverter is connected to the second data input terminal of the first-stage clocked stacked inverter unit, the second input terminal of the third C unit, and the output terminal of the second-stage clocked stacked inverter unit;

[0019] The first and second clock input terminals of the second-stage clocked inverter are connected to the output signals CLKN and CLKNN of the clock filter circuit; the output terminal of the second-stage clocked inverter is connected to the second data input terminal of the second-stage clocked stacked inverter unit, the first input terminal of the third C unit, and the output terminal of the first-stage clocked stacked inverter unit;

[0020] The first and second clock input terminals of the first-stage clocked stacked inverter unit are connected to the output signals CLKNN and CLKN of the clock filter circuit, respectively; the first data input terminal of the first-stage clocked stacked inverter unit is connected to the output terminal of the third C unit and the first data input terminal of the second-stage clocked stacked inverter unit, and serves as the output terminal of the latch circuit and is connected to the input terminal of the stacked inverter circuit; the first and second clock input terminals of the second-stage clocked stacked inverter unit are connected to the output signals CLKNN and CLKN of the clock filter circuit, respectively;

[0021] Furthermore, in the above circuit structure, the first-stage clocked inverter circuit includes PMOS transistors P311 and P312 and NMOS transistors N311 and N312. The gate of the PMOS transistor P311 is connected to the gate of the NMOS transistor N312 and serves as the data input terminal of the first-stage clocked inverter circuit and is connected to the output terminal of the delay filter circuit. The source of the PMOS transistor P311 is connected to the power supply VDD, and the drain of the PMOS transistor P311 is connected to the source of the PMOS transistor P312. The gate of the S-transistor P312 is connected to the output signal CLKN of the clock filter circuit as a first clock input terminal. The drain of the PMOS transistor P312 is connected to the drain of the NMOS transistor N311 and serves as the output terminal of the first-stage clocked inverter circuit. The gate of the NMOS transistor N311 is connected to the output signal CLKNN of the clock filter circuit as a second clock input terminal. The source of the NMOS transistor N311 is connected to the drain of the NMOS transistor N312. The source of the NMOS transistor N312 is connected to the power ground GND.

[0022] The second-stage clocked inverter circuit includes PMOS transistors P321 and P322 and NMOS transistors N321 and N322. The gate of the PMOS transistor P321 is connected to the gate of N322 and serves as a data input terminal of the second-stage clocked inverter circuit and is connected to the output terminal of the delay filter circuit. The source of the PMOS transistor P321 is connected to the power supply VDD, and the drain of the PMOS transistor P321 is connected to the source of P322. The gate of the PMOS transistor P322 serves as a first clock input terminal and is connected to the output signal CLKN of the clock filter circuit. The drain of the PMOS transistor P322 is connected to the drain of the NMOS transistor N321 and serves as the output terminal of the second-stage clocked inverter circuit. The gate of the NMOS transistor N321 serves as a second clock input terminal and is connected to the output signal CLKNN of the clock filter circuit. The source of the NMOS transistor N321 is connected to the drain of the NMOS transistor N322. The source of the NMOS transistor N322 is connected to the power ground GND.

[0023] Furthermore, in the above circuit structure, the first-stage clocked stacked inverter circuit includes PMOS transistors P331, P332, and P333 and NMOS transistors N331, N332, and N333; the gate of the PMOS transistor P331 is connected to the gate of the NMOS transistor N333 and serves as the first data input terminal of the clocked stacked inverter circuit, connected to the output terminal of the third C unit; the source of the PMOS transistor P331 is connected to the power supply signal VDD, and the drain of the PMOS transistor P331 is connected to the source of the PMOS transistor P332; the gate of the PMOS transistor P332 serves as the first clock input terminal of the clocked stacked inverter circuit, connected to the output signal CLKNN of the clock delay circuit, and the drain of the PMOS transistor P332 is connected to the NMOS transistor N331. The gate of the NMOS transistor N331 is connected to the gate of the PMOS transistor P333 and serves as a second data input terminal of the clocked stack inverter circuit, connected to the output terminal of the first-stage clocked inverter; the drain of the NMOS transistor N331 is connected to the drain of the PMOS transistor P333 and serves as an output terminal of the clocked stack inverter circuit, connected to the output terminal of the second-stage clocked inverter; the source of the PMOS transistor P333 is connected to the drain of the NMOS transistor N332; the gate of the NMOS transistor N332 serves as a second clock input terminal of the clocked stack inverter circuit, connected to the output signal CLKN of the clock delay circuit, the source of the NMOS transistor N332 is connected to the drain of the NMOS transistor N333; the source of the NMOS transistor N333 is connected to the power ground GND;

[0024] The second-stage clocked stack inverter circuit includes PMOS transistors P341, P342, and P343 and NMOS transistors N341, N342, and N343; the gate of the PMOS transistor P341 is connected to the gate of the NMOS transistor N343 and serves as the first data input terminal of the clocked stack inverter circuit and is connected to the output terminal of the third C unit; the source of the PMOS transistor P341 is connected to the power supply signal VDD, and the drain of the PMOS transistor P341 is connected to the source of the PMOS transistor P342; the gate of the PMOS transistor P342 serves as the first clock input terminal of the clocked stack inverter circuit and is connected to the output signal CLKNN of the clock delay circuit, and the drain of the PMOS transistor P342 is connected to the source of the NMOS transistor N341; The gate of the MOS transistor N341 is connected to the gate of the PMOS transistor P343 and serves as a second data input terminal of the clocked stack inverter circuit, connected to the output terminal of the second-stage clocked inverter. The drain of the NMOS transistor N341 is connected to the drain of the PMOS transistor P343 and serves as an output terminal of the clocked stack inverter circuit, connected to the output terminal of the first-stage clocked inverter. The source of the PMOS transistor P343 is connected to the drain of the NMOS transistor N342. The gate of the NMOS transistor N342 serves as a second clock input terminal of the clocked stack inverter circuit, connected to the output signal CLKN of the clock delay circuit. The source of the NMOS transistor N342 is connected to the drain of the NMOS transistor N343. The source of the NMOS transistor N343 is connected to the power ground GND.

[0025] The third C unit includes PMOS transistors P351 and P352 and NMOS transistors N351 and N352; the gate of the PMOS transistor P351 is connected to the gate of the NMOS transistor N351 and serves as the first input terminal of the C unit, connected to the output terminal of the second-stage clocked inverter circuit, the source of the PMOS transistor P351 is connected to the power supply VDD, and the drain of the PMOS transistor P351 is connected to the source of the PMOS transistor P352; the gate of the PMOS transistor P352 is connected to the gate of N352 and serves as the second input terminal of the C unit, connected to the output terminal of the first-stage clocked inverter circuit, the drain of the PMOS transistor P352 is connected to the drain of the NMOS transistor N351 and serves as the output terminal of the third C unit, connected to the input terminal of the stacked transistor circuit; the source of the NMOS transistor N351 is connected to the drain of the NMOS transistor N352; the source of the NMOS transistor N352 is connected to the power ground GND.

[0026] Furthermore, in the above circuit structure, the transistor stack circuit includes PMOS transistors P401 and P402 and NMOS transistors N401 and N402; wherein, the gates of the PMOS transistors P401, P402, and NMOS transistors N401 and N402 are connected and serve as the input end of the stacked inverter unit, connected to the output end of the latch circuit, the source of the PMOS transistor P401 is connected to the power supply VDD, and the drain of the PMOS transistor P401 is connected to the source of the PMOS transistor P402; the drain of the PMOS transistor P402 is connected to the drain of the NMOS transistor N401 and serves as the output end of the transistor stack circuit, connected to the output signal Q; the source of the NMOS transistor N401 is connected to the drain of the NMOS transistor N402; and the source of the NMOS transistor N402 is connected to the power ground GND.

[0027] The beneficial effects of the present invention and the prior art are:

[0028] (1) The present invention provides a single-particle upset-resistant latch circuit structure with fewer sensitive nodes, which uses a delay filter structure to filter out SET pulses at the clock and data input terminals, uses a C-unit structure to implement single-particle upset reinforcement in the latched state, and implements internal node level correction in the latched state based on a redundant interlocking structure.

[0029] (2) The circuit structure provided by the present invention has good single-particle resistance, few sensitive nodes, low overhead and is easy to implement. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 Schematic diagram of the circuit structure of the present invention;

[0031] Figure 2 is a structural diagram of a clock delay circuit in the circuit structure of the present invention;

[0032] Figure 3 FIG1 is a structural diagram of a time delay filter circuit in the circuit structure of the present invention;

[0033] Figure 4 is a structural diagram of a delay unit in the circuit structure of the present invention;

[0034] Figure 5 Schematic diagram and structural diagram of the latch circuit in the circuit structure of the present invention; (a) is the schematic diagram; (b) is the structural diagram;

[0035] Figure 6 Schematic diagram of a clocked inverter unit in the latch circuit structure of the present invention;

[0036] Figure 7 Schematic diagram of a clocked stacked inverter unit in the latch circuit structure of the present invention;

[0037] Figure 8 Schematic diagram of unit C in the latch circuit structure of the present invention;

[0038] Figure 9 FIG. 4 is a circuit structure diagram of a stacked inverter in the circuit structure of the present invention. DETAILED DESCRIPTION

[0039] The present invention will be further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0040] The present invention will be further described below with reference to the accompanying drawings.

[0041] All features disclosed in this specification, or steps in all methods or processes disclosed, except for mutually exclusive features and / or steps, can be combined in any manner.

[0042] Any feature disclosed in this specification, unless otherwise stated, may be replaced by other equivalent or alternative features with similar purposes.

[0043] The present invention utilizes a clock filter circuit 001 and a time delay filter circuit 002 composed of a delay circuit and a C unit to implement single-particle transient pulse filtering at the clock and input signal ends; and utilizes a latch circuit unit 003 with fewer sensitive nodes composed of a redundant feedback network and C units to implement single-particle upset reinforcement in the latched state and correction of the internal storage node level.

[0044] Figure 1 The figure shows a schematic diagram of a SEU-resistant latch circuit with fewer sensitive nodes, provided by an embodiment of the present invention. It includes a clock filter circuit 001, a delay filter circuit 002, a latch circuit 003, and a stacked inverter circuit 004. The delay filter structure, formed by the delay unit and the C unit, filters out SET pulses at the clock and input data ports. The feedback structure designed within the latch circuit implements SEU reinforcement and level recovery.

[0045] Figure 2 The figure shows an implementation of clock filter circuit 001, which consists of a delay unit, a C unit, and a stacked inverter unit. The delay unit and C unit are used to filter SET pulses, and the stacked inverter is used to provide an inverted clock signal. The input of clock filter circuit 001 is connected to the clock signal CLK, and the output signals CLKN and CLKNN of clock filter circuit 001 are connected to the input of latch circuit 003.

[0046] Among them, the first C unit 102 is composed of PMOS transistors P101 and P102 and NMOS transistors N101 and N102; the gate of P101 is connected to the gate of NMOS transistor N101 and serves as the first input terminal of the C unit, connected to the input clock signal CLK, the source of P101 is connected to the power supply VDD, and the drain of P101 is connected to the source of PMOS transistor P102; the gate of P102 is connected to the gate of N102 and serves as the second input terminal of the C unit, the drain of P102 is connected to the drain of NMOS transistor N101 and serves as the output terminal of the C unit, connected to the reverse output clock signal CLKN; the source of N101 is connected to the gate of NMOS transistor N101 and serves as the output terminal of the C unit, connected to the reverse output clock signal CLKN. The drain of the transistor N102; the source of N102 is connected to the power ground GND; the stacked inverter unit 103 is composed of PMOS transistors P103, P104, and NMOS transistors N103 and N104; the gates of P103, P104, N103, and N104 are connected and serve as the input terminal of the stacked inverter unit 103, the source of P103 is connected to the power supply VDD, and the drain of P103 is connected to the source of P104; the drain of P104 is connected to the drain of N103 and serves as the output terminal of the stacked circuit and is connected to CLKNN; the source of N103 is connected to the drain of the NMOS transistor N104; the source of the NMOS transistor N104 is connected to the power ground GND;

[0047] The clock filtering circuit implements SET reinforcement as follows: CLK and the signal CN output by the delay unit serve as the two inputs of unit C, where the delay value is determined by the SET pulse width. Unit C outputs an inverted signal only when the signals at the first and second inputs are identical. When the levels at the two inputs are inconsistent, the output level of unit C is held. Therefore, after a SET pulse is generated by the clock input signal CLK, the delay causes the logic levels at CLK and CN to differ. Unit C enters a hold state, maintaining the correct level before the SET pulse is generated until the CN delay pulse expires, at which point the output of unit C enters an inverted state. Therefore, the SET pulse does not affect the output of unit C, thus achieving SET pulse filtering at the clock end.

[0048] Figure 3 The figure shows the implementation of delay filter circuit 002. It consists of a delay unit and a C unit. The input of the delay unit 202 is connected to the input signal D; the input of the second C unit 202 is connected to the input signal D and the output of the second delay unit 201; the output of the second C unit 202 is connected to the input of latch circuit 003. The circuit can filter SET pulses at the input data end, and its implementation principle is similar to that of the clock filter circuit.

[0049] The second C unit 202 is composed of PMOS transistors P201 and P202 and NMOS transistors N201 and N202; the gate of P201 is connected to the gate of NMOS transistor N201 and serves as the first input terminal of the C unit, connected to the input signal D, the source of P201 is connected to the power supply VDD, and the drain of P201 is connected to the source of PMOS transistor P202; the gate of P202 is connected to the gate of N202 and serves as the second input terminal of the C unit, connected to the output terminal of the second delay unit 201, the drain of P202 is connected to the drain of NMOS transistor N201, and serves as the output terminal of the C unit, connected to the input terminal of the latch circuit 003; the source of N201 is connected to the drain of NMOS transistor N202; the source of N202 is connected to the power ground GND.

[0050] Figure 4 The figure shows the implementation of the delay units 101 and 102 inside the clock filter circuit 001 and the delay filter circuit 002. The delay unit is an n-stage cascade stacked inverter unit, consisting of PMOS transistors P11, P12, P21, P22...Pm1, Pm2...Pn1, Pn2 and NMOS transistors N11, N12, N21, N22...Nm1, Nm2...Nn1, Nn2, where m and n represent the number of inverter stages, m < n; taking the mth stage stacked inverter as an example, the gates of the PMOS transistors Pm1, Pm2, Nm1, Nm2 are connected as the mth stage stacked inverter. The input end of the m-th inverter is connected to the output end of the m-1th inverter, the source of the PMOS transistor Pm1 is connected to the power supply signal VDD, and the drain of Pm1 is connected to the source of the PMOS transistor Pm2; the drain of the PMOS transistor Pm2 is connected to the drain of Nm1 and serves as the output end of the m-th inverter, connected to the input end of the m+1th inverter; the source of the NMOS transistor Nm1 is connected to the drain of the NMOS transistor Nm2; and the source of the NMOS transistor Nm2 is connected to the power ground signal GND.

[0051] The delay unit utilizes the delay characteristics of inverters, employing a multi-stage cascade structure to achieve SET pulse delay. The number of cascaded inverters is determined by the SET pulse width. In circuit design, the delay unit utilizes a stacked inverter structure, saving layout area while maintaining a consistent number of transistors.

[0052] Figure 5The structure and circuit implementation of the latch circuit in the circuit structure of the present invention; the latch circuit 003 is composed of a first-stage clocked inverter unit 301, a second-stage clocked inverter unit 302, a first-stage clocked stacked inverter unit 303, a second-stage clocked stacked inverter unit 304, and a third C unit 305; the data input terminal of the first-stage clocked inverter 301 is connected to the data input terminal of the second-stage clocked inverter 302, and is connected to the output terminal of the delay filter circuit 002 as the input terminal of the latch circuit; the first and second clock input terminals of the first-stage clocked inverter 301 are respectively connected to the output signals CLKN and CLKNN of the clock filter circuit 001; the output terminal of the first-stage clocked inverter 301 is connected to the second data input terminal of the first-stage clocked stacked inverter unit 303, the second input terminal of the third C unit 305, and the output terminal of the second-stage clocked stacked inverter unit 304;

[0053] The first and second clock input terminals of the second-stage clocked inverter 302 are connected to the output signals CLKN and CLKNN of the clock filter circuit 001; the output terminal of the second-stage clocked inverter 302 is connected to the second data input terminal of the second-stage clocked stacked inverter unit 304, the first input terminal of the third C unit 305, and the output terminal of the first-stage clocked stacked inverter unit 303;

[0054] The first and second clock input terminals of the first-stage clocked stacked inverter unit 303 are connected to the output signals CLKNN and CLKN of the clock filter circuit 001, respectively. The first data input terminal of the first-stage clocked stacked inverter unit 303 is connected to the output terminal of the third C unit 305 and the first data input terminal of the second-stage clocked stacked inverter unit 304, and serves as the output terminal of the latch circuit and is connected to the input terminal of the stacked inverter circuit 004. The first and second clock input terminals of the second-stage clocked stacked inverter unit 304 are connected to the output signals CLKNN and CLKN of the clock filter circuit 001, respectively.

[0055] The latch circuit structure utilizes a redundant feedback network combined with C-units to prevent output level flips caused by single-event upsets (SUTs). A pair of pull-up NMOS and pull-down PMOS transistors are added internally to effectively prevent SUT propagation and facilitate logic level recovery. Compared to the traditional DICE structure, the latch portion of this circuit has only three sensitive nodes, N1, N2, and N3. If any sensitive node flips, the feedback mechanism or C-unit structure can be used to restore the erroneous data to the correct value, achieving robustness against SUTs.

[0056] Since N1 and N2 are symmetrical in the circuit structure, the following description only focuses on the flipping of nodes N1 and N3. When node N1 flips 1-0, N2 is in a high-level state. Under the action of the C unit, the output terminal N3 maintains the low-level state before the flip, and the output Q state remains unchanged, thereby achieving SEU reinforcement. The clocked stacked inverter 303 is in the off state due to the pull-up NMOS transistor N331. Therefore, the error of N1 does not propagate to N2 through the clocked stacked inverter 303. The clocked stacked inverter 304 is still in the on state and outputs a high level. Since its output terminal is connected to node N1, it can promote the correction of the level state of N1.

[0057] When N1 flips from 0 to 1, N2 is at a low level. Due to the action of the third C unit 305, the level of node N3 remains high, and the Q terminal is in a correct low level state. The clocked stack circuit 303 is in an off state due to the action of the pull-down network PMOS transistor P333. Therefore, the flip of N1 does not affect the logic state of N2. The clocked stack inverter 304 remains in an on state and outputs a low level, which can promote the recovery of the level of node N1.

[0058] When N3 flips from 0 to 1, the clocked stacked inverter circuit's pull-up NMOS transistor and pull-down PMOS transistor clamp the output level, keeping both clocked stacked circuits 303 and 304 in the off state. Therefore, the flip of N3 has no effect on N1 and N2, which remain in the correct high-level state. Furthermore, N1 and N2 output the correct low-level logic via the C unit, enabling self-recovery of the N3 node state.

[0059] Figure 6 This is the implementation form of the first clocked inverter 301 and the second clocked inverter 302 in the latch circuit structure of the present invention; the two circuit structures are identical and the electrical connections are complementary. Taking the first-stage clocked inverter circuit 301 as an example, it is composed of PMOS transistors P311 and P312 and NMOS transistors N311 and N312. The gate of P311 is connected to the gate of N312 and serves as the data input terminal of the first-stage clocked inverter circuit and is connected to DIN. The source of P311 is connected to the power supply VDD, and the drain of P311 is connected to the source of P312. The gate of PMOS transistor P312 serves as the first clock input terminal and is connected to CLKN. The drain of P312 is connected to the drain of NMOS transistor N311 and serves as the output terminal of the clocked inverter circuit. The gate of N311 serves as the second clock input terminal and is connected to CLKNN. The source of N311 is connected to the drain of N312. The source of N312 is connected to the power ground GND.

[0060] Compared to traditional inverter units, the clocked inverter circuit adds a clock control terminal, enabling data transmission with low power consumption. In the latch transparent state, CLKN is low and CLKNN is high. The clocked inverter unit is turned on, enabling data transmission via the C unit. In the latched state, the clocked inverter unit is turned off and does not affect the latch circuit.

[0061] Figure 7 This is the implementation method of the first-stage clocked stacked inverter circuit 303 and the second-stage clocked stacked inverter circuit 304 in the latch circuit structure of the present invention; the two circuit structures are the same, and the electrical connections are complementary. Taking the first-stage clocked stacked inverter circuit 303 as an example, it is composed of PMOS transistors P331, P332, P333 and NMOS transistors N331, N332, N333; the gate of P331 is connected to the gate of NMOS transistor N333, and is connected to N3 as the first data input terminal of the clocked stacked inverter circuit; the source of P331 is connected to the power supply signal VDD, and the drain of P331 is connected to the source of PMOS transistor P332; the gate of P332 is connected to CLKNN as the first clock input terminal of the clocked stacked inverter circuit, and the drain of P332 is connected to NMOS transistor N3 31; the gate of N331 is connected to the gate of the PMOS transistor P333, and is connected to N1 as the second data input terminal of the clocked stack inverter circuit; the drain of N331 is connected to the drain of the PMOS transistor P333, and is connected to N2 as the output terminal of the clocked stack inverter circuit 303; the source of the PMOS transistor P333 is connected to the drain of the NMOS transistor N332; the gate of the NMOS transistor N332 is connected to the signal CLKN as the second clock input terminal of the clocked stack inverter circuit, the source of N332 is connected to the drain of N333; the source of N333 is connected to the power ground GND.

[0062] Taking the clocked stacked inverter circuit 303 as an example, its implementation principle is explained: compared with the traditional inverter structure, the stacked inverter structure adds a pair of complementary clock control signals. The inverter circuit is in working state only when the latch is in the latched state; when the latch is in the transparent state, since the clock-controlled P NMOS are all turned on, the circuit is always in the off state.

[0063] In addition, the clocked stacked inverter incorporates an NMOS transistor N331 in the pull-up PMOS network and a PMOS transistor P333 in the pull-down NMOS network, both serving as the second data input of the inverter circuit. This structure enhances the level clamping effect of the inverter. In the latched state, the pull-down network conducts when and only when the first data input N3 is high and the second data input N1 is low, and the clocked stacked inverter output N2 outputs a low level. Furthermore, the pull-up network conducts when and only when the first data input N3 is low and the second data input N1 is high, and the clocked stacked inverter output N2 outputs a high level. When either inverter input N1 or N3 flips, the circuit remains off because neither the pull-up nor the pull-down network conducts, and errors do not propagate along the inverter to the output N2.

[0064] Figure 8 This is an implementation of the third C unit 305 in the latch circuit structure of the present invention, which is composed of PMOS transistors P351 and P352 and NMOS transistors N351 and N352; the gate of P351 is connected to the gate of N351 and serves as the first input terminal of the C unit, connected to the output terminal N2 of the second-stage clocked inverter circuit 302; the source of P351 is connected to the power supply VDD, and the drain of P351 is connected to the source of the PMOS transistor P352; the gate of P352 is connected to the gate of N352 and serves as the second input terminal of the C unit, connected to the output terminal N1 of the first-stage clocked inverter circuit 301; the drain of P352 is connected to the drain of the NMOS transistor N351 and serves as the output terminal of the C unit, connected to N3; the source of N351 is connected to the drain of the NMOS transistor N352; and the source of N352 is connected to the power ground GND.

[0065] The implementation principle is as follows: when the input signals N1 and N2 are the same, the C unit circuit N3 outputs a reverse signal. When the N1 and N2 signals are different, the C unit output N3 output maintains the current state. Therefore, when a single-particle upset occurs in one of the two inputs, the error number will not be transmitted to the output end, which plays the role of single-particle reinforcement.

[0066] Figure 9This is an implementation of the stacked inverter circuit 004 in the circuit structure of the present invention, wherein the gates of the PMOS transistors P401, P402, N401, and N402 are connected and serve as the input of the stacked inverter unit 004, connected to the output terminal N3 of the latch circuit 003, the source of the PMOS transistor P401 is connected to the power supply VDD, and the drain is connected to the source of the PMOS transistor P402; the drain of the PMOS transistor P402 is connected to the drain of the NMOS transistor N401 and serves as the output of the stacked circuit and is connected to the output signal Q; the source of the NMOS transistor N401 is connected to the drain of the NMOS transistor N402; and the source of the NMOS transistor N402 is connected to the power ground GND.

[0067] The function of the stacked inverter circuit is to output the inverted signal of N3 to achieve the correct signal output Q. The stacked inverter unit has a certain ability to resist single-event events. Taking the state of high input as an example, the pull-up PMOS network is turned off and the pull-down NMOS network is turned on. If any of the PMOS transistors is bombarded by a single event and becomes conductive, the pull-up network will not be turned on because the other series PMOS is not conductive, and the output level will still not be in the correct low-level state.

[0068] The contents not described in detail in the present invention specification belong to the common knowledge of those skilled in the art. Although the embodiments of the present invention are described in conjunction with the drawings, those skilled in the art can make various modifications or variations within the scope of the appended claims.

[0069] Although the present invention has been described in detail through the above preferred embodiments, it should be understood that the above description is not intended to limit the present invention. After reading the above description, various modifications and substitutions of the present invention will become apparent to those skilled in the art. Therefore, the scope of protection of the present invention should be defined by the appended claims.

[0070] The contents not described in detail in the specification of the present invention belong to the common knowledge of professionals in this field.

Claims

1. A single event upset resistant latch circuit structure with fewer sensitive nodes, characterized in that: include: A clock filter circuit (001), a delay filter circuit (002), a latch circuit (003) and a stacked inverter circuit (004); wherein, The input end of the clock filter circuit (001) is connected to the clock signal CLK, and the output end signals CLKN and CLKNN of the clock filter circuit (001) are connected to the clock input end of the latch circuit (003). The clock filter circuit (001) is used to provide the clock signal to the latch circuit (003) and realize single-particle transient pulse filtering at the clock end; The input end of the delay filter circuit (002) is connected to the input signal D, and the output end of the delay filter circuit (002) is connected to the input end of the latch circuit (003); the delay filter circuit (002) comprises a delay unit and a C unit, and is used to provide an input signal to the latch circuit (003) and filter the single-particle transient pulse generated by the input signal; The output end of the latch circuit (003) is connected to the input end of the stacked inverter circuit (004); the latch circuit (003) is used to realize data transmission and latching, and to realize single event upset resistance in the latched state; The output end of the stacked inverter circuit (004) is connected to the output signal Q; the stacked inverter circuit (004) is used to achieve the inversion of the logic level and keep the output level consistent with the input; The clock filter circuit (001) comprises a first delay unit (101), a first C unit (102) and a stacked inverter unit (103); wherein the input end of the first delay unit (101) is connected to the clock input signal CLK; the input end of the first C unit (102) is connected to the clock signal CLK and the output end of the first delay unit (101); the output end of the first C unit (102) is connected to the output signal CLKN and the input end of the stacked inverter unit (103); and the output end of the stacked inverter unit (103) is connected to the output signal CLKNN. The latch circuit (003) comprises a first-stage clocked inverter unit (301), a second-stage clocked inverter unit (302), a first-stage clocked stacked inverter unit (303), a second-stage clocked stacked inverter unit (304) and a third C unit (305); wherein the data input end of the first-stage clocked inverter unit (301) is connected to the data input end of the second-stage clocked inverter (302), and is connected to the output end of the delay filter circuit (002) as the input end of the latch circuit (003); the first and second clock input ends of the first-stage clocked inverter unit (301) are respectively connected to the output signals CLKN and CLKNN of the clock filter circuit (001); the output end of the first-stage clocked inverter unit (301) is connected to the second data input end of the first-stage clocked stacked inverter unit (303), the second input end of the third C unit (305) and the output end of the second-stage clocked stacked inverter unit (304); The first and second clock input terminals of the second-stage clocked inverter (302) are connected to the output signals CLKN and CLKNN of the clock filter circuit (001); the output terminal of the second-stage clocked inverter (302) is connected to the second data input terminal of the second-stage clocked stacked inverter unit (304), the first input terminal of the third C unit (305), and the output terminal of the first-stage clocked stacked inverter unit (303); The first and second clock input terminals of the first-stage clocked stacked inverter unit (303) are respectively connected to the output signals CLKNN and CLKN of the clock filter circuit (001); the first data input terminal of the first-stage clocked stacked inverter unit (303) is connected to the output terminal of the third C unit (305) and the first data input terminal of the second-stage clocked stacked inverter unit (304), and serves as the output terminal of the latch circuit (003) and is connected to the input terminal of the stacked inverter circuit (004); the first and second clock input terminals of the second-stage clocked stacked inverter unit (304) are respectively connected to the output signals CLKNN and CLKN of the clock filter circuit (001).

2. The latch circuit structure according to claim 1, wherein: The first delay unit (101) is an n-stage cascaded stacked inverter unit; the m-th stage stacked inverter unit includes PMOS transistors Pm1 and Pm2 and NMOS transistors Nm1 and Nm2; the gates of the PMOS transistors Pm1 and Pm2 and the NMOS transistors Nm1 and Nm2 are connected, serving as the input end of the stacked inverter unit and connected to the output end of the m-1-th stage inverter; the source of the PMOS transistor Pm1 is connected to the power supply signal VDD, and the drain of the PMOS transistor Pm1 is connected to the source of the PMOS transistor Pm2; the drain of the PMOS transistor Pm2 is connected to the drain of Nm1 and serves as the output end of the m-th stage inverter and connected to the input end of the m+1-th stage inverter; the source of the NMOS transistor Nm1 is connected to the drain of the NMOS transistor Nm2; the source of the NMOS transistor Nm2 is connected to the power ground signal GND; wherein n≥m≥1.

3. The latch circuit structure according to claim 1, wherein: The first C unit (102) includes PMOS transistors P101 and P102 and NMOS transistors N101 and N102; the gate of the PMOS transistor P101 is connected to the gate of the NMOS transistor N101 and serves as a first input terminal of the C unit and is connected to an input clock signal CLK; the source of the PMOS transistor P101 is connected to a power supply VDD; the drain of the PMOS transistor P101 is connected to the source of the PMOS transistor P102; the gate of the PMOS transistor P102 is connected to the gate of N102 and serves as a second input terminal of the C unit and is connected to the output terminal of the first delay unit (101); the drain of the PMOS transistor P102 is connected to the drain of the NMOS transistor N101 and is connected as an output terminal of the C unit and is connected to an inverted output clock signal CLKN; the source of the NMOS transistor N101 is connected to the drain of the NMOS transistor N102; the source of the NMOS transistor N102 is connected to a power ground GND.

4. The latch circuit structure according to claim 1, wherein: The stacked inverter unit (103) comprises PMOS transistors P103 and P104, and NMOS transistors N103 and N104; the gates of the PMOS transistors P103 and P104 and the NMOS transistors N103 and N104 are connected and serve as the input end of the stacked inverter unit (103) and are connected to the output end of the first C unit (102); the source of the PMOS transistor P103 is connected to the power supply VDD, and the drain of the PMOS transistor P103 is connected to the source of the PMOS transistor P104; the drain of the PMOS transistor P104 is connected to the drain of the NMOS transistor N103 and serves as the output end of the stacked inverter unit (103) and is connected to the output clock signal CLKNN; the source of the NMOS transistor N103 is connected to the drain of the NMOS transistor N104; and the source of the NMOS transistor N104 is connected to the power ground GND.

5. The latch circuit structure according to claim 1, wherein: The delay filter circuit (002) comprises a second delay unit (201) and a second C unit (202); wherein the input end of the second delay unit (201) is connected to the input signal D; the input end of the second C unit (202) is connected to the input signal D and the output end of the second delay unit (201); and the output end of the second C unit (202) is connected to the input end of the latch circuit (003); The second C unit (202) includes PMOS transistors P201 and P202 and NMOS transistors N201 and N202; the gate of the PMOS transistor P201 is connected to the gate of the NMOS transistor N201 and serves as the first input terminal of the second C unit (202) and is connected to the input signal D; the source of the PMOS transistor P201 is connected to the power supply VDD, and the drain of the PMOS transistor P201 is connected to the source of the PMOS transistor P202; the PMOS transistor P20 The gate of the PMOS transistor P202 is connected to the gate of N202 and serves as the second input terminal of the second C unit (202) and is connected to the output terminal of the second delay unit (201); the drain of the PMOS transistor P202 is connected to the drain of the NMOS transistor N201 and serves as the output terminal of the second C unit (202) and is connected to the input terminal of the latch circuit (003); the source of the NMOS transistor N201 is connected to the drain of the NMOS transistor N202; and the source of the NMOS transistor N202 is connected to the power ground GND.

6. The latch circuit structure according to claim 5, wherein: The first-stage clocked inverter unit (301) includes PMOS transistors P311 and P312 and NMOS transistors N311 and N312. The gate of the PMOS transistor P311 is connected to the gate of the NMOS transistor N312 and serves as the data input terminal of the first-stage clocked inverter unit (301) and is connected to the output terminal of the delay filter circuit (002). The source of the PMOS transistor P311 is connected to the power supply VDD, and the drain of the PMOS transistor P311 is connected to the source of the PMOS transistor P312. The gate of the PMOS transistor P312 is connected to the output signal CLKN of the clock filter circuit (001) as a first clock input terminal, the drain of the PMOS transistor P312 is connected to the drain of the NMOS transistor N311 and serves as the output terminal of the first-stage clock-controlled inverter unit (301); the gate of the NMOS transistor N311 is connected to the output signal CLKNN of the clock filter circuit (001) as a second clock input terminal, and is connected to the output signal CLKNN of the clock filter circuit (001); the source of the NMOS transistor N311 is connected to the drain of the NMOS transistor N312; the source of the NMOS transistor N312 is connected to the power ground GND; The second-stage clocked inverter circuit (302) includes PMOS transistors P321 and P322 and NMOS transistors N321 and N322. The gate of the PMOS transistor P321 is connected to the gate of the NMOS transistor N322 and serves as the data input of the second-stage clocked inverter circuit (302) and is connected to the output of the delay filter circuit (002). The source of the PMOS transistor P321 is connected to the power supply VDD, and the drain of the PMOS transistor P321 is connected to the source of P322. The gate of the PMOS transistor P322 is connected to the gate of the NMOS transistor N322. The output signal CLKN of the clock filter circuit (001) is connected as a first clock input terminal, the drain of the PMOS transistor P322 is connected to the drain of the NMOS transistor N321, and serves as the output terminal of the second-stage clocked inverter circuit (302); the gate of the NMOS transistor N321 serves as a second clock input terminal, connected to the output signal CLKNN of the clock filter circuit (001), the source of the NMOS transistor N321 is connected to the drain of the NMOS transistor N322; and the source of the NMOS transistor N322 is connected to the power ground GND.

7. The latch circuit structure according to claim 6, wherein: The first-stage clocked stacked inverter circuit (303) comprises PMOS transistors P331, P332, and P333 and NMOS transistors N331, N332, and N333; the gate of the PMOS transistor P331 is connected to the gate of the NMOS transistor N333 and serves as the first data input terminal of the first-stage clocked stacked inverter circuit (303) and is connected to the output terminal of the third C unit (305); the source of the PMOS transistor P331 is connected to the power supply signal VDD, and the drain of the PMOS transistor P331 is connected to the source of the PMOS transistor P332; The gate of the PMOS transistor P332 serves as the first clock input terminal of the first-stage clocked stacked inverter circuit (303) and is connected to the output signal CLKNN of the clock filter circuit (001). The drain of the PMOS transistor P332 is connected to the source of the NMOS transistor N331. The gate of the NMOS transistor N331 is connected to the gate of the PMOS transistor P333 and serves as the second data input terminal of the first-stage clocked stacked inverter circuit (303) and is connected to the output terminal of the first-stage clocked inverter unit (301). The drain of the NMOS transistor N331 is connected to the source of the NMOS transistor N331. The drain of the PMOS transistor P333 is connected and serves as the output terminal of the first-stage clocked stacked inverter circuit (303), and is connected to the output terminal of the second-stage clocked inverter circuit (302); the source of the PMOS transistor P333 is connected to the drain of the NMOS transistor N332; the gate of the NMOS transistor N332 serves as the second clock input terminal of the first-stage clocked stacked inverter circuit (303), and is connected to the output signal CLKN of the clock filter circuit (001); the source of the NMOS transistor N332 is connected to the drain of the NMOS transistor N333; the source of the NMOS transistor N333 is connected to the power ground GND; The second-stage clocked stacked inverter circuit (304) includes PMOS transistors P341, P342, and P343 and NMOS transistors N341, N342, and N343; the gate of the PMOS transistor P341 is connected to the gate of the NMOS transistor N343 and serves as the first data input terminal of the second-stage clocked stacked inverter circuit (304) and is connected to the output terminal of the third C unit (305); the source of the PMOS transistor P341 is connected to the power supply signal VDD, and the drain of the PMOS transistor P341 is connected to the source of the PMOS transistor P342; The gate of the PMOS transistor P342 serves as the first clock input terminal of the second-stage clocked stacked inverter circuit (304) and is connected to the output signal CLKNN of the clock filter circuit (001). The drain of the PMOS transistor P342 is connected to the source of the NMOS transistor N341. The gate of the NMOS transistor N341 is connected to the gate of the PMOS transistor P343 and serves as the second data input terminal of the second-stage clocked stacked inverter circuit (304) and is connected to the output terminal of the second-stage clocked inverter circuit (302). The drain of the NMOS transistor N341 is connected to the gate of the PMOS transistor P343. The drain of the PMOS transistor P343 is connected and serves as the output terminal of the second-stage clocked stacked inverter circuit (304), and is connected to the output terminal of the first-stage clocked inverter unit (301); the source of the PMOS transistor P343 is connected to the drain of the NMOS transistor N342; the gate of the NMOS transistor N342 serves as the second clock input terminal of the second-stage clocked stacked inverter circuit (304), and is connected to the output signal CLKN of the clock filter circuit (001); the source of the NMOS transistor N342 is connected to the drain of the NMOS transistor N343; the source of the NMOS transistor N343 is connected to the power ground GND; The third C unit (305) includes PMOS transistors P351 and P352 and NMOS transistors N351 and N352; the gate of the PMOS transistor P351 is connected to the gate of the NMOS transistor N351 and serves as the first input terminal of the third C unit (305) and is connected to the output terminal of the second-stage clocked inverter circuit (302); the source of the PMOS transistor P351 is connected to the power supply VDD, and the drain of the PMOS transistor P351 is connected to the source of the PMOS transistor P352; the PMOS transistor The gate of P352 is connected to the gate of N352 and serves as the second input of the third C unit (305) and is connected to the output of the first-stage clocked inverter circuit unit (301). The drain of the PMOS transistor P352 is connected to the drain of the NMOS transistor N351 and serves as the output of the third C unit (305) and is connected to the input of the stacked inverter circuit (004). The source of the NMOS transistor N351 is connected to the drain of the NMOS transistor N352. The source of the NMOS transistor N352 is connected to the power ground GND.

8. The latch circuit structure according to claim 1, wherein: The stacked inverter circuit (004) comprises PMOS transistors P401 and P402 and NMOS transistors N401 and N402; wherein the gates of the PMOS transistors P401 and P402 and the NMOS transistors N401 and N402 are connected and serve as the input end of the stacked inverter circuit (004) and are connected to the output end of the latch circuit (003); the source of the PMOS transistor P401 is connected to the power supply VDD, and the drain of the PMOS transistor P401 is connected to the source of the PMOS transistor P402; the drain of the PMOS transistor P402 is connected to the drain of the NMOS transistor N401 and serves as the output end of the stacked inverter circuit (004) and is connected to the output signal Q; The source of the NMOS transistor N401 is connected to the drain of the NMOS transistor N402 ; the source of the NMOS transistor N402 is connected to the power ground GND.

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