Data sampling circuit and memory

Abstract

The present disclosure relates to a data sampling circuit and a memory, the data sampling circuit comprising: an initial reference voltage generating module configured to generate a first initial reference voltage, a second initial reference voltage, a third initial reference voltage and a fourth initial reference voltage; a data receiving module configured to compare a to-be-sampled data with the first initial reference voltage to generate first data, compare the to-be-sampled data with the second initial reference voltage to generate second data, compare the to-be-sampled data with the third initial reference voltage to generate third data, compare the to-be-sampled data with the fourth initial reference voltage to generate fourth data, and compensate one side of the to-be-sampled data or one side of the first initial reference voltage to the fourth initial reference voltage by a compensation current during the comparison; and a first selection circuit and a second selection circuit configured to select a sampling result data based on the first data, the second data, the third data or the fourth data.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of semiconductor circuit design, and particularly relates to a data sampling circuit and a memory. BACKGROUND

[0002] In the design of a memory receiver circuit, the data to be sampled is usually sampled based on the effective edge of a sampling clock. The sampling of the data to be sampled, i.e. comparing the level of the data to be sampled with a reference voltage, if the level of the data to be sampled is greater than the reference voltage, a data "1" is output, i.e. the sampling result is high, and if the level of the data to be sampled is less than the reference voltage, a data "0" is output, i.e. the sampling result is low.

[0003] In a high-speed computer link, as the transmission speed of data signals becomes faster and faster, it is inevitable that significant inter symbol interference (ISI) will occur. The influence of ISI can cause the level of the data to be sampled to be unable to rise to a level greater than the reference voltage, resulting in the receiver incorrectly sampling and outputting a data "0", or the level of the data to be sampled to be unable to fall to a level less than the reference voltage, resulting in the receiver incorrectly sampling and outputting a data "1". SUMMARY

[0004] Embodiments of the present disclosure provide a data sampling circuit and a memory to improve the accuracy of data sampling by the memory.

[0005] One embodiment of this disclosure provides a data sampling circuit, including: an initial reference voltage generation module, configured to receive an original code, a first code, and a second code, and generate a first initial reference voltage based on the original code + the first code + the second code, generate a second initial reference voltage based on the original code + the first code - the second code, generate a third initial reference voltage based on the original code - the first code + the second code, and generate a fourth initial reference voltage based on the original code - the first code - the second code; and a data receiving module, configured to receive the first initial reference voltage, the second initial reference voltage, the third initial reference voltage, the fourth initial reference voltage, a third selection signal, and data to be sampled, configured to: compare the data to be sampled and the first initial reference voltage based on the third selection signal to generate first data; compare the data to be sampled and the second initial reference voltage based on the third selection signal to generate second data; compare the data to be sampled and the third initial reference voltage based on the third selection signal to generate third data; and compare the data to be sampled and the fourth initial reference voltage based on the third selection signal to generate fourth data; the third selection signal is configured to: when the first initial reference voltage, the first initial reference voltage, the second initial reference voltage, the third initial reference voltage, and the second initial reference voltage are used to generate a third initial reference voltage; the third selection signal is configured to: when the first initial reference voltage, the second initial reference voltage, and the third initial reference voltage are used to generate a fourth initial reference voltage; the third initial reference voltage is configured to: when the first initial reference voltage, the second initial reference voltage, and the third initial reference voltage are used to generate a third initial reference voltage; the third initial reference voltage ... third initial reference voltage; the third initial reference voltage is configured to: when During the comparison of the first initial reference voltage, the third initial reference voltage, the fourth initial reference voltage, and the data to be sampled, a compensation current is provided to the side containing the first initial reference voltage, the second initial reference voltage, the third initial reference voltage, and the fourth initial reference voltage, or to the side containing the data to be sampled. A first selection circuit, used to receive the first data, the second data, the third data, the fourth data, and a second selection signal, is configured to select either the first data or the second data to output the first reference data based on the second selection signal, and to select either the third data or the fourth data to output the second reference data based on the second selection signal. A second selection circuit, used to receive the first reference data, the second reference data, and the first selection signal, is configured to select either the first reference data or the second reference data to output the sampling result data based on the first selection signal. The second selection signal is used to consider the influence of the previous second bit data on the current data to be sampled, the first selection signal is used to consider the influence of the previous first bit data on the current data to be sampled, and the third selection signal is used to consider the influence of at least the previous third bit data among all data before the first two bits on the current data to be sampled.

[0006] For the sampling circuit provided by the embodiment, based on the influence of the plurality of data before the previous 2 bits on the sampling of the current to-be-sampled data, the side where the to-be-sampled data is located or the side where the first initial reference voltage to the fourth initial reference voltage is located is compensated by the compensation current, so as to offset the influence of the plurality of data before the previous 2 bits on the sampling of the current to-be-sampled data; and based on the influence of the previous first bit data and the previous second bit data on the sampling of the current to-be-sampled data, an adaptive comparison result is selected as the sampling result data of the memory, so as to offset the influence of the previous first bit data and the previous second bit data on the sampling of the current to-be-sampled data, thereby improving the accuracy of data sampling of the memory.

[0007] Optionally, the data receiving module comprises: a first receiving circuit configured to receive the first initial reference voltage, the third selection signal and the to-be-sampled data, and configured to compare the to-be-sampled data and the first initial reference voltage based on the third selection signal to generate the first data, the third selection signal being configured to provide the compensation current to the side where the first initial reference voltage is located or to the side where the to-be-sampled data is located during the comparison between the first initial reference voltage and the to-be-sampled data; a second receiving circuit configured to receive the second initial reference voltage, the third selection signal and the to-be-sampled data, and configured to compare the to-be-sampled data and the second initial reference voltage based on the third selection signal to generate the second data, the third selection signal being configured to provide the compensation current to the side where the second initial reference voltage is located or to the side where the to-be-sampled data is located during the comparison between the second initial reference voltage and the to-be-sampled data; a third receiving circuit configured to receive the third initial reference voltage, the third selection signal and the to-be-sampled data, and configured to compare the to-be-sampled data and the third initial reference voltage based on the third selection signal to generate the third data, the third selection signal being configured to provide the compensation current to the side where the third initial reference voltage is located or to the side where the to-be-sampled data is located during the comparison between the third initial reference voltage and the to-be-sampled data; and a fourth receiving circuit configured to receive the fourth initial reference voltage, the third selection signal and the to-be-sampled data, and configured to compare the to-be-sampled data and the fourth initial reference voltage based on the third selection signal to generate the fourth data, the third selection signal being configured to provide the compensation current to the side where the fourth initial reference voltage is located or to the side where the to-be-sampled data is located during the comparison between the fourth initial reference voltage and the to-be-sampled data.

[0008] Optionally, the first receiving circuit comprises: a first N-type transistor, a control terminal of the first N-type transistor configured to receive a first initial reference voltage, a first terminal of the first N-type transistor configured to output the first data, and a second terminal of the first N-type transistor connected to a first terminal of a first current source, and a second terminal of the first current source connected to a ground; a second N-type transistor, a control terminal of the second N-type transistor configured to receive the data to be sampled, a first terminal of the second N-type transistor connected to control terminals of a first P-type transistor and a second P-type transistor, and a second terminal of the second N-type transistor connected to the first terminal of the first current source; a first terminal of the first P-type transistor configured to receive a power supply signal, a second terminal of the first P-type transistor connected to the first terminal of the first N-type transistor; a first terminal of the second P-type transistor connected to the first terminal of the first P-type transistor, and a second terminal of the second P-type transistor connected to the first terminal of the second N-type transistor; and an adjusting unit connected to the first terminal of the first N-type transistor and the first terminal of the second N-type transistor, and configured to provide a compensation current to the first terminal of the first N-type transistor or the first terminal of the second N-type transistor based on a third selection signal.

[0009] Optionally, the adjusting unit comprises: a third N-type transistor, a first terminal of the third N-type transistor connected to the first terminal of the first N-type transistor, a control terminal of the third N-type transistor configured to receive a first adjusting voltage, a voltage value of the first adjusting voltage adjusted based on a third code, and the voltage value of the first adjusting voltage positively correlated to a value of the third code; a fourth N-type transistor, a first terminal of the fourth N-type transistor connected to a second terminal of the third N-type transistor, a control terminal of the fourth N-type transistor configured to receive the third selection signal, and a second terminal of the fourth N-type transistor connected to a first terminal of a second current source, and a second terminal of the second current source connected to the ground; a fifth N-type transistor, a first terminal of the fifth N-type transistor connected to the first terminal of the second N-type transistor, and a control terminal of the fifth N-type transistor configured to receive the first adjusting voltage; and a sixth N-type transistor, a first terminal of the sixth N-type transistor connected to a second terminal of the fifth N-type transistor, a control terminal of the sixth N-type transistor configured to receive an inverted signal of the third selection signal, and a second terminal of the sixth N-type transistor connected to the first terminal of the second current source.

[0010] Optionally, the adjusting unit comprises: a third P-type transistor, a first terminal of the third P-type transistor configured to receive the power supply signal, and a control terminal of the third P-type transistor configured to receive a second adjusting voltage, a voltage value of the second adjusting voltage adjusted based on a third code, and the voltage value of the second adjusting voltage negatively correlated to a value of the third code; a fourth P-type transistor, a first terminal of the fourth P-type transistor connected to a second terminal of the third P-type transistor, a control terminal of the fourth P-type transistor configured to receive the third selection signal, and a second terminal of the fourth P-type transistor connected to the first terminal of the first N-type transistor; a fifth P-type transistor, a first terminal of the fifth P-type transistor connected to the first terminal of the third P-type transistor, and a control terminal of the fifth P-type transistor configured to receive the second adjusting voltage; and a sixth P-type transistor, a first terminal of the sixth P-type transistor connected to a second terminal of the fifth P-type transistor, a control terminal of the sixth P-type transistor configured to receive an inverted signal of the third selection signal, and a second terminal of the sixth P-type transistor connected to the first terminal of the second N-type transistor.

[0011] Optionally, the initial reference voltage generation module is further configured to generate the first adjusting voltage based on the third code.

[0012] Optionally, the voltage value of the first initial reference voltage > the voltage value of the second initial reference voltage > the voltage value of the third initial reference voltage > the voltage value of the fourth initial reference voltage.

[0013] Optionally, the initial reference voltage generation module comprises: a voltage dividing circuit comprising N voltage output terminals, and each voltage output terminal outputs different voltage, N being an integer greater than 1; a decoding circuit configured to receive the original code, the first code and the second code, and configured to generate the first processing signal based on the original code + the first code + the second code decoding, generate the second processing signal based on the original code + the first code - the second code decoding, generate the third processing signal based on the original code - the first code + the second code decoding, and generate the fourth processing signal based on the original code - the first code - the second code decoding; a first processing circuit connected to the voltage dividing circuit and the decoding circuit, and configured to select the corresponding voltage output terminal of the voltage dividing circuit to output the first initial reference voltage based on the first processing signal; a second processing circuit connected to the voltage dividing circuit and the decoding circuit, and configured to select the corresponding voltage output terminal of the voltage dividing circuit to output the second initial reference voltage based on the second processing signal; a third processing circuit connected to the voltage dividing circuit and the decoding circuit, and configured to select the corresponding voltage output terminal of the voltage dividing circuit to output the third initial reference voltage based on the third processing signal; and a fourth processing circuit connected to the voltage dividing circuit and the decoding circuit, and configured to select the corresponding voltage output terminal of the voltage dividing circuit to output the fourth initial reference voltage based on the fourth processing signal.

[0014] Optionally, the voltage dividing circuit comprises: N-1 first resistors connected in series, wherein the first end of the first first resistor is configured to receive a first internal voltage, the second end of the last first resistor is configured to receive a second internal voltage, and the second end of each first resistor is connected to the first end of the next first resistor; the voltage value of the first internal voltage is greater than the voltage value of the second internal voltage; the two ends of each first resistor are used as output ports to form N voltage output terminals; the first processing signal comprises N first sub-signals, and only one valid signal is included in the N first sub-signals; the first processing circuit comprises: N first switching transistors, the control end of each first switching transistor corresponds to receive a corresponding first sub-signal; the first terminal of each first switching transistor corresponds to connect to a corresponding voltage output terminal of the N voltage output terminals, and the second terminal is connected to the output terminal of the first processing circuit to output the first initial reference voltage.

[0015] Another embodiment of the present disclosure also provides a memory comprising the data sampling circuit provided by the above-mentioned embodiments, so as to improve the accuracy of data sampling of the memory. BRIEF DESCRIPTION OF DRAWINGS

[0016] One or more embodiments are illustrated by way of example in the drawings and described herein in connection with the enumerated embodiments. These embodiments are not intended to limit the scope of the embodiments to their specific constructions, but, on the contrary, to cover all possible modifications and equivalent arrangements, unless otherwise specified. Although the drawings represent the current embodiments, the drawings are not necessarily to scale and certain features can have been exaggerated or minimized. When a feature is considered to be in the prior art, then the drawing will generally indicate that with the reference numeral followed by "prior art" or "PA". The drawings are included to provide a description of the principles of operation of the various embodiments and not as a definition of the claims. Embodiments of the disclosure will be described below with reference to the accompanying drawings of which:

[0017] Figure 1 A schematic diagram of the effects of the previous one bit data and the previous two bit data on the to-be-sampled data DQ according to an embodiment of the disclosure;

[0018] Figure 2 A schematic diagram of the principle of sampling the to-be-sampled data DQ by different reference voltages according to an embodiment of the disclosure;

[0019] Figure 3 A schematic diagram of the structure of a data sampling circuit according to an embodiment of the disclosure;

[0020] Figure 4 A schematic diagram of the structure of a data receiving module according to an embodiment of the disclosure;

[0021] Figure 5 A schematic diagram of the structure of a first receiving circuit according to an embodiment of the disclosure;

[0022] Figure 6 A schematic diagram of the structure of an adjusting unit according to an embodiment of the disclosure;

[0023] Figure 7 A schematic diagram of the structure of another adjusting unit according to an embodiment of the disclosure;

[0024] Figure 8 A schematic diagram of the structure of an initial reference voltage generating module according to an embodiment of the disclosure;

[0025] Figure 9 A schematic diagram of the structure of a voltage dividing circuit and a first processing circuit according to an embodiment of the disclosure. DETAILED DESCRIPTION

[0026] As can be known from the background art, in a computer high-speed link, as the transmission speed of a data signal becomes faster and faster, obvious inter symbol interference (ISI) is inevitably generated. The influence of ISI can cause the level of the data to be sampled to be unable to rise to a level greater than a reference voltage, causing the receiver to output data "0" by error sampling, or cause the level of the data to be sampled to be unable to fall to a level less than the reference voltage, causing the receiver to output data "1" by error sampling.

[0027] An embodiment of the present disclosure provides a data sampling circuit to improve the accuracy of data sampling of a memory.

[0028] Those skilled in the art can understand that, in the embodiments of the present disclosure, many technical details are proposed in order to enable the reader to better understand the present disclosure. However, the technical solutions claimed by the present disclosure can be implemented even without these technical details and various changes and modifications based on the following embodiments. The division of the following embodiments is for the convenience of description, and should not constitute any limitation on the specific implementation modes of the present disclosure. The embodiments can be combined with each other and mutually referenced without contradiction.

[0029] Figure 1 A schematic diagram of the influence of the previous one-bit data and the previous two-bit data on the data to be sampled DQ provided for the embodiment, Figure 2 A schematic diagram of the principle of sampling the data to be sampled DQ by different reference voltages provided for the embodiment, Figure 3 A structural schematic diagram of the data sampling circuit provided for the embodiment, Figure 4 A structural schematic diagram of the data receiving module provided for the embodiment, Figure 5 A structural schematic diagram of the first receiving circuit provided for the embodiment, Figure 6 A structural schematic diagram of the adjusting unit provided for the embodiment, Figure 7 A structural schematic diagram of another adjusting unit provided for the embodiment, Figure 8 A structural schematic diagram of the initial reference voltage generation module provided for the embodiment, Figure 9 A structural schematic diagram of the voltage dividing circuit and the first processing circuit provided for the embodiment, the data sampling circuit provided for the embodiment is described in detail below in combination with the accompanying drawings, and specifically as follows:

[0030] For the memory, the signal sampling of the memory is implemented based on a comparator. Specifically, the comparator compares the voltage of the data to be sampled DQ with the reference voltage based on the active edge of the sampling signal, and outputs a high level, i.e., data "1", if the voltage of the data to be sampled DQ is greater than the reference voltage, and outputs a low level, i.e., data "0", if the voltage of the data to be sampled DQ is less than the reference voltage.

[0031] However, in high-speed links of computers, the transmission speed of data signals is getting faster and faster, and the time interval of the effective edge of the sampling clock is getting smaller and smaller, so as to collect more data in a unit of time, but this operation causes obvious Inter Symbol Interference (ISI) in the sampling of the memory.

[0032] For ISI, refer to Figure 1 In an example, when the to-be-sampled data DQ changes from "0" to "1", because the time interval between the effective edges of the sampling clock is reduced, when the effective edge of the sampling clock arrives, the actual level of the to-be-sampled data DQ has not risen to a sufficient height, which may cause the actual voltage of the to-be-sampled data DQ to be still less than the reference voltage at this time, and the comparator may make an error collection, so as to output data "0"; when the to-be-sampled data DQ changes from "1" to "0", because the time interval between the effective edges of the sampling clock is reduced, when the effective edge of the sampling clock arrives, the actual level of the to-be-sampled data DQ has not fallen to a sufficient height, which may cause the actual voltage of the to-be-sampled data DQ to be still greater than the reference voltage at this time, and the comparator may make an error collection, so as to output data "1".

[0033] For the influence of ISI, the current common solution is to set the reference voltage as a high reference voltage VCH and a low reference voltage VCL, and adjust the reference voltage used by the comparator to sample the current to-be-sampled data DQ based on the data of the previous bit. For example, if the previous bit data is "0", the comparator is set to sample the current to-be-sampled data DQ based on the low reference voltage VCL, and if the current to-be-sampled data DQ changes from "0" to "1", although the actual level of the to-be-sampled data DQ has not risen to a sufficient height, by using the low reference voltage VCL as the reference voltage, the possibility that the actual level of the to-be-sampled data DQ is less than the reference voltage is reduced, thereby to a certain extent, the influence of ISI is alleviated; similarly, if the previous bit data is "1", the comparator is set to sample the current to-be-sampled data DQ based on the high reference voltage VCH, and if the current to-be-sampled data DQ changes from "1" to "0", although the actual level of the to-be-sampled data DQ has not fallen to a sufficient height, by using the high reference voltage VCH as the reference voltage, the possibility that the actual level of the to-be-sampled data DQ is greater than the reference voltage is reduced, thereby to a certain extent, the influence of ISI is alleviated.

[0034] However, this scheme only considers the influence of the previous first bit data on the sampling of the current to-be-sampled data DQ, and the previous second bit data, and the previous third bit data… also have certain influence on the sampling of the current to-be-sampled data DQ; if only the influence of the previous first bit data on the sampling of the current to-be-sampled data DQ is considered, in actual application, the comparator still has the problem of error sampling.

[0035] The influence of the first bit data and the second bit data on the to-be-sampled data DQ can be referred to Figure 1 , assuming that, in an ideal case, the high level of the to-be-sampled data DQ is set to 1 and the low level is set to 0; the previous bit data is “0” and the current to-be-sampled data DQ is intended to jump to “1”, when the active edge of the sampling clock arrives, the level of the to-be-sampled data rises to 0.7, if the second bit data is also “0”, when the active edge of the sampling clock arrives, the level of the to-be-sampled data only rises to 0.6, if the second bit data is “1”, when the active edge of the sampling clock arrives, the level of the to-be-sampled data rises to 0.8; the previous bit data is “1” and the current to-be-sampled data DQ is intended to jump to “0”, when the active edge of the sampling clock arrives, the level of the to-be-sampled data falls to 0.3, if the second bit data is also “1”, when the active edge of the sampling clock arrives, the level of the to-be-sampled data only falls to 0.4, if the second bit data is “0”, when the active edge of the sampling clock arrives, the level of the to-be-sampled data falls to 0.2; thus, it can be known that, after the influence of the second bit data and the third bit data …, the change range of the current to-be-sampled data DQ is larger, and the memory still has the problem of error sampling.

[0036] And the influence of the third bit data, the fourth bit data … on the current to-be-sampled data DQ is similar to the influence of the first bit data on the current to-be-sampled data DQ and the influence of the second bit data on the current to-be-sampled data DQ, only the influence of the bit data farther away on the current to-be-sampled data DQ is smaller.

[0037] In order to consider the influence of the data before the to-be-sampled data DQ on the current to-be-sampled data DQ, reference can be made to Figure 2 , in combination with the influence of the first bit data on the to-be-sampled data DQ, the embodiment adjusts one reference voltage V into two reference voltages V+ and V-, and in combination with the influence of the second bit data on the to-be-sampled data DQ, the two reference voltages V+ and V- are expanded into four reference voltages V++, V+, V- and V--. In the sampling process, the four reference voltages or the to-be-sampled data DQ are fine-tuned based on the influence of the third bit data and the previous data on the current to-be-sampled data DQ, so as to improve the accuracy of data sampling of the memory.

[0038] Specifically, reference can be made to Figure 3 , the data sampling circuit 100 provided by the embodiment comprises:

[0039] An initial reference voltage generation module 103 is configured to receive an original code code, a first code c1 and a second code c2, and generate a first reference voltage V+ and a second reference voltage V- based on the original code code <a:0>+ first encoding c1 <a:0>+ second encoding c2 <a:0>generating a first initial reference voltage Vr1 based on an original code code <a:0>+ first encoding c1 <a:0>- second encoding c2 <a:0>generating a second initial reference voltage Vr2 based on the original code code <a:0>- a first encoding c1 <a:0>+ second encoding c2 <a:0>generating a third initial reference voltage Vr3 based on the original code code <a:0>- first encoding c1 <a:0>- second encoding c2 <a:0>A fourth initial reference voltage Vr4 is generated.

[0040] For the initial reference voltage generating module 103, in one example, the greater the code used to generate the initial reference voltage, the greater the initial reference voltage generated; in another example, it can also be set that the greater the code used to generate the initial reference voltage, the smaller the initial reference voltage generated; in the subsequent description of the embodiment, the initial reference voltage generating module 103 is described in detail taking the example that the greater the code used to generate the initial reference voltage, the greater the initial reference voltage generated.

[0041] Specifically, the initial reference voltage generating module 103 only generates the initial reference voltage Vr4 based on the original code code <a:0>The generated voltage, i.e. the reference voltage V mentioned above, i.e. the original code code <a:0>the size of the reference voltage V; the first code c1 <a:0>The size of the first bit data is used to measure the influence parameter of the previous first bit data on the current to-be-sampled data DQ, and the initial reference voltage generation module 103 generates the initial reference voltage Vref based on the original code code <a:0>+ first encoding c1 <a:0>The generated voltage is the reference voltage V+△V1, i.e. V+ mentioned above; the initial reference voltage generation module 103 generates the initial reference voltage based on the original code code <a:0>- first encoding c1 <a:0>The generated voltage is the reference voltage V - ΔV1, i.e. V - mentioned above; the second code c2 <a:0>The size of the second bit data is used to measure the influence parameter of the previous second bit data on the current to-be-sampled data DQ, and the initial reference voltage generation module 103 generates the initial reference voltage Vref based on the original code code <a:0>+ first encoding c1 <a:0>+ second encoding c2 <a:0>The generated voltage is the reference voltage V+△V1+△V2, i.e. the first initial reference voltage Vr1, i.e. the aforementioned V++. The initial reference voltage generation module 103 generates the initial reference voltage Vr1 based on the original code code <a:0>+ first encoding c1 <a:0>- second encoding c2 <a:0>The generated voltage is the reference voltage V+△V1-△V2, i.e. the second initial reference voltage Vr2, i.e. the aforementioned V+; the initial reference voltage generation module 103 generates the initial reference voltage Vr2 based on the original code code <a:0>- a first encoding c1 <a:0>+ second encoding c2 <a:0>The generated voltage is the reference voltage V - ΔV1+ ΔV2, i.e. the third initial reference voltage Vr3, i.e. V -+ mentioned above; the initial reference voltage generation module 103 generates the initial reference voltage Vr3 based on the original code code <a:0>- first encoding c1 <a:0>- second encoding c2 <a:0>The generated voltage is the reference voltage V -△V1-△V2, i.e. the fourth initial reference voltage Vr4 mentioned above V-.

[0042] In combination with the foregoing, in this arrangement, the voltage value of the first initial reference voltage Vr1 > the voltage value of the second initial reference voltage Vr2 > the voltage value of the third initial reference voltage Vr3 > the voltage value of the fourth initial reference voltage Vr4.

[0043] Since the original code code <a:0>the size of the reference voltage V, the first code c1 <a:0>the size of the first bit data is used to measure the influence parameter of the previous first bit data on the current to-be-sampled data DQ, and the second encoding c2 <a:0>The size of the first bit data is used to measure the influence parameter of the second bit data on the current to-be-sampled data DQ, and the influence of the first bit data on the current to-be-sampled data DQ is greater than the influence of the second bit data on the current to-be-sampled data DQ, that is, the original code <a:0>value of the first encoding c1 <a:0>value of the first encoding c1 > value of the second encoding c2 <a:0>the value of the first initial reference voltage Vr1.

[0044] With reference back to Figure 3 The data sampling circuit 100 further comprises a data receiving module 104 configured to receive the first initial reference voltage Vr1, the second initial reference voltage Vr2, the third initial reference voltage Vr3, the fourth initial reference voltage Vr4, and the third selection signal sel3 and the data to be sampled DQ. The data receiving module 104 is configured to compare the data to be sampled DQ with the first initial reference voltage Vr1 based on the third selection signal sel3 to generate the first data SJ1, compare the data to be sampled DQ with the second initial reference voltage Vr2 based on the third selection signal sel3 to generate the second data SJ2, compare the data to be sampled DQ with the third initial reference voltage Vr3 based on the third selection signal sel3 to generate the third data SJ3, and compare the data to be sampled DQ with the fourth initial reference voltage Vr4 based on the third selection signal sel3 to generate the fourth data SJ4. The third selection signal sel3 is configured to provide a compensation current to the side where the first initial reference voltage Vr1, the second initial reference voltage Vr2, the third initial reference voltage Vr3, and the fourth initial reference voltage Vr4 are located, or to the side where the data to be sampled DQ is located, during the comparison of the first initial reference voltage Vr1, the second initial reference voltage Vr2, the third initial reference voltage Vr3, the fourth initial reference voltage Vr4, and the data to be sampled DQ. The third selection signal sel3 is used to consider the influence of at least the previous third bit of data on the current data to be sampled DQ among all data before the previous two bits.

[0045] In some embodiments, the third selection signal sel3 is used to consider the influence of multiple data on the current data to be sampled DQ before the previous two bits, in which case the value of the third selection signal sel3 is the weighted sum of each bit of data in the considered data range, and the sum of the weights is 1. The closer the data to the current data to be sampled DQ, the greater the weight. In one example, assuming that the third selection signal sel3 is used to consider the influence of the previous third bit of data, the fourth bit of data, and the fifth bit of data on the current data to be sampled DQ, the weight of the previous third bit of data is assigned as 0.6, the weight of the previous fourth bit of data is assigned as 0.25, and the weight of the previous fifth bit of data is assigned as 0.15, i.e., the third selection signal sel3 = the value of the previous third bit of data * 0.6 + the value of the previous fourth bit of data * 0.25 + the value of the previous fifth bit of data * 0.15.

[0046] In some embodiments, the third selection signal sel3 is only used to consider the influence of the previous third bit of data on the current data to be sampled DQ. In some embodiments, the value of the third selection signal sel3 can be directly set based on the previous third bit of data to directly feed back the compensation object of the compensation current based on the value of the previous third bit of data.

[0047] Specifically, when the influence of the previous 2 bits of data on the current to-be-sampled data DQ is equivalent to the influence of the previous third bit of data being "0" on the current to-be-sampled data DQ, the third selection signal sel3 is used to control the data sampling circuit 104 to load a compensation current on the side where the to-be-sampled data DQ is located in the comparison process, and when the influence of the previous 2 bits of data on the current to-be-sampled data DQ is equivalent to the influence of the previous third bit of data being "1" on the current to-be-sampled data DQ, the third selection signal sel3 is used to control the data sampling circuit 104 to load a compensation current on the side where the first initial reference voltage Vr1, the second initial reference voltage Vr2, the third initial reference voltage Vr3 and the fourth initial reference voltage Vr4 are located in the comparison process, so as to offset the sampling influence of the previous 2 bits of data on the current to-be-sampled data DQ.

[0048] The first selection circuit 101 is configured to receive the first data SJ1, the second data SJ2, the third data SJ3, the fourth data SJ4 and the second selection signal sel2, and is configured to select the first reference data SJC1 based on the first data SJ1 or the second data SJ2 based on the second selection signal sel2, and select the second reference data SJC2 based on the third data SJ3 or the fourth data SJ4 based on the second selection signal sel2, wherein the second selection signal sel2 is used to consider the influence of the previous second bit of data on the current to-be-sampled data.

[0049] Specifically, when the previous second bit of data is "0", the second selection signal sel2 is used to control the first selection circuit 101 to output the first reference data SJC1 based on the second data SJ2 and output the second reference data SJC2 based on the fourth data SJ4, wherein the second data SJ2 is obtained based on the comparison of the second initial reference voltage Vr2, and the fourth data SJ4 is obtained based on the comparison of the fourth initial reference voltage Vr4, that is, the comparison result affected by the decrease of the second encoding c2 is selected based on the reference voltage V, so as to offset the sampling influence of the previous second bit of data on the current to-be-sampled data DQ; when the previous second bit of data is "1", the second selection signal sel2 is used to control the first selection circuit 101 to output the first reference data SJC1 based on the first data SJ1 and output the second reference data SJC2 based on the third data SJ3, wherein the first data SJ1 is obtained based on the comparison of the first initial reference voltage Vr1, and the third data SJ3 is obtained based on the comparison of the third initial reference voltage Vr3, that is, the comparison result affected by the increase of the second encoding c2 is selected based on the reference voltage V, so as to offset the sampling influence of the previous second bit of data on the current to-be-sampled data DQ.

[0050] In some embodiments, the second selection signal sel2 can be directly set based on the previous second bit data, to directly feedback control the selection result of the first selection circuit 101 based on the value of the previous second bit data.

[0051] The second selection circuit 102 is configured to receive the first reference data SJC1, the second reference data SJC2 and the first selection signal sel1, and select the sampling result data SJ based on the first reference data SJC1 or the second reference data SJC2 based on the first selection signal sel1, wherein the first selection signal sel1 is used to consider the influence of the previous first bit data on the current data to be sampled, and the sampling result data SJ is the sampling result of the data sampling circuit, i.e., the sampling result of the memory.

[0052] Specifically, when the previous first bit data is "0", the first selection signal sel1 is used to control the second selection circuit 102 to output the sampling result data SJ based on the second reference data SJC2, wherein the second reference data SJC2 is obtained based on the comparison of the third initial reference voltage Vr3 or the fourth initial reference voltage Vr4, i.e., the comparison result of the decrease of the influence of the first encoding cl on the basis of the reference voltage V is selected to offset the sampling influence of the previous first bit data on the current data to be sampled DQ; when the previous first bit data is "1", the first selection signal sel1 is used to control the second selection circuit 102 to output the sampling result data SJ based on the first reference data SJC1, wherein the first reference data SJC1 is obtained based on the comparison of the first initial reference voltage Vr1 or the second initial reference voltage Vr2, i.e., the comparison result of the increase of the influence of the first encoding cl on the basis of the reference voltage V is selected to offset the sampling influence of the previous first bit data on the current data to be sampled DQ.

[0053] In some embodiments, the first selection signal sel1 can be directly set based on the previous first bit data, to directly feedback control the selection result of the second selection circuit 102 based on the value of the previous first bit data.

[0054] For the sampling circuit provided in the embodiment, based on the sampling influence of the plurality of data before the previous 2 bits on the current data to be sampled DQ, the side where the data to be sampled is located or the side where the first initial reference voltage ~ the fourth initial reference voltage is located is compensated by a compensation current, so as to offset the sampling influence of the plurality of data before the previous 2 bits on the current data to be sampled DQ; and based on the sampling influence of the previous first bit data and the previous second bit data on the current data to be sampled DQ, an appropriate comparison result is selected as the sampling result data of the memory, so as to offset the sampling influence of the previous first bit data and the previous second bit data on the current data to be sampled DQ, thereby improving the accuracy of data sampling of the memory.

[0055] For the data receiving module 104, in some embodiments, referring to Figure 4 , the data receiving module 104 comprises:

[0056] The first receiving circuit 410 is configured to receive the first initial reference voltage Vr1, the third selection signal sel3 and the to-be-sampled data DQ, and is configured to compare the to-be-sampled data DQ and the first initial reference voltage Vr1 based on the third selection signal sel3 to generate the first data SJ1, and the third selection signal sel3 is configured to provide a compensation current to the side where the first initial reference voltage Vr1 is located or to the side where the to-be-sampled data DQ is located in the process of comparing the first initial reference voltage Vr1 and the to-be-sampled data DQ.

[0057] The second receiving circuit 420 is configured to receive the second initial reference voltage Vr2, the third selection signal sel3 and the to-be-sampled data DQ, and is configured to compare the to-be-sampled data DQ and the second initial reference voltage Vr2 based on the third selection signal sel3 to generate the second data SJ2, and the third selection signal sel3 is configured to provide a compensation current to the side where the second initial reference voltage Vr2 is located or to the side where the to-be-sampled data DQ is located in the process of comparing the second initial reference voltage Vr2 and the to-be-sampled data DQ.

[0058] The third receiving circuit 430 is configured to receive the third initial reference voltage Vr3, the third selection signal sel3 and the to-be-sampled data DQ, and is configured to compare the to-be-sampled data DQ and the third initial reference voltage Vr3 based on the third selection signal sel3 to generate the third data SJ3, and the third selection signal sel3 is configured to provide a compensation current to the side where the third initial reference voltage Vr3 is located or to the side where the to-be-sampled data DQ is located in the process of comparing the third initial reference voltage Vr3 and the to-be-sampled data DQ.

[0059] The fourth receiving circuit 440 is configured to receive the fourth initial reference voltage Vr4, the third selection signal sel3 and the to-be-sampled data DQ, and is configured to compare the to-be-sampled data DQ and the fourth initial reference voltage Vr4 based on the third selection signal sel3 to generate the fourth data SJ4, and the third selection signal sel3 is configured to provide a compensation current to the side where the fourth initial reference voltage Vr4 is located or to the side where the to-be-sampled data DQ is located in the process of comparing the fourth initial reference voltage Vr4 and the to-be-sampled data DQ.

[0060] In some embodiments, referring to Figure 5 The first receiving circuit 410 comprises: a first N-type transistor N101, a control terminal for receiving a first initial reference voltage Vr1, a first terminal for outputting a first data SJ1, and a second terminal connected to a first terminal of a first current source I1, and a second terminal of the first current source I1 grounded; a second N-type transistor N102, a control terminal for receiving a data to be sampled DQ, a first terminal connected to control terminals of a first P-type transistor P101 and a second P-type transistor P102, and a second terminal connected to the first terminal of the first current source; the first P-type transistor P101, a first terminal for receiving a power supply signal, and a second terminal connected to the first terminal of the first N-type transistor N101; the second P-type transistor P102, a first terminal connected to the first terminal of the first P-type transistor P101, and a second terminal connected to the first terminal of the second N-type transistor N102; and an adjusting unit 450, connected to the first terminal of the first N-type transistor N101 and the first terminal of the second N-type transistor N102, and configured to provide a compensation current to the first terminal of the first N-type transistor N101 or the first terminal of the second N-type transistor N102 based on a third selection signal sel3.

[0061] Specifically, the first receiving circuit 410 realizes the comparison based on the first initial reference voltage Vr1 and the data to be sampled DQ through the setting mode of the differential amplification circuit, and adjusts the object of providing the compensation current through the adjusting unit 450 in the comparison process to offset the sampling influence of a plurality of data before the previous 2 bits on the current data to be sampled DQ.

[0062] Reference Figure 5 The circuit shown, ideally, when the first initial reference voltage Vr1 > the data to be sampled DQ, the output of the first data SJ1 is "0", i.e. low level; in actual conditions, when the effective edge of the sampling signal arrives, the falling degree of the data to be sampled DQ is not enough, which may lead to the case that the data to be sampled DQ > the first initial reference voltage Vr1, at this time, the adjusting unit 450 accelerates the pull-down of the potential at the first terminal of the first N-type transistor N101, which is equivalent to increasing the first initial reference voltage Vr1 to increase the pull-down effect of the first terminal of the first N-type transistor N101 when the first N-type transistor N101 is turned on, the effect of the adjusting unit 450 can be regarded as increasing the voltage of the first initial reference voltage Vr1, which avoids the case that the data to be sampled DQ > the first initial reference voltage Vr1 to a certain extent, thereby offsetting the sampling influence of the previous multiple data on the current data to be sampled DQ. Ideally, when the first initial reference voltage Vr1 < the data to be sampled DQ, the output of the first data SJ1 is "1", i.e. high level; in actual conditions, when the effective edge of the sampling signal arrives, the rising degree of the data to be sampled DQ is not enough. Which may lead to the case that the data to be sampled DQ < the first initial reference voltage Vr1, at this time, the adjusting unit 450 accelerates the pull-down of the potential at the first terminal of the second N-type transistor N102, which is equivalent to increasing the data to be sampled DQ to increase the pull-down effect of the first terminal of the second N-type transistor N102 when the second N-type transistor N102 is turned on, the effect of the adjusting unit 450 can be regarded as increasing the voltage of the data to be sampled DQ, which avoids the case that the data to be sampled DQ < the first initial reference voltage Vr1 to a certain extent, thereby offsetting the sampling influence of the previous multiple data on the current data to be sampled DQ.

[0063] For the adjusting unit 450, reference is made to Figure 6 In one example, the adjusting unit 450 comprises: a third N-type transistor N103, the first terminal of which is connected to the first terminal of the first N-type transistor N101, and the control end is used for receiving a first adjusting voltage, the voltage value of the first adjusting voltage is adjusted based on the third code c3, and the voltage value of the first adjusting voltage is positively correlated with the value of the third code c3; a fourth N-type transistor N104, the first terminal of which is connected to the second terminal of the third N-type transistor N103, the control end is used for receiving a third selection signal sel3, the second terminal is connected to the first end of a second current source I2, and the second end of the second current source I2 is grounded; a fifth N-type transistor N105, the first terminal of which is connected to the first terminal of the second N-type transistor N102, and the control end is used for receiving the first adjusting voltage; a sixth N-type transistor N106, the first terminal of which is connected to the second terminal of the fifth N-type transistor N105, the control end is used for receiving the inverse signal of the third selection signal sel3, and the second terminal is connected to the first end of the second current source I2.

[0064] For Figure 6 For the circuit shown in Fig. 3, the third code c3 <a:0>for generating the first regulating voltage, and the third code c3 <a:0>The greater, the stronger the pull-down capability of the adjustment unit 450 on the first terminal of the first N-type transistor N101 or the second N-type transistor N102.

[0065] Specifically, when the third selection signal sel3 is "1", i.e., the third bit of the previous data is "1", and the to-be-sampled data is "0", at this time, the to-be-sampled data DQ can not be pulled down to a sufficient extent, the adjustment unit 450 accelerates the pull-down of the potential at the first terminal of the first N-type transistor N101, which is equivalent to increasing the first initial reference voltage Vr1 to increase the pull-down effect of the potential at the first terminal of the first N-type transistor N101 when the first N-type transistor N101 is turned on, and the effect of the adjustment unit 450 can be regarded as increasing the voltage of the first initial reference voltage Vr1, which to some extent avoids the case that the to-be-sampled data DQ > the first initial reference voltage Vr1, thereby offsetting the sampling influence of the previous 2 bits of data on the current to-be-sampled data DQ. When the third selection signal sel3 is "0", i.e., the third bit of the previous data is "0", and the to-be-sampled data is "1", at this time, the to-be-sampled data DQ can not be pulled up to a sufficient extent, the adjustment unit 450 accelerates the pull-down of the potential at the first terminal of the second N-type transistor N102, which is equivalent to increasing the to-be-sampled data DQ to increase the pull-down effect of the potential at the first terminal of the second N-type transistor N102 when the second N-type transistor N102 is turned on, and the effect of the adjustment unit 450 can be regarded as increasing the voltage of the to-be-sampled data DQ, which to some extent avoids the case that the to-be-sampled data DQ < the first initial reference voltage Vr1, thereby offsetting the sampling influence of the previous 2 bits of data on the current to-be-sampled data DQ.

[0066] In some embodiments, the initial reference voltage generation module 103 is further configured to generate the third initial reference voltage Vr3 based on the third encoding c3 <a:0>a first adjustment voltage is generated.

[0067] Referring to Figure 7 In another example, the adjustment unit 450 comprises: a third P-type transistor P103, a first terminal for receiving the power supply signal, a control terminal for receiving a second adjustment voltage, a voltage value of the second adjustment voltage being adjusted based on a third code c3, and the voltage value of the second adjustment voltage being negatively related to the value of the third code c3; a fourth P-type transistor P104, a first terminal connected to a second terminal of the third P-type transistor P103, a control terminal for receiving a third selection signal sel3, and a second terminal connected to a first terminal of the first N-type transistor N101; a fifth P-type transistor P105, a first terminal connected to a first terminal of the third P-type transistor P103, a control terminal for receiving the second adjustment voltage; a sixth P-type transistor P106, a first terminal connected to a second terminal of the fifth P-type transistor P105, a control terminal for receiving an inverted signal of the third selection signal sel3, and a second terminal connected to a first terminal of the second N-type transistor N102.

[0068] For Figure 7 For the circuit shown in FIG. 6, the third code c3 <a:0>for generating a second regulated voltage, and a third code c3 <a:0>The smaller, the stronger the pull-up ability of the adjusting unit 450 to the first terminal of the first N-type transistor N101 or the second N-type transistor N102. Figure 7 The circuit principle shown is basically the same as Figure 6 The circuit principle shown is basically the same as

[0069] It should be noted that the structures of the second receiving circuit 420, the third receiving circuit 430, and the fourth receiving circuit 440 are the same as those of the first receiving circuit 410, and the details can be referred to Figure 5-7 The details are not repeated in this embodiment.

[0070] For the initial reference voltage generation module 103, in some embodiments, the reference Figure 8 , the initial reference voltage generation module 103 includes:

[0071] The voltage dividing circuit 200 includes N voltage output terminals, and the voltages output by each voltage output terminal are different, and N is an integer greater than 1.

[0072] For the voltage dividing circuit 200, refer to Figure 9 In one example, the voltage dividing circuit 200 includes N-1 first resistors in series, the first end of the first first resistor is used to receive a first internal voltage V1, the second end of the last first resistor is used to receive a second internal voltage V2, and the second end of each first resistor is connected to the first end of the next first resistor; the voltage value of the first internal voltage V1 is greater than the voltage value of the second internal voltage V2, and the two ends of each first resistor are used as an output port to form N voltage output terminals.

[0073] Specifically, with reference to Figure 9 The N voltage output terminals are respectively used to output voltages Q<0>~Q <n>Since the resistances of the voltage dividers are all the first resistance, the voltage difference between adjacent voltage outputs is the same, i.e. Q <x>=(V1-V2) / N*x, x is any integer from 0 to N.

[0074] It should be noted that in other embodiments, the resistance values of the different first resistances can be different, in which case the voltage differences between adjacent voltage output terminals are different, but still conform to Q <n> ＞Q <n-1>... > Q <1> > Q <0>.

[0075] In some embodiments, the first internal voltage VI is implemented based on an internal supply voltage VDD of the memory, and the second internal voltage V2 is implemented based on an internal ground voltage VSS of the memory.

[0076] With continued reference to Figure 8 , a decoding circuit 201 for receiving the original code code <a:0>, first encoding c1 <a:0>and a second code c2 <a:0>, the decoding circuit 201 is configured to decode the original code code <a:0>+ first encoding c1 <a:0>+ second encoding c2 <a:0>generating a first processed signal based on the original code code <a:0>+ first encoding c1 <a:0>- second encoding c2 <a:0>generating a second processed signal based on the original code code <a:0>- first encoding c1 <a:0>+ second encoding c2 <a:0>generating a third processed signal based on the original code code <a:0>- a first encoding c1 <a:0>- second encoding c2 <a:0>a fourth processing signal is generated.

[0077] In one example, assuming a=3, the original code code<3:0>="1000", the first code c1<3:0>="0010", the second code c2<3:0>="0001", the first processing signal is "1011", the second processing signal is "1001", the third processing signal is "0111", and the fourth processing signal is "0101".

[0078] The first processing circuit 210 is connected to the voltage dividing circuit 200 and the decoding circuit 201, and is configured to select a corresponding voltage output terminal in the voltage dividing circuit 200 to output a first initial reference voltage Vr1 based on the first processing signal. The second processing circuit 220 is connected to the voltage dividing circuit 200 and the decoding circuit 201, and is configured to select a corresponding voltage output terminal in the voltage dividing circuit 200 to output a second initial reference voltage Vr2 based on the second processing signal. The third processing circuit 230 is connected to the voltage dividing circuit 200 and the decoding circuit 201, and is configured to select a corresponding voltage output terminal in the voltage dividing circuit 200 to output a third initial reference voltage Vr3 based on the third processing signal. The fourth processing circuit 240 is connected to the voltage dividing circuit 200 and the decoding circuit 201, and is configured to select a corresponding voltage output terminal in the voltage dividing circuit 200 to output a fourth initial reference voltage Vr4 based on the fourth processing signal.

[0079] For the first processing circuit 210, refer to Figure 9 In some embodiments, the first processing signal includes N first sub-signals (X1<0>~X1 <n>), and only one valid signal is included in the N first sub-signals, the first processing circuit 210 includes N first switch transistors, a control end of each first switch transistor corresponds to receive a corresponding first sub-signal, a first terminal of each first switch transistor corresponds to connect a corresponding voltage output end of the N voltage output ends, and a second terminal is connected to an output end of the first processing circuit 210 to output a first initial reference voltage Vr1.

[0080] Specifically, based on the above example, when a = 3, the first processing signal, the second processing signal, the third processing signal and the fourth processing signal are all 4-bit signals, and the 4-bit signal corresponds to 16 binary combinations. At this time, N = 15, the binary signal "0000" corresponds to the first sub-signal X1<0> to output the corresponding Q<0>, the binary signal "0001" corresponds to the first sub-signal X1<1> to output the corresponding Q<1>... the binary signal "1110" corresponds to the first sub-signal X1<14> to output the corresponding Q<14>, and the binary signal "1111" corresponds to the first sub-signal X1<15> to output the corresponding Q<15>. In addition, only one valid signal exists in the N first sub-signals included in the first processing signal, that is, when X1<0> outputs "1" valid, X1<1>~X1<15> outputs "0" invalid; when X1 <d>X1<0>~X1 <d-1>and X1<0>~X1<15> are output as "0" invalid.

[0081] Note that the above example outputs "1" for X1<0>~X1 <n>Valid when output is "1", X1<0>~X1 <n>The output is invalid when it is "0", which is used for illustration and does not constitute a limitation to the embodiment. In other embodiments, it can also be set to X1 <n>valid when output is "0", X1<0>~X1 <n>Invalid when output is "1".

[0082] More specifically, in the present embodiment, the first processing signal "1011" corresponds to the first sub-signal X1<11> to output the corresponding Q<11> as the first initial reference voltage Vr1.

[0083] Similarly, for the second processing circuit 220, in some embodiments, the second processing signal includes N second sub-signals (X2<0>~X2 <n>), and only one valid signal is included in the N second sub-signals, the second processing circuit 220 includes N second switch transistors, a control terminal of each second switch transistor corresponds to receive a corresponding second sub-signal, a first terminal of each second switch transistor corresponds to connect a corresponding voltage output end of the N voltage output ends, and a second terminal connects an output end of the second processing circuit 220 to output a second initial reference voltage Vr2.

[0084] Correspondingly, in the embodiment, the second processing signal "1001" corresponds to the second sub-signal X2<9> to output a corresponding Q<9> as the second initial reference voltage Vr2.

[0085] Similarly, for the third processing circuit 230, in some embodiments, the third processing signal includes N third sub-signals (X3<0>~X3 <n>), and only one valid signal is included in the N third sub-signals, the third processing circuit 230 includes N third switch transistors, a control end of each third switch transistor corresponds to receive a corresponding third sub-signal, a first terminal of each third switch transistor corresponds to connect a corresponding voltage output end of N voltage output ends, and a second terminal connects an output end of the third processing circuit 230 to output a third initial reference voltage Vr3.

[0086] Correspondingly, in the embodiment, the third processing signal "0111" corresponds to the third sub-signal X3<7> to output a corresponding Q<7> as the third initial reference voltage Vr3.

[0087] Similarly, for the fourth processing circuit 240, in some embodiments, the fourth processing signal includes N fourth sub-signals (X4<0>~X4 <n>), and only one valid signal is included in the N fourth sub-signals, the fourth processing circuit 240 includes N fourth switch transistors, a control end of each fourth switch transistor corresponds to receive a corresponding fourth sub-signal, a first terminal of each fourth switch transistor corresponds to connect a corresponding voltage output end of N voltage output ends, and a second terminal is connected to an output end of the fourth processing circuit 240 to output a fourth initial reference voltage Vr4.

[0088] Correspondingly, in the embodiment, the fourth processing signal "0101" corresponds to the fourth sub-signal X4<5> to output a corresponding Q<5> as the fourth initial reference voltage Vr4.

[0089] It should be noted that the relationship between the second processing circuit 220, the third processing circuit 230, the fourth processing circuit 240 and the decoding circuit 201 and the voltage dividing circuit 200 is the same as that of the first processing circuit 210, which can be directly replaced with the examples of Figure 9 .

[0090] For the sampling circuit provided in the embodiment, based on the sampling influence of the previous multiple data on the current to-be-sampled data DQ, the current on one side of the to-be-sampled data or the first initial reference voltage~the fourth initial reference voltage is compensated, so as to offset the sampling influence of the previous multiple data on the current to-be-sampled data DQ; and based on the sampling influence of the previous first bit data and the previous second bit data on the current to-be-sampled data DQ, an appropriate comparison result is selected as the sampling result data of the memory, so as to offset the sampling influence of the previous first bit data and the previous second bit data on the current to-be-sampled data DQ, and further improve the accuracy of data sampling of the memory.

[0091] It should be noted that the features disclosed in the data sampling circuit provided in the above embodiments can be combined arbitrarily without conflict, and a new data sampling circuit embodiment can be obtained.

[0092] Another embodiment of the present disclosure provides a memory including the data sampling circuit provided in the above embodiments to improve the accuracy of data sampling of the memory.

[0093] Specifically, reference Figure 3 When the previous third bit data is "0", the third selection signal sel3 is used to control the data sampling circuit 104 to load a compensation current on the side where the current to be sampled data DQ is located in the comparison process, and when the previous third bit data is "1", the third selection signal sel3 is used to control the data sampling circuit 104 to load a compensation current on the side where the first initial reference voltage Vr1, the second initial reference voltage Vr2, the third initial reference voltage Vr3 and the fourth initial reference voltage Vr4 are located in the comparison process, so as to offset the sampling influence of the previous 2 bits of data on the current to be sampled data DQ.

[0094] When the previous second bit data is "0", the second selection signal sel2 is used to control the first selection circuit 101 to output the first reference data SJC1 with the second data SJ2 and output the second reference data SJC2 with the fourth data SJ4, wherein the second data SJ2 is obtained based on the comparison of the second initial reference voltage Vr2, and the fourth data SJ4 is obtained based on the comparison of the fourth initial reference voltage Vr4, that is, the comparison result of the decrease of the influence of the second encoding c2 on the basis of the reference voltage V is selected to offset the sampling influence of the previous second bit data on the current to be sampled data DQ; when the previous second bit data is "1", the second selection signal sel2 is used to control the first selection circuit 101 to output the first reference data SJC1 with the first data SJ1 and output the second reference data SJC2 with the third data SJ3, wherein the first data SJ1 is obtained based on the comparison of the first initial reference voltage Vr1, and the third data SJ3 is obtained based on the comparison of the third initial reference voltage Vr3, that is, the comparison result of the increase of the influence of the second encoding c2 on the basis of the reference voltage V is selected to offset the sampling influence of the previous second bit data on the current to be sampled data DQ.

[0095] When the previous first bit data is "0", the first selection signal sel1 is used to control the second selection circuit 102 to output the sampling result data SJ with the second reference data SJC2, wherein the second reference data SJC2 is obtained based on the comparison of the third initial reference voltage Vr3 or the fourth initial reference voltage Vr4, i.e. the comparison result affected by the decrease of the first encoding cl on the basis of the reference voltage V is selected to offset the sampling influence of the previous first bit data on the current to-be-sampled data DQ; when the previous first bit data is "1", the first selection signal sel1 is used to control the second selection circuit 102 to output the sampling result data SJ with the first reference data SJC1, wherein the first reference data SJC1 is obtained based on the comparison of the first initial reference voltage Vr1 or the second initial reference voltage Vr2, i.e. the comparison result affected by the increase of the first encoding cl on the basis of the reference voltage V is selected to offset the sampling influence of the previous first bit data on the current to-be-sampled data DQ.

[0096] For the sampling circuit provided by the embodiment, based on the sampling influence of the previous plurality of data on the current to-be-sampled data, the side where the to-be-sampled data is located or the side where the first initial reference voltage ~ the fourth initial reference voltage is located is compensated by the compensation current, so as to offset the sampling influence of the previous plurality of data on the current to-be-sampled data; and based on the sampling influence of the previous first bit data and the previous second bit data on the current to-be-sampled data, the appropriate comparison result is selected as the sampling result data of the memory, so as to offset the sampling influence of the previous first bit data and the previous second bit data on the current to-be-sampled data, thereby improving the accuracy of data sampling of the memory.

[0097] It should be noted that the memory can be a storage unit or device based on a semiconductor device or component. For example, the memory device can be a volatile memory, such as a dynamic random access memory DRAM, a synchronous dynamic random access memory SDRAM, a double data rate synchronous dynamic random access memory DDR SDRAM, a low power double data rate synchronous dynamic random access memory LPDDR SDRAM, a graphics double data rate synchronous dynamic random access memory GDDR SDRAM, a double data rate type two synchronous dynamic random access memory DDR2 SDRAM, a double data rate type three synchronous dynamic random access memory DDR3 SDRAM, a double data rate fourth generation synchronous dynamic random access memory DDR4 SDRAM, a thyristor random access memory TRAM, etc.; or can be a non-volatile memory, such as a phase change random access memory PRAM, a magnetic random access memory MRAM, a resistive random access memory RRAM, etc.

[0098] It is understood by those of ordinary skill in the art that the above embodiments are specific embodiments for implementing the present disclosure, and various changes can be made in form and details in practical applications without departing from the spirit and scope of the present disclosure.< / n> < / n> < / n> < / n> < / n> < / n> < / n> < / d> < / n> < / n> < / x> < / n>

Claims

1. A data sampling circuit, characterized in that, include: An initial reference voltage generation module is used to receive an original code, a first code, and a second code, and generate a first initial reference voltage based on the original code + the first code + the second code, generate a second initial reference voltage based on the original code + the first code - the second code, generate a third initial reference voltage based on the original code - the first code + the second code, and generate a fourth initial reference voltage based on the original code - the first code - the second code. A data receiving module is configured to receive a first initial reference voltage, a second initial reference voltage, a third initial reference voltage, a fourth initial reference voltage, a third selection signal, and data to be sampled. The module is configured to: compare the data to be sampled with the first initial reference voltage based on the third selection signal to generate first data; compare the data to be sampled with the second initial reference voltage based on the third selection signal to generate second data; compare the data to be sampled with the third initial reference voltage based on the third selection signal to generate third data; and compare the data to be sampled with the fourth initial reference voltage based on the third selection signal to generate fourth data. The third selection signal is configured to provide a compensation current to the side containing the first initial reference voltage, the second initial reference voltage, the third initial reference voltage, the fourth initial reference voltage, and the data to be sampled, or to provide the compensation current to the side containing the data to be sampled, during the comparison process based on the first initial reference voltage, the second initial reference voltage, the third initial reference voltage, the fourth initial reference voltage, and the data to be sampled. A first selection circuit is configured to receive the first data, the second data, the third data, the fourth data, and a second selection signal, and to select based on the second selection signal to output first reference data based on the first data or the second data, and to select based on the second selection signal to output second reference data based on the third data or the fourth data. The second selection circuit is used to receive the first reference data, the second reference data and the first selection signal, and is configured to select based on the first selection signal to output sampling result data based on the first reference data or the second reference data. Wherein, the second selection signal is used to consider the influence of the previous second bit data on the current sampled data, the first selection signal is used to consider the influence of the previous first bit data on the current sampled data, and the third selection signal is used to consider the influence of at least the previous third bit data among all data before the first two bits on the current sampled data; the size of the first code is used to measure the influence parameter of the previous first bit data on the current sampled data, and the size of the second code is used to measure the influence parameter of the previous second bit data on the current sampled data.

2. The data sampling circuit according to claim 1, characterized in that, The data receiving module includes: A first receiving circuit is configured to receive a first initial reference voltage, a third selection signal, and data to be sampled, and to compare the data to be sampled and the first initial reference voltage based on the third selection signal to generate first data. The third selection signal is configured to provide the compensation current to the side where the first initial reference voltage is located, or to provide the compensation current to the side where the data to be sampled is located, during the comparison of the first initial reference voltage and the data to be sampled. The second receiving circuit is configured to receive the second initial reference voltage, the third selection signal, and the data to be sampled, and to compare the data to be sampled and the second initial reference voltage based on the third selection signal to generate second data. The third selection signal is used to provide the compensation current to the side where the second initial reference voltage is located, or to provide the compensation current to the side where the data to be sampled is located, during the comparison between the second initial reference voltage and the data to be sampled. A third receiving circuit is configured to receive the third initial reference voltage, the third selection signal, and the data to be sampled, and to compare the data to be sampled and the third initial reference voltage based on the third selection signal to generate third data. The third selection signal is used to provide the compensation current to the side where the third initial reference voltage is located, or to provide the compensation current to the side where the data to be sampled is located, during the comparison of the third initial reference voltage and the data to be sampled. A fourth receiving circuit is configured to receive the fourth initial reference voltage, the third selection signal, and the data to be sampled, and to compare the data to be sampled and the fourth initial reference voltage based on the third selection signal to generate fourth data. The third selection signal is used to provide the compensation current to the side where the fourth initial reference voltage is located, or to provide the compensation current to the side where the data to be sampled is located, during the comparison of the fourth initial reference voltage and the data to be sampled.

3. The data sampling circuit according to claim 2, characterized in that, The first receiving circuit includes: The first N-type transistor has a control terminal for receiving the first initial reference voltage, a first terminal for outputting first data, and a second terminal connected to the first terminal of a first current source, with the second terminal of the first current source grounded. The second N-type transistor has a control terminal for receiving the data to be sampled, a first terminal connected to the control terminals of the first P-type transistor and the second P-type transistor, and a second terminal connected to the first terminal of the first current source. The first terminal of the first P-type transistor is used to receive a power signal, and the second terminal is connected to the first terminal of the first N-type transistor. The first terminal of the second P-type transistor is connected to the first terminal of the first P-type transistor, and the second terminal is connected to the first terminal of the second N-type transistor. The regulating unit, connected to the first terminal of the first N-type transistor and the first terminal of the second N-type transistor, is configured to provide the compensation current to the first terminal of the first N-type transistor or the first terminal of the second N-type transistor based on the third selection signal.

4. The data sampling circuit according to claim 3, characterized in that, The adjustment unit includes: The third N-type transistor has a first terminal connected to the first terminal of the first N-type transistor, and a control terminal for receiving a first regulated voltage. The voltage value of the first regulated voltage is regulated based on a third code, and the voltage value of the first regulated voltage is positively correlated with the value of the third code. The fourth N-type transistor has its first terminal connected to the second terminal of the third N-type transistor, its control terminal used to receive the third selection signal, and its second terminal connected to the first terminal of the second current source, the second terminal of the second current source being grounded. The fifth N-type transistor has its first terminal connected to the first terminal of the second N-type transistor, and its control terminal is used to receive the first regulated voltage. The sixth N-type transistor has its first terminal connected to the second terminal of the fifth N-type transistor, its control terminal used to receive the inverted signal of the third selection signal, and its second terminal connected to the first terminal of the second current source.

5. The data sampling circuit according to claim 3, characterized in that, The adjustment unit includes: The third P-type transistor has a first terminal for receiving a power signal and a control terminal for receiving a second regulated voltage. The voltage value of the second regulated voltage is regulated based on a third code, and the voltage value of the second regulated voltage is negatively correlated with the value of the third code. The fourth P-type transistor has its first terminal connected to the second terminal of the third P-type transistor, and its control terminal used to receive the inverted signal of the third selection signal. Its second terminal is connected to the first terminal of the first N-type transistor. The fifth P-type transistor has its first terminal connected to the first terminal of the third P-type transistor, and its control terminal is used to receive the second regulated voltage. The sixth P-type transistor has its first terminal connected to the second terminal of the fifth P-type transistor, and its control terminal used to receive the third selection signal. Its second terminal is connected to the first terminal of the second N-type transistor.

6. The data sampling circuit according to claim 4, characterized in that, The initial reference voltage generation module is also configured to generate the first adjustment voltage based on the third encoding.

7. The data sampling circuit according to claim 1, characterized in that, The voltage value of the first initial reference voltage > the voltage value of the second initial reference voltage > the voltage value of the third initial reference voltage > the voltage value of the fourth initial reference voltage.

8. The data sampling circuit according to claim 1, characterized in that, The initial reference voltage generation module includes: A voltage divider circuit includes N voltage output terminals, and each voltage output terminal outputs a different voltage, where N is an integer greater than 1. A decoding circuit, used to receive the original code, the first code, and the second code, is configured to generate a first processing signal based on decoding the original code + the first code + the second code, generate a second processing signal based on decoding the original code + the first code - the second code, generate a third processing signal based on decoding the original code - the first code + the second code, and generate a fourth processing signal based on decoding the original code - the first code - the second code. A first processing circuit, connected to the voltage divider circuit and the decoding circuit, is configured to select the corresponding voltage output terminal in the voltage divider circuit to output the first initial reference voltage based on the first processing signal. The second processing circuit, connected to the voltage divider circuit and the decoding circuit, is configured to select the corresponding voltage output terminal in the voltage divider circuit to output the second initial reference voltage based on the second processing signal. A third processing circuit, connected to the voltage divider circuit and the decoding circuit, is configured to select the corresponding voltage output terminal in the voltage divider circuit to output the third initial reference voltage based on the third processing signal. A fourth processing circuit, connected to the voltage divider circuit and the decoding circuit, is configured to select the corresponding voltage output terminal in the voltage divider circuit based on the fourth processing signal to output the fourth initial reference voltage.

9. The data sampling circuit according to claim 8, characterized in that, include: The voltage divider circuit includes: N-1 first resistors connected in series, wherein the first terminal of the first first resistor is used to receive a first internal voltage, the second terminal of the last first resistor is used to receive a second internal voltage, and the second terminal of each first resistor is connected to the first terminal of the next first resistor. The voltage value of the first internal voltage is greater than the voltage value of the second internal voltage; The two ends of each of the first resistors serve as output ports to form the N voltage output terminals; The first processing signal includes N first sub-signals, and only one of the N first sub-signals is a valid signal. The first processing circuit includes: There are N first switching transistors, and the control terminal of each first switching transistor receives the corresponding first sub-signal. Each first switching transistor has its first terminal connected to one of the N voltage output terminals, and its second terminal connected to the output terminal of the first processing circuit to output the first initial reference voltage.

10. A memory, characterized in that, Includes the data sampling circuit as described in any one of claims 1 to 9.

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