Bypass diode with low reverse leakage current and preparation method thereof

Abstract

The invention provides a bypass diode with low reverse leakage current and a preparation method thereof, and belongs to the technical field of diodes, the bypass diode comprises a substrate, a boron isolation ring, a phosphorus heavily doped layer, a silicon oxide layer, an upper electrode, a black rubber ring and a lower electrode, the boron isolating ring is arranged in the second groove, the phosphorus heavily doped layer is arranged in the first groove, and the silicon oxide layer covers the boron isolating ring and part of the phosphorus heavily doped layer to form a third groove; the upper electrode covers the third groove and circumferentially extends to cover part of the silicon oxide layer; the black rubber ring covers the exposed silicon oxide layer; the lower electrode is arranged on the back surface of the substrate. According to the invention, the black rubber ring is arranged above the silicon oxide layer, so that the design of the local upper electrode is realized, and short circuit during scribing is avoided; the black adhesive has low light transmittance, and effectively shields the edge of the substrate together with the upper electrode, so that the reverse leakage current of the diode is at a lower level when the diode is in a dark characteristic and under an illumination condition, and the requirement of space application is met.

Description

Technical Field

[0001] The invention belongs to the technical field of diodes, and in particular relates to a bypass diode with low reverse leakage current and a preparation method thereof. Background Art

[0002] In order to prevent the solar cell array from being damaged by the hot spot effect during operation, a diode is usually connected in parallel next to the solar cell module. When the cell is working normally, the bypass diode is reversely cut off and has no effect on the circuit. When the cell is damaged and cannot generate electricity, the bypass diode is forward-conducted, so that the solar cell module can continue to generate electricity, and the power generation circuit will not be blocked due to a problem with a cell. Therefore, for solar cells used in space, the bypass diode is an indispensable and critical component. One of the criteria for measuring the quality of the bypass diode is the reverse leakage index. The smaller the reverse leakage, the better the unidirectional conduction characteristics of the diode, and the smaller the loss of the solar cell module during normal operation.

[0003] At present, the prior art generally adopts technologies such as boron isolation rings, local N regions, and oxide isolation rings to enable the reverse leakage current of the diode to reach a very low level during dark characteristics. However, since the upper electrode completely covers the edge of the diode, the upper electrode at the edge is easily adhered to the substrate and the lower electrode during dicing to form a short circuit between the upper and lower electrodes. However, if a local upper electrode design is adopted, when light irradiates the bypass diode, the reverse leakage current of the diode increases sharply, even up to tens of microamperes, seriously affecting the working performance, reliability and safety of the solar cell module, and reducing the service life of the diode. Summary of the invention

[0004] In order to solve the above technical problems, the present invention provides a bypass diode with low reverse leakage and a preparation method thereof, so that the reverse leakage of the diode can reach a very low level in both dark characteristics and light, and has high reliability and good stability.

[0005] The technical solution adopted by the present invention is: a bypass diode with low reverse leakage current, comprising:

[0006] A substrate, wherein the substrate has a front side and a back side opposite to each other, the front side is provided with a first groove and a second groove which is arranged at an edge of the substrate and surrounds an outer side of the first groove;

[0007] a boron isolation ring, disposed in the second groove;

[0008] A phosphorus heavily doped layer is disposed in the first groove;

[0009] a silicon oxide layer, covering the boron isolation ring and a portion of the phosphorus heavily doped layer, and forming a third groove above the phosphorus heavily doped layer;

[0010] an upper electrode, covering the third groove and extending circumferentially to cover a portion of the silicon oxide layer;

[0011] A black plastic ring, covering the exposed silicon oxide layer, with an inner ring tightly fitting the edge of the upper electrode and an outer ring aligned with the edge of the substrate;

[0012] The lower electrode is arranged on the back side.

[0013] Furthermore, the optical density value of the black plastic ring is 0.27 / μm-0.32 / μm, the response wavelength is 350nm-500nm, and the resolution is 1μm-5μm.

[0014] Furthermore, the thickness of the black plastic ring is 6um-10um.

[0015] Furthermore, the black plastic ring covers a portion of the upper electrode.

[0016] Furthermore, the silicon oxide layer is disposed between the second groove and the first groove.

[0017] Furthermore, the third groove shrinks inwardly relative to the first groove.

[0018] A method for preparing a bypass diode with low reverse leakage as described above comprises the following preparation process:

[0019] A second groove is formed after removing a portion of the silicon oxide layer on the front side of the substrate;

[0020] Diffusion of boron in the second groove forms a boron isolation ring;

[0021] growing a silicon oxide layer over the boron isolation ring;

[0022] Removing part of the silicon oxide layer to form a first groove;

[0023] Diffusion of phosphorus in the first groove forms a phosphorus heavily doped layer;

[0024] Generating a silicon oxide layer again on the heavily phosphorus-doped layer;

[0025] Removing a portion of the silicon oxide layer above the phosphorus heavily doped layer to form a third groove;

[0026] Producing an upper electrode;

[0027] Producing a lower electrode;

[0028] A black glue ring is formed on the exposed silicon oxide layer.

[0029] Furthermore, the production process of the vinyl ring includes:

[0030] Using a spin coating process, black glue is applied to the front side of the substrate to form a black glue layer;

[0031] Baking in an oven to preliminarily dry the black glue layer;

[0032] Expose and develop by photolithography process, and remove part of the black glue layer to form the black glue ring;

[0033] The black glue ring is baked again in the oven to solidify the black glue ring.

[0034] Furthermore, the baking is carried out in an oven, and the temperature in the oven is 85°C.

[0035] Furthermore, the baking is performed again in the oven, the temperature in the oven is 220° C., and the time is 30 minutes.

[0036] The advantages and positive effects of the present invention are:

[0037] The present invention adopts a method of arranging a silicon oxide layer above the boron isolation ring and a black glue ring above the silicon oxide layer, so that the black glue ring surrounds the upper electrode, realizing the design of a local upper electrode, avoiding the short circuit caused by the adhesion of the upper and lower electrodes during dicing, and improving the reliability and safety of the diode; the black glue in the present application has a low light transmittance, and together with the upper electrode, forms an effective shielding for the edge of the substrate, so that the reverse leakage current of the diode is at a low level both in dark characteristics and under illumination conditions, meeting the needs of space applications; the black glue is photolithographic, which is convenient for forming a black glue ring through a photolithography process, and has good stability, ensuring the working performance of the solar cell module. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 is a cross-sectional schematic diagram of a bypass diode with low reverse leakage current according to a specific embodiment of the present invention;

[0039] Figure 2 is a schematic top view of a bypass diode with low reverse leakage current according to a specific embodiment of the present invention;

[0040] Figure 3 It is a schematic diagram of the preparation process of a bypass diode with low reverse leakage current according to a specific embodiment of the present invention.

[0041] In the figure:

[0042] 1. Vinyl ring 2. Silicon oxide layer 21. First groove

[0043] 22, second groove 23, third groove 3, upper electrode

[0044] 4. Phosphorus heavily doped layer 5. Boron isolation ring 6. Lower electrode

[0045] 7. Substrate DETAILED DESCRIPTION

[0046] The embodiments of the present invention are described below with reference to the accompanying drawings.

[0047] like Figure 1 As shown, the present invention proposes a bypass diode with low reverse leakage, comprising a substrate 7, a boron isolation ring 5, a phosphorus heavily doped layer 4, a silicon oxide layer 2, an upper electrode 3, a black plastic ring 1 and a lower electrode 6: wherein the substrate 7 is a silicon wafer, having a front side and a back side opposite to each other, wherein the front side is a polished surface, the back side is a non-polished surface, and the front side is provided with a first groove 21 and a second groove 22 arranged at the edge of the substrate 7 and surrounding the outside of the first groove 21; the boron isolation ring 5 is arranged in the second groove 22, and the phosphorus heavily doped layer 4 is arranged in the first groove 21, it can be understood that the boron isolation ring 5 is made by p+ boron heavy doping process, and the phosphorus heavy doping layer 4 is made by n+ phosphorus heavy doping process; the silicon oxide layer 2 covers the boron isolation ring 5 and part of the phosphorus heavy doping layer 4, and a third groove 23 is formed above the phosphorus heavy doping layer 4; the upper electrode 3 covers the third groove 23 and extends circumferentially to cover part of the silicon oxide layer 2; the black plastic ring 1 covers the exposed silicon oxide layer 2, and its inner ring is tightly attached to the edge of the upper electrode 3, and the outer ring coincides with the edge of the substrate 7; the lower electrode 6 is arranged on the back side of the substrate 7.

[0048] The above-mentioned black plastic ring 1 fits tightly with the upper electrode 3, and the two can work together to block light. The black plastic ring 1 mainly plays a light-shielding role on the edge of the diode, which greatly reduces the impact of light on the edge of the diode. The principle is that light absorption at the edge of the diode under illumination conditions will cause a substantial increase in photogenerated carriers in the diode material, reduce resistance, and ultimately increase leakage current; in addition, the edge junction formed by the boron isolation ring 5 and the phosphorus heavily doped layer 4 was originally designed to reduce edge leakage, but under illumination, the junction characteristics of the edge junction become weak, and when reverse biased, surface junction leakage is formed under the intervention of an external electric field. The present application reduces the above-mentioned impact of light on edge leakage by adding the design of the black plastic ring 1, significantly reduces leakage during illumination, and optimizes the electrical characteristics of the diode.

[0049] The above-mentioned black glue ring 1 has low transmittance, and its optical density value od is preferably 0.27 / μm-0.32 / μ, so as to achieve a good light shielding effect; at the same time, the glue response wavelength is 350nm-500nm, and it has the characteristics of photoresist. The required graphics can be designed and manufactured using conventional photolithography process methods, with a resolution of 1μm-5μm. After exposure, the black glue can be corroded by the developer, which is convenient for removing the excess part of the black glue by photolithography to ensure that the exposed area of ​​the upper electrode 3 is sufficient for welding with the lead; preferably, the black glue ring 1 is mainly made of photosensitive resin, solvent, black filler, etc., and a high-thickness glue film can be achieved. In a specific embodiment, its thickness can reach 10μm, which is beneficial to further reduce light transmittance. In addition, the high-thickness glue film can achieve a high span of the metal electrode, realize a seamless connection between the electrode and the glue film, and reduce the influence of light leakage at the joint.

[0050] In order to ensure that the black plastic ring 1 can achieve a good shielding effect and is easy to apply and remove by photolithography, the thickness of the black plastic ring 1 is 6um-10um, preferably 8um.

[0051] Furthermore, the black plastic ring 1 covers a portion of the upper electrode 3 to ensure that there is no gap between the black plastic ring 1 and the upper electrode 3, and the two can be closely combined to form an effective shielding for the edge of the diode.

[0052] Furthermore, the second groove 22 and the first groove 21 are spaced apart, and a silicon oxide layer 2 is provided therebetween, so that no contact occurs between the heavily phosphorus-doped layer 4 and the boron isolation ring 5, thereby avoiding the formation of a PN junction short circuit when the upper electrode 3 covers the upper surface of the heavily phosphorus-doped layer 4, and the silicon oxide layer 2 acts as an insulating layer.

[0053] Furthermore, the third groove 23 shrinks inward relative to the first groove 21 , that is, the third groove 23 is smaller than the first groove 21 . The purpose of this design is that when the upper electrode 3 is evaporated, the upper electrode 3 will not contact the non-N region, otherwise a short circuit will be caused.

[0054] The present invention also provides a method for preparing a bypass diode with low reverse leakage, comprising the following preparation process:

[0055] A second groove 22 is formed after removing part of the oxide layer on the front side of the substrate 7;

[0056] Boron is diffused in the second groove 22 to form a boron isolation ring 5;

[0057] A silicon oxide layer 2 is formed on the boron isolation ring 5;

[0058] Removing part of the silicon oxide layer 2 to form a first groove 21;

[0059] Phosphorus is diffused in the first groove 21 to form a phosphorus heavily doped layer 4;

[0060] A silicon oxide layer 2 is again generated on the heavily phosphorus doped layer 4;

[0061] Removing a portion of the silicon oxide layer 2 above the heavily phosphorus-doped layer 4 to form a third groove 23;

[0062] Producing an upper electrode 3;

[0063] Producing the lower electrode 6;

[0064] A black glue ring 1 is formed on the exposed silicon oxide layer 2 .

[0065] The production process of the vinyl ring 1 includes:

[0066] Applying black glue on the front side of the substrate 7 to form a black glue layer;

[0067] Baking in an oven to preliminarily dry the black glue layer;

[0068] Exposure and development are performed using a photolithography process to remove part of the black glue layer to form a black glue ring 1;

[0069] Baking in the oven again to solidify the black glue ring 1;

[0070] When the baking process is carried out in the oven, the temperature in the oven is 85°C.

[0071] When the curing process is carried out in the oven, the temperature in the oven is 220°C and the time is 30 minutes.

[0072] Example

[0073] First, a right-angled triangular P-type silicon wafer is polished on one side to form a front side and a back side. Figure 1 , Figure 2 and Figure 3 The substrate 7 is then prepared according to the following steps:

[0074] S1, oxidation substrate 7;

[0075] SiO2 is grown by high-temperature wet oxygen oxidation process, and the specific method is as follows: open the diffusion furnace, place the quartz boat carrying the substrate 7 in the constant temperature zone, raise the temperature to 1050°C, keep it for 10 minutes, and pass dry oxygen during the process; then turn off the dry oxygen, pass wet oxygen, and keep it at 1050°C for 60 minutes; finally turn off the wet oxygen, turn on the dry oxygen, keep it at 1050°C for 10 minutes, then turn off the diffusion furnace for heating, and take out the substrate 7 when the temperature is about 500°C. The oxygen flow rate in this process should be determined according to the size of the diffusion furnace.

[0076] S2, forming a second groove 22 after removing part of the oxide layer on the front side of the substrate 7;

[0077] In this embodiment, the photolithography etching process is used to remove the oxide layer at the position of the second groove 22. The specific method is as follows: positive photoresist is coated on the front side of the substrate 7, the rotation speed is set at 3000rpm, and the coating time is 15s; after coating, the coating is baked, the temperature is set at 90°C, and the time is 10min; after baking, the photolithography machine is used for exposure, the photoresist is placed, the photoresist pattern is at the center of the wafer stage, the chrome surface of the photoresist faces the coating surface of the substrate 7, the substrate 7 is loaded on the wafer stage of the photolithography machine, the exposure time is set to 16s, and then exposure is started; after exposure, the exposed substrate 7 is placed in the developer for 30s; after development, the substrate 7 is placed in HF for etching to remove the oxide layer at the position of the second groove 22, so as to form the second groove 22.

[0078] S3, performing boron diffusion in the second groove 22 to form a boron isolation ring 5;

[0079] In this embodiment, a high-temperature diffusion process is adopted, which specifically includes: placing the substrate 7 with the second groove 22 formed thereon into a diffusion furnace with a boron source, turning on the heating power supply, and starting the timing when the temperature rises to 925°C for 40 minutes, then turning off the heating power supply, and taking out the substrate 7 when the temperature drops to about 500°C. At this time, the second groove 22 of the substrate 7 diffuses out the boron isolation ring 5, thereby realizing the P-type diffusion in the diode PN structure.

[0080] S4, forming a silicon oxide layer 2 above the boron isolation ring 5;

[0081] In this embodiment, a high-temperature dry oxygen oxidation process is used to grow SiO2, specifically including: opening a diffusion furnace, placing the substrate 7 forming the boron isolation ring 5 in a quartz boat, placing the quartz boat in a constant temperature zone, heating to 1050°C, maintaining for 10 minutes, then closing the diffusion furnace for heating, and taking out the substrate 7 when the temperature reaches about 500°C. At this time, a silicon oxide layer 2 is formed above the boron isolation ring 5 and above the area surrounded by the boron isolation ring 5.

[0082] S5, removing part of the silicon oxide layer 2 to form a first groove 21;

[0083] The oxide layer at the corresponding position of the first groove 21 is removed by a photolithography etching process. The specific method is the same as that in step S3. A pattern of the first groove 21 is engraved on the photoresist using a photomask. The pattern is offset inward by a set distance with the inner circle of the boron isolation ring 5 as the boundary. The silicon oxide layer 2 at the corresponding position of the first groove 21 is removed so that the first groove 21 forms a silicon exposed surface, while retaining the silicon oxide layer 2 above the boron isolation ring 5.

[0084] S6, diffusing phosphorus in the first groove 21 to form a phosphorus heavily doped layer 4;

[0085] In this embodiment, a high-temperature diffusion process is adopted, which specifically includes: loading the substrate 7 into a diffusion quartz boat in a back-to-back manner. Turn on the nitrogen and control the flow rate at 2L / min, and the diffusion temperature is controlled at 820°C. After the temperature is reached, push the diffusion boat into the constant temperature zone of the diffusion furnace, preheat for 15 minutes without the diffusion source, and then turn on the source nitrogen and reactive oxygen, adjust the flow rate of the carrying nitrogen (N2) to 500ml / min, and adjust the flow rate of oxygen (O2) to 250ml / min. The diffusion time is 26min. After the diffusion time is reached, turn off the carrying nitrogen and oxygen, continue to pass the diluted nitrogen, and take out the substrate 7 after 10min. At this time, a layer of phosphorus-doped layer 4 is formed on the exposed silicon surface of the first groove 21, realizing the N-type diffusion in the diode PN structure.

[0086] S7, generating a silicon oxide layer 2 again on the heavily phosphorus-doped layer 4;

[0087] In this embodiment, a high-temperature oxidation process is used to grow SiO2. The specific method is the same as that in step S4 and will not be repeated here. After completion, a silicon oxide layer 2 is formed above the boron isolation ring 5, between the boron isolation ring 5 and the phosphorus heavily doped layer 4, and above the phosphorus heavily doped layer 4.

[0088] S8, removing a portion of the silicon oxide layer 2 above the heavily phosphorus-doped layer 4 to form a third groove 23;

[0089] In this embodiment, a photolithography etching process is adopted, and the specific method is as follows: negative photoresist is coated on the front of the substrate 7, the rotation speed is set at 1000rpm, and the coating time is 20s; after coating, the coating is started (hot plate), the temperature is set at 90°C, and the time is 1min; after coating, the photolithography machine is used for exposure, the photoresist is placed, the photoresist pattern is at the center of the wafer stage, the chrome surface of the photoresist faces the coating surface, the coated substrate 7 is loaded on the wafer stage of the photolithography machine, the exposure time is set to 10s, and then exposure is started; after exposure, the coating is performed again, the temperature is set at 90°C, and the time is 10min; finally, the exposed substrate 7 is placed in a developer for development, the development time is 50s, and after development, it is dried for standby use. At this time, the phosphorus heavily doped layer 4 at the position of the third groove 23 is exposed.

[0090] S9, manufacturing the upper electrode 3;

[0091] The high vacuum coating process is used to evaporate the metal of the upper electrode 3 in the third groove 23. The specific method is as follows: put the substrate 7 with the third groove 23 formed on the mold, with the third groove 23 facing downward, and load it into the vacuum chamber of the high vacuum coating machine. Put the cleaned titanium, palladium and silver film materials into the corresponding crucibles respectively, start the control panel of the high vacuum coating machine computer, perform the vacuum operation, and the system starts to vacuum. Call up the upper electrode 3 evaporation program and check the parameter settings. The thickness of the titanium film layer is set to The rate is set to The thickness of the palladium film is set to The rate is set to The total thickness of the silver film layer is set to The rate is set to The control starts the program to perform automatic evaporation. The upper electrode 3 produced covers all the heavily doped layers and part of the silicon oxide layer 2, and is located in the middle of the substrate 7 as a whole, while the rest of the silicon oxide layer 2 is exposed.

[0092] S10, manufacturing the lower electrode 6;

[0093] The lower electrode 6 is made on the back of the substrate 7 by high vacuum coating process. The specific method is as follows: put the substrate 7 on the mold plate, with the back side facing down, and put it into the vacuum chamber. Put the cleaned aluminum, titanium, palladium and silver film materials into the corresponding crucibles respectively. Start the control panel of the high vacuum coating machine computer, start the electrode evaporation and plating program, close the vacuum chamber, and start evacuation. Call up the evaporation program of the lower electrode 6 and check the parameter settings. The thickness of the aluminum film layer is set to The rate is set to The thickness of the titanium film is set to The rate is set to The thickness of the palladium film is set to The rate is set to The total thickness of the silver film layer is set to The rate is set to Start the program for automatic evaporation.

[0094] S11, Sintering

[0095] The upper and lower electrodes 6 are sintered by high vacuum annealing process. The specific method is as follows: the substrate 7 is placed in a high vacuum annealing furnace, and vacuuming and heating are started. The vacuum degree is set to 10 -5 pa, the temperature is set to 360°C, when the temperature is reached, keep it for 25 minutes, and take out the substrate 7 after cooling down.

[0096] S12, forming a black plastic ring 1 on the exposed silicon oxide layer 2.

[0097] In this embodiment, the optical density value od of the black glue used in the black glue ring 1 is 0.27 / μm, the response wavelength is 365nm, and it has good photolithography characteristics, the resolution is 5μm, and the black glue can be corroded by the developer after exposure. The specific method is:

[0098] A. Apply black glue to the front side of substrate 7, the coating thickness is 8um, the rotation speed is set at 500rpm, and the coating time is 10s;

[0099] B. Bake in an oven to preliminarily dry the black glue layer, set the temperature to 85°C, and the time to 15 minutes;

[0100] C. After the glue is baked, the photolithography process is used for exposure and development, and part of the black glue layer is removed to form a black glue ring 1; specifically, the following steps are used: using a photolithography machine, placing the photolithography plate, making the photolithography plate pattern at the center of the wafer stage, and the chrome surface of the photolithography plate facing the glue-distributing surface of the substrate 7, placing the substrate 7 on the wafer stage of the photolithography machine, setting the exposure time to 7s, and then starting exposure; developing after exposure, placing the exposed substrate 7 in a 4.2% concentration KOH solution for development, and the development time is 90s; after development, the substrate 7 is cleaned with deionized water;

[0101] D. Bake in the oven again to solidify the black plastic ring 1; specifically, put the substrate 7 into the oven after cleaning, set the temperature to 220°C, and keep it for 30 minutes. Put the substrate 7 with the black plastic ring 1 into a thermal resistance oven for drying, and the temperature in the oven is 220°C for 30 minutes.

[0102] S13, Slicing

[0103] Using an automatic grinding wheel scribing device, the substrate 7 is placed with the pattern surface facing upward, and automatic scribing is performed along the edge of the diode according to the set scribing mark.

[0104] After testing, the diode made by the above method has a reverse leakage current of less than 1μA under dark conditions when the reverse voltage is 4V; under light conditions, the reverse leakage current is less than 0.1μA, which is much better than the reverse leakage effect of the diode using only an oxide ring and only using a boron isolation ring 5 to isolate the edge.

[0105] The present invention adopts a method of arranging a silicon oxide layer above the boron isolation ring and a black glue ring above the silicon oxide layer, so that the black glue ring surrounds the upper electrode, realizing the design of a local upper electrode, and avoiding the short circuit caused by the adhesion of the upper and lower electrodes during dicing, thereby improving the reliability and safety of the diode; the black glue in the present application has a low light transmittance, and together with the upper electrode, forms an effective shielding for the edge of the substrate, so that the reverse leakage current of the diode is at a low level both in dark characteristics and under illumination conditions, meeting the needs of space applications; the black glue is photolithographic, which is convenient for forming a black glue ring through a photolithography process, and has good stability, thereby ensuring the working performance of the solar cell module.

[0106] The embodiments of the present invention are described in detail above, but the contents described are only preferred embodiments of the present invention and cannot be considered to limit the scope of implementation of the present invention. All equivalent changes and improvements made within the scope of the present invention should still fall within the scope of the patent coverage of the present invention.

Claims

1. A bypass diode with low reverse leakage current, characterized in that ,include: A substrate, wherein the substrate has a front side and a back side opposite to each other, the front side is provided with a first groove and a second groove which is arranged at an edge of the substrate and surrounds an outer side of the first groove; a boron isolation ring, disposed in the second groove; A phosphorus heavily doped layer is disposed in the first groove; a silicon oxide layer, covering the boron isolation ring and a portion of the phosphorus heavily doped layer, and forming a third groove above the phosphorus heavily doped layer; an upper electrode, covering the third groove and extending circumferentially to cover a portion of the silicon oxide layer; A black plastic ring, covering the exposed silicon oxide layer, with an inner ring tightly fitting the edge of the upper electrode and an outer ring aligned with the edge of the substrate; The lower electrode is arranged on the back side.

2. The bypass diode with low reverse leakage according to claim 1, characterized in that: The optical density value of the black plastic ring is 0.27 / μm-0.32 / μm, the response wavelength is 350nm-500nm, and the resolution is 1μm-5μm.

3. The bypass diode with low reverse leakage according to claim 2, characterized in that: The thickness of the black rubber ring is 6um-10um.

4. The bypass diode with low reverse leakage according to any one of claims 1 to 3, characterized in that: The black plastic ring covers a portion of the upper electrode.

5. The bypass diode with low reverse leakage according to claim 4, characterized in that: The silicon oxide layer is disposed between the second groove and the first groove.

6. The bypass diode with low reverse leakage according to claim 5, characterized in that: The third groove is contracted inwardly relative to the first groove.

7. A method for preparing a bypass diode with low reverse leakage current as claimed in any one of claims 1 to 5, characterized in that: The preparation process includes the following: A second groove is formed after removing a portion of the silicon oxide layer on the front side of the substrate; Diffusion of boron in the second groove forms a boron isolation ring; growing a silicon oxide layer over the boron isolation ring; Removing part of the silicon oxide layer to form a first groove; Diffusion of phosphorus in the first groove forms a phosphorus heavily doped layer; Generating a silicon oxide layer again on the heavily phosphorus-doped layer; Removing a portion of the silicon oxide layer above the phosphorus heavily doped layer to form a third groove; Producing an upper electrode; Producing a lower electrode; A black glue ring is formed on the exposed silicon oxide layer.

8. A method for preparing a bypass diode with low reverse leakage as claimed in claim 1, characterized in that: The production process of the vinyl ring includes: Using a spin coating process, black glue is applied to the front side of the substrate to form a black glue layer; Baking in an oven to preliminarily dry the black glue layer; Expose and develop by photolithography process, and remove part of the black glue layer to form the black glue ring; The black glue ring is baked again in the oven to solidify the black glue ring.

9. A method for preparing a bypass diode with low reverse leakage as claimed in claim 1, characterized in that: The baking is carried out in an oven, and the temperature in the oven is 85°C.

10. A method for preparing a bypass diode with low reverse leakage as claimed in claim 1, characterized in that: The baking is performed again in the oven, the temperature in the oven is 220° C., and the time is 30 minutes.

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