IGBT device structure and preparation method thereof

Abstract

The present invention provides an IGBT device structure and a method for fabricating the same, comprising: forming multiple gate trenches, a gate oxide layer, and a polysilicon layer within an active area; forming a gate line mask pattern; forming a polysilicon gate line, with the gate line mask pattern retained on the polysilicon gate line; depositing a hard mask dielectric to form a first window and a second window exposing the active area surface, with the second window exposing the gate line mask pattern on the gate line; performing etching, wherein, based on an etching selectivity, the semiconductor substrate within the first window is partially removed to form an emitter region contact hole, while the gate line mask pattern within the second window is not removed to protect the gate line; and wet-processing the gate line mask pattern within the second window to form a gate line contact hole. The present invention allows the fabrication of emitter region contact holes and line contact holes using only one mask plate for photolithography and etching, effectively eliminating one mask plate compared to conventional processes, simplifying the process flow, shortening the production cycle, reducing tape-out costs, and improving production efficiency.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor integrated circuit design and manufacturing, and in particular relates to an IGBT device structure and a preparation method thereof. Background Art

[0002] In the field of power semiconductors, the development of insulated gate bipolar transistor (IGBT) technology has undergone a transition from planar to trench technology. This transition is accompanied by a reduction in the cell pitch, that is, the size of the smallest repeating unit is getting smaller and smaller. This high-density integration brings a series of manufacturing challenges, especially wafer warpage, which directly affects the alignment accuracy of the contact hole mask and the trench gate mask during the manufacturing process. This is crucial to ensure the consistency of the saturation voltage drop (Vcesat) within the IGBT wafer.

[0003] With the advancement of trench IGBT technology, the distance between the active area contact hole and the trench gate continues to shrink, and the requirements for alignment accuracy are also increasing. Misalignment will result in an insufficient distance between the contact hole and the trench gate, which in turn affects IGBT performance. To prevent the Bus Poly from being cut, existing IGBTs typically require two separate etching masks when fabricating the emitter contact hole and the gate line (Bus Poly) contact hole. This dual-mask process improves product reliability and performance, but significantly increases the complexity of the manufacturing process.

[0004] It should be noted that the above introduction to the technical background is merely intended to provide a clear and complete description of the technical solutions of this application and facilitate understanding by those skilled in the art. Simply because these solutions are described in the background technology section of this application, it should not be assumed that the above technical solutions are well known to those skilled in the art. Summary of the Invention

[0005] In view of the above-mentioned shortcomings of the prior art, the object of the present invention is to provide an IGBT device structure and a preparation method thereof, so as to solve the problem of the contact hole etching process of the IGBT in the prior art.

[0006] To achieve the above-mentioned purpose and other related purposes, the present invention provides a method for preparing an IGBT device structure, the method comprising: providing a semiconductor substrate, wherein an active region, a transition region, and a terminal region are arranged in sequence on the semiconductor substrate; forming a plurality of gate trenches arranged at intervals in the active region, and forming a gate oxide layer at the bottom and sidewalls of each of the gate trenches; forming a polysilicon layer in the gate trenches and on the surface of the semiconductor substrate; forming a dielectric protection layer on the surface of the polysilicon layer, and patterning and etching the dielectric protection layer to form a gate line mask pattern; etching the polysilicon layer based on the gate line mask pattern to form a polysilicon gate line, and retaining the gate line mask pattern on the polysilicon gate line; depositing a plurality of gate trenches on the semiconductor substrate; forming a plurality of gate trenches arranged at intervals in the active region, and forming a gate oxide layer on the bottom and sidewalls of each of the gate trenches; forming a polysilicon layer in the gate trenches and on the surface of the semiconductor substrate; forming a dielectric protection layer on the surface of the polysilicon layer, and patterning and etching the dielectric protection layer to form a gate line mask pattern; etching the polysilicon layer based on the gate line mask pattern to form a polysilicon gate line, and retaining the gate line mask pattern on the polysilicon gate line; depositing a plurality of gate trenches on the semiconductor substrate; A hard mask medium is provided, and the hard mask medium is patterned to form a first window exposing the surface of the active area and a second window exposing the gate line contact area, the second window exposing the gate line mask pattern on the gate line; etching is performed based on the hard mask medium, and by setting the etching selection ratio of the semiconductor substrate and the gate line mask pattern, the semiconductor substrate in the first window at the active area is partially removed to form an emitter area contact hole, and the gate line mask pattern in the second window at the gate line contact area is not removed to protect the gate line; the gate line mask pattern in the second window is removed by a wet process to form a gate line contact hole exposing the gate line; and a front metal is formed in the emitter area contact hole and the gate line contact hole.

[0007] Optionally, before forming a plurality of spaced-apart gate trenches in the active area, the method further comprises the step of forming a field oxide layer on the surface of the terminal area.

[0008] Optionally, before forming a field oxide layer on the surface of the terminal region, the method further includes the steps of: forming a lateral variable doping region in the transition region and the terminal region by ion implantation; and forming a cutoff ring doping region at the edge of the terminal region by ion implantation.

[0009] Optionally, the dielectric protection layer includes a silicon nitride layer, or the dielectric protection layer includes a composite layer of a stacked silicon dioxide layer and a silicon nitride layer.

[0010] Optionally, when etching the polysilicon layer based on the gate line mask pattern, the polysilicon layer on each gate trench is removed, and the polysilicon layer in each gate trench is partially removed to form a groove, and the preparation method also includes the step of forming a thermal oxide layer on the bottom and sidewalls of the groove and the surface of the active area.

[0011] Optionally, forming the emitter contact hole includes the steps of: etching based on the hard mask medium, and based on the etching selectivity of the semiconductor substrate exposed between the bottom and sidewall thermal oxide layer of the groove and the groove, self-aligning and removing a portion of the semiconductor substrate at the active area to form the emitter contact hole.

[0012] Optionally, the preparation method further comprises the step of: performing ion implantation on the active region in sequence to form a carrier storage region, a body region and an emitter region in the active region.

[0013] Optionally, depositing a hard mask dielectric on the semiconductor substrate includes the steps of: depositing a borophosphosilicate glass layer on the semiconductor substrate, and then performing a reflow process on the borophosphosilicate glass layer to form a hard mask dielectric.

[0014] Optionally, before forming the front metal, the steps are also included: forming an injection blocking layer on the side walls and bottom of the emitter contact hole and the gate line contact hole; removing the injection blocking layer at the bottom of the emitter contact hole and the gate line contact hole through an etch-back process; forming a contact doping region at the bottom of the emitter contact hole and the gate line contact hole through an ion implantation process; and removing the injection blocking layer through a wet process.

[0015] Optionally, after forming the front metal, the method further includes the following steps: performing ion implantation on the back side of the semiconductor substrate to form a collector region; performing ion implantation on the back side of the semiconductor substrate to form a hydrogen ion doped region, wherein the hydrogen ion doped region is arranged adjacent to the collector region; and forming a back metal layer on the back side of the semiconductor substrate.

[0016] The present invention also provides an IGBT device structure, which is prepared using the method for preparing an IGBT device structure as described in any one of the above solutions.

[0017] As described above, the IGBT device structure and the manufacturing method thereof of the present invention have the following beneficial effects:

[0018] The present invention provides a process for preparing emitter contact holes through a self-alignment process, which can automatically achieve precise positioning of the emitter contact holes, ensure the distance from the emitter contact holes to the trench gate, and thus ensure the consistency of the saturation voltage drop (Vcesat) of each IGBT device in the wafer.

[0019] The present invention optimizes and adjusts the etching process of gate line contact holes and emitter area contact holes. While realizing automatic quasi-emitter area contact hole etching, the present invention pre-produces and retains the gate line mask pattern. When the emitter area contact hole is etched, the gate line is protected from being etched in the process, thereby avoiding the problem of gate line breakage caused by etching. Subsequently, the gate line contact hole only needs to be removed by a wet process to form the gate line contact hole. The preparation of the emitter area contact hole and the line contact hole only needs to use one mask plate for photolithography and etching. Compared with the traditional process, one contact hole etching mask plate can be effectively reduced, thereby simplifying the entire process flow, shortening the production cycle, reducing the wafer production cost and improving the production efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The accompanying drawings are included to provide a further understanding of the embodiments of the present application, and constitute a part of the specification, and are used to illustrate the implementation of the present application and, together with the text description, to explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application.

[0021] Figures 1 to 15 It is a schematic diagram showing the structure of each step of the method for preparing the IGBT device structure according to an embodiment of the present invention, wherein: Figure 15 Shown is a structural schematic diagram of an IGBT device structure according to an embodiment of the present invention.

[0022] Component number description:

[0023] 1. Semiconductor substrate

[0024] 1a Gate trench

[0025] 2 Lateral variable doping region

[0026] 3 Field oxide layer

[0027] 4. Stop ring doping region

[0028] 5 Gate oxide layer

[0029] 6 Polysilicon layer

[0030] 7 Gate line mask pattern

[0031] 8 grooves

[0032] 9 Carrier storage area

[0033] 10 body zones

[0034] 11 Launch Area

[0035] 12 Thermal Oxide Layer

[0036] 13 borophosphosilicate glass layer

[0037] 14. Emitter contact hole

[0038] 15 Contact doping region

[0039] 16 Bottom front metal layer

[0040] 17 Top front metal layer

[0041] 18 Collector region

[0042] 19 Hydrogen ion doped region

[0043] 191 The first N-type doping peak

[0044] 192 The second N-type doping peak

[0045] 193 The third N-type doping peak

[0046] 194 The fourth N-type doping peak

[0047] 20 Back metal layer DETAILED DESCRIPTION

[0048] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0049] It should be emphasized that the term "include / comprising" when used herein refers to the presence of features, integers, steps or components, but does not exclude the presence or addition of one or more other features, integers, steps or components.

[0050] Features described and / or illustrated with respect to one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0051] For example, when describing the embodiments of the present invention, cross-sectional views of device structures may be partially enlarged to scale for ease of explanation. Furthermore, these schematic views are merely illustrative and should not limit the scope of the present invention. Furthermore, in actual manufacturing, three-dimensional dimensions, including length, width, and depth, should be included.

[0052] For convenience, spatially relative terms such as "under," "below," "below," "below," "above," and "on" may be used herein to describe the relationship of one element or feature to other elements or features shown in the drawings. It will be understood that these spatially relative terms are intended to encompass orientations of the device in use or operation in addition to the orientation depicted in the drawings. Additionally, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

[0053] In the context of the present application, a structure described as a first feature being "above" a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature is formed between the first and second features, such that the first and second features may not be in direct contact.

[0054] It should be noted that the illustrations provided in this embodiment are only used to schematically illustrate the basic concept of the present invention. Therefore, the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complicated.

[0055] like Figures 1 to 15 As shown, this embodiment provides a method for preparing an IGBT device structure, and the preparation method includes the following steps:

[0056] like Figure 1 As shown, first, step 1) is performed to provide a semiconductor substrate 1, on which an active region, a transition region and a terminal region arranged in sequence are provided.

[0057] In one embodiment, the semiconductor substrate 1 may be a silicon substrate, a silicon germanium substrate, a silicon carbide substrate, or the like. The semiconductor substrate 1 may be doped, and its doping concentration and thickness may be set according to the withstand voltage requirements of the IGBT device. In this embodiment, the semiconductor substrate 1 is a silicon substrate, and its doping type is N-type doping.

[0058] like Figures 2 and 3 As shown, step 2) is then performed to form a plurality of spaced-apart gate trenches 1a in the active area, and to form a gate oxide layer 5 at the bottom and sidewall of each gate trench 1a; and to form a polysilicon layer 6 in the gate trench 1a and on the surface of the semiconductor substrate 1.

[0059] In one embodiment, before forming a plurality of spaced-apart gate trenches 1a in the active region, the process further includes the following steps: forming a lateral variable doping region 2 in the transition region and the terminal region by ion implantation; and forming a stop ring doping region 4 at the edge of the terminal region by ion implantation. Specifically, P-type ions (such as boron) can be implanted in the transition region and the terminal region through a mask, and the implantation dose can be 1e12 cm -2 ~5e13cm -2 The injection energy can be 60keV~200keV, and then N-type ions (such as phosphorus) are injected into the edge of the terminal area through the mask, with an injection dose of 1e15cm -2 ~1e16cm -2The implantation energy is 60keV to 200keV, and a thermal process (such as an annealing process) is performed at a temperature of 1050°C to 1250°C for 30 minutes to 300 minutes to form a P-type doped field limiting ring (JTE) or a lateral variable doping region 2 (VLD) terminal in the P-type ion implantation region, and an N-type doped stop ring doping region 4 in the N-type ion implantation region. Of course, in other embodiments, the stop ring doping region 4 may not be additionally formed to save process costs.

[0060] In one embodiment, before forming a plurality of spaced-apart gate trenches 1a in the active area, the step is further included: forming a field oxide layer 3 on the surface of the terminal area. For example, the field oxide layer 3 can be formed on the surface of the semiconductor substrate 1 by a thermal oxidation process, and then the field oxide layer 3 is formed on the surface of the terminal area by a photolithography and etching process.

[0061] In one embodiment, a plurality of spaced-apart gate trenches 1a can be formed in the active area through photolithography and etching processes, and then a gate oxide layer 5 is formed on the bottom and sidewalls of each gate trench 1a through a thermal oxidation process (such as heating through a furnace tube in an air or oxygen atmosphere, etc.); and then a polysilicon layer 6 is formed in the gate trench 1a and on the surface of the semiconductor substrate 1 through a deposition process.

[0062] like Figures 4 and 5 As shown, step 3 is then performed to form a dielectric protection layer on the surface of the polysilicon layer 6 and pattern-etch the dielectric protection layer to form a gate line mask pattern 7.

[0063] In one embodiment, the dielectric protective layer is selected to be a material having a high etching selectivity ratio with the semiconductor substrate 1 material. The high selectivity ratio can be, for example, semiconductor substrate 1: dielectric protective layer greater than or equal to 50:1, etc. For example, when the semiconductor substrate 1 is a silicon substrate, the dielectric protective layer can be a silicon nitride layer, or the dielectric protective layer can be a composite layer of a stack of silicon dioxide layer and silicon nitride layer, wherein the silicon dioxide is the bottom layer and the silicon nitride layer is the top layer.

[0064] like Figure 6 As shown, step 4 is then performed to etch the polysilicon layer 6 based on the gate line mask pattern 7 to form a polysilicon gate line, and the gate line mask pattern 7 is retained on the polysilicon gate line.

[0065] like Figures 7 and 8 As shown, when the polysilicon layer 6 is etched based on the gate line mask pattern 7, the polysilicon layer 6 on each gate trench 1a is removed, and the polysilicon layer 6 in each gate trench 1a is partially removed to form a groove 8, and the depth of the groove 8 can be 0.4 microns to 0.7 microns.

[0066] Afterwards, ion implantation is performed sequentially on the active region to form a carrier storage region 9 , a body region 10 and an emitter region 11 in the active region.

[0067] Specifically, the carrier storage area 9 is injected through a mask or the carrier storage area 9 is generally injected without a mask. The injected ions may be phosphorus and the injection dose may be 1e12 cm -2 ~5e13cm -2 The implantation energy can be 80KeV~2MeV, the push temperature can be 1050℃~1250℃, the time can be 30min~300min, and then the body region 10 general implantation can be performed. The implanted ions can be boron, and the implantation dose is 4e13cm -2 ~1e14cm -2 The injection energy is 60keV~200keV, the push temperature can be 1050℃~1250℃, the time is 10min~120min, and then the emitter area 11 is injected through the mask. The injection ion can be arsenic and the injection dose can be 5e15cm -2 ~2e16cm -2 The injection energy can be 60keV to 600keV, the advancement temperature can be 900℃ to 1000℃, and the time can be 30min to 120min.

[0068] Finally, a thermal oxide layer 12 is formed on the bottom and sidewalls of the groove 8 and the surface of the active area. For example, a furnace tube can be used to grow the thermal oxide layer 12, and the thickness of the thermal oxide layer 12 can be 1000 angstroms to 3000 angstroms.

[0069] like Figure 9 and Figure 10 As shown, step 5 is then performed to deposit a hard mask medium on the semiconductor substrate 1 and pattern the hard mask medium to form a first window exposing the surface of the active area and a second window exposing the gate line contact area, wherein the second window exposes the gate line mask pattern 7 on the gate line.

[0070] In one embodiment, depositing a hard mask dielectric on the semiconductor substrate 1 includes the steps of depositing a borophosphosilicate glass (BPSG) layer 13 on the semiconductor substrate 1, and then reflowing the BPSG layer 13 to form the hard mask dielectric. Specifically, the thickness of the deposited BPSG layer 13 can be 8,000 angstroms to 15,000 angstroms, and the reflow temperature of the BPSG layer 13 can be 900° C. to 1,000° C. for 30 minutes to 240 minutes.

[0071] like Figure 11As shown, step 6 is then performed, etching is performed based on the hard mask medium, and by setting the etching selection ratio of the semiconductor substrate 1 and the gate line mask pattern 7, the semiconductor substrate 1 in the first window at the active area is partially removed to form the emitter area contact hole 14, and the gate line mask pattern 7 in the second window at the gate line contact area is not removed to protect the gate line.

[0072] In one embodiment, forming the emitter contact hole 14 includes the steps of: performing etching based on the hard mask dielectric, and based on the etching selectivity of the semiconductor substrate 1 (such as a silicon substrate) exposed between the bottom and sidewall thermal oxide layer 12 of the groove 8 and the groove 8, self-aligningly removing a portion of the semiconductor substrate 1 at the active area to form the emitter contact hole 14, such as Figure 11 As shown. The present invention provides a process for preparing emitter contact holes 14 through a self-aligned process. This process automatically achieves precise positioning of emitter contact holes 14, ensuring the distance between emitter contact holes 14 and the trench gate, thereby ensuring the consistency of the saturation voltage drop (Vcesat) of each IGBT device within the wafer. Simultaneously, the hard mask dielectric exposes the stop ring doped region 4, and the emitter contact holes 14 are etched to form contact holes in the stop ring doped region 4.

[0073] like Figure 12 As shown, before forming the front metal, the steps include: forming an injection barrier layer on the sidewalls and bottom of the emitter contact hole 14 and the gate line contact hole; removing the injection barrier layer at the bottom of the emitter contact hole 14 and the gate line contact hole by an etch-back process; forming a contact doping region 15 at the bottom of the emitter contact hole 14 and the gate line contact hole by an ion implantation process; and removing the injection barrier layer by a wet process. Specifically, considering that when injecting into the emitter contact hole 14, the implantation of the sidewalls of the emitter contact hole 14 will affect the doping of the emitter 11, a silicon nitride with a thickness of 500 angstroms to 1500 angstroms is first deposited before the emitter contact hole 14 is implanted, and then etched back. The silicon nitride retained on the sidewalls of the emitter contact hole 14 can prevent P-type ions from being implanted into the sidewall region of the emitter contact hole 14, and then boron or BF2 is implanted into the contact hole to form a P+ type contact doping region 15, wherein the implantation energy of BF2 can be 20keV to 50keV, and the implantation dose can be 5e14cm -2 ~5e15cm -2 , or the boron implantation energy can be 40keV to 100keV, and the implantation dose can be 5e12cm -2 ~5e14cm -2 Finally, the silicon nitride on the sidewall is removed by a wet process. It should be noted that the implantation of the contact doping region 15 can also be performed after the gate line mask pattern 7 is subsequently removed by a wet process, and is not limited to the example listed here.

[0074] like Figure 13 As shown, step 7 is then performed to remove the gate line mask pattern 7 in the second window by a wet process without a mask to form a gate line contact hole exposing the gate line.

[0075] The present invention optimizes and adjusts the etching process of the gate line contact hole and the emitter area contact hole 14. While realizing automatic quasi-emitter area contact hole 14 etching, the gate line is protected from being etched during the process of etching the emitter area contact hole 14 by pre-fabricating and retaining the gate line mask pattern 7, thereby avoiding the problem of the gate line being etched and caused to break. Subsequently, the gate line contact hole can be formed by removing the gate line mask pattern 7 through a wet process, so that the preparation of the emitter area contact hole 14 and the line contact hole only requires the use of one mask plate for photolithography and etching. Compared with the traditional process, one contact hole etching mask plate can be effectively reduced, thereby simplifying the entire process flow, shortening the production cycle, reducing the wafer production cost and improving the production efficiency.

[0076] like Figure 14 As shown, step 8) is then performed to form a front metal in the emitter region contact hole 14 and the gate line contact hole.

[0077] In one embodiment, a bottom front metal layer 16 (e.g., Ti / TiN / W) is prepared by a metal deposition process and then etched back. An upper front metal layer 17 (e.g., AlCu) is then deposited by a metal deposition process, followed by metal photolithography and etching to form a front metal layer. Specifically, the front metal layer can be used to lead out the emitter region 11, the gate line, and the stop ring doped region 4. At the same time, if field plate polysilicon is present, the front metal layer can also simultaneously lead out the field plate polysilicon.

[0078] like Figure 15 As shown, step 9 is finally performed, ion implantation is performed on the back side of the semiconductor substrate 1 to form a collector region 18; ion implantation is performed on the back side of the semiconductor substrate 1 to form a hydrogen ion doping region 19, wherein the hydrogen ion doping region 19 is arranged adjacent to the collector region 18; and a back metal layer 20 is formed on the back side of the semiconductor substrate 1.

[0079] In one embodiment, the semiconductor substrate 1 is first turned over and thinned to a certain thickness, which depends on the withstand voltage requirement of the IGBT device. Then, a boron ion implantation is performed with an implantation energy of 60KeV to 20KeV and an implantation dose of 3e12cm -2 ~1e14cm -2, forming a P-type collector region 18, and then using laser annealing equipment to activate the injected boron ions; then hydrogen is injected four times from the back of the semiconductor substrate 1 and annealed to form a hydrogen ion doped region 19 (191 represents the first N-type doping peak formed by hydrogen injection; 192 represents the second N-type doping peak formed by hydrogen injection; 193 represents the third N-type doping peak formed by hydrogen injection; 194 represents the fourth N-type doping peak formed by hydrogen injection, and the concentration of the doping peak can be gradually increased from 191 to 194). It should be noted that the hydrogen injection is 5 times, 3 times, 2 times or 1 time, and is not limited to the examples listed here. Finally, a back metal layer 20 is formed on the back of the semiconductor substrate 1, and the back metal layer 20 can be Al / Ti / Ni / Ag.

[0080] like Figure 15 As shown, this embodiment further provides an IGBT device structure, which is prepared by the preparation method of the IGBT device structure described in any of the above embodiments.

[0081] As described above, the IGBT device structure and the manufacturing method thereof of the present invention have the following beneficial effects:

[0082] The present invention provides a process for preparing emitter contact holes through a self-alignment process, which can automatically achieve precise positioning of the emitter contact holes, ensure the distance from the emitter contact holes to the trench gate, and thus ensure the consistency of the saturation voltage drop (Vcesat) of each IGBT device in the wafer.

[0083] The present invention optimizes and adjusts the etching process of gate line contact holes and emitter area contact holes. While realizing automatic quasi-emitter area contact hole etching, the present invention pre-produces and retains the gate line mask pattern. When the emitter area contact hole is etched, the gate line is protected from being etched in the process, thereby avoiding the problem of gate line breakage caused by etching. Subsequently, the gate line contact hole only needs to be removed by a wet process to form the gate line contact hole. The preparation of the emitter area contact hole and the line contact hole only needs to use one mask plate for photolithography and etching. Compared with the traditional process, one contact hole etching mask plate can be effectively reduced, thereby simplifying the entire process flow, shortening the production cycle, reducing the wafer production cost and improving the production efficiency.

[0084] Therefore, the present invention effectively overcomes various shortcomings of the prior art and has high industrial utilization value.

[0085] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A method for preparing an IGBT device structure, characterized in that: The preparation method comprises: Providing a semiconductor substrate, wherein an active region, a transition region and a terminal region are arranged in sequence; forming a plurality of gate trenches arranged at intervals in the active area, and forming a gate oxide layer on the bottom and sidewalls of each gate trench; forming a polysilicon layer in the gate trench and on the surface of the semiconductor substrate; forming a dielectric protection layer on the surface of the polysilicon layer, and pattern-etching the dielectric protection layer to form a gate line mask pattern; etching the polysilicon layer based on the gate line mask pattern to form a polysilicon gate line, with the gate line mask pattern remaining on the polysilicon gate line; Depositing a hard mask dielectric on the semiconductor substrate and patterning the hard mask dielectric to form a first window exposing the surface of the active area and a second window exposing the gate line contact area, wherein the second window exposes the gate line mask pattern on the gate line; Etching is performed based on the hard mask dielectric, and by setting an etching selectivity ratio between the semiconductor substrate and the gate line mask pattern, the semiconductor substrate in the first window at the active area is partially removed to form an emitter region contact hole, and the gate line mask pattern in the second window at the gate line contact area is not removed to protect the gate line; removing the gate line mask pattern in the second window by a wet process to form a gate line contact hole exposing the gate line; A front metal is formed in the emitter region contact hole and the gate line contact hole.

2. The method for preparing an IGBT device structure according to claim 1, wherein: Before forming a plurality of gate trenches spaced apart in the active area, the method further includes the following steps: A field oxide layer is formed on the surface of the terminal region.

3. The method for preparing an IGBT device structure according to claim 2, wherein: Before forming a field oxide layer on the surface of the terminal region, the method further includes the following steps: forming a lateral variable doping region in the transition region and the terminal region by ion implantation; A cut-off ring doping region is formed at the edge of the terminal region by ion implantation.

4. The method for preparing an IGBT device structure according to claim 1, wherein: The dielectric protection layer includes a silicon nitride layer, or the dielectric protection layer includes a composite layer of a silicon dioxide layer and a silicon nitride layer stacked together.

5. The method for preparing an IGBT device structure according to claim 1, wherein: When etching the polysilicon layer based on the gate line mask pattern, the polysilicon layer on each gate trench is removed, and the polysilicon layer in each gate trench is partially removed to form a groove. The preparation method further includes the steps of: A thermal oxide layer is formed on the bottom and sidewall of the groove and the surface of the active area.

6. The method for preparing an IGBT device structure according to claim 5, wherein: Forming the emitter region contact hole includes the following steps: Etching is performed based on the hard mask dielectric, and based on the etching selectivity of the semiconductor substrate exposed between the thermal oxide layer at the bottom and sidewall of the groove and the groove, a portion of the semiconductor substrate at the active area is self-alignedly removed to form an emitter contact hole.

7. The method for preparing an IGBT device structure according to claim 1, wherein: The preparation method further comprises the steps of: Ion implantation is performed sequentially on the active region to form a carrier storage region, a body region and an emission region in the active region.

8. The method for preparing an IGBT device structure according to claim 1, wherein: Depositing a hard mask dielectric on the semiconductor substrate comprises the steps of: A borophosphosilicate glass layer is deposited on the semiconductor substrate, and then a reflow process is performed on the borophosphosilicate glass layer to form a hard mask dielectric.

9. The method for preparing an IGBT device structure according to claim 1, wherein: Before forming the front metal, the following steps are also included: forming an injection blocking layer on the sidewalls and bottom of the emitter region contact hole and the gate line contact hole; Removing the injection barrier layer at the bottom of the emitter contact hole and the gate line contact hole by an etch-back process; forming a contact doping region at the bottom of the emitter region contact hole and the gate line contact hole by an ion implantation process; The implantation barrier layer is removed by a wet process.

10. The method for preparing an IGBT device structure according to claim 1, wherein: After forming the front metal, the following steps are also included: Performing ion implantation on the back side of the semiconductor substrate to form a collector region; Performing ion implantation on the back surface of the semiconductor substrate to form a hydrogen ion doped region, wherein the hydrogen ion doped region is disposed adjacent to the collector region; A back metal layer is formed on the back side of the semiconductor substrate.

11. An IGBT device structure, characterized in that: The IGBT device structure is prepared by the method for preparing an IGBT device structure according to any one of claims 1 to 10.

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