Integrated structure of hybrid heterogeneous integrated circuit and preparation method thereof

Abstract

The present invention provides an integrated structure of a hybrid heterogeneous integrated circuit and a method for fabricating the same. S1: Fabricating a GaN HEMT device, comprising a first substrate, a buffer layer, a GaN channel, a first gate, a first source, a first drain, and a barrier layer; S2: Fabricating a SiC JFET device, comprising a second substrate, a SiC channel, an n-EPI layer, a second source, and a second drain; S3: Bonding the first drain and first source of the GaN HEMT device to the corresponding second drain and second source of the SiC JFET device, respectively, to obtain the integrated structure of the hybrid heterogeneous integrated circuit. The present invention reduces the pitch and improves the connection density of the integrated circuit.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductors, and in particular relates to an integrated structure of a hybrid heterogeneous integrated circuit and a preparation method thereof. Background Art

[0002] Power semiconductor materials such as Si, GaN, and SiC each have their own advantages and disadvantages. Si is more mature, but its bandgap is relatively short, resulting in higher performance for power devices. GaN HEMT devices, on the other hand, offer excellent two-dimensional electron gas concentration and high mobility. However, at high voltage levels, their vertical substrate withstand voltage is limited. Furthermore, the required epitaxial thickness, which matches the voltage level, increases epitaxial growth costs. SiC MOSFET devices offer excellent thermal conductivity and voltage resistance, but due to numerous defects at the gate oxide interface, channel mobility is low, resulting in increased resistance. Therefore, a new power device structure that fully integrates the advantages of different materials is needed. Because horizontal devices offer the inherent advantage of horizontal integration, the basic components of traditional integrated circuits are horizontal structures, such as LDMOS and CMOS in the BCD process. However, these integrated circuits suffer from issues such as component dispersion, large area, and low transmission efficiency. Consequently, traditional horizontal circuits are gradually evolving towards vertical or 3D circuits to achieve higher integration density. Traditional vertical integration involves stacking two functional materials and vertically interconnecting them through through-silicon vias (TSVs). However, due to the limitation of the aspect ratio of TSV, the size of the connection port cannot be guaranteed, which limits the further reduction of the pitch. Summary of the Invention

[0003] In view of this, the present invention provides an integrated structure of a hybrid heterogeneous integrated circuit and a preparation method thereof, wherein GaN HEMT devices and SiC JFET devices are first prepared separately, and then the GaN HEMT devices and SiC JFET devices are bonded together, thereby reducing the pitch and improving the connection density of the integrated circuit.

[0004] In order to achieve the above object, the present invention adopts the following technical solutions:

[0005] First, the present invention provides a method for preparing an integrated structure of a hybrid heterogeneous integrated circuit, comprising the following steps:

[0006] S1. Prepare a GaN HEMT device, the GaN HEMT device comprising a first substrate, a buffer layer, a GaN channel, a first gate, a first source, a first drain, and a barrier layer, wherein the first substrate, the buffer layer, the GaN channel, and the barrier layer are stacked in sequence, the first gate is located on a side of the barrier layer away from the GaN channel, one end of the first source and the first drain are located on a side of the barrier layer away from the GaN channel, and the other end is connected to the GaN channel;

[0007] S2. Prepare a SiC JFET device, wherein the SiC JFET device includes a second substrate, a SiC channel, an n-EPI layer, a second source, and a second drain, wherein the second substrate, the SiC channel, and the n-EPI layer are stacked in sequence, a p-type doped region and an n-type doped region are provided on a side of the n-EPI layer away from the SiC channel, the second drain and the second source are located on a side of the n-EPI layer away from the SiC channel, the second drain is connected to the n-type doped region, and the second source is connected to the p-type doped region;

[0008] S3. The first drain and the first source of the GaN HEMT device are bonded to the second drain and the second source of the SiC JFET device respectively, to obtain an integrated structure of a hybrid heterogeneous integrated circuit.

[0009] Preferably, in step S1 , the other ends of the first source and the first drain of the GaN HEMT device are both located on a side of the buffer layer close to the first substrate.

[0010] Preferably, in step S3, the specific step of bonding connection is to remove the first substrate, and the first source and the first drain are located at the end of the buffer layer close to the first substrate and are bonded to the second source and the second drain of the SiC JFET device respectively.

[0011] Preferably, in step S3, the specific step of bonding is to rotate the GaN HEMT device until the barrier layer is close to the n-EPI layer of the SiC JFET device, and then bond the first source and the first drain to the second source and the second drain respectively.

[0012] Preferably, the bonding connection is solder bump bonding or hybrid bonding.

[0013] Preferably, the number of the first source electrodes is two, the number of the second source electrodes is two, and the two first source electrodes and the two second source electrodes are bonded in a one-to-one correspondence.

[0014] Preferably, the number of the first drain electrode is one, and two first gate electrodes are sandwiched outside the first drain electrode; the number of the second drain electrode is one, and two second source electrodes are sandwiched outside the second drain electrode.

[0015] Preferably, the GaN HEMT device further includes a current-carrying layer, and the current-carrying layer is located on a side of the barrier layer away from the GaN channel.

[0016] Preferably, the material of the first substrate includes at least one of Si or SiC.

[0017] Secondly, the present invention provides an integrated structure of a hybrid heterogeneous integrated circuit, and the integrated structure is prepared by adopting the manufacturing method.

[0018] Compared with the prior art, the present invention has the following beneficial effects:

[0019] (1) The present invention first prepares GaN HEMT devices and SiC JFET devices separately, and then bonds the GaN HEMT devices and SiC JFET devices together, thereby reducing the pitch and improving the connection density of the integrated circuit.

[0020] (2) The present invention first prepares GaN HEMT devices and SiC JFET devices separately, and then bonds the GaN HEMT devices and SiC JFET devices, thereby avoiding the problem of ohmic contact temperature mismatch.

[0021] (3) The GaN HEMT device and the SiC JFET device of the present invention form a metal-to-metal bond or a hybrid bond through a dielectric-metal hybrid interface, resulting in low contact resistance, high interconnection density, and high reliability. Furthermore, the electrical connection distance between the GaN HEMT device and the SiC JFET device is short, parasitics are small, and fast switching response speed can be achieved.

[0022] (4) In the present invention, when the rear-end parasitics of the first source and the first drain in the GaN HEMT device are small, the GaN HEMT device is rotated to the n-EPI layer of the SiC JFET device near the barrier layer through a flip-chip process, and then the first source and the first drain are bonded to the second source and the second drain respectively. There is no need to perform a complex TGV through-hole process, and the operation is simple and fast. At the same time, the quality of the GaN HEMT device prepared in this way is higher than that of the direct epitaxial method, and fast switching with low on-resistance can be achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 The preparation process of the integrated structure of the hybrid heterogeneous integrated circuit provided in Example 1 of the present invention;

[0024] Figure 2 The preparation process of the integrated structure of the hybrid heterogeneous integrated circuit provided in Examples 2 and 3 of the present invention;

[0025] Figure 3 A schematic diagram of the GaN HEMT device architecture provided by one embodiment of the present invention;

[0026] Figure 4 A schematic diagram of a SiC JFET device architecture provided by an embodiment of the present invention.

[0027] Reference numerals: integrated structure 100 of hybrid heterojunction integrated circuit, GaN HEMT device 1, first substrate 11, buffer layer 12, GaN channel 13, first gate 14, first source 15, first drain 16, barrier layer 17, current-carrying layer 18, SiC JFET device 2, second substrate 21, SiC channel 22, n-EPI layer 23, p-type doped region 231, n-type doped region 232, second source 24, second drain 25. DETAILED DESCRIPTION

[0028] The present invention will be further described in detail below with reference to specific embodiments so that those skilled in the art can understand the present invention more clearly.

[0029] like Figure 1-4 As shown, the present invention provides a method for preparing an integrated structure 100 of a hybrid heterogeneous integrated circuit, comprising the following steps:

[0030] S1. Prepare a GaN HEMT device 1, wherein the GaN HEMT device 1 includes a first substrate 11, a buffer layer 12, a GaN channel 13, a first gate 14, a first source 15, a first drain 16, and a barrier layer 17, wherein the first substrate 11, the buffer layer 12, the GaN channel 13, and the barrier layer 17 are stacked in sequence, the first gate 14 is located on a side of the barrier layer 17 away from the GaN channel 13, and one end of the first source 15 and the first drain 16 are located on a side of the barrier layer 17 away from the GaN channel 13, and the other end is connected to the GaN channel 13;

[0031] Specifically, the GaN HEMT device 1, also known as a gallium nitride high electron mobility transistor, features a first substrate 11 typically made of sapphire, silicon (Si), silicon carbide (SiC), or gallium nitride (GaN). The choice of first substrate 11 affects device performance and cost. A buffer layer 12 is located between the first substrate 11 and the GaN channel 13 to reduce lattice mismatch and stress. This layer is typically a thin film of aluminum nitride (AlN) or gallium nitride (GaN). The GaN channel 13 primarily comprises a high-electron-mobility two-dimensional electron gas (2DEG) layer. This layer is typically a heterostructure composed of aluminum nitride (Al) and gallium nitride (GaN). A common structure is an AlGaN / GaN heterostructure, where the aluminum content of the AlGaN layer determines the electron gas density. The first gate 14, a key component for controlling current flow, is typically made of a metal material such as tungsten or gold. The design and dimensions of the first gate 14 significantly influence the switching characteristics and frequency response of the device. The design and layout of the first source 15 and the first drain 16 are crucial to the current conduction capability and power characteristics of the device. They are also usually made of metal materials and form good contact with the active layer. The barrier layer 17 plays an important role in semiconductor materials, which is used to control the flow of electrons, form a special energy band structure and realize the function of the device. The design and manufacturing process of these structures directly affect the performance of the GaN HEMT device 1, such as switching speed, power handling capability and thermal management capability. The specific structure of the GaN HEMT device 1 can be as follows: Figure 3 shown.

[0032] S2. Prepare a SiC JFET device 2, wherein the SiC JFET device 2 includes a second substrate 21, a SiC channel 22, an n-EPI layer 23, a second source 24, and a second drain 25. The second substrate 21, the SiC channel 22, and the n-EPI layer 23 are stacked in sequence. A p-type doped region 231 and an n-type doped region 232 are provided on a side of the n-EPI layer 23 away from the SiC channel 22. The second drain 25 and the second source 24 are located on a side of the n-EPI layer 23 away from the SiC channel 22. The second drain 25 is connected to the n-type doped region 232, and the second source 24 is connected to the p-type doped region 231.

[0033] Specifically, the SiC JFET device 2, also known as a silicon carbide junction field-effect transistor, typically uses single-crystal silicon carbide for the second substrate 21, which provides the device with high thermal conductivity and high electric field tolerance. The SiC channel 22 is the flow path for electrons or holes and is typically composed of n-type or p-type materials with a low degree of doping. The design of the SiC channel 22 directly affects the device's conductivity and switching speed. The n-EPI layer 23 refers to an n-type doped layer formed through epitaxial growth technology and is widely used in modern semiconductor devices to provide excellent electronic properties and performance. The gate of a SiC JFET is typically a p-type or n-type region connected to the source. The gate controls the current between the second source 24 and the second drain 25 by applying a voltage. The second source 24 and the second drain 25 are the input and output terminals of the current and are typically formed on the SiC substrate through doping. The second source 24 is generally n-type doped, while the second drain 25 can be p-type or n-type doped, depending on the device design. The SiC JFET device 2 is widely used in power electronics, electric vehicles, renewable energy, industrial control and other fields due to its high temperature, high power and high frequency performance.

[0034] S3 , the first drain 16 and the first source 15 of the GaN HEMT device 1 are bonded to the second drain 25 and the second source 24 of the SiC JFET device 2 , respectively, to obtain an integrated structure 100 of a hybrid heterogeneous integrated circuit.

[0035] In the above technical solution, the present invention first separately fabricates a GaN HEMT device 1 and a SiC JFET device 2, and then bond-connects the GaN HEMT device 1 and the SiC JFET device 2, thereby reducing the pitch and improving the connection density of the integrated circuit. Furthermore, because the present invention first separately fabricates the GaN HEMT device 1 and the SiC JFET device 2, and then bond-connects the GaN HEMT device 1 and the SiC JFET device 2, the problem of ohmic contact temperature mismatch is avoided. The GaN HEMT device 1 and the SiC JFET device 2 of the present invention form a metal-to-metal bond or a hybrid bond through a dielectric-metal hybrid interface, resulting in low contact resistance, high interconnection density, and high reliability.

[0036] In some embodiments, as Figure 1As shown, in step S1, the other ends of the first source 15 and first drain 16 of the GaN HEMT device 1 are both located on the side of the buffer layer 12 close to the first substrate 11. Furthermore, in step S3, the bonding step is specifically to remove the first substrate 11, and then bond the first source 15 and first drain 16 located at the ends of the buffer layer 12 close to the first substrate 11 to the second source 24 and second drain 25 of the SiC JFET device 2, respectively. This approach shortens the electrical connection distance between the GaN HEMT device 1 and the SiC JFET device 2, minimizing parasitics and enabling fast switching response.

[0037] In some embodiments, in step S3, the specific step of bonding is to rotate the GaN HEMT device 1 so that the barrier layer 17 is close to the n-EPI layer 23 of the SiC JFET device 2, and then bond the first source 15 and the first drain 16 to the second source 24 and the second drain 25 respectively. This method is flip-chip bonding, such as Figure 2 As shown, the GaN HEMT device 1 is first rotated 180°, so that the barrier layer 17 is close to the n-EPI layer 23 of the SiC JFET device 2. The first source 15 and the first drain 16 are then bonded to the second source 24 and the second drain 25, respectively. When the back-end parasitics of the first source 15 and the first drain 16 in the GaN HEMT device 1 are small, the GaN HEMT device 1 and the SiC JFET device 2 are bonded using a flip-chip process. This eliminates the need for complex TGV (through-hole) processes, making the process simple and fast. Furthermore, the GaN HEMT device 1 fabricated using this method is of higher quality than that fabricated using direct epitaxy, enabling fast switching with low on-resistance.

[0038] Furthermore, the bonding connection is solder bump bonding or hybrid bonding. Solder bump bonding is a common chip bonding technology commonly used for packaging and connecting chips. In this method, a layer of solder is applied to the metal surface of the chip, then the chip is bonded to another substrate or chip. Bonding is achieved by applying heat and pressure. The solder melts upon heating, forming a reliable connection. In some embodiments, the main process steps for bump bonding include: step 1: underbump metallization (UBM); step 2: chip bumping; step 3: assembling the bumped chip onto the substrate / board; and step 4: filling the pores under the chip with a non-conductive material. Hybrid bonding is a modern, advanced bonding technology used to stack two or more chips in the same package to create so-called 3D chips. The core of this technology is to align the crystal planes of different chips through a specialized process and achieve bonding at the atomic level, thereby achieving high-density, high-performance chip stacking. Hybrid bonding technology is widely used in processors, memory, AI, and other fields, helping to reduce chip size and improve performance and energy efficiency.

[0039] In some embodiments, there are two first source electrodes 15 and two second source electrodes 24, and the two first source electrodes 15 are bonded to the two second source electrodes 24 in a one-to-one correspondence. The two first source electrodes 15 are equivalent to two GaN devices for one SiC device, and the actual device structure is half, with the middle TSV shared.

[0040] Furthermore, there is one first drain electrode 16 , and two first gate electrodes 14 are sandwiched outside the first drain electrode 16 ; there is one second drain electrode 25 , and two second source electrodes 24 are sandwiched outside the second drain electrode 25 .

[0041] In some embodiments, the GaN HEMT device 1 further includes a current-carrying layer 18, which is located on a side of the barrier layer 17 away from the GaN channel 13. The current-carrying layer 18 is Figure 1 The carrier layer in the semiconductor material is the particle responsible for charge transport.

[0042] In some embodiments, the material of the first substrate 11 includes at least one of Si or SiC.

[0043] The present invention further provides an integrated structure 100 of a hybrid heterogeneous integrated circuit, and the integrated structure is manufactured using the manufacturing method.

[0044] Example 1

[0045] S1. Prepare a GaN HEMT device 1, wherein the GaN HEMT device 1 includes a first substrate 11, a buffer layer 12, a GaN channel 13, a first gate 14, a first source 15, a first drain 16, and a barrier layer 17, wherein the first substrate 11, the buffer layer 12, the GaN channel 13, and the barrier layer 17 are stacked in sequence, the first gate 14 is located on a side of the barrier layer 17 away from the GaN channel 13, one end of the first source 15 and the first drain 16 are located on a side of the barrier layer 17 away from the GaN channel 13, and the other end is connected to the GaN channel 13, wherein the other end of the first source 15 and the first drain 16 of the GaN HEMT device 1 are both located on a side of the buffer layer 12 close to the first substrate 11

[0046] S2. Prepare a SiC JFET device 2, wherein the SiC JFET device 2 includes a second substrate 21, a SiC channel 22, an n-EPI layer 23, a second source 24, and a second drain 25. The second substrate 21, the SiC channel 22, and the n-EPI layer 23 are stacked in sequence. A p-type doped region 231 and an n-type doped region 232 are provided on a side of the n-EPI layer 23 away from the SiC channel 22. The second drain 25 and the second source 24 are located on a side of the n-EPI layer 23 away from the SiC channel 22. The second drain 25 is connected to the n-type doped region 232, and the second source 24 is connected to the p-type doped region 231.

[0047] S3. The first substrate 11 is removed, and the first source 15 and the first drain 16 are located at the end of the buffer layer 12 close to the first substrate 11 and are respectively connected to the second source 24 and the second drain 25 of the SiC JFET device 2 by hybrid bonding.

[0048] Example 2

[0049] S1. Prepare a GaN HEMT device 1, wherein the GaN HEMT device 1 includes a first substrate 11, a buffer layer 12, a GaN channel 13, a first gate 14, a first source 15, a first drain 16, and a barrier layer 17, wherein the first substrate 11, the buffer layer 12, the GaN channel 13, and the barrier layer 17 are stacked in sequence, the first gate 14 is located on a side of the barrier layer 17 away from the GaN channel 13, and one end of the first source 15 and the first drain 16 are located on a side of the barrier layer 17 away from the GaN channel 13, and the other end is connected to the GaN channel 13;

[0050] S2. Prepare a SiC JFET device 2, wherein the SiC JFET device 2 includes a second substrate 21, a SiC channel 22, an n-EPI layer 23, a second source 24, and a second drain 25. The second substrate 21, the SiC channel 22, and the n-EPI layer 23 are stacked in sequence. A p-type doped region 231 and an n-type doped region 232 are provided on a side of the n-EPI layer 23 away from the SiC channel 22. The second drain 25 and the second source 24 are located on a side of the n-EPI layer 23 away from the SiC channel 22. The second drain 25 is connected to the n-type doped region 232, and the second source 24 is connected to the p-type doped region 231.

[0051] S3. Rotate the GaN HEMT device 1 until the barrier layer 17 is close to the n-EPI layer 23 of the SiC JFET device 2, and then hybrid-bond the first source 15 and the first drain 16 to the second source 24 and the second drain 25, respectively.

[0052] Example 3

[0053] S1. Prepare a GaN HEMT device 1, wherein the GaN HEMT device 1 includes a first substrate 11, a buffer layer 12, a GaN channel 13, a first gate 14, a first source 15, a first drain 16, and a barrier layer 17, wherein the first substrate 11, the buffer layer 12, the GaN channel 13, and the barrier layer 17 are stacked in sequence, the first gate 14 is located on a side of the barrier layer 17 away from the GaN channel 13, and one end of the first source 15 and the first drain 16 are located on a side of the barrier layer 17 away from the GaN channel 13, and the other end is connected to the GaN channel 13;

[0054] S2. Prepare a SiC JFET device 2, wherein the SiC JFET device 2 includes a second substrate 21, a SiC channel 22, an n-EPI layer 23, a second source 24, and a second drain 25. The second substrate 21, the SiC channel 22, and the n-EPI layer 23 are stacked in sequence. A p-type doped region 231 and an n-type doped region 232 are provided on a side of the n-EPI layer 23 away from the SiC channel 22. The second drain 25 and the second source 24 are located on a side of the n-EPI layer 23 away from the SiC channel 22. The second drain 25 is connected to the n-type doped region 232, and the second source 24 is connected to the p-type doped region 231.

[0055] S3. Rotate the GaN HEMT device 1 until the barrier layer 17 is close to the n-EPI layer 23 of the SiC JFET device 2, and then bond the first source 15 and the first drain 16 to the corresponding solder bumps of the second source 24 and the second drain 25, respectively.

[0056] The raw materials not specifically described in the present invention are all existing materials that can be directly purchased from the market.

[0057] The above is only a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A method for preparing an integrated structure of a hybrid heterogeneous integrated circuit, characterized in that: The following steps are involved: S1. Prepare a GaN HEMT device, the GaN HEMT device comprising a first substrate, a buffer layer, a GaN channel, a first gate, a first source, a first drain, and a barrier layer, wherein the first substrate, the buffer layer, the GaN channel, and the barrier layer are stacked in sequence, the first gate is located on a side of the barrier layer away from the GaN channel, one end of the first source and the first drain are located on a side of the barrier layer away from the GaN channel, and the other end is connected to the GaN channel; S2. Prepare a SiC JFET device, wherein the SiC JFET device includes a second substrate, a SiC channel, an n-EPI layer, a second source, and a second drain, wherein the second substrate, the SiC channel, and the n-EPI layer are stacked in sequence, a p-type doped region and an n-type doped region are provided on a side of the n-EPI layer away from the SiC channel, the second drain and the second source are located on a side of the n-EPI layer away from the SiC channel, the second drain is connected to the n-type doped region, and the second source is connected to the p-type doped region; S3. The first drain and the first source of the GaN HEMT device are bonded to the second drain and the second source of the SiC JFET device respectively, to obtain an integrated structure of a hybrid heterogeneous integrated circuit.

2. The method according to claim 1, characterized in that In step S1 , the other ends of the first source and the first drain of the GaN HEMT device are both located on a side of the buffer layer close to the first substrate.

3. The method according to claim 2, characterized in that In step S3, the specific step of bonding connection is to remove the first substrate, and the first source and the first drain are located at the end of the buffer layer close to the first substrate and are bonded to the second source and the second drain of the SiC JFET device respectively.

4. The method according to claim 1, wherein In step S3, the specific steps of bonding are: rotating the GaN HEMT device until the barrier layer is close to the n-EPI layer of the SiC JFET device, and then bonding the first source and the first drain to the second source and the second drain respectively.

5. The method according to claim 4, characterized in that The bonding connection is solder bump bonding or hybrid bonding.

6. The method according to claim 1, characterized in that There are two first source electrodes, and there are two second source electrodes. The two first source electrodes and the two second source electrodes are bonded in a one-to-one correspondence.

7. The method according to claim 6, characterized in that There is one first drain electrode, and two first gate electrodes are sandwiched outside the first drain electrode; there is one second drain electrode, and two second source electrodes are sandwiched outside the second drain electrode.

8. The method according to claim 1, characterized in that The GaN HEMT device further includes a current-carrying layer located on a side of the barrier layer away from the GaN channel.

9. The method according to claim 1, characterized in that The material of the first substrate includes at least one of Si and SiC.

10. An integrated structure of a hybrid heterogeneous integrated circuit, characterized in that: The integrated structure is prepared by the preparation method described in any one of claims 1 to 9.

Images