Semiconductor structure, forming method thereof and transistor

Abstract

Semiconductor structures and methods of forming the same are provided. In an embodiment, an exemplary semiconductor structure includes a first transistor. The first transistor includes: a first gate structure wrapping a plurality of first nanostructures disposed over a substrate; a first source / drain feature electrically coupled to a topmost nanostructure of the plurality of first nanostructures and isolated from a bottommost nanostructure of the plurality of first nanostructures by a first dielectric layer; and a first semiconductor layer disposed between the substrate and the first source / drain feature, where the first source / drain feature is in direct contact with a top surface of the first semiconductor layer. The embodiment of the invention also relates to a semiconductor structure, a forming method thereof and a transistor.

Description

Technical Field

[0001] Embodiments of the present application relate to a semiconductor structure, a method for forming the same, and a transistor. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced multiple generations of ICs, each with smaller and more complex circuits than the previous generation. Over the course of IC development, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component (or line) that can be created using a manufacturing process) has decreased. This shrinking process generally provides benefits by increasing production efficiency and reducing associated costs.

[0003] For example, as integrated circuit (IC) technology moves toward smaller technology nodes, multi-gate devices are introduced to improve gate control by increasing gate-channel coupling, reducing off-state current, and reducing short channel effect (SCE). A multi-gate device generally refers to a device having a gate structure or portion thereof disposed above more than one side of a channel region. Fin field effect transistors (FinFETs) and gate-all-around (GAA) transistors are examples of multi-gate devices, which have become popular and promising candidate devices for high-performance and low-leakage applications. FinFETs have an elevated channel wrapped by a gate on more than one side (e.g., the gate wraps the top and sidewalls of a semiconductor material "fin" extending from a substrate). A gate-all-around (GAA) transistor has a gate structure that can extend partially or completely around a channel region to provide access to a channel region on two or more sides. The channel region of a GAA transistor can be formed by nanowires, nanosheets, other nanostructures, and / or other suitable structures, and a GAA transistor can also be referred to as a nanostructure transistor. Because semiconductor ICs can typically include a variety of different device types with different performance requirements. Therefore, providing multi-gate devices (eg, GAA transistors) that can meet such different device performance requirements remains a challenge.Thus, the prior art has not proven to be completely satisfactory in all respects. Summary of the invention

[0004] Some embodiments of the present application provide a semiconductor structure, including: a first transistor, including: a first gate structure, wrapping a plurality of first nanostructures disposed above a substrate; a first source / drain component, electrically coupled to a topmost nanostructure of the plurality of first nanostructures and isolated from a bottommost nanostructure of the plurality of first nanostructures by a first dielectric layer; and a first semiconductor layer, disposed between the substrate and the first source / drain component, wherein the first source / drain component is in direct contact with a top surface of the first semiconductor layer.

[0005] Other embodiments of the present application provide a transistor, comprising: a gate structure wrapping a plurality of nanostructures disposed above a substrate; an undoped semiconductor layer disposed in and above the substrate, wherein a top surface of the undoped semiconductor layer is coplanar with a top surface of a bottommost nanostructure of the plurality of nanostructures or is disposed above a top surface of the bottommost nanostructure of the plurality of nanostructures; a dielectric layer disposed between the undoped semiconductor layer and the bottommost nanostructure of the plurality of nanostructures; and a source / drain component adjacent to the plurality of nanostructures, wherein a bottom surface of the source / drain component is in direct contact with a top surface of the undoped semiconductor layer.

[0006] Some other embodiments of the present application provide a method for forming a semiconductor structure, comprising: forming a first fin-shaped active region extending from a substrate and comprising a plurality of channel layers interlaced with a plurality of sacrificial layers; forming a first gate stack above a first channel region of the first fin-shaped active region; recessing a first source / drain region of the first fin-shaped active region to form a first source / drain opening; forming a first semiconductor layer in a bottom portion of the first source / drain opening; forming a first dielectric layer extending along a sidewall surface of a middle portion of the first source / drain opening and located on the first semiconductor layer, wherein the entire sidewall surface of a bottommost channel layer of the plurality of channel layers is covered by the first dielectric layer; forming a second semiconductor layer on the first semiconductor layer, wherein a sidewall surface of the second semiconductor layer is in direct contact with the first dielectric layer; forming a first source / drain component on the second semiconductor layer; and replacing the first gate stack and the plurality of sacrificial layers with a gate structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The disclosed embodiments are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are only used for illustration purposes. In fact, the size of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1 A flow chart of a method for forming a semiconductor structure according to one or more aspects of an embodiment of the present disclosure is shown.

[0009] Figure 2 Shows the experience of various aspects according to the embodiments of the present disclosure Figure 1 A partial top view of an exemplary semiconductor structure at various stages of operation in a method of manufacturing the semiconductor device.

[0010] Figure 3A , Figure 4A , Figure 5A , Fig. 6A , Fig. 7A , Fig. 8A, Fig. 9A , Fig. 10A , Fig.11A , Fig. 12A , Fig.13A , Fig.14A , Fig.15A and Fig.16A ( FIG. 3A to FIG. 16A ) shows an example of one or more aspects of an embodiment of the present disclosure. Figure 1 During the various manufacturing stages of the method, Figure 2 A partial cross-sectional view of the semiconductor structure taken along line AA′ shown in FIG.

[0011] Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B , Fig. 9B , Fig. 10B , Fig. 11B , Fig. 12B , Fig. 13B , Fig. 14B , Fig. 15B and Fig. 16B ( FIG. 3B to FIG. 16B ) shows an example of one or more aspects of an embodiment of the present disclosure. Figure 1 During the various manufacturing stages of the method, Figure 2 A local cross-sectional view of the semiconductor structure taken along line BB′ shown in FIG.

[0012] Figure 3C , Figure 4C , Figure 5C , Figure 6C , Figure 7C , Figure 8C , Fig. 9C , Fig. 10C , Fig. 11C , Fig. 12C , Fig. 13C , Fig. 14C , Fig. 15C and Fig. 16C ( Figures 3C to 16C ) shows an example of one or more aspects of an embodiment of the present disclosure. Figure 1 During the various manufacturing stages of the method, Figure 2 A local cross-sectional view of the semiconductor structure taken along line CC' shown in FIG.

[0013] Figure 3D , Figure 4D , Figure 5D , Fig.6D , Fig.7D , Fig.8D , Fig.9D , Fig. 10D , Fig.11D , Fig.12D , Fig.13D , Fig.14D , Fig.15D and Fig.16D ( Figures 3D to 16D ) shows an example of one or more aspects of an embodiment of the present disclosure. Figure 1 During the various manufacturing stages of the method, Figure 2 A local cross-sectional view of the semiconductor structure taken along line DD′ shown in FIG.

[0014] Figure 3E , Figure 4E , Fig.11E , Fig.14E and Fig.16E According to one or more aspects of the present disclosure, Figure 1 During the various manufacturing stages of the method, Figure 2 A local cross-sectional view of the semiconductor structure taken along line EE′ shown in FIG.

[0015] Figure 3F , Figure 4F , Fig.11F , Fig.14F and Fig.16F According to one or more aspects of the present disclosure, Figure 1 During the various manufacturing stages of the method, Figure 2 A local cross-sectional view of the semiconductor structure taken along line FF′ shown in FIG.

[0016] Figure 3G , Figure 4G , Fig.11G , Figure 14G and Figure 16G According to one or more aspects of the present disclosure, Figure 1 During the various manufacturing stages of the method, Figure 2 A local cross-sectional view of the semiconductor structure taken along line GG' shown in FIG.

[0017] Figure 3H , Figure 4H , Fig.11H , Fig.14H and Fig.16H According to one or more aspects of the present disclosure, Figure 1 During the various manufacturing stages of the method, Figure 2 A local cross-sectional view of the semiconductor structure taken along line HH′ shown in FIG.

[0018] Fig.17 A flow chart of a first alternative method for forming a semiconductor structure according to one or more aspects of the embodiments of the present disclosure is shown.

[0019] Fig.18A , Fig.19A , Fig. 20A , Fig.21A and Fig.22A ( FIG. 18A to FIG. 22A ) shows an example of one or more aspects of an embodiment of the present disclosure. Fig.17 During the various manufacturing stages of the method, Figure 2 A partial cross-sectional view of the semiconductor structure taken along line AA′ shown in FIG.

[0020] Fig.18B , Fig.19B , Fig. 20B , Fig.21B and Fig. 22B ( FIG. 18B to FIG. 22B ) shows an example of one or more aspects of an embodiment of the present disclosure. Fig.17 During the various manufacturing stages of the method, Figure 2 A local cross-sectional view of the semiconductor structure taken along line BB′ shown in FIG.

[0021] Fig. 18C , Fig.19C , Fig. 20C , Fig. 21C and Fig. 22C ( FIG. 18C to FIG. 22C ) shows an example of one or more aspects of an embodiment of the present disclosure. Fig.17 During the various manufacturing stages of the method, Figure 2 A local cross-sectional view of the semiconductor structure taken along line CC' shown in FIG.

[0022] Fig.18D , Fig.19D , Fig.20D , Fig.21D and Fig.22D ( FIG. 18D to FIG. 22D ) shows an example of one or more aspects of an embodiment of the present disclosure. Fig.17 In the first alternative method, the various manufacturing stages are performed along the Figure 2 A local cross-sectional view of the semiconductor structure taken along line DD′ shown in FIG.

[0023] Fig.23A , Fig. 23B , Fig.23C , Fig.23D According to one or more aspects of the embodiments of the present disclosure, Fig.17 In the first alternative method, the various manufacturing stages are performed along the Figure 2 Optional partial cross-sectional views of the semiconductor structure taken along lines AA′, BB′, CC′, and DD′ shown in FIG.

[0024] Fig.24A, Fig. 24B , Fig.24C , Fig.24D , Fig.24E , Fig.24F , Figure 24G and Fig.24H According to one or more aspects of the embodiments of the present disclosure, Fig.17 In the first alternative method, the various manufacturing stages are performed along the Figure 2 Optional partial cross-sectional views of the semiconductor structure taken along lines AA', BB', CC', DD', EE', FF', GG', and HH' shown in FIG.

[0025] Fig.25 A flow chart of a second alternative method for forming a semiconductor structure according to one or more aspects of the embodiments of the present disclosure is shown.

[0026] Fig.26A and Fig.27A , Fig.26B and Fig.27B , Fig.26C and Fig.27C , Fig.26D and Fig.27D According to one or more aspects of the embodiments of the present disclosure, Fig.25 In the second alternative method, the various manufacturing stages are performed along the Figure 2 A partial cross-sectional view of the semiconductor structure taken along lines AA′, BB′, CC′, and DD′ shown in FIG.

[0027] Fig.28A , Fig.28B , Fig.28C , Fig.28D According to one or more aspects of the embodiments of the present disclosure, Fig.25 In the second alternative method, the various manufacturing stages are performed along the Figure 2 Optional partial cross-sectional views of the semiconductor structure taken along lines AA′, BB′, CC′, and DD′ shown in FIG.

[0028] Fig.29A , Fig.29B , Fig.29C , Fig.29D , Fig.29E , Fig.29F , Figure 29G and Fig.29H According to one or more aspects of the embodiments of the present disclosure, Fig.25 In the second alternative method, the various manufacturing stages are performed along the Figure 2Optional partial cross-sectional views of the semiconductor structure taken along lines AA', BB', CC', DD', EE', FF', GG', and HH' shown in FIG. DETAILED DESCRIPTION

[0029] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the disclosed embodiments. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the disclosed embodiments may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0030] For ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0031] In addition, when "about," "approximately," etc. are used to describe a value or a range of values, as understood by one of ordinary skill in the art, the terms are intended to encompass values ​​within a reasonable range that takes into account variations that inherently occur during manufacturing. For example, based on known manufacturing tolerances associated with manufacturing components having properties associated with the value, a value or range of values ​​encompasses a reasonable range that includes the described value, such as within + / - 10% of the described value. For example, a material layer having a thickness of "about 5 nm" may include a size range from 4.25 nm to 5.75 nm, where the manufacturing tolerance associated with depositing material layers known to one of ordinary skill in the art is + / - 15%.

[0032] GAA transistors have a wide range of applications. In some implementations (e.g., low-power devices), GAA transistors can be designed to provide low leakage current to reduce power consumption, while in some other implementations (e.g., high-performance devices), GAA transistors can be designed to have high drive current and high speed. eff) tend to have higher performance in terms of switching speed and on-state current. eff ) tend to have lower power consumption. For example, a logic hybrid cell may include high-performance transistors and low-power transistors. Manufacturing GAA transistors to meet different application requirements may involve complex processes associated with high costs. In addition, forming a p-type GAA transistor with satisfactory strain performance while providing low leakage current remains a challenge.

[0033] The disclosed embodiments provide a hybrid nanostructure scheme, which can form a semiconductor structure having a high-speed GAA transistor and a low-power GAA transistor by configuring different numbers of effective channel layers coupled to corresponding source / drain components. In an embodiment, a low-power GAA transistor may have a smaller number of channel layers coupled to its corresponding n-type / p-type source / drain components; and a high-speed GAA transistor may have a larger number of channel layers coupled to its corresponding n-type / p-type source / drain components. The lower-power GAA transistor includes a vertical sidewall dielectric layer that provides isolation between the source / drain component and, for example, the bottommost channel layer in the channel region. By implementing this hybrid nanostructure scheme, GAA transistors with different electrical characteristics can be formed on the same substrate. In addition, forming such a vertical sidewall dielectric layer to provide isolation can allow the p-type source / drain component of the p-type lower-power GAA transistor to grow epitaxially from the bottom to the top, and thus maintain satisfactory strain performance.

[0034] Various aspects of the disclosed embodiments will now be described in more detail with reference to the accompanying drawings. Figure 1 1 is a flow chart showing a method 100 for forming a semiconductor structure according to an embodiment of the present disclosure. Figure 2 and FIG. 3A to FIG. 16H Describing method 100, Figure 2 and FIG. 3A to FIG. 16H are partial top view / cross-sectional views of a semiconductor structure 200 at various stages of fabrication according to an embodiment of the method 100 . Fig.17 3 is a flow chart showing a method 300 for forming a semiconductor structure according to an embodiment of the present disclosure. Figure 2 and FIG. 18A to FIG. 24H Describing method 300, Figure 2 and FIG. 18A to FIG. 24H are partial top view / cross-sectional views of a semiconductor structure 400 / 400 ′ at various stages of fabrication according to an embodiment of the method 300 . Fig.25 5 is a flow chart showing a method 500 for forming a semiconductor structure according to an embodiment of the present disclosure. Figure 2 and FIG. 26A to FIG. 29H Describing method 500, Figure 2 and FIG. 26A to FIG. 29Hare partial top view / cross-sectional views of a semiconductor structure 600 / 600 ′ at various stages of fabrication according to an embodiment of the method 500 .

[0035] Methods 100 / 300 / 500 are merely examples and are not intended to limit the disclosed embodiments to those explicitly shown therein. Additional steps may be provided before, during, and after methods 100 / 300 / 500, and some of the steps described may be replaced, eliminated, or moved around for additional embodiments of the methods. For the sake of simplicity, not all steps are described in detail herein. For the avoidance of doubt, Figures 2 to 16H , FIG. 18A to FIG. 24H and FIG. 26A to FIG. 29H The X, Y, and Z directions in the EMBODIMENT 1 are perpendicular to each other and are used consistently throughout the embodiments of the present disclosure. Throughout the embodiments of the present disclosure, the same reference numerals represent the same components unless otherwise specified.

[0036] refer to Figure 1 , Figure 2 and 3A to 3H The method 100 includes block 102 , where a semiconductor structure 200 including a first region 10 and a second region 20 is received. Figure 2 Describes the experience of various aspects according to the embodiments of the present disclosure Figure 1 FIG. 1 is a partial top view of a semiconductor structure 200 at various stages of operation in the method 100 . Figure 3A , Figure 3B , Figure 3C , Figure 3D , Figure 3E , Figure 3F , Figure 3G and Figure 3H They are shown along Figure 2 2 is a partial cross-sectional view of the semiconductor structure 200 taken along lines AA′, BB′, CC′, DD′, EE′, FF′, GG′, and HH′ shown in FIG.

[0037] like 3A to 3HAs shown in , the semiconductor structure 200 includes a substrate 202. The substrate 202 can be: an elemental (single element) semiconductor, such as silicon (Si) or germanium (Ge) in a crystal structure; a compound semiconductor, such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and / or indium antimonide (InSb); an alloy semiconductor, such as silicon germanium (SiGe), gallium arsenic phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and / or gallium indium arsenide phosphide (GaInAsP); a non-semiconductor material, such as soda lime glass, fused silica, fused quartz, and / or calcium fluoride (CaF2); and / or combinations thereof. In one embodiment, the substrate 202 is a silicon (Si) substrate. The substrate 202 may be uniform in composition or may include various layers, some of which may be selectively etched to form fin-shaped active regions (e.g., fin-shaped active regions 204a-204b). The layers may have similar or different compositions, and in various embodiments, some substrate layers have non-uniform compositions to induce device strain and thereby adjust device performance. Examples of layered substrates include silicon-on-insulator (SOI) substrates 202. In some such instances, the layers of the substrate 202 may include insulators such as semiconductor oxides, semiconductor nitrides, semiconductor oxynitrides, semiconductor carbides, and / or other suitable insulator materials. Doped regions such as wells may be formed in the substrate 202. In Figure 2In the embodiment shown in , the portion of the substrate 202 located in the first region 10 is doped with a p-type dopant and can be referred to as a p-type well (not shown), and the portion of the substrate 202 located in the second region 20 is doped with an n-type dopant and can be referred to as an n-type well (not shown). The p-type dopant can include boron (B), boron difluoride (BF2), or indium (In). The n-type dopant can include phosphorus (P) or arsenic (As). The n-type well and the p-type well can be formed using ion implantation or thermal diffusion and can be considered to be part of the substrate 202. As will be further described below, the first region 10 is an n-type field effect transistor (NFET) region for forming an NFET with a different number of nanostructures, and the second region 20 is a p-type field effect transistor (PFET) region for forming a PFET with a different number of nanostructures. In the embodiment of the present disclosure, a high-speed n-type device and a high-speed p-type device will be formed in the first n-type device region 200N3 and the first p-type device region 200P3, respectively; a low-power n-type device and a low-power p-type device will be formed in the second n-type device region 200N2 and the second p-type device region 200P2, respectively. As will be described below, the source / drain components of the GAA transistor formed in the second n-type device region 200N2 / the second p-type device region 200P2 will be coupled to a smaller number of channel layers (i.e., nanostructures) than the source / drain components of the GAA transistor formed in the first n-type device region 200N3 / the first p-type device region 200P3.

[0038] Still reference Figure 2 and 3A to 3H The semiconductor structure 200 includes a plurality of fin-shaped active regions (eg, fin-shaped active regions 204a, 204b) protruding from the substrate 202. In the present embodiment, the first region 10 includes the fin-shaped active region 204a, and the second region 20 includes the fin-shaped active region 204b. Figure 2 The number of fin-shaped active regions depicted in FIG. 2 is merely an example, and the semiconductor structure 200 may include any suitable number of active regions. Each of the fin-shaped active regions 204a-204b may be formed by a top portion 202t ( Figure 3E ) and a vertical stack 207 (shown in FIG. 207 ) of alternating semiconductor layers disposed on a top surface of the substrate 202 Figure 3E) is formed. In an embodiment, the vertical stack 207 includes a plurality of channel layers (e.g., channel layers 208b, 208m, 208t) interlaced with a plurality of sacrificial layers 206. The channel layers 208b, 208m, 208t may be referred to individually or collectively as channel layers 208. Each of the channel layers 208 may include a semiconductor material such as silicon, germanium, silicon carbide, silicon germanium, GeSn, SiGeSn, SiGeCSn, other suitable semiconductor materials, or combinations thereof, and each sacrificial layer 206 has a composition different from that of the channel layer 208. In an embodiment, the channel layer 208 includes silicon (Si) and the sacrificial layer 206 includes silicon germanium (SiGe). Although the vertical stack 207 of the depicted example includes three channel layers 208b, 208m, 208t and three sacrificial layers 206, it should be understood that the vertical stack 207 may include any suitable number (e.g., 2 to 10) of channel layers and any suitable number of sacrificial layers. The vertical stack 207 and the top portion 202t of the substrate 202 are then patterned to form fin-shaped active regions 204a-204b. In some embodiments, the patterned top portion 202t of the substrate 202 may be referred to as a mesa structure 202t. Each of the fin-shaped active regions 204a-204b extends longitudinally along the X direction and is divided into a channel region 204C that overlaps with a dummy gate stack 210 (described below) and a source / drain region 204SD that does not overlap with the dummy gate stack 210. The source / drain region 204SD may refer to a source region or a drain region, either individually or collectively depending on the context. Each of the channel regions 204C is disposed between two source / drain regions 204SD along the X direction. In an embodiment, each of the fin-shaped active regions 204a-204b has a uniform width (e.g., width W1).

[0039] The semiconductor structure 200 also includes an isolation feature 205 ( FIG. 3E to FIG. 3H ) to isolate one fin-shaped active region from an adjacent fin-shaped active region. The isolation feature 205 may include a shallow trench isolation (STI) feature 205, and may include silicon oxide, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectrics, combinations thereof, and / or other suitable materials.

[0040] The semiconductor structure 200 also includes a dummy gate stack 210. Each of the dummy gate stacks 210 includes a dummy gate dielectric layer 210a, a dummy gate electrode layer 210b above the dummy gate dielectric layer 210a, and a gate top hard mask layer 210c above the dummy gate electrode layer 210b. The dummy gate dielectric layer 210a may include silicon oxide. The dummy gate electrode layer 210b may include polysilicon. The gate top hard mask layer 210c may include silicon oxide, silicon nitride and / or other suitable materials. The dummy gate stack 210 may be formed using suitable deposition processes, photolithography and etching processes. In this embodiment, a gate replacement process (or a gate-last process) is used, in which the dummy gate stack 210 is used as a gate for a functional gate structure (e.g., FIG. 15A to FIG. 15D 242) is a placeholder for the gate structure 242 shown in FIG. Other processes and configurations are also possible. Figure 2 Four dummy gate stacks 210 are shown in FIG. 2 , but the semiconductor structure 200 may include any suitable number of dummy gate stacks 210 .

[0041] The semiconductor structure 200 also includes a gate spacer layer 212 above the substrate 202. The gate spacer layer 212 can be a single layer structure or a multilayer structure. In an exemplary process, a first spacer layer (not separately labeled) is conformally deposited above the semiconductor structure 200, and a second spacer layer (not separately labeled) is conformally deposited above the first spacer layer. The first spacer layer and the second spacer layer can be conformally deposited by atomic layer deposition (ALD), chemical vapor deposition (CVD), or any other suitable deposition process. The term "conformal" can be used herein to facilitate describing a layer having a substantially uniform thickness above various regions of the semiconductor structure 200. The first spacer layer may include silicon oxide, silicon nitride, silicon oxycarbide, silicon oxycarbonitride, silicon carbonitride, metal nitride, or other suitable dielectric material. The second spacer layer may include silicon oxide, silicon nitride, silicon oxycarbide, silicon oxycarbonitride, silicon carbonitride, metal nitride, or other suitable dielectric material. The composition of the first spacer layer is different from the composition of the second spacer layer. In an embodiment, the second spacer layer includes silicon nitride (SiN).

[0042] refer to Figure 1 and 4A to 4H The method 100 includes a block 104 in which the source / drain regions 204SD of the fin-shaped active regions 204a-204b are recessed to form source / drain openings 214. An etching process is performed to remove a portion of the gate spacer layer 212 located above the top-facing surface of the semiconductor structure 200 to form gate spacers 212a extending along sidewalls of the dummy gate stack 210 and fin sidewall spacers 212b extending along lower portions of the sidewalls of the fin-shaped active regions 204a-204b. FIG. 4E to FIG. 4H ).

[0043] In some embodiments, the source / drain regions 204SD of the fin-shaped active regions 204a-204b are anisotropically etched by plasma etching with a suitable etchant, such as a fluorine-containing etchant, an oxygen-containing etchant, a hydrogen-containing etchant, a fluorine-containing etchant (e.g., CF4, SF6, CH2F2, CHF3, and / or C2F6), a chlorine-containing etchant (e.g., Cl2, CHCl3, CCl4, and / or BCl3), a bromine-containing etchant (e.g., HBr and / or CHBr3), an iodine-containing etchant, other suitable etchants, and / or combinations thereof. In the present embodiment, the source / drain openings 214 extend into the top portion 202t of the substrate 202.

[0044] refer to Figure 1 and FIG. 5A to FIG. 5D , the method 100 includes a block 106, in which an internal spacer component (e.g., internal spacer components 216b, 216m, 216t) is formed. After forming the source / drain openings 214, the sacrificial layer 206 exposed in the source / drain openings 214 is selectively and partially recessed to form an internal spacer groove (filled by the internal spacer component), while the exposed channel layer 208 is substantially not etched. In some embodiments, the selective recessing may include a selective isotropic etching process (e.g., a selective dry etching process or a selective wet etching process), and the extent to which the sacrificial layer 206 is recessed is controlled by the duration of the etching process. After forming the internal spacer groove, an internal spacer material layer is then conformally deposited over the semiconductor structure 200 (including over and in the internal spacer groove) using CVD or ALD. The internal spacer material may include silicon nitride, silicon oxycarbonitride, silicon carbonitride, silicon oxide, silicon oxycarbon, silicon carbide, or silicon oxynitride. The inner spacer material layer is then etched back to form inner spacer features (eg, inner spacer features 216b, 216m, and 216t), as shown in FIG. FIG. 5A to FIG. 5D . In some embodiments, the composition of the inner spacer material layer is different from the composition of the gate spacer 212a and the fin sidewall spacer 212b, so that the etching back of the inner spacer material layer does not substantially etch the gate spacer 212a and the fin sidewall spacer 212b. In the illustrated embodiment, the bottommost inner spacer component 216b is disposed between the substrate 202 and the bottommost channel layer 208b, the middle inner spacer component 216m is disposed between the bottommost channel layer 208b and the middle channel layer 208m, and the topmost inner spacer component 216t is disposed between the middle channel layer 208m and the topmost channel layer 208t. The inner spacer components 216b, 216m, and 216t may be individually or collectively referred to as inner spacer components 216. It should be understood that the number of inner spacer components 216 is a function of the number of sacrificial layers, and the semiconductor structure 200 may include any suitable number of inner spacer components.

[0045] Reference now Figure 1 and FIG. 6A to FIG. 6D , the method 100 includes a frame 108, in which a first semiconductor layer 218 is formed in the source / drain opening 214. In the present embodiment, after forming the internal spacer member 216, the first semiconductor layer 218 is formed in the source / drain opening 214 by, for example, using an epitaxial process. Each of the first semiconductor layers 218 can be undoped or not intentionally doped. In some embodiments, the first semiconductor layer 218 can include undoped silicon (Si), undoped germanium (Ge), undoped silicon germanium (SiGe), or other suitable materials. In an embodiment, the first semiconductor layer 218 in the device regions 200N3, 200N2, 200P3, and 200P2 is formed simultaneously by a common epitaxial process and includes undoped silicon (Si).

[0046] Reference now Figure 1 and FIG. 7A to FIG. 7D , method 100 includes frame 110, in which a first dielectric layer 220 is conformally deposited over the semiconductor structure 200. The first dielectric layer 220 may include silicon nitride, silicon carbon nitride, silicon oxycarbide, silicon oxycarbonitride, other suitable materials, or combinations thereof. In the present embodiment, the first dielectric layer 220 is conformally deposited over the semiconductor structure 200 (including in the source / drain openings 214) by any suitable method (such as CVD, ALD, physical vapor deposition (PVD), other suitable methods, or combinations thereof). The term "conformal" may be used herein to facilitate describing a layer having a substantially uniform thickness over various regions of the semiconductor structure 200. The first dielectric layer 220 has a deposition thickness T1. As FIG. 7A to FIG. 7D , the first dielectric layer 220 partially fills the source / drain openings 214. For ease of description, the portion of the first dielectric layer 220 that is in direct contact with the first semiconductor layer 218 but not in direct contact with the inner spacer component 216 or the channel layer 208 is referred to as a horizontal portion 220b; the portion of the first dielectric layer 220 that is in direct contact with the inner spacer component 216, the channel layer 208, and the gate spacer 212a is referred to as a vertical portion 220a; and the portion of the first dielectric layer 220 formed above the dummy gate stack 210 is referred to as a top portion 220t.

[0047] Reference now Figure 1 and FIG. 8A to FIG. 8D, the method 100 includes a block 112, in which a patterned mask layer 222 is formed over the semiconductor structure 200. The patterned mask layer 222 may include a patterned photoresist layer or a combination of a patterned hard mask layer and a patterned photoresist layer formed on the patterned hard mask layer. In an exemplary process, a photoresist layer is deposited over the semiconductor structure 200 using spin coating or a suitable process. The photoresist layer is patterned using a photolithography process to form the patterned mask layer 222. In the present embodiment, the patterned mask layer 222 has a first opening 222a ( 222b ) exposing a horizontal portion 220b of the first dielectric layer 220 in the second n-type device region 200N2. Figure 8B ) and a second opening 222b (shown in FIG. 200B ) exposing a horizontal portion 220b of the first dielectric layer 220 in the second p-type device region 200P2. Fig.8D The patterned mask layer 222 covers other portions of the first dielectric layer 220 in the semiconductor structure 200 (eg, portions of the first dielectric layer 220 formed in the first n-type device region 200N3 and the first p-type device region 200P3 ).

[0048] Reference now Figure 1 and 9A to 9D , the method 100 includes a block 114, in which a first etching process 224 is performed to etch the first dielectric layer 220. When the patterned mask layer 222 is used as an etching mask, the first etching process 224 is performed to etch the first dielectric layer 220 to remove the horizontal portion 220b of the first dielectric layer 220 exposed by the first opening 222a and the horizontal portion 220b of the first dielectric layer 220 exposed by the second opening 222b. In an embodiment, the first etching process 224 is an anisotropic etching process. After performing the first etching process 224, the patterned mask layer 222 may be selectively removed. 9A to 9D, performing the first etching process 224 removes the horizontal portion 220b of the first dielectric layer 220 in the second n-type device region 200N2 and the horizontal portion 220b of the first dielectric layer 220 in the second p-type device region 200P2. Therefore, in the second n-type device region 200N2 and the second p-type device region 200P2, the portion of the top surface of the first semiconductor layer 218 covered by the horizontal portion 220b of the first dielectric layer 220 is now exposed in the source / drain opening 214. The top surface of the first semiconductor layer 218 in the first n-type device region 200N3 and the first p-type device region 200P3 is still covered by the first dielectric layer 220. In some embodiments, performing the first etching process 224 may also reduce the thickness of the vertical portion 220a of the first dielectric layer 220 in the second n-type device region 200N2 and the second p-type device region 200P2. After performing the first etching process 224, the vertical portion 220a of the first dielectric layer 220 in the second n-type device region 200N2 and the second p-type device region 200P2 has a thickness T2 ( T2 ) less than the deposition thickness T1. Fig. 9B In some embodiments, the thickness T2 is in a range between about 1 nm and 4 nm. It should be noted that the vertical portion 220a in the second n-type device region 200N2 and the second p-type device region 200P2 is still in direct contact with a portion of the top surface of the first semiconductor layer 218.

[0049] Reference now Figure 1 and FIG. 10A to FIG. 10D, the method 100 includes a block 116, in which a second semiconductor layer 226 is formed on the first semiconductor layer 218 in the second n-type device region 200N2 and the second p-type device region 200P2. After partially exposing the top surface of the first semiconductor layer 218 in the second n-type device region 200N2 and the second p-type device region 200P2, the second semiconductor layer 226 is formed on the first semiconductor layer 218. In an embodiment, the second semiconductor layer 226 is formed using an epitaxial growth process, and is thus selectively formed from the bottom up (i.e., along the Z direction) on the first semiconductor layer 218 in the second n-type device region 200N2 and the second p-type device region 200P2, without growing in the first n-type device region 200N3 and the first p-type device region 200P3. Each of the second semiconductor layers 226 may be undoped or not intentionally doped. In some embodiments, the second semiconductor layer 226 may include undoped silicon (Si), undoped germanium (Ge), undoped silicon germanium (SiGe), or other suitable materials. In an embodiment, the second semiconductor layer 226 in the second n-type device region 200N2 and the second p-type device region 200P2 is formed simultaneously and includes undoped silicon (Si). In this embodiment, the top surface 226ts of the second semiconductor layer 226 is at least coplanar with the bottom surface of the middle inner spacer component 216m, and is located below the top surface of the middle inner spacer component 216m or coplanar with the top surface of the middle inner spacer component 216m. For ease of description, in the second n-type device region 200N2 and the second p-type device region 200P2, the portion of the vertical portion 220a that is in direct contact with the second semiconductor layer 226 is referred to as the lower portion 220a1 of the first dielectric layer 220, and the portion of the vertical portion 220a that is not in direct contact with the second semiconductor layer 226 is referred to as the upper portion 220au of the first dielectric layer 220. Fig. 10B and Fig. 10D As depicted in FIG. 2 , upper portions 220 au of the first dielectric layer 220 in the second n-type device region 200N2 and the second p-type device region 200P2 are exposed in the source / drain openings 214 .

[0050] Reference now Figure 1 and FIG. 11A to FIG. 11H, the method 100 includes a block 118, wherein a second etching process 228 is performed to isotropically etch the first dielectric layer 220. After forming the second semiconductor layer 226 in the second n-type device region 200N2 and the second p-type device region 200P2, the second etching process 228 is applied to the semiconductor structure 200. In an embodiment, the second etching process 228 is an isotropic etching process. The second etching process 228 is performed to remove the portion of the first dielectric layer 220 that is not covered / protected by the second semiconductor layer 226, so that the lower portion 220a1 of the first dielectric layer 220 surrounds the second semiconductor layer 226 in the second n-type device region 200N2 and the second p-type device region 200P2. After the second etching process 228 is performed, the lower portion 220a1 of the first dielectric layer 220 can be referred to as a sidewall dielectric layer 220a1. As depicted herein, the sidewall dielectric layer 220a1 provides isolation between the bottommost channel layer 208b and the second semiconductor layer 226. In this embodiment, in order to reduce the number of channel layers electrically coupled to the source / drain features in the second n-type device region 200N2 and the second p-type device region 200P2, the top surface of the sidewall dielectric layer 220al is located above or coplanar with the bottom surface of the middle inner spacer feature 216m, and is located below or coplanar with the top surface of the middle inner spacer feature 216m. The height H1 of the sidewall dielectric layer 220al can be in the range between about 10nm and about 20nm. In this embodiment, the second etching process 228 selectively etches the first dielectric layer 220 without removing or substantially removing portions of the second semiconductor layer 226 and the channel layer 208. As shown in FIG. Fig.11A , Fig. 11C , Fig.11E and Fig.11G As shown in FIG. 2 , after the second etching process 228 is performed, the top surface of the first semiconductor layer 218 in the first n-type device region 200N3 and the first p-type device region 200P3 is exposed in the source / drain opening 214 .

[0051] Reference now Figure 1 and FIG. 12A to FIG. 12D , the method 100 includes block 120, in which p-type source / drain features 232a and 232b are formed in the source / drain openings 214 in the first p-type device region 200P3 and the second p-type device region 200P2, respectively. The source / drain features may be referred to as sources or drains, individually or collectively depending on the context. After etching the first dielectric layer 220 to form sidewall dielectric layers 220a1 in the second n-type device region 200N2 and the second p-type device region 200P2 and exposing the top surface of the first semiconductor layer 218 in the first n-type device region 200N3 and the first p-type device region 200P3, as shown in FIG. FIG. 12A to FIG. 12DAs depicted in FIG. 1 , a patterned mask layer 230 is formed over the semiconductor structure 200. The patterned mask layer 230 covers the first n-type device region 200N3 and the second n-type device region 200N2, but does not cover the first p-type device region 200P3 and the second p-type device region 200P2. An epitaxial growth process, such as vapor phase epitaxy (VPE), ultra-high vacuum chemical vapor deposition (UHV-CVD), molecular beam epitaxy (MBE), and / or other suitable processes, is then performed to form p-type source / drain features 232a and 232b in the first p-type device region 200P3 and the second p-type device region 200P2, respectively. Because the first semiconductor layer 218 is exposed by the source / drain opening 214 in the first p-type device region 200P3, and the second semiconductor layer 226 is exposed by the source / drain opening 214 in the second p-type device region 200P2, the p-type source / drain components 232a and 232b are allowed to grow from the bottom up (i.e., along the Z direction) to provide satisfactory strain performance. Exemplary p-type source / drain components 232a and 232b may include germanium, gallium-doped silicon germanium, boron-doped silicon germanium, or other suitable materials, and may be in-situ doped by introducing a P-type dopant (such as boron or gallium) during the epitaxial process, or ex-situ doped using a junction implantation process. In some embodiments, each of the p-type source / drain components 232a and 232b may include multiple semiconductor layers with different doping concentrations.

[0052] In the first p-type device region 200P3, the p-type source / drain features 232a are coupled to all channel layers (ie, channel layers 208b, 208m, and 208t) of the channel region 204C. Fig. 12C As depicted in the cross-sectional view shown, the entire bottom surface of the p-type source / drain feature 232a is in direct contact with the first semiconductor layer 218, and the p-type source / drain feature 232a is in direct contact with all of the channel layers (i.e., channel layers 208b, 208m, and 208t) and the inner spacer features 216b, 216m, 216t of the channel region 204C.

[0053] In the second p-type device region 200P2, the p-type source / drain feature 232b is coupled to the upper portion of the channel region 204C (eg, the channel layers 208m and 208t) and is isolated from the bottom portion (eg, the bottommost channel layer 208b) by the sidewall dielectric layer 220a1. Fig.12DAs depicted in the cross-sectional view shown, the bottom surface of the p-type source / drain feature 232b is in direct contact with the top surface of the second semiconductor layer 226 and the top surface of the sidewall dielectric layer 220a1. That is, the bottom surface of the p-type source / drain feature 232b is located above the bottom surface of the p-type source / drain feature 232a. In some embodiments, the volume of the p-type source / drain feature 232a can be greater than the volume of the p-type source / drain feature 232b. After forming the p-type source / drain features 232a and 232b, the patterned mask layer 230 can be selectively removed.

[0054] Reference now Figure 1 and FIG. 13A to FIG. 13D , the method 100 includes block 122, in which a second dielectric layer 234 is formed over the semiconductor structure 200. In the present embodiment, the second dielectric layer 234 is formed on a top surface of the first semiconductor layer 218 in the first n-type device region 200N3, on a top surface of the sidewall dielectric layer 220a1 and the second semiconductor layer 226 in the second n-type device region 200N2, on a top surface of the p-type source / drain feature 232a in the first p-type device region 200P3, and on a top surface of the p-type source / drain feature 232b in the second p-type device region 200P2.

[0055] In an exemplary process, to form the second dielectric layer 234, an insulating layer is first deposited over the semiconductor structure 200 using a physical vapor deposition (PVD) process. The insulating layer may include silicon nitride, silicon carbonitride, silicon oxycarbide, silicon oxycarbonitride, combinations thereof, or other suitable materials. Due to the characteristics of the PVD process, a portion of the insulating layer formed on the top or flat surface is thicker than a portion of the insulating layer formed on the sidewall surface. Then, portions of the insulating layer formed on the top surface of the gate spacer 212 a, the top surface of the dummy gate stack 210, and the sidewall surfaces of the components (e.g., the sidewall surfaces of the gate spacer 212 a, the sidewall surfaces of the exposed channel region 204C, and the sidewall surfaces of the inner spacer component 216) are removed by a combination of planarization, deposition, photolithography, and / or etching processes, thereby leaving a bottom portion of the insulating layer in the source / drain openings 214 in the first n-type device region 200N3 and the second n-type device region 200N2 and a bottom portion of the insulating layer on the p-type source / drain components 232 a and 232 b in the first p-type device region 200P3 and the second p-type device region 200P2. The bottom portion of the insulating layer is referred to as a second dielectric layer 234.

[0056] The second dielectric layer 234 in the first n-type device region 200N3 is formed in the source / drain openings 214 and is in direct contact with the first semiconductor layer 218. The bottom surface of the second dielectric layer 234 in the first n-type device region 200N3 is located below or coplanar with the top surface of the bottommost inner spacer feature 216b, so that the n-type source / drain features in the first n-type device region 200N3 will be electrically coupled to all channel layers in the channel region 204C.

[0057] The second dielectric layer 234 in the second n-type device region 200N2 is formed in the source / drain opening 214 and is in direct contact with the sidewall dielectric layer 220a1 and the second semiconductor layer 226. In this present embodiment, the bottom surface of the second dielectric layer 234 in the second n-type device region 200N2 is located below or coplanar with the top surface of the middle inner spacer component 216m. Forming the second dielectric layer 234 in the first n-type device region 200N3 and the second n-type device region 200N2 will substantially inhibit and / or eliminate the formation of the metal gate structure 242 ( FIG. 16A to FIG. 16D ), n-type source / drain features 236a / 236b ( FIG. 14A to FIG. 14B ) and any parasitic transistors between the mesa structures 202t below, thereby reducing and / or blocking leakage current through the mesa structures 202t in the first n-type device region 200N3 and the second n-type device region 200N2. In some embodiments, the second dielectric layer 234 may also be formed on the top surface of the STI feature 205 when viewed from the X direction.

[0058] Reference now Figure 1 and FIG. 14A to FIG. 14H, the method 100 includes a block 124, in which n-type source / drain features 236a and 236b are formed in the source / drain openings 214 in the first n-type device region 200N3 and the second n-type device region 200N2, respectively. The source / drain feature may refer to a source or a drain, either alone or together depending on the context. After forming the second dielectric layer 234, an epitaxial growth process, such as vapor phase epitaxy (VPE), ultra-high vacuum chemical vapor deposition (UHV-CVD), molecular beam epitaxy (MBE), and / or other suitable processes, is then performed to form n-type source / drain features 236a and 236b in the first n-type device region 200N3 and the second n-type device region 200N2, respectively. Exemplary N-type source / drain features 236a and 236b may include silicon, phosphorus-doped silicon, arsenic-doped silicon, antimony-doped silicon, or other suitable materials, and may be in-situ doped by introducing N-type dopants such as phosphorus, arsenic, or antimony during an epitaxial process, or ex-situ doped using a junction implantation process. In some embodiments, each of the n-type source / drain features 236a and 236b may include multiple semiconductor layers having different doping concentrations.

[0059] In the first n-type device region 200N3, the n-type source / drain feature 236a is coupled to and in direct contact with all channel layers (ie, channel layers 208b, 208m, and 208t) of the channel region 204C. Fig.14A As depicted in the cross-sectional view shown, the entire bottom surface of the n-type source / drain feature 236 a is in direct contact with the second dielectric layer 234 .

[0060] In the second n-type device region 200N2, the n-type source / drain feature 236b is coupled to the upper portion of the channel region 204C (e.g., channel layers 208m and 208t) and is isolated from the bottom portion (e.g., the bottommost channel layer 208b) by the sidewall dielectric layer 220a1. Fig. 14B As depicted in the cross-sectional view shown, the entire bottom surface of the n-type source / drain feature 236b is in direct contact with the second dielectric layer 234. Forming the second dielectric layer 234 in the first n-type device region 200N3 and the second n-type device region 200N2 blocks the conductive path between the n-type source / drain features 236a / 236b and the underlying mesa structure 202t. The bottom surface of the n-type source / drain feature 236b is located above the bottom surface of the n-type source / drain feature 236a. In some embodiments, the volume of the n-type source / drain feature 236a can be greater than the volume of the n-type source / drain feature 236b.

[0061] Reference now Figure 1 and FIG. 15A to FIG. 15D, the method 100 includes block 126, in which the dummy gate stack 210 and the sacrificial layer 206 are replaced with a gate structure 242. A contact etch stop layer (CESL) 238 and a first interlayer dielectric (ILD) layer 240 are deposited over the semiconductor structure 200. The CESL 238 may include silicon nitride, silicon oxynitride, and / or other suitable materials, and may be formed by an ALD, a plasma enhanced chemical vapor deposition (PECVD) process, and / or other suitable deposition or oxidation processes. After depositing the CESL 238, the first ILD layer 240 is deposited over the semiconductor structure 200 by a PECVD process or other suitable deposition technique. The first ILD layer 240 may include a material such as tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide, such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silica glass (BSG), and / or other suitable dielectric materials. A planarization process, such as a chemical mechanical polishing (CMP) process, may be performed on the semiconductor structure 200 to remove excess material to expose the top surface of the dummy gate electrode layer 210b in the dummy gate stack 210. A first etching process may be performed to selectively remove the dummy gate electrode layer 210b and the dummy gate dielectric layer 210a of the dummy gate stack 210 without substantially removing the gate spacer 212a to form a gate trench. After removing the dummy gate stack 210, the sacrificial layer 206 in the channel region 204C is selectively removed to release the channel layer 208 as a nanostructure (or channel member) 208. The selective removal of the sacrificial layer 206 forms a gate opening below the gate trench.

[0062] After removing the dummy gate stack 210 and the sacrificial layer 206, a metal gate structure 242 is formed in the gate trench and the gate opening. Forming the metal gate structure 242 includes forming an interface layer to wrap around and over each of the nanostructures 208. The interface layer may include silicon oxide or other suitable materials. The interface layer may be formed using a suitable method, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), thermal oxidation or other suitable methods. In an embodiment, the interface layer is formed by thermal oxidation and is therefore formed only on the surface of the nanostructure 208. That is, the interface layer does not extend along the sidewall surface of the gate spacer 212a, and does not extend along the sidewall surface of the internal spacer component 216. In another embodiment, the interface layer is formed by ALD and is therefore conformally formed on the surface of the semiconductor structure 200. That is, the interface layer also extends along the sidewall surface of the gate spacer 212a and the sidewall surface of the internal spacer component 216. After forming the interface layer, a dielectric layer is formed over the semiconductor structure 200 to wrap around and over each of the nanostructures 208. In an embodiment, a dielectric layer is conformally deposited over the semiconductor structure 200. The term "conformal" is used herein to facilitate describing a layer having a substantially uniform thickness over various regions. In some embodiments, the dielectric layer is a high-k dielectric layer because its dielectric constant is greater than the dielectric constant of silicon dioxide (~3.9). In some embodiments, the dielectric layer may include titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium silicon oxide (HfSiO4), zirconium dioxide (ZrO2), zirconium oxide silicon (ZrSiO2), aluminum oxide (Al2O3), zirconium oxide (ZrO), yttrium oxide (Y2O3), SrTiO3 (STO), BaTiO3 (BTO), BaZrO, aluminum silicon oxide (AlSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), (Ba, Sr)TiO3 (BST), silicon nitride (SiN), silicon oxynitride (SiON), combinations thereof, or other suitable materials. The dielectric layer and the interface layer may be collectively referred to as a gate dielectric layer.

[0063] Forming the metal gate structure 242 also includes forming a gate electrode above the gate dielectric layer. The gate electrode may be a multilayer structure including at least one work function layer and a metal fill layer. For example, at least one work function layer may include titanium nitride (TiN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum aluminum (TaAl), tantalum aluminum nitride (TaAlN), tantalum aluminum carbide (TaAlC), tantalum carbonitride (TaCN) or tantalum carbide (TaC). The metal gate structure 242 formed in the first p-type device region 200P3 and the second p-type device region 200P2 may include at least a p-type work function layer. The p-type work function layer may include titanium nitride (TiN), tungsten carbonitride (WCN), tantalum nitride (TaN) or molybdenum nitride (MoN). The metal gate structure 242 formed in the first n-type device region 200N3 and the second n-type device region 200N2 may include at least an n-type work function layer. The n-type work function layer may include a titanium aluminum-based metal, such as titanium aluminum carbon (TiAlC) or titanium aluminum (TiAl). The metal filling layer may include aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), ruthenium (Ru), cobalt (Co), platinum (Pt), tantalum silicon nitride (TaSiN), copper (Cu), other refractory metals or other suitable metal materials or combinations thereof. In various embodiments, the gate electrode may be formed by ALD, PVD, CVD, electron beam evaporation or other suitable processes. In various embodiments, a planarization process, such as a chemical mechanical polishing (CMP) process, may be implemented to remove excess material above the first ILD layer 240 to provide a substantially flat top surface and facilitate the implementation of further processes.

[0064] Reference now Figure 1 and 16A to 16H, the method 100 includes a block 128, wherein further processes are performed. Such further processes may include forming an etch stop layer 244 and a second ILD layer 246 over the semiconductor structure 200. In terms of composition and formation process, the etch stop layer 244 may be similar to the contact etch stop layer 238, and the second ILD layer 246 may be similar to the first ILD layer 240. The etch stop layer 244 may indicate an etch stop point for forming a gate via opening over the metal gate structure 242. A combination of a photolithography process and an etching process is used to form a source / drain contact opening (now filled with the silicide layer 250 and the source / drain contact 252) to expose the p-type source / drain features 232a-232b and / or the n-type source / drain features 236a-236b. In an exemplary process, a hard mask layer and a photoresist are deposited over the semiconductor structure 200. The photoresist layer is then exposed to patterned radiation transmitted through or reflected from the photomask, baked in a post-exposure bake process, developed in a developer solution, and then rinsed to form a patterned photoresist layer. The patterned photoresist layer is then applied as an etching mask to etch the hard mask layer to form a patterned hard mask layer. The patterned hard mask layer is then applied as an etching mask to etch the second ILD layer 246, the etching stop layer 244, the first ILD layer 240, and the CESL 238 to form source / drain contact openings in the first n-type device region 200N3 and the second n-type device region 200N2. The patterned hard mask layer is also applied as an etching mask to etch the second ILD layer 246, the etching stop layer 244, the first ILD layer 240, the CESL 238, and the second dielectric layer 234 to form source / drain contact openings in the first p-type device region 200P3 and the second p-type device region 200P2. After forming the source / drain contact openings, a silicide layer 250 and a source / drain contact 252 are formed therein. The silicide layer 250 in the first n-type device region 200N3 and the second n-type device region 200N2 may include nickel silicide, titanium silicide, tantalum silicide, cobalt silicide, tungsten silicide or other suitable materials. The silicide layer 250 in the first p-type device region 200P3 and the second p-type device region 200P2 may include nickel silicide, nickel germanium, nickel germanium silicon, titanium silicide, titanium germanium, titanium germanium silicon, tantalum silicide, tantalum germanium, tantalum germanium silicon, cobalt silicide, cobalt germanium, cobalt germanium, tungsten silicide, tungsten germanium and / or tungsten germanium silicon or other suitable materials. Then, a source / drain contact 252 is formed in the source / drain contact openings and on the silicide layer 250. The source / drain contacts 252 may include aluminum (Al), copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru) or molybdenum (Mo) or other suitable materials, and may be formed by any suitable process. Although not shown, in some embodiments, a barrier layer may be formed to extend along the sidewall surface of the source / drain contacts 252.Such further processes may include forming gate vias and interconnect structures above the semiconductor structure 200. In some embodiments, the interconnect structure may include multiple intermetallic dielectric (IMD) layers and multiple metal lines or contact vias in each of the IMD layers. In some instances, the IMD layer and the first ILD layer 240 may share similar compositions. The metal lines and contact vias in each IMD layer may be formed of metals such as aluminum, tungsten, ruthenium or copper. In some embodiments, the metal lines and contact vias may be lined with a barrier layer to insulate the metal lines and contact vias from the IMD layer and prevent electromigration. Such further processes may include forming an interconnect structure below the back side of the semiconductor structure 200.

[0065] In some alternative embodiments, the electrical characteristics of the devices in the semiconductor structure 200 may be further adjusted. For example, the effective width of the nanostructures 208 along the X-direction may be adjusted, for example, to provide improved DC performance. Fig.17 1 is a flow chart showing a method 300 for forming a semiconductor structure 400 / 400' according to one or more aspects of the embodiments of the present disclosure. Fig.17 , method 300 includes blocks 102, 104, 106, and 108. In this embodiment, FIG. 6A to FIG. 6D The semiconductor structure 200 shown in (including the first n-type device region 200N3 and the second n-type device region 200N2 and the first p-type device region 200P3 and the second p-type device region 200P2) can be referred to as a semiconductor structure 400, and the semiconductor structure 400 includes the first n-type device region 400N3 and the second n-type device region 400N2 and the first p-type device region 400P3 and the second p-type device region 400P2.

[0066] refer to Fig.17 and 18A to 18D The method 300 also includes block 310, in which a patterned mask layer 410 is formed to cover the features in the first n-type device region 400N3. The patterned mask layer 410 can be similar to the patterned mask layer 222 or the patterned mask layer 230. 18A to 18D As depicted, the patterned mask layer 410 covers the channel layers (e.g., channel layers 208b, 208m, and 208t) in the first n-type device region 400N3, while the channel layers (e.g., channel layers 208b, 208m, and 208t) in the second n-type device region 400N2, the first p-type device region 400P3, and the second p-type device region 400P2 are exposed.

[0067] refer to Fig.17 and FIG. 19A to FIG. 19D, the method 300 also includes a block 320, in which an etching process 420 is performed to selectively recess the channel layers (e.g., channel layers 208b, 208m, and 208t) in the second n-type device region 200N2, the first p-type device region 200P3, and the second p-type device region 200P2. When the patterned mask layer 410 is used as an etching mask, the etching process 420 is performed to selectively recess the channel layers not covered by the patterned mask layer 410. Therefore, the channel layers (e.g., channel layers 208b, 208m, and 208t) in the second n-type device region 400N2, the first p-type device region 400P3, and the second p-type device region 400P2 are recessed and thus have a width W3 along the X direction that is reduced from the width W2 of the channel layer in the first n-type device region 400N3. The channel layers (e.g., channel layers 208b, 208m, and 208t) are recessed to form openings 430 in the second n-type device region 400N2, the first p-type device region 400P3, and the second p-type device region 400P2. In some embodiments, performing the etching process 420 may also slightly etch the first semiconductor layer 218 in the second n-type device region 400N2, the first p-type device region 400P3, and the second p-type device region 400P2. FIG. 19B to FIG. 19D As depicted in FIG. 4 , the top surfaces of the first semiconductor layer 218 in the second n-type device region 400N2 , the first p-type device region 400P3 , and the second p-type device region 400P2 are bent toward the center. After the etching process 420 is performed, the patterned mask layer 410 may be selectively removed.

[0068] refer to Fig.17 as well as FIG. 20A to FIG. 20D , FIG. 21A to FIG. 21D and FIG. 22A to FIG. 22D , the method 300 also includes blocks 110-128. After recessing the channel layers (e.g., channel layers 208b, 208m, and 208t) in the second n-type device region 400N2, the first p-type device region 400P3, and the second p-type device region 400P2, the operations in blocks 110-128 of the method 100 are performed to form the semiconductor structure 400. For example, with respect to FIG. 20A to FIG. 20D , the first dielectric layer 220 is conformally deposited over the semiconductor structure 400. The first dielectric layer 220 in the semiconductor structure 400 also fills the opening 430. Then, regarding FIG. 21A to FIG. 21D, a second semiconductor layer 226 is formed in the second n-type device region 400N2 and the second p-type device region 400P2, and a portion of the first dielectric layer 220 is removed, thereby leaving a sidewall dielectric layer 220a1 in the second n-type device region 400N2 and the second p-type device region 400P2. The sidewall dielectric layers 220a1 of the semiconductor structure 400 are similar to the sidewall dielectric layers 220a1 of the semiconductor structure 200, wherein one of the differences includes that each of the sidewall dielectric layers 220a1 of the semiconductor structure 400 also includes a portion that fills the opening 430 and is therefore vertically disposed between the bottommost inner spacer component 216b and the middle inner spacer component 216m. Therefore, the sidewall dielectric layer 220a1 has a non-uniform thickness from the bottom to the top. In an embodiment, the top portion and the bottom portion of the sidewall dielectric layer 220al that are in direct contact with the sidewall surface of the internal spacer component have a thickness T2 in the range between about 1nm and about 4nm, and the middle portion of the sidewall dielectric layer 220al that is in direct contact with the bottommost channel layer 208b has a thickness T3 in the range between about 3nm and about 7nm.

[0069] FIG. 22A to FIG. 22D A partial cross-sectional view of the final structure of the semiconductor structure 400 is depicted. The final structure of the semiconductor structure 400 is similar to FIG. 16A to FIG. 16D , and one of the differences between the semiconductor structure 400 and the final structure of the semiconductor structure 200 includes the profile of the sidewall dielectric layer 220a1. As described above, the sidewall dielectric layer 220a1 of the semiconductor structure 400 also includes a portion vertically disposed between the bottommost inner spacer component 216b and the middle inner spacer component 216m. Another difference between the semiconductor structure 400 and the final structure of the semiconductor structure 200 includes different channel widths in the semiconductor structure 400. More specifically, the width W3 ( W32) of the channel layers (e.g., channel layers 208b, 208m, and 208t) in the second n-type device region 400N2, the first p-type device region 400P3, and the second p-type device region 400P2 is greater than or equal to 0. Fig.19B ) is smaller than the width W2 (eg, the width W2 of the channel layers 208b, 208m, and 208t) in the first n-type device region 200N3. Fig.19A ).

[0070] In reference FIG. 21A to FIG. 21D and FIG. 22A to FIG. 22DIn the above described embodiment, the entire sidewall surface of the second semiconductor layer 226 of the semiconductor structure 400 is lined by the sidewall dielectric layer 220a1. The profile of the sidewall dielectric layer 220a1 can be further adjusted by controlling the etching duration of the first etching process 224 performed in block 114. In an alternative embodiment, the first etching process 224 is performed so that the vertical portion 220a of the first dielectric layer 220 extending along the sidewall surface of the inner spacer members 216b, 216m and 216t can be substantially removed, leaving the portion of the first dielectric layer 220 formed in the opening 430. FIG. 23A to FIG. 23D As depicted, the sidewall surfaces of the second semiconductor layer 226 of the semiconductor structure 400' are in direct contact with the sidewall dielectric layer 220al, the bottommost internal spacer component 216b, and the internal spacer components (e.g., the middle internal spacer component 216m in the illustrated example) disposed directly above the bottommost internal spacer component 216b. FIG. 24A to FIG. 24H A partial cross-sectional view of the final structure of the semiconductor structure 400 ′ is depicted. FIG. 24A to FIG. 24D The final structure of the semiconductor structure 400' depicted in FIG. FIG. 22A to FIG. 22D The semiconductor structure 400 depicted in FIG. 4 , one of the differences between these semiconductor structures 400′ and 400 includes the profile of the sidewall dielectric layer 220al and the relative positional relationship between the sidewall dielectric layer 220al and its surrounding components, such as Fig. 24B and Fig.24D shown. FIG. 24E to FIG. 24H A cross-sectional view of an alternative final structure of semiconductor structure 400' is depicted when viewed from the X direction. FIG. 24E to FIG. 24H In the illustrated embodiment, when viewed from the X direction, the entire sidewall surface of the second semiconductor layer 226 is in direct contact with the fin sidewall spacer 212 b .

[0071] In reference Figures 17 to 24H In the above described embodiments, the operations in blocks 310 and 320 of method 300 (eg, FIG. 19A to FIG. 19D The etching process 420 shown in FIG. 4 is performed after performing the operation in block 108 (e.g., forming the first semiconductor layer 218) and before performing the operation in block 110 (e.g., depositing the first dielectric layer 220). In some optional embodiments, the operations in blocks 310 and 320 are performed after performing the operation in block 118 to form another optional semiconductor structure 600 / 600'. Fig.25 A flow chart of a method 500 for forming an alternative semiconductor structure 600 / 600' according to one or more aspects of the embodiments of the present disclosure is shown. Fig.25 and FIG. 11A to FIG. 11H, method 500 includes blocks 102, 104, 106, 108, 110, 112, 114, 116, and 118. In this embodiment, after the operation in block 118 is performed, for ease of description, FIG. 11A to FIG. 11H The semiconductor structure 200 shown in FIG. 2 may be referred to as a semiconductor structure 600, and the semiconductor structure 600 includes a first n-type device region 600N3 and a second n-type device region 600N2 and a first p-type device region 600P3 and a second p-type device region 600P2. FIG. 11A to FIG. 11H As shown, the semiconductor structure 600 includes a sidewall dielectric layer 220a1 formed in the second n-type device region 600N2 and the second p-type device region 600P2. Figures 1 to 11H A detailed description of the sidewall dielectric layer 220a1 is described, and for the sake of simplicity, a repeated description is omitted.

[0072] refer to Fig.25 and FIG. 26A to FIG. 26D The method 500 also includes block 310, in which a patterned mask layer 410 is formed to cover the features in the first n-type device region 600N3. The patterned mask layer 410 may be similar to the patterned mask layer 222 or the patterned mask layer 230. 18A to 18D As depicted in FIG. 4 , all channel layers (e.g., channel layers 208 b, 208 m, and 208 t) in the first n-type device region 600N3 are covered by the patterned mask layer 410. All channel layers (e.g., channel layers 208 b, 208 m, and 208 t) in the first p-type device region 600P3, channel layers (e.g., channel layers 208 m and 208 t) in the second n-type device region 600N2 that are not covered by the sidewall dielectric layer 220 a1, and channel layers (e.g., channel layers 208 m and 208 t) in the second p-type device region 600P2 that are not covered by the sidewall dielectric layer 220 a1 are not protected by the patterned mask layer 410.

[0073] Still reference Fig.25 and FIG. 26A to FIG. 26D, the method 500 also includes a block 320, in which an etching process 420 is performed to selectively recess the channel layers that are not protected by the patterned mask layer 410. When the patterned mask layer 410 is used as an etching mask, the etching process 420 is performed to selectively recess the channel layers that are not covered by the patterned mask layer 410. Therefore, the channel layers 208m and 208t in the second n-type device region 600N2, the channel layers 208b, 208m and 208t in the first p-type device region 600P3, and the channel layers 208m and 208t in the second p-type device region 600P2 are recessed and thus have a reduced width along the X direction. In addition, in the second n-type device region 600N2 and the second p-type device region 600P2, the widths of the channel layers 208m and 208t are less than the width of the corresponding bottommost channel layer 208b that is not recessed during the performance of the etching process 420. Recessing the channel layer forms openings 430 in the second n-type device region 600N2, the first p-type device region 600P3, and the second p-type device region 600P2. In this embodiment, the etching process 420 is performed to recess the channel layer without substantially etching the second semiconductor layer 226.

[0074] refer to Fig.25 and FIG. 27A to FIG. 27D , method 500 also includes blocks 120, 122, 124, 126, and 128. After performing the operations in block 320, the operations in blocks 120-128 of method 100 are performed to facilitate the formation of the final structure of semiconductor structure 600. Semiconductor structure 600 is similar to 16A to 16H The semiconductor structure 200 shown in FIG. 1 and some of the differences between the semiconductor structure 200 and the semiconductor structure 600 include that in the second n-type device region 600N2 and the second p-type device region 600P2, the channel layers 208t and 208m have a reduced width, and the corresponding source / drain features 236b / 232b include a first portion vertically disposed between the gate spacer 212a and the topmost inner spacer feature 216t and a second portion vertically disposed between the topmost inner spacer feature 216t and the middle inner spacer feature 216m. two parts; in the first p-type device region 600P3, all channel layers (for example, channel layers 208t and 208m and 208b) have a reduced width, and the p-type source / drain component 232a includes a first part vertically disposed between the gate spacer 212a and the topmost inner spacer component 216t, a second part vertically disposed between the topmost inner spacer component 216t and the middle inner spacer component 216m, and a third part vertically disposed between the middle inner spacer component 216m and the bottommost inner spacer component 216b.

[0075] exist FIG. 26A to FIG. 27DIn the illustrated embodiment, the etching process 420 is configured to selectively recess the channel layer without substantially etching the second semiconductor layer 226. FIG. 28A to FIG. 28D In another embodiment shown, the etching process 420 is configured to recess the channel layer and the second semiconductor layer 226. FIG. 28A to FIG. 28D As depicted, after the etching process 420 is performed, the top surface of the second semiconductor layer 226 of the semiconductor structure 600′ is located below the top surface of the sidewall dielectric layer 220a1. FIG. 29A to FIG. 29H Depicted in. FIG. 29A to FIG. 29H The semiconductor structure 600' shown is similar to FIG. 27A to FIG. 27D The semiconductor structure 600 is shown, and some of the differences between the two semiconductor structures include: in the second n-type device region 600N2 of the semiconductor structure 600′, the second dielectric layer 234 is in direct contact with at least a portion of the sidewall surface of the sidewall dielectric layer 220al, and may be further formed on and in direct contact with the top surface of the sidewall dielectric layer 220al, depending on the thickness of the second dielectric layer 234 and the recessed thickness of the second semiconductor layer 226; Fig.29D and Fig.29H In the second p-type device region 600P2 of the semiconductor structure 600' shown, the p-type source / drain component 232b includes a bottom portion extending between and in direct contact with the sidewall surfaces of the two sidewall dielectric layers 220a1 formed in the source / drain opening 214. That is, the volume of the p-type source / drain component 232b of the semiconductor structure 600' is greater than the volume of the p-type source / drain component 232b of the semiconductor structure 600. Similarly, the volume of the n-type source / drain component 236b of the semiconductor structure 600' is greater than the volume of the n-type source / drain component 236b of the semiconductor structure 600. For simplicity, the volume of the n-type source / drain component 236b is omitted. FIG. 29E to FIG. 29H Some of the parts in.

[0076] Although not intended to be limiting, one or more embodiments of the present disclosure provide many benefits to semiconductor structures and their formation. The present disclosure provides methods and structures that can provide a multi-gate device with multiple semiconductor channel layers selected based on preferred performance (e.g., low leakage current or high drive current) without sacrificing the strain performance of the p-type source / drain components of the p-type multi-gate device. The method can be applied to active areas with the same or different configurations (e.g., spacing and width). By implementing the method, different regions of the semiconductor structure can be manufactured as GAAs with different performance.

[0077] The embodiments of the present disclosure provide many different embodiments. Semiconductor structures and methods for manufacturing the same are disclosed herein. In one exemplary aspect, the embodiments of the present disclosure relate to a semiconductor structure. The semiconductor structure includes: a first transistor, including: a first gate structure, wrapping a plurality of first nanostructures disposed above a substrate; a first source / drain component, electrically coupled to the topmost nanostructure of the plurality of first nanostructures, and isolated from the bottommost nanostructure of the plurality of first nanostructures by a first dielectric layer; and a first semiconductor layer, disposed between the substrate and the first source / drain component, wherein the first source / drain component is in direct contact with a top surface of the first semiconductor layer.

[0078] In some embodiments, the first dielectric layer may extend along a sidewall surface of the first semiconductor layer. In some embodiments, the first transistor may also include: a plurality of internal spacer components disposed between two adjacent nanostructures of the plurality of first nanostructures, wherein the first dielectric layer extends along a sidewall surface of a bottommost internal spacer component of the plurality of internal spacer components. In some embodiments, a portion of the first dielectric layer may be disposed above a top surface of a bottommost internal spacer component of the plurality of internal spacer components and in direct contact with a top surface of a bottommost internal spacer component of the plurality of internal spacer components. In some embodiments, a sidewall surface of the first semiconductor layer may be in direct contact with the first dielectric layer and the bottommost internal spacer component of the plurality of internal spacer components. In some embodiments, the first source / drain component may be a p-type source / drain component. In some embodiments, the first source / drain component may be disposed adjacent to the plurality of first nanostructures along a first direction, and the bottommost nanostructure of the plurality of first nanostructures may have a width along the first direction greater than a width of other nanostructures of the plurality of first nanostructures. In some embodiments, a top surface of the first dielectric layer may be located above a top surface of the first semiconductor layer. In some embodiments, the semiconductor structure may also include: a second transistor, including: a second gate structure, wrapping a plurality of second nanostructures disposed above the substrate; a second source / drain component, electrically coupled to the topmost nanostructure of the plurality of second nanostructures, and isolated from the bottommost nanostructure of the plurality of second nanostructures by a second dielectric layer; and a second semiconductor layer, adjacent to the second dielectric layer, and isolated from the second source / drain component by a third dielectric layer. In some embodiments, the first dielectric layer and the second dielectric layer may include the same composition and the same thickness. In some embodiments, the second source / drain component may be an n-type source / drain component. In some embodiments, the third dielectric layer may be in direct contact with the second source / drain component, the second dielectric layer, and the second semiconductor layer.

[0079] In another exemplary aspect, the disclosed embodiments relate to a transistor. The transistor includes: a gate structure encapsulating a plurality of nanostructures disposed above a substrate; an undoped semiconductor layer disposed in and above the substrate, wherein a top surface of the undoped semiconductor layer is coplanar with or above a top surface of a bottommost nanostructure of the plurality of nanostructures; a dielectric layer disposed between the undoped semiconductor layer and the bottommost nanostructure of the plurality of nanostructures; and a source / drain component adjacent to the plurality of nanostructures, wherein a bottom surface of the source / drain component is in direct contact with a top surface of the undoped semiconductor layer.

[0080] In some embodiments, the undoped semiconductor layer may also include a first portion embedded in the substrate and a second portion located on the substrate, and the entire sidewall surface of the second portion of the undoped semiconductor layer may be covered by the dielectric layer. In some embodiments, the transistor may also include: a plurality of internal spacer components vertically disposed between two adjacent nanostructures of the plurality of nanostructures, wherein the dielectric layer is disposed between the undoped semiconductor layer and the bottommost internal spacer component of the plurality of internal spacer components. In some embodiments, the dielectric layer may be in direct contact with the source / drain component, the undoped semiconductor layer, and the bottommost internal spacer component of the plurality of internal spacer components.

[0081] In yet another exemplary aspect, the disclosed embodiments relate to a method. The method includes: forming a first fin-shaped active region extending from a substrate and including a plurality of channel layers interlaced with a plurality of sacrificial layers; forming a first gate stack above a first channel region of the first fin-shaped active region; recessing a first source / drain region of the first fin-shaped active region to form a first source / drain opening; forming a first semiconductor layer in a bottom portion of the first source / drain opening; forming a first dielectric layer extending along a sidewall surface of a middle portion of the first source / drain opening and located on the first semiconductor layer, wherein the entire sidewall surface of a bottommost channel layer of the plurality of channel layers is covered by the first dielectric layer; forming a second semiconductor layer on the first semiconductor layer, wherein a sidewall surface of the second semiconductor layer is in direct contact with the first dielectric layer; forming a first source / drain component on the second semiconductor layer; and replacing the first gate stack and the plurality of sacrificial layers with a gate structure.

[0082] In some embodiments, the method may also include: selectively etching the sacrificial layer to form an internal spacer recess; and forming an internal spacer component in the internal spacer recess. In some embodiments, the first source / drain component is a p-type source / drain component and is in direct contact with the second semiconductor layer and the first dielectric layer. In some embodiments, forming the first dielectric layer may also include: conformally depositing an insulating layer above the substrate, the insulating layer including a vertical portion extending along a sidewall surface of the first source / drain opening and a horizontal portion extending along a top surface of the first semiconductor layer; performing a first etching process to remove the horizontal portion of the insulating layer; and after forming the second semiconductor layer, performing a second etching process to remove a portion of the vertical portion of the insulating layer that is not covered by the second semiconductor layer.

[0083] Some embodiments of the present application provide a semiconductor structure, including: a first transistor, including: a first gate structure, wrapping a plurality of first nanostructures disposed above a substrate; a first source / drain component, electrically coupled to a topmost nanostructure of the plurality of first nanostructures and isolated from a bottommost nanostructure of the plurality of first nanostructures by a first dielectric layer; and a first semiconductor layer, disposed between the substrate and the first source / drain component, wherein the first source / drain component is in direct contact with a top surface of the first semiconductor layer.

[0084] In some embodiments, the first dielectric layer extends along the sidewall surface of the first semiconductor layer. In some embodiments, the first transistor further comprises: a plurality of internal spacer components disposed between two adjacent nanostructures of the plurality of first nanostructures, wherein the first dielectric layer extends along the sidewall surface of the bottommost internal spacer component of the plurality of internal spacer components. In some embodiments, a portion of the first dielectric layer is disposed above a top surface of the bottommost internal spacer component of the plurality of internal spacer components and is in direct contact with a top surface of the bottommost internal spacer component of the plurality of internal spacer components. In some embodiments, a sidewall surface of the first semiconductor layer is in direct contact with the first dielectric layer and the bottommost internal spacer component of the plurality of internal spacer components. In some embodiments, the first source / drain component is a p-type source / drain component. In some embodiments, the first source / drain component is disposed adjacent to the plurality of first nanostructures along a first direction, and the bottommost nanostructure of the plurality of first nanostructures has a width along the first direction greater than a width of other nanostructures of the plurality of first nanostructures. In some embodiments, a top surface of the first dielectric layer is located above the top surface of the first semiconductor layer. In some embodiments, the semiconductor structure further comprises: a second transistor comprising: a second gate structure encapsulating a plurality of second nanostructures disposed above the substrate; a second source / drain component electrically coupled to a topmost nanostructure of the plurality of second nanostructures and isolated from a bottommost nanostructure of the plurality of second nanostructures by a second dielectric layer; and a second semiconductor layer adjacent to the second dielectric layer and isolated from the second source / drain component by a third dielectric layer. In some embodiments, the first dielectric layer and the second dielectric layer comprise the same composition and the same thickness. In some embodiments, the second source / drain component is an n-type source / drain component. In some embodiments, the third dielectric layer is in direct contact with the second source / drain component, the second dielectric layer, and the second semiconductor layer.

[0085] Other embodiments of the present application provide a transistor, comprising: a gate structure wrapping a plurality of nanostructures disposed above a substrate; an undoped semiconductor layer disposed in and above the substrate, wherein a top surface of the undoped semiconductor layer is coplanar with a top surface of a bottommost nanostructure of the plurality of nanostructures or is disposed above a top surface of the bottommost nanostructure of the plurality of nanostructures; a dielectric layer disposed between the undoped semiconductor layer and the bottommost nanostructure of the plurality of nanostructures; and a source / drain component adjacent to the plurality of nanostructures, wherein a bottom surface of the source / drain component is in direct contact with a top surface of the undoped semiconductor layer.

[0086] In some embodiments, the undoped semiconductor layer includes a first portion embedded in the substrate and a second portion located on the substrate, wherein the entire sidewall surface of the second portion of the undoped semiconductor layer is covered by the dielectric layer. In some embodiments, the transistor further includes: a plurality of internal spacer components vertically disposed between two adjacent nanostructures of the plurality of nanostructures, wherein the dielectric layer is disposed between the undoped semiconductor layer and a bottommost internal spacer component of the plurality of internal spacer components. In some embodiments, the dielectric layer is in direct contact with the source / drain component, the undoped semiconductor layer, and the bottommost internal spacer component of the plurality of internal spacer components.

[0087] Some other embodiments of the present application provide a method for forming a semiconductor structure, comprising: forming a first fin-shaped active region extending from a substrate and comprising a plurality of channel layers interlaced with a plurality of sacrificial layers; forming a first gate stack above a first channel region of the first fin-shaped active region; recessing a first source / drain region of the first fin-shaped active region to form a first source / drain opening; forming a first semiconductor layer in a bottom portion of the first source / drain opening; forming a first dielectric layer extending along a sidewall surface of a middle portion of the first source / drain opening and located on the first semiconductor layer, wherein the entire sidewall surface of a bottommost channel layer of the plurality of channel layers is covered by the first dielectric layer; forming a second semiconductor layer on the first semiconductor layer, wherein a sidewall surface of the second semiconductor layer is in direct contact with the first dielectric layer; forming a first source / drain component on the second semiconductor layer; and replacing the first gate stack and the plurality of sacrificial layers with a gate structure.

[0088] In some embodiments, the method further comprises: selectively etching the sacrificial layer to form an internal spacer recess; and forming an internal spacer component in the internal spacer recess. In some embodiments, the first source / drain component is a p-type source / drain component and is in direct contact with the second semiconductor layer and the first dielectric layer. In some embodiments, forming the first dielectric layer comprises: conformally depositing an insulating layer above the substrate, the insulating layer comprising a vertical portion extending along a sidewall surface of the first source / drain opening and a horizontal portion extending along a top surface of the first semiconductor layer; performing a first etching process to remove the horizontal portion of the insulating layer; and after forming the second semiconductor layer, performing a second etching process to remove a portion of the vertical portion of the insulating layer that is not covered by the second semiconductor layer.

[0089] The features of several embodiments are summarized above so that those of ordinary skill in the art can better understand the various aspects of the embodiments of the present disclosure. Those of ordinary skill in the art should understand that they can easily use the embodiments of the present disclosure as a basis to design or modify other processes and structures for performing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those of ordinary skill in the art should also be aware that such equivalent constructions do not deviate from the spirit and scope of the embodiments of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. A semiconductor structure comprising: A first transistor comprising: A first gate structure encapsulating a plurality of first nanostructures disposed above the substrate; a first source / drain feature electrically coupled to a topmost nanostructure of the plurality of first nanostructures and isolated from a bottommost nanostructure of the plurality of first nanostructures by a first dielectric layer; and A first semiconductor layer is disposed between the substrate and the first source / drain component, wherein the first source / drain component is in direct contact with a top surface of the first semiconductor layer.

2. The semiconductor structure according to claim 1, wherein: The first dielectric layer extends along a sidewall surface of the first semiconductor layer.

3. The semiconductor structure according to claim 1, wherein: The first transistor further includes: A plurality of inner spacer features are disposed between two adjacent nanostructures of the plurality of first nanostructures, wherein the first dielectric layer extends along a sidewall surface of a bottommost inner spacer feature of the plurality of inner spacer features.

4. The semiconductor structure according to claim 3, wherein: A portion of the first dielectric layer is disposed over and in direct contact with a top surface of the bottommost inner spacer component of the plurality of inner spacer components.

5. The semiconductor structure according to claim 4, wherein: A sidewall surface of the first semiconductor layer is in direct contact with the first dielectric layer and the bottommost inner spacer member of the plurality of inner spacer members.

6. The semiconductor structure according to claim 1, wherein: The first source / drain feature is a p-type source / drain feature.

7. The semiconductor structure according to claim 1, wherein: The first source / drain feature is disposed adjacent to the plurality of first nanostructures along a first direction, and a width of the bottommost nanostructure of the plurality of first nanostructures along the first direction is greater than widths of other nanostructures of the plurality of first nanostructures.

8. The semiconductor structure according to claim 1, wherein: A top surface of the first dielectric layer is located above the top surface of the first semiconductor layer.

9. A transistor comprising: A gate structure encapsulating a plurality of nanostructures disposed above the substrate; an undoped semiconductor layer disposed in and above the substrate, wherein a top surface of the undoped semiconductor layer is coplanar with a top surface of a bottommost nanostructure of the plurality of nanostructures or is disposed above a top surface of a bottommost nanostructure of the plurality of nanostructures; a dielectric layer disposed between the undoped semiconductor layer and the bottommost nanostructure of the plurality of nanostructures; and A source / drain component is adjacent to the plurality of nanostructures, wherein a bottom surface of the source / drain component is in direct contact with a top surface of the undoped semiconductor layer.

10. A method of forming a semiconductor structure, comprising: forming a first fin-shaped active region extending from a substrate and comprising a plurality of channel layers interleaved with a plurality of sacrificial layers; forming a first gate stack over a first channel region of the first fin-shaped active region; recessing a first source / drain region of the first fin-shaped active region to form a first source / drain opening; forming a first semiconductor layer in a bottom portion of the first source / drain opening; forming a first dielectric layer extending along the sidewall surface of the middle portion of the first source / drain opening and located on the first semiconductor layer, wherein the entire sidewall surface of the bottommost channel layer of the plurality of channel layers is covered by the first dielectric layer; forming a second semiconductor layer on the first semiconductor layer, wherein a sidewall surface of the second semiconductor layer is in direct contact with the first dielectric layer; forming a first source / drain feature on the second semiconductor layer; and The first gate stack and the plurality of sacrificial layers are replaced with a gate structure.

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