Semiconductor device and manufacturing method thereof, power module, power conversion circuit, and vehicle

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof, a power module, a power conversion circuit, and a vehicle. The semiconductor device comprises a semiconductor body which comprises a well region, a first region and a second region; the first surface is also provided with a groove comprising a first sub-groove and a second sub-groove; the conduction type of the first region and the conduction type of the well region are the same and opposite; the first sub-groove comprises a first side wall and a second side wall which are overlapped in vertical projection on the first surface, and the second region surrounds the first side wall, the second side wall and a part of the bottom, connected with the second side wall, of the second sub-groove; the conduction type of the second region is the same as that of the well region, and the doping concentration of the second region is greater than that of the well region; the pressure-resistant filling layer is located in the second sub-trench; the source electrode is located on the first surface. According to the technical scheme provided by the embodiment of the invention, the specific on-resistance and the peak electric field at the bottom of the gate structure are reduced, so that the electrical performance of the semiconductor device is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, a power module, a power conversion circuit and a vehicle. Background Art

[0002] Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) of third-generation wide-bandgap semiconductors such as silicon carbide or gallium nitride has the characteristics of large critical breakdown electric field strength, high thermal conductivity, large bandgap width and high electron saturation drift velocity, making third-generation wide-bandgap semiconductor materials such as silicon carbide or gallium nitride a research hotspot for power semiconductor devices, and silicon carbide devices are given high expectations in high-power applications such as high-speed railways, hybrid vehicles, and intelligent high-voltage direct current transmission.

[0003] Currently, MOSFET semiconductor devices including trench gate structures cannot simultaneously reduce the specific on-resistance and the peak electric field at the bottom of the gate structure, resulting in relatively poor electrical performance of the semiconductor devices. Summary of the invention

[0004] The present invention provides a semiconductor device, a power module, a power conversion circuit and a vehicle, so as to reduce the specific on-resistance and the peak electric field at the bottom of the gate structure, thereby improving the electrical performance of the semiconductor device.

[0005] In a first aspect, the present invention provides a semiconductor device, comprising:

[0006] A semiconductor body, comprising a first surface and a second surface arranged opposite to each other; the semiconductor body further comprises a well region, a first area and a second area; the first area is arranged on the first surface, and the well region is arranged on a side of the first area away from the first surface; a groove is also arranged on the first surface, and the groove comprises a first sub-groove and a second sub-groove, the first sub-groove is arranged on the first surface, the second sub-groove is connected to the first sub-groove, and the second sub-groove is located between the first sub-groove and the second surface; the conductivity type of the first area is the same as the conductivity type of the well region and is opposite; the vertical projection of the second sub-groove on the first surface coincides with the vertical projection of the first sub-groove on the first surface; the first sub-groove comprises a first sidewall, the second sub-groove comprises a second sidewall, and the vertical projections of the first sidewall and the second sidewall on the first surface coincide; the second area surrounds the first sidewall, the second sidewall and the bottom portion of the second sub-groove connected to the second sidewall; the conductivity type of the second area is the same as the conductivity type of the well region, and the doping concentration of the second area is greater than the doping concentration of the well region;

[0007] A pressure-resistant filling layer, located in the second sub-groove;

[0008] A gate structure, located in the first sub-trench;

[0009] A source electrode, located on the first surface;

[0010] The drain is located on the second surface.

[0011] Optionally, the semiconductor body includes a first drift layer and a second drift layer;

[0012] The second drift layer is located on a surface of the first drift layer; a surface of the second drift layer away from the first drift layer is a first surface of the semiconductor body;

[0013] The second region includes a connected bottom region and a sidewall region; the bottom region surrounds a portion of the bottom of the second sub-groove connected to the second sidewall, and the sidewall region surrounds the first sidewall and the second sidewall; or, the bottom region surrounds a portion of the bottom of the second sub-groove connected to the second sidewall and a first portion of the second sidewall, and the sidewall region surrounds the first sidewall and a second portion of the second sidewall, and the first portion of the second sidewall and the second portion of the second sidewall constitute the second sidewall;

[0014] The bottom region is disposed in the first drift layer.

[0015] Optionally, the material of the voltage-resistant filling layer includes at least one of silicon oxide, silicon nitride and polysilicon.

[0016] Optionally, the second region further includes at least two sub-regions, and the at least two sub-regions are arranged at intervals in a direction from the second surface to the first surface.

[0017] Optionally, the semiconductor body includes a silicon carbide semiconductor body or a gallium nitride semiconductor body.

[0018] In a second aspect, the present invention provides a method for manufacturing a semiconductor device, comprising:

[0019] A semiconductor body is provided, the semiconductor body comprising a first surface and a second surface arranged opposite to each other; the semiconductor body further comprising a well region, a first area and a second area; the first area is arranged on the first surface, and the well region is arranged on a side of the first area away from the first surface; a groove is also arranged on the first surface, the groove comprises a first sub-groove and a second sub-groove, the first sub-groove is arranged on the first surface, the second sub-groove is connected to the first sub-groove, and the second sub-groove is located between the first sub-groove and the second surface; the conductivity type of the first area is the same as the conductivity type of the well region and is opposite; the vertical projection of the second sub-groove on the first surface coincides with the vertical projection of the first sub-groove on the first surface; the first sub-groove comprises a first sidewall, the second sub-groove comprises a second sidewall, and the vertical projections of the first sidewall and the second sidewall on the first surface coincide; the second area surrounds the first sidewall, the second sidewall and the bottom portion of the second sub-groove connected to the second sidewall; the conductivity type of the second area is the same as the conductivity type of the well region, and the doping concentration of the second area is greater than the doping concentration of the well region;

[0020] forming a voltage-resistant filling layer in the second sub-groove;

[0021] forming a gate structure in the first sub-trench;

[0022] forming a source electrode on the first surface;

[0023] A drain electrode is formed on the second surface.

[0024] Optionally, providing a semiconductor body comprises:

[0025] providing a first drift layer;

[0026] forming a bottom region on a surface of the first drift layer;

[0027] forming a second drift layer on a surface of the first drift layer where the bottom region is provided; a surface of the second drift layer away from the first drift layer is a first surface of the semiconductor body;

[0028] forming a well region and a first region on a surface of the second drift layer away from the first drift layer;

[0029] A groove is formed on a surface of the second drift layer away from the first drift layer, the groove includes a first sub-groove and a second sub-groove, the first sub-groove is arranged on the first surface, and the second sub-groove is connected to the first sub-groove; the bottom area surrounds a portion of the bottom of the second sub-groove connected to the second sidewall; or, the bottom area surrounds a portion of the bottom of the second sub-groove connected to the second sidewall and a first portion of the second sidewall;

[0030] A side wall region is formed on the first side wall and the second side wall, wherein the side wall region and the bottom region are connected.

[0031] Optionally, providing a first drift layer, and forming a bottom region in the first drift layer comprises:

[0032] A first drift layer is provided, and a bottom region including at least two sub-regions is formed in the first drift layer, wherein the at least two sub-regions are arranged at intervals in a direction from the second surface to the first surface.

[0033] In a third aspect, the present invention provides a power module, comprising a substrate and at least one semiconductor device as described in any of the embodiments of the present invention, wherein the substrate is used to carry the semiconductor device.

[0034] In a fourth aspect, the present invention provides a power conversion circuit, wherein the power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction;

[0035] The power conversion circuit includes a circuit board and at least one semiconductor device as described in any of the embodiments of the present invention, and the semiconductor device is electrically connected to the circuit board.

[0036] In a fifth aspect, the present invention provides a vehicle, comprising a load and a power conversion circuit as described in any embodiment of the present invention, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

[0037] The semiconductor device and manufacturing method, power module, power conversion circuit and vehicle provided by the embodiment of the present invention have a voltage-resistant filling layer located at the bottom of the gate structure, which reduces the peak electric field at the bottom of the trench-type gate structure and prevents the gate structure from being broken down. In the above-mentioned MOSFET semiconductor device, it is not necessary to set the source electrode to the area of ​​the semiconductor body occupied by the trench-type source electrode structure to reduce the peak electric field at the bottom of the trench-type gate structure, thereby reducing the specific on-resistance of the semiconductor device and improving the electrical performance of the semiconductor device. The second region surrounds the first side wall, the second side wall and the bottom of the part where the second sub-groove is connected to the second side wall; the conductivity type of the second region is the same as the conductivity type of the well region, and the doping concentration of the second region is greater than the doping concentration of the well region, that is, the drift region between the second region and the second surface constitutes a depletion layer, which improves the pressure-bearing capacity of the first side wall and the second side wall, and can further reduce the peak electric field at the bottom of the trench-type gate structure, further preventing the gate structure from being broken down.

[0038] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0040] Figure 1 It is a structural schematic diagram of a semiconductor device provided by the prior art;

[0041] Figure 2 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present invention;

[0042] Figure 3 is a schematic structural diagram of another semiconductor device provided by an embodiment of the present invention;

[0043] Figure 4 is a schematic structural diagram of another semiconductor device provided by an embodiment of the present invention;

[0044] Figure 5 is a schematic structural diagram of another semiconductor device provided by an embodiment of the present invention;

[0045] Figure 6 is a schematic structural diagram of another semiconductor device provided by an embodiment of the present invention;

[0046] Figure 7 is a flow chart of a method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0047] Figure 8-Figure 11 It is a structural schematic diagram corresponding to each step of a method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0048] Fig.12 yes Figure 7 The flowchart included in S110;

[0049] Figure 13-Figure 18 yes Fig.12 The structural schematic diagram corresponding to each step in the figure;

[0050] Figure 19-21 yes Fig.12 Schematic diagram of the structure corresponding to the refinement step of S1102. DETAILED DESCRIPTION

[0051] In order to enable those skilled in the art to better understand the solution of the present invention, the technical solution in the embodiment of the present invention will be described clearly and completely in conjunction with the drawings in the embodiment of the present invention. Obviously, the described embodiment is only a part of the embodiment of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0052] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations of "including" and "having" are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or devices is not necessarily limited to those steps or devices that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0053] Figure 1 It is a schematic diagram of the structure of a semiconductor device provided by the prior art. Figure 1As shown, the semiconductor device includes a semiconductor body 100, including a first surface 101 and a second surface 102 arranged opposite to each other. The semiconductor body 100 also includes a well region 103, a first region 104 and a third region 105, the conductivity type of the first region 104 is opposite to the conductivity type of the well region 103, the conductivity type of the third region 105 is the same as the conductivity type of the well region 103, and the doping concentration of the third region 105 is greater than the doping concentration of the well region 103. The first surface 101 is provided with a gate trench T1 and a source trench T2. The semiconductor device also includes a gate structure 200, a source structure 300 and a drain 400. The gate structure 200 includes a first insulating layer 201 and a gate electrode 202. The gate structure 200 is located in the gate trench T1. The spacer insulating layer 203 is used to space the gate structure 200 and the source structure 300. The source structure 300 is located in the source trench T2 , and includes a source 301 , an ohmic contact layer 302 , a polysilicon filling layer 303 and a second insulating layer 304 .

[0054] Figure 1 The MOSFET semiconductor device shown is a double trench MOSFET semiconductor device, and the source structure 300 is located in the source trench T2. Although the setting of the source structure 300 can reduce the peak electric field at the first insulating layer 201 at the bottom of the gate structure 200, the source structure 300 occupies the area of ​​the semiconductor body 100, reduces the specific on-resistance of the semiconductor device, and makes the electrical performance of the semiconductor device relatively poor.

[0055] In order to reduce the specific on-resistance of a MOSFET semiconductor device and the peak electric field at the bottom of the gate structure, thereby improving the electrical performance of the semiconductor device, the embodiment of the present invention provides the following technical solutions:

[0056] like Figure 2 As shown, Figure 21 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present invention, the semiconductor device comprising: a semiconductor body 100, comprising a first surface 101 and a second surface 102 arranged opposite to each other; the semiconductor body 100 further comprises a well region 103, a first region 104 and a second region 106; the first region 104 is arranged on the first surface 101, and the well region 103 is arranged on a side of the first region 104 away from the first surface 101; the first surface 101 is further provided with a trench T3, the trench T3 comprises a first sub-trench T4 and a second sub-trench T5, the first sub-trench T4 is arranged on the first surface 101, the second sub-trench T5 is connected to the first sub-trench T4, and the second sub-trench T5 is located between the first sub-trench T4 and the second surface 102; the conductivity type of the first region 104 is the same as and opposite to the conductivity type of the well region 103; the second sub-trench T5 is connected to the first sub-trench T4, and the second sub-trench T5 is located between the first sub-trench T4 and the second surface 102; the conductivity type of the first region 104 is the same as and opposite to the conductivity type of the well region 103; The vertical projection of the trench T5 on the first surface 101 coincides with the vertical projection of the first sub-trench T4 on the first surface; the first sub-trench T4 includes a first side wall T04, the second sub-trench T5 includes a second side wall T05, and the vertical projections of the first side wall T04 and the second side wall T05 on the first surface 101 coincide with each other; the second region 106 surrounds the first side wall T04, the second side wall T05, and a portion of the bottom T06 where the second sub-trench T5 is connected to the second side wall T05; the conductivity type of the second region 106 is the same as the conductivity type of the well region 103, and the doping concentration of the second region 106 is greater than the doping concentration of the well region 103; the voltage-resistant filling layer 107 is located in the second sub-trench T5; the gate structure 200 is located in the first sub-trench T4; the source 305 is located on the first surface 101; and the drain 400 is located on the second surface 102.

[0057] For example, Figure 2 As shown, the semiconductor body 100 includes a substrate 10 and an epitaxial layer 20. In some embodiments of the present invention, the semiconductor body 100 may also include only the epitaxial layer 20. In other embodiments of the present invention, the semiconductor body 100 may also include a substrate 10 and a semiconductor layer formed by other processes. Among them, the epitaxial layer 20 is a semiconductor layer formed by a single epitaxial process on the basis of the substrate 10, and the epitaxial process includes chemical vapor epitaxy (CVE), molecular beam epitaxy (MBD) and atomic layer epitaxy (ALE) and other processes.

[0058] Optionally, in other embodiments, the MOSFET semiconductor device may further include a third region, the conductivity type of the third region is the same as the conductivity type of the well region 103, the doping concentration of the third region is greater than the doping concentration of the well region 103, and the third region is electrically connected to the source 305 to form a good ohmic contact with the source 305. The third region is located on a side of the well region 103 away from the second surface 102.

[0059] MOSFET semiconductor devices include N-type MOSFET semiconductor devices or P-type MOSFET semiconductor devices. Taking the N-type MOSFET semiconductor device as an example, the semiconductor body 100 is an N-type semiconductor body, the first region 104 is an N+ doped region, the third region is a P+ doped region, the second region 106 is a P+ doped region, and the well region 103 is a P-well region.

[0060] The gate structure 200 includes a first insulating layer 201 and a gate electrode 202. The gate structure 200 is located in the first sub-trench T4. The spacing insulating layer 203 is used to space the gate structure 200 and the source 305. The ohmic contact layer 302 enables the source 305 to form a good ohmic contact with the first region 104. The material of the ohmic contact layer 302 includes one or more of metal Ni, an alloy or stack of metal Ti and metal Ni, an alloy or stack of metal Ni and metal Pt, metal Co, an alloy or stack of metal Ti and metal Al, and a stack of metal Ti and TiN.

[0061] Optionally, the thickness of the voltage-resistant filling layer 107 is greater than or equal to 0.5 micrometers and less than or equal to 8 micrometers. Optionally, the depth of the trench T3 is greater than or equal to 2 micrometers and less than or equal to 10 micrometers.

[0062] In the MOSFET semiconductor device provided by the embodiment of the present invention, the voltage-resistant filling layer 107 is located at the bottom of the gate structure 200, which reduces the peak electric field at the bottom of the trench-type gate structure 200 and prevents the gate structure 200 from being broken down. In the above-mentioned MOSFET semiconductor device, it is not necessary to set the source 305 as a trench-type source structure to occupy the area of ​​the semiconductor body to reduce the peak electric field at the bottom of the trench-type gate structure 200, thereby reducing the specific on-resistance of the semiconductor device and improving the electrical performance of the semiconductor device. The second region 106 surrounds the first side wall T04, the second side wall T05 and the bottom portion T06 where the second sub-trench T5 is connected to the second side wall T05; the conductivity type of the second region 106 is the same as the conductivity type of the well region 103, and the doping concentration of the second region 106 is greater than the doping concentration of the well region 103, that is, the drift layer between the second region 106 and the second surface 102 constitutes a depletion layer, which improves the pressure bearing capacity of the first side wall T04 and the second side wall T05, can further reduce the peak electric field at the bottom of the trench-type gate structure 200, and further avoids the gate structure 200 from being broken down.

[0063] Optionally, based on the above technical solution, Figure 2As shown, the semiconductor body 100 includes a first drift layer 108 and a second drift layer 109; the second drift layer 109 is located on the surface of the first drift layer 108; the surface of the second drift layer 109 away from the first drift layer 108 is the first surface of the semiconductor body 100; the second region 106 includes a connected bottom region 1061 and a sidewall region 1062; the bottom region 1061 surrounds a portion of the bottom T06 where the second sub-trench T5 is connected to the second sidewall T05, and the sidewall region 1062 surrounds the first sidewall T04 and the second sidewall T05; or, the bottom region 1061 surrounds a portion of the bottom T06 where the second sub-trench T5 is connected to the second sidewall T05 and a first portion of the second sidewall T05, the sidewall region 1062 surrounds the first sidewall T04 and the second portion of the second sidewall T05, and the first portion of the second sidewall T05 and the second portion of the second sidewall T05 constitute the second sidewall T05; the bottom region 1061 is disposed in the first drift layer 108.

[0064] It should be noted that Figure 2 A structure is shown in which the bottom region 1061 surrounds the partial bottom T06 connecting the second sub-trench T5 and the second side wall T05 and the first portion of the second side wall T05, and the side wall region 1062 surrounds the first side wall T04 and the second portion of the second side wall T05. In other embodiments, the technical solution is also included in which the bottom region 1061 surrounds the partial bottom T06 connecting the second sub-trench T5 and the second side wall T05, and the side wall region 1062 surrounds the first side wall T04 and the second side wall T05.

[0065] Specifically, the bottom region 1061 of the second region 106 is disposed in the first drift layer 108, and can be directly prepared on the surface of the first drift layer 108 by an ion doping process before forming the second drift layer 109. Compared with the technical solution of forming the bottom region 1061 of the second region 106 on the first surface of the semiconductor body 100, the diffusion distance of the ion doping is reduced, and the difficulty of ion doping of the bottom region 1061 of the second region 106 is reduced. Among them, the ion doping process includes ion implantation, ion diffusion or vapor deposition.

[0066] The sidewall region 1062 of the second region 106 surrounds the first sidewall T04 and the second sidewall T05 . After the trench T3 is completed on the first surface, the sidewall region 1062 can be prepared by ion implantation at a single tilt angle.

[0067] Optionally, based on the above technical solution, the material of the voltage-resistant filling layer 107 includes at least one of silicon oxide, silicon nitride and polysilicon.

[0068] like Figure 2-Figure 4 As shown, Figure 3is a schematic structural diagram of another semiconductor device provided by an embodiment of the present invention, Figure 4 1 is a schematic diagram of the structure of another semiconductor device provided by an embodiment of the present invention, wherein the material of the voltage-resistant filling layer 107 includes silicon oxide. Figure 5 As shown, Figure 5 1 is a schematic diagram of the structure of another semiconductor device provided by an embodiment of the present invention, wherein the material of the voltage-resistant filling layer 107 includes silicon nitride. Figure 6 As shown, Figure 6 1 is a schematic structural diagram of another semiconductor device provided by an embodiment of the present invention, wherein the material of the voltage-resistant filling layer 107 includes polysilicon.

[0069] Specifically, the material of the voltage-resistant filling layer 107 includes at least one of silicon oxide, silicon nitride and polysilicon, which increases the thickness of the dielectric layer at the bottom of the gate structure 200 , thereby further reducing the peak electric field at the bottom of the trench-type gate structure 200 .

[0070] Optionally, based on the above technical solution, Figure 3-Figure 6 As shown, the bottom area 1061 includes at least two sub-areas 1063 , and the at least two sub-areas 1063 are arranged at intervals in the direction from the second surface 102 to the first surface 101 .

[0071] The direction from the second surface 102 to the first surface 101 is the Y direction in the figure.

[0072] For example, Figure 4-Figure 6 As shown, the bottom region 1061 includes three sub-regions 1063, the first drift layer 108 includes a first sub-drift layer 1081 and two second sub-drift layers 1082, and the three sub-regions 1063 are arranged at intervals in the direction from the second surface 102 to the first surface 101. Figure 3 As shown, the bottom region 1061 includes two sub-regions 1063 , the first drift layer 108 includes a first sub-drift layer 1081 and a second sub-drift layer 1082 , and the two sub-regions 1063 are arranged at intervals in the direction from the second surface 102 to the first surface 101 .

[0073] Specifically, the more the number of second sub-drift layers 1082 is, the more the number of sub-regions 1063 is. In the process of preparing the sub-regions 1063 by ion doping on the surface where the first sub-drift layer 1081 and the second sub-drift layer 1082 are in contact and on the surface of the second sub-drift layer 1082 away from the first sub-drift layer 1081, the diffusion distance of the ion doping is shorter and the difficulty of ion doping in the bottom region 1061 is lower.

[0074] Optionally, based on the above technical solution, the semiconductor body 100 includes a silicon carbide semiconductor body or a gallium nitride semiconductor body.

[0075] Specifically, the semiconductor body 100 includes a silicon carbide semiconductor body, and the MOSFET semiconductor device is a silicon carbide MOSFET semiconductor device. The semiconductor body 100 includes a gallium nitride semiconductor body, and the MOSFET semiconductor device is a gallium nitride MOSFET semiconductor device. Silicon carbide MOSFET semiconductor devices or gallium nitride MOSFET semiconductor devices have the advantages of high withstand voltage, low on-resistance and high frequency, which can further improve the performance of semiconductor devices.

[0076] The embodiment of the present invention also provides a method for manufacturing a semiconductor device. Figure 7 As shown, Figure 7 1 is a flow chart of a method for manufacturing a semiconductor device provided by an embodiment of the present invention, and the method for manufacturing a semiconductor device comprises the following steps:

[0077] S110. Provide a semiconductor body, the semiconductor body comprising a first surface and a second surface arranged opposite to each other; the semiconductor body also comprises a well region, a first area and a second area; the first area is arranged on the first surface, and the well region is arranged on a side of the first area away from the first surface; the first surface is also provided with a groove, the groove comprises a first sub-groove and a second sub-groove, the first sub-groove is arranged on the first surface, the second sub-groove is connected to the first sub-groove, and the second sub-groove is located between the first sub-groove and the second surface; the conductivity type of the first area is the same as and opposite to the conductivity type of the well region; the vertical projection of the second sub-groove on the first surface coincides with the vertical projection of the first sub-groove on the first surface; the first sub-groove comprises a first sidewall, the second sub-groove comprises a second sidewall, and the vertical projections of the first sidewall and the second sidewall on the first surface coincide; the second area surrounds the first sidewall, the second sidewall and the bottom portion of the second sub-groove connected to the second sidewall; the conductivity type of the second area is the same as the conductivity type of the well region, and the doping concentration of the second area is greater than the doping concentration of the well region.

[0078] like Figure 8As shown, a semiconductor body 100 is provided. The semiconductor body 100 includes a first surface 101 and a second surface 102 arranged opposite to each other; the semiconductor body 100 also includes a well region 103, a first region 104 and a second region 106; the first region 104 is arranged on the first surface 101, and the well region 103 is arranged on a side of the first region 104 away from the first surface 101; the first surface 101 is also provided with a trench T3, the trench T3 includes a first sub-trench T4 and a second sub-trench T5, the first sub-trench T4 is arranged on the first surface 101, the second sub-trench T5 is connected to the first sub-trench T4, and the second sub-trench T5 is located between the first sub-trench T4 and the second surface 102; the conductivity type of the first region 104 and The conductivity types of the well region 103 are the same and opposite; the vertical projection of the second sub-trench T5 on the first surface 101 coincides with the vertical projection of the first sub-trench T4 on the first surface; the first sub-trench T4 includes a first side wall T04, the second sub-trench T5 includes a second side wall T05, and the vertical projections of the first side wall T04 and the second side wall T05 on the first surface 101 coincide with each other; the second region 106 surrounds the first side wall T04, the second side wall T05, and the bottom portion T06 where the second sub-trench T5 is connected to the second side wall T05; the conductivity type of the second region 106 is the same as the conductivity type of the well region 103, and the doping concentration of the second region 106 is greater than the doping concentration of the well region 103.

[0079] For example, Figure 8 As shown, the semiconductor body 100 includes a substrate 10 and an epitaxial layer 20. In some embodiments of the present invention, the semiconductor body 100 may also include only the epitaxial layer 20. In other embodiments of the present invention, the semiconductor body 100 may also include a substrate 10 and a semiconductor layer formed by other processes. Among them, the epitaxial layer 20 is a semiconductor layer formed by a single epitaxial process on the basis of the substrate 10, and the epitaxial process includes chemical vapor epitaxy (CVE), molecular beam epitaxy (MBD) and atomic layer epitaxy (ALE) and other processes.

[0080] Optionally, in other embodiments, the MOSFET semiconductor device may further include a third region, the conductivity type of the third region is the same as the conductivity type of the well region 103, the doping concentration of the third region is greater than the doping concentration of the well region 103, and the third region is electrically connected to the source 305 to form a good ohmic contact with the source 305. The third region is located on a side of the well region 103 away from the second surface 102.

[0081] MOSFET semiconductor devices include N-type MOSFET semiconductor devices or P-type MOSFET semiconductor devices. Taking the N-type MOSFET semiconductor device as an example, the semiconductor body 100 is an N-type semiconductor body, the first region 104 is an N+ doped region, the third region is a P+ doped region, the second region 106 is a P+ doped region, and the well region 103 is a P-well region.

[0082] S120 , forming a voltage-resistant filling layer in the second sub-trench.

[0083] like Fig. 9 As shown, a voltage-resistant filling layer 107 is formed in the second sub-trench T5. Optionally, the material of the voltage-resistant filling layer 107 includes at least one of silicon oxide, silicon nitride and polysilicon.

[0084] S130 , forming a gate structure in the first sub-trench.

[0085] like Fig.10 As shown, a gate structure 200 is formed in the first sub-trench T4. The gate structure 200 includes a first insulating layer 201 and a gate electrode 202. The gate structure 200 is located in the first sub-trench T4. Fig.11 As shown, the process also includes forming a spacer insulating layer 203 , where the spacer insulating layer 203 is used to separate the gate structure 200 and the source 305 formed subsequently.

[0086] S140, forming a source on the first surface.

[0087] like Figure 2 As shown, a source 305 is formed on the first surface 101. Fig.11 As shown, before forming the source electrode 305 , an ohmic contact layer 302 is further formed. The ohmic contact layer 302 enables the source electrode 305 to form a good ohmic contact with the first region 104 .

[0088] S150, forming a drain on the second surface.

[0089] like Figure 2 As shown, a drain electrode 400 is formed on the second surface 102. The drain electrode 400 may include a stack of metal Ti, metal Ni, and metal Ag.

[0090] The embodiment of the present invention provides a MOSFET semiconductor device obtained by the preparation method, wherein the voltage-resistant filling layer 107 is located at the bottom of the gate structure 200, which reduces the peak electric field at the bottom of the trench-type gate structure 200 and prevents the gate structure 200 from being broken down. In the above-mentioned MOSFET semiconductor device, it is not necessary to set the source 305 as the area of ​​the trench-type source structure occupied by the semiconductor body to reduce the peak electric field at the bottom of the trench-type gate structure 200, thereby reducing the specific on-resistance of the semiconductor device and improving the electrical performance of the semiconductor device. The second region 106 surrounds the first side wall T04, the second side wall T05 and the bottom portion T06 where the second sub-trench T5 is connected to the second side wall T05; the conductivity type of the second region 106 is the same as the conductivity type of the well region 103, and the doping concentration of the second region 106 is greater than the doping concentration of the well region 103, that is, the second region 106 and the drift region between the second region 106 and the second surface 102 constitute a depletion layer, which improves the pressure bearing capacity of the first side wall T04 and the second side wall T05, can further reduce the peak electric field at the bottom of the trench-type gate structure 200, and further avoid the gate structure 200 from being broken down.

[0091] Optionally, based on the above technical solution, Fig.12 As shown, Fig.12 yes Figure 7 The flowchart included in S110, S110 provides a semiconductor body including:

[0092] S1101 . Provide a first drift layer.

[0093] like Fig.13 As shown, a first drift layer 108 is provided. Fig.13 As shown, the first drift layer 108 includes a substrate 10 and an epitaxial layer 20. In some embodiments of the present invention, the first drift layer 108 may also include only the epitaxial layer 20. In other embodiments of the present invention, the first drift layer 108 may also include the substrate 10 and a semiconductor layer formed by other processes. Among them, the epitaxial layer 20 is a semiconductor layer formed by a single epitaxial process on the basis of the substrate 10, and the epitaxial process includes chemical vapor epitaxy (CVE), molecular beam epitaxy (MBD) and atomic layer epitaxy (ALE) and other processes.

[0094] S1102 , forming a bottom region in the first drift layer.

[0095] like Fig.14 As shown, the bottom region 1061 of the second region 106 is formed in the first drift layer 108 by an ion doping process. The ion doping process includes ion implantation, ion diffusion or vapor deposition.

[0096] S1103 , forming a second drift layer on a surface of the first drift layer where a bottom region is provided; a surface of the second drift layer away from the first drift layer is a first surface of the semiconductor body.

[0097] like Fig.15 As shown, the second drift layer 109 is formed on the surface of the first drift layer 108 where the bottom region 1061 is provided; the surface of the second drift layer 109 away from the first drift layer 108 is the first surface 101 of the semiconductor body 100. The second drift layer 109 may be an epitaxial layer.

[0098] S1104 , forming a well region and a first region on a surface of the second drift layer away from the first drift layer.

[0099] like Fig.16 As shown, the well region 103 and the first region 104 are formed on the surface of the second drift layer 109 away from the first drift layer 108 by an ion doping process. Optionally, a third region may be formed on the surface of the second drift layer 109 away from the first drift layer 108 by an ion doping process, and the conductivity type of the third region is the same as that of the well region 103.

[0100] S1105. Form a groove on the surface of the second drift layer away from the first drift layer, the groove includes a first sub-groove and a second sub-groove, the first sub-groove is arranged on the first surface, and the second sub-groove is connected to the first sub-groove; the bottom area surrounds the part of the bottom of the second sub-groove connected to the second sidewall; or, the bottom area surrounds the part of the bottom of the second sub-groove connected to the second sidewall and the first part of the second sidewall.

[0101] like Fig.17 As shown, a mask layer 500 is formed on the first surface 101 of the semiconductor body 100, and a trench T3 is formed on the surface of the second drift layer 109 away from the first drift layer 108 by photolithography and etching processes, wherein the trench T3 includes a first sub-trench T4 and a second sub-trench T5, wherein the first sub-trench T4 is disposed on the first surface 101, and the second sub-trench T5 is connected to the first sub-trench T4. A portion of the bottom T06 of the second sub-trench T5 connected to the second sidewall T05 exposes a bottom region 1061, so that the bottom region 1061 surrounds a portion of the bottom T06 of the second sub-trench T5 connected to the second sidewall T05; or, the second sub-trench T5 extends from the surface of the bottom region 1061 away from the second surface 102 to the bottom region 1061, so that the bottom region 1061 surrounds a portion of the bottom T06 of the second sub-trench T5 connected to the second sidewall T05 and a first portion of the second sidewall T05.

[0102] It should be noted that Fig.17A solution is shown in which the second sub-groove T5 extends from the surface of the bottom area 1061 away from the second surface 102 to the bottom area 1061. In other embodiments, a technical solution is also included in which a portion of the bottom T06 of the second sub-groove T5 connected to the second side wall T05 exposes the bottom area 1061.

[0103] S1106. Form a sidewall region on the first sidewall and the second sidewall, wherein the sidewall region is connected to the bottom region.

[0104] like Fig.18 As shown, the sidewall region 1062 is prepared by ion implantation at a single tilt angle, and the sidewall region 1062 is formed on the first sidewall T04 and the second sidewall T05, wherein the sidewall region 1062 is connected to the bottom region 1061. Figure 8 As shown, after the preparation of the sidewall region 1062 is completed, the mask layer 500 is removed.

[0105] Specifically, the bottom region 1061 of the second region 106 is disposed on the surface where the first drift layer 108 and the second drift layer 109 are in contact. Before forming the second drift layer 109, it can be directly prepared by an ion doping process on the surface of the first drift layer 108. Compared with the technical solution of forming the bottom region 1061 of the second region 106 on the first surface of the semiconductor body 100, the diffusion distance of the ion doping is reduced, and the difficulty of ion doping of the bottom region 1061 of the second region 106 is reduced. Among them, the ion doping process includes ion implantation, ion diffusion or vapor deposition.

[0106] The sidewall region 1062 of the second region 106 surrounds the first sidewall T04 and the second sidewall T05 . After the trench T3 is completed on the first surface, the sidewall region 1062 can be prepared by ion implantation at a single tilt angle.

[0107] Optionally, based on the above technical solution, S1101 provides a first drift layer, and S1102 forms a bottom region in the first drift layer includes:

[0108] A first drift layer is provided, and a bottom region including at least two sub-regions is formed in the first drift layer. The at least two sub-regions are arranged at intervals in a direction from the second surface to the first surface.

[0109] like Figure 19-21 As shown, a first drift layer 108 is provided, and a bottom region 1061 including at least two sub-regions 1063 is formed in the first drift layer 108, and the at least two sub-regions 1063 are arranged at intervals in a direction from the second surface 102 to the first surface 101. Fig.19 As shown, a first sub-drift layer 1081 is provided.

[0110] like Fig.19 As shown, the sub-region 1063 is formed on the surface of the first sub-drift layer 1081 by an ion doping process. The ion doping process includes ion implantation, ion diffusion or vapor deposition.

[0111] like Fig. 20 As shown, a first second sub-drift layer 1082 is formed on one side of the first sub-drift layer 1081 where the sub-region 1063 is provided. Fig.21 As shown, a second sub-drift layer 1082 is formed on one side of the first sub-drift layer 1081 where the sub-region 1063 is provided. The second sub-drift layer 1082 may be an epitaxial layer.

[0112] like Fig.21 As shown, after each formation of the second sub-drift layer 1082 , it also includes: forming a sub-region 1063 on the surface of the second sub-drift layer 1082 away from the first sub-drift layer 1081 ; at least two sub-regions 1063 spaced apart or continuously arranged in the direction from the second surface 102 to the first surface 101 constitute the second region 106 .

[0113] Exemplarily, the above manufacturing method prepares the bottom region 1061 of the second region 106 including three sub-regions 1063, the first drift layer 108 includes a first sub-drift layer 1081 and two second sub-drift layers 1082, and the three sub-regions 1063 are arranged at intervals in the direction from the second surface 102 to the first surface 101. The direction from the second surface 102 to the first surface 101 is the Y direction in the figure.

[0114] Specifically, the more the number of second sub-drift layers 1082 is, the more the number of sub-regions 1063 is. In the process of preparing the sub-region 1063 by ion doping on the surface where the first sub-drift layer 1081 and the second sub-drift layer 1082 are in contact and on the surface of the second sub-drift layer 1082 away from the first sub-drift layer 1081, the shorter the diffusion distance of the ion doping is, the lower the difficulty of ion doping in the sub-region 1063 is.

[0115] The embodiment of the present invention provides a power module, including a substrate and at least one semiconductor device described in any embodiment of the present invention, wherein the substrate is used to carry the semiconductor device. Therefore, the beneficial effects of the power module including the semiconductor device described in any embodiment of the present invention are not described in detail here.

[0116] An embodiment of the present invention provides a power conversion circuit, which is used for one or more of current conversion, voltage conversion, and power factor correction; the power conversion circuit includes a circuit board and at least one semiconductor device described in any embodiment of the present invention, and the semiconductor device is electrically connected to the circuit board. Therefore, the beneficial effects of the power conversion circuit including any semiconductor device described in the embodiment of the present invention are not repeated here.

[0117] The embodiment of the present invention further provides a vehicle, comprising a load and any power conversion circuit as in the embodiment of the present invention, the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power, and then input it into the load. Therefore, the beneficial effects of the power conversion circuit described in any embodiment of the present invention are not repeated here.

[0118] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0119] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A semiconductor device, characterized in that: include: A semiconductor body, comprising a first surface and a second surface arranged opposite to each other; the semiconductor body further comprising a well region, a first area, and a second area; the first area is arranged on the first surface, and the well region is arranged on a side of the first area away from the first surface; the first surface is further provided with a groove, the groove comprising a first sub-groove and a second sub-groove, the first sub-groove is arranged on the first surface, the second sub-groove is connected to the first sub-groove, and the second sub-groove is located between the first sub-groove and the second surface; the conductivity type of the first area is the same as and opposite to the conductivity type of the well region; the vertical projection of the second sub-groove on the first surface coincides with the vertical projection of the first sub-groove on the first surface; The first sub-groove comprises a first sidewall, the second sub-groove comprises a second sidewall, and vertical projections of the first sidewall and the second sidewall on the first surface overlap; The second region surrounds the first sidewall, the second sidewall, and a portion of the bottom of the second sub-trench connected to the second sidewall; the conductivity type of the second region is the same as the conductivity type of the well region, and the doping concentration of the second region is greater than the doping concentration of the well region; A pressure-resistant filling layer, located in the second sub-groove; A gate structure, located in the first sub-trench; A source electrode, located on the first surface; The drain is located on the second surface.

2. The semiconductor device according to claim 1, wherein: The semiconductor body includes a first drift layer and a second drift layer; The second drift layer is located on a surface of the first drift layer; a surface of the second drift layer away from the first drift layer is a first surface of the semiconductor body; The second region includes a connected bottom region and a sidewall region; the bottom region surrounds a portion of the bottom of the second sub-groove connected to the second sidewall, and the sidewall region surrounds the first sidewall and the second sidewall; or, the bottom region surrounds a portion of the bottom of the second sub-groove connected to the second sidewall and a first portion of the second sidewall, and the sidewall region surrounds the first sidewall and a second portion of the second sidewall, and the first portion of the second sidewall and the second portion of the second sidewall constitute the second sidewall; The bottom region is disposed in the first drift layer.

3. The semiconductor device according to claim 1, wherein: The material of the voltage-resistant filling layer includes at least one of silicon oxide, silicon nitride and polysilicon.

4. The semiconductor device according to claim 2, characterized in that The second region further includes at least two sub-regions, and the at least two sub-regions are arranged at intervals in a direction from the second surface to the first surface.

5. The semiconductor device according to claim 1, wherein: The semiconductor body includes a silicon carbide semiconductor body or a gallium nitride semiconductor body.

6. A method for manufacturing a semiconductor device, characterized in that: include: A semiconductor body is provided, the semiconductor body comprising a first surface and a second surface arranged opposite to each other; the semiconductor body further comprising a well region, a first area, and a second area; the first area is arranged on the first surface, and the well region is arranged on a side of the first area away from the first surface; the first surface is further provided with a groove, the groove comprising a first sub-groove and a second sub-groove, the first sub-groove is arranged on the first surface, the second sub-groove is connected to the first sub-groove, and the second sub-groove is located between the first sub-groove and the second surface; the conductivity type of the first area is the same as and opposite to the conductivity type of the well region; the vertical projection of the second sub-groove on the first surface coincides with the vertical projection of the first sub-groove on the first surface; The first sub-groove comprises a first sidewall, the second sub-groove comprises a second sidewall, and vertical projections of the first sidewall and the second sidewall on the first surface overlap; The second region surrounds the first sidewall, the second sidewall, and a portion of the bottom of the second sub-trench connected to the second sidewall; the conductivity type of the second region is the same as the conductivity type of the well region, and the doping concentration of the second region is greater than the doping concentration of the well region; forming a voltage-resistant filling layer in the second sub-groove; forming a gate structure in the first sub-trench; forming a source electrode on the first surface; A drain electrode is formed on the second surface.

7. The method for manufacturing a semiconductor device according to claim 6, wherein: The semiconductor body provided includes: providing a first drift layer; forming a bottom region in the first drift layer; forming a second drift layer on a surface of the first drift layer where the bottom region is provided; a surface of the second drift layer away from the first drift layer is a first surface of the semiconductor body; forming a well region and a first region on a surface of the second drift layer away from the first drift layer; A groove is formed on a surface of the second drift layer away from the first drift layer, the groove includes a first sub-groove and a second sub-groove, the first sub-groove is arranged on the first surface, and the second sub-groove is connected to the first sub-groove; the bottom area surrounds a portion of the bottom of the second sub-groove connected to the second sidewall; or, the bottom area surrounds a portion of the bottom of the second sub-groove connected to the second sidewall and a first portion of the second sidewall; A side wall region is formed on the first side wall and the second side wall, wherein the side wall region and the bottom region are connected.

8. The method for manufacturing a semiconductor device according to claim 7, wherein: Providing a first drift layer, and forming a bottom region in the first drift layer includes: A first drift layer is provided, and a bottom region including at least two sub-regions is formed in the first drift layer, wherein the at least two sub-regions are arranged at intervals in a direction from the second surface to the first surface.

9. A power module, characterized in that: It comprises a substrate and at least one semiconductor device according to any one of claims 1 to 5, wherein the substrate is used for carrying the semiconductor device.

10. A power conversion circuit, characterized in that: The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit comprises a circuit board and at least one semiconductor device according to any one of claims 1 to 5, wherein the semiconductor device is electrically connected to the circuit board.

11. A vehicle, characterized in that: It includes a load and a power conversion circuit as claimed in claim 10, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

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