Terminal structure of semiconductor device and semiconductor device

Abstract

The invention provides a terminal structure of a semiconductor device and the semiconductor device. The terminal structure comprises a semiconductor substrate which is provided with a first surface, and the first surface is provided with at least one first etching groove; the at least one first doped region extends into the semiconductor substrate from the surface of the first etching groove, and the conduction type of the first doped region is different from that of the semiconductor substrate; the field oxide layer is located on the side, with the first surface, of the semiconductor substrate; and the at least one metal field plate is located in the first etching groove, and the metal field plate is connected with the first doped region and the field oxide layer. According to the invention, the problem of low reliability of the semiconductor device in the prior art is solved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a terminal structure of a semiconductor device, a method for preparing the terminal structure of a semiconductor device, and a semiconductor device. Background Art

[0002] The performance of traditional silicon-based semiconductor devices has gradually approached the physical limits of the material, while devices made of third-generation semiconductor materials represented by silicon carbide have excellent working capabilities such as high frequency, high voltage, high temperature resistance, and radiation resistance. SiC devices have many excellent characteristics such as low conduction loss, fast switching speed, high operating frequency and high breakdown voltage. They have gradually been promoted and used in application scenarios such as electric vehicles, charging piles, new energy power generation, industrial control and flexible direct current transmission. They need to challenge some extreme environments, such as using them in high voltage environments, so it is necessary to improve the voltage resistance and reliability of silicon carbide devices.

[0003] In order to improve the voltage resistance and reliability of silicon carbide devices, the prior art generally adopts terminal structures such as field limiting rings, JTE, field limiting ring and JTE composite or bevel terminal structures in silicon carbide devices. However, the above terminal structures increase the terminal area of ​​the silicon carbide device, thereby reducing the reliability of the semiconductor device. Summary of the invention

[0004] The main purpose of the present invention is to provide a terminal structure of a semiconductor device, a method for preparing the terminal structure of a semiconductor device, and a semiconductor device, so as to solve the problem of low reliability of semiconductor devices in the prior art.

[0005] In order to achieve the above-mentioned purpose, according to one aspect of the present invention, a terminal structure of a semiconductor device is provided, and the terminal structure includes: a semiconductor substrate having a first surface, the first surface having at least one first etching groove; at least one first doping region extending from the surface of the first etching groove into the semiconductor substrate, and the first doping region and the semiconductor substrate have different conductivity types; a field oxide layer located on a side of the semiconductor substrate having the first surface; at least one metal field plate located in the first etching groove, and the metal field plate connects the first doping region and the field oxide layer.

[0006] Optionally, the terminal structure also includes: at least one second etching groove extending from the first surface into the semiconductor substrate, and the first etching groove and the second etching groove are spaced apart along a first direction, and the first direction is parallel to the first surface; at least one second doping region extending from the surface of the second etching groove into the semiconductor substrate, and the first doping region and the second doping region are spaced apart along the first direction, and the first doping region and the second doping region have the same conductivity type.

[0007] Optionally, the terminal structure further includes: at least one third doped region extending from the first surface into the semiconductor substrate, and the first doped region and the third doped region are spaced apart along the first direction, and the third doped region and the semiconductor substrate have the same conductivity type.

[0008] Optionally, the plurality of first etching grooves are arranged at intervals along the first direction, and an extension length of the plurality of first etching grooves in the second direction is equal to an extension length of the semiconductor substrate, and the second direction is parallel to the first surface.

[0009] Optionally, a plurality of first etching grooves are distributed in an array on the first surface.

[0010] Optionally, a metal field plate fills the first etched groove.

[0011] Optionally, the first etched groove has a first width in the first direction, the metal field plate has a second width in the first direction, and the first width is greater than the second width.

[0012] According to another aspect of the present invention, a method for preparing a terminal structure of a semiconductor device is provided, the preparation method comprising: providing a semiconductor substrate having a first surface; forming at least one first etching groove on the first surface; forming at least one first doping region in the semiconductor substrate, the first doping region extending from the surface of the first etching groove into the semiconductor substrate, the first doping region and the semiconductor substrate having different conductivity types; forming a field oxide layer on a side of the semiconductor substrate having the first surface; and forming at least one metal field plate in the first etching groove, the metal field plate being respectively arranged in contact with the bottom of the first etching groove and the field oxide layer.

[0013] Optionally, the preparation method further comprises: in the step of forming the metal field plate, forming a contact electrode on the first surface, so that the contact electrode contacts the active area.

[0014] According to another aspect of the present invention, there is provided a semiconductor device, such as the terminal structure described above; an active region extending from a first surface of a semiconductor substrate in the semiconductor device into the semiconductor substrate, and the active region is located outside the terminal structure; a contact electrode comprising a first electrode and a second electrode, the semiconductor substrate having a second surface opposite to the first surface, the first electrode being located on the first surface, and the contact electrode being in contact with the active region, and the second electrode being located on the second surface.

[0015] By applying the technical solution of the present invention, the terminal structure of the semiconductor device includes a semiconductor substrate, at least one first doped region, a field oxide layer and at least one metal field plate. The semiconductor substrate has a first surface, and the first surface has at least one first etched groove; the first doped region extends from the surface of the first etched groove to the semiconductor substrate in a one-to-one correspondence, and the first doped region and the semiconductor substrate have different conductivity types; the field oxide layer is located on the side of the semiconductor substrate having the first surface; at least one metal field plate is located in the first etched groove, and the metal field plate connects the first doped region and the field oxide layer. It can be seen that the terminal structure of the present application forms a field limiting ring structure integrating the first doped region and the metal field plate in the semiconductor device through the above-mentioned first etched groove, thereby improving the withstand voltage and reliability of the silicon carbide device. Furthermore, since the first doped region in the present application extends from the surface of the first etched groove to the semiconductor substrate, compared with the traditional field limiting ring, the field limiting ring structure of the present application can be deeper in the direction perpendicular to the first surface, so that the depletion layer of the semiconductor device can be extended as much as possible into the body of the semiconductor device, thereby saving the terminal area of ​​the semiconductor device. In addition, since the metal field plate in the present application is located in the first etched groove and connects the first doped region and the field oxide layer, the metal field plate serves as a floating field plate in the semiconductor device and can be used to fix the charge to affect the charge distribution on the first surface, thereby changing the electric field distribution in the semiconductor device, thereby reducing the peak electric field in the semiconductor device; and, for a chip integrated with a semiconductor device having the above-mentioned terminal structure, the above-mentioned metal field plate can also reduce the chip's sensitivity to external charges, thereby improving the chip's reliability. In summary, the present application solves the problem of low reliability of semiconductor devices in the prior art. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The accompanying drawings constituting a part of the present invention are used to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the accompanying drawings:

[0017] Figure 1 A cross-sectional schematic diagram of a terminal structure according to an embodiment of the present invention is shown.

[0018] The above drawings include the following reference numerals:

[0019] 10. semiconductor substrate; 20. first etching groove; 30. first doping region; 40. field oxide layer; 50. metal field plate; 60. third doping region; 70. active region. DETAILED DESCRIPTION

[0020] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments can be combined with each other. The present invention will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0021] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0022] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so as to describe the embodiments of the present invention described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0023] As described in the background technology, SiC devices have many excellent characteristics such as low conduction loss, fast switching speed, high operating frequency, high breakdown voltage, etc., and have gradually been promoted and used in application scenarios such as electric vehicles, charging piles, new energy power generation, industrial control, and flexible direct current transmission. At this time, it is necessary to challenge some extreme environments, including but not limited to use in high voltage environments. Therefore, in order to make SiC devices still applicable in extreme environments, it is necessary to improve the voltage resistance and reliability of silicon carbide devices. On this basis, in order to improve the voltage resistance and reliability of silicon carbide devices, the prior art usually adopts terminal structures such as field limiting rings, JTEs, field limiting rings and JTE composites or bevel terminal structures in silicon carbide devices. However, the above-mentioned terminal structure increases the terminal area of ​​the silicon carbide device, thereby making the reliability of the semiconductor device low. In order to solve the problem of low reliability of semiconductor devices in the prior art, the present application provides a terminal structure of a semiconductor device, a preparation method of a terminal structure of a semiconductor device, and a semiconductor device.

[0024] In some optional embodiments, a terminal structure of a semiconductor device is provided, such as Figure 1As shown, the terminal structure includes: a semiconductor substrate 10 having a first surface, wherein the first surface has at least one first etching groove 20; at least one first doping region 30 extending from the surface of the first etching groove 20 to the semiconductor substrate 10, wherein the first doping region 30 and the semiconductor substrate 10 have different conductivity types; a field oxide layer 40 located on a side of the semiconductor substrate 10 having the first surface; and at least one metal field plate 50 located in the first etching groove 20, wherein the metal field plate 50 connects the first doping region 30 and the field oxide layer 40.

[0025] Specifically, the semiconductor substrate 10 may be a silicon carbide substrate.

[0026] Optionally, the morphology of the first etched groove 20 in the first surface may be strip-shaped or block-shaped. In the case of strip-shaped, the number of the first etched groove 20 in the first surface may be one or more; in the case of block-shaped, the number of the first etched groove 20 in the first surface may be more than one.

[0027] For example, Figure 1 As shown, in the case where there are multiple first etching grooves 20, the multiple first etching grooves 20 can be arranged at intervals along the first direction A, and the extension length of each of the first etching grooves 20 in the second direction B can be equal to the extension length of the semiconductor substrate 10 in the second direction B, and the second direction B is parallel to the first surface.

[0028] Optionally, the first direction A is perpendicular to the second direction B.

[0029] For example, Figure 1 As shown, when there are multiple first etching grooves 20, the multiple first etching grooves 20 can be distributed in an array on the first surface, and the extension length of each of the first etching grooves 20 in the second direction B can be smaller than the extension length of the semiconductor substrate 10 in the second direction B.

[0030] Exemplarily, the depth of the first etched groove 20 in a direction perpendicular to the first surface may be 0.01-5 μm.

[0031] Specifically, the number of the first doping regions 30 in the semiconductor substrate 10 may correspond one to one with the number of the first etching grooves 20 in the first surface. Exemplarily: when the number of the first etching grooves 20 is one, the number of the first doping region 30 is one, and the first doping region 30 extends from the surface of the first etching groove 20 into the semiconductor substrate 10; when the number of the first etching grooves 20 is multiple, the number of the first doping regions 30 is multiple, and the multiple first etching grooves 20 and the multiple first doping regions 30 correspond one to one, and the multiple first doping regions 30 extend one to one from the surface of the multiple first etching grooves 20 into the semiconductor substrate 10. It is mentioned here that the surface of the above-mentioned first etching groove 20 includes the side surface and the bottom surface of the first etching groove 20.

[0032] Exemplarily, the width of the first doping region 30 in the first direction A may be 0.1-10 μm, and the first direction A is parallel to the first surface.

[0033] For example, the ion implantation concentration of the first doping region 30 may be 1×10 18 cm -3 -1×10 20 cm -3 .

[0034] Specifically, the field oxide layer 40 may be located on the first surface. The material of the field oxide layer 40 may include but is not limited to at least one of silicon oxide, a semi-insulating oxide film and silicon nitride.

[0035] Exemplarily, the field oxide layer 40 may be located on a portion of the surface of the first surface except the surface of the first groove, and the portion of the surface covers the first doping region 30 and a portion of the surface between the adjacent first doping region 30 ; in this case, the metal field plate 50 may fill the first etching groove 20 .

[0036] Alternatively, the field oxide layer 40 may also cover a portion of the surface of the first groove, that is, the field oxide layer 40 may also be located on the sidewall and a portion of the bottom surface of the first surface. In this case, if the first etched groove 20 has a first width in the first direction A, and the metal field plate 50 has a second width in the first direction A, then the first width is greater than the second width, that is, the metal field plate 50 covers the surface of the first etched groove 20 that is not covered by the field oxide layer 40.

[0037] Optionally, the number of the metal field plates 50 may correspond to the number of the first etching grooves 20. For example, when the number of the first etching grooves 20 is one, the number of the metal field plate 50 is also one, and the metal field plate 50 is located in the first etching groove 20; when the number of the first etching grooves 20 is multiple, the number of the metal field plates 50 is also multiple, and the multiple metal field plates 50 are located in the multiple first etching grooves 20 in a one-to-one correspondence. The material of the metal field plate 50 may include but is not limited to aluminum.

[0038] Optionally, the number of the metal field plates 50 may be greater than the number of the first etching grooves 20. For example, when there is one first etching groove 20, there may be multiple metal field plates 50, and the multiple metal field plates 50 are located in the first etching groove 20.

[0039] By applying the technical solution of the present invention, the terminal structure of the semiconductor device includes a semiconductor substrate 10, at least one first doping region 30, a field oxide layer 40 and at least one metal field plate 50. The semiconductor substrate 10 has a first surface, and the first surface has at least one first etching groove 20; the first doping region 30 extends from the surface of the first etching groove 20 to the semiconductor substrate 10 in a one-to-one correspondence, and the first doping region 30 and the semiconductor substrate 10 have different conductivity types; the field oxide layer 40 is located on the side of the semiconductor substrate 10 having the first surface; at least one metal field plate 50 is located in the first etching groove 20, and the metal field plate 50 connects the first doping region 30 and the field oxide layer 40. It can be seen that the terminal structure of the present application forms a field limiting ring structure integrating the first doping region 30 and the metal field plate 50 in the semiconductor device through the above-mentioned first etching groove 20, thereby improving the voltage resistance and reliability of the silicon carbide device. Furthermore, since the first doped region 30 in the present application extends from the surface of the first etched groove 20 to the semiconductor substrate 10, compared with the traditional field limiting ring, the field limiting ring structure of the present application can have a deeper ion implantation depth in the direction perpendicular to the first surface, so that the depletion layer of the semiconductor device can be extended as far as possible into the body of the semiconductor device, thereby saving the terminal area of ​​the semiconductor device. In addition, since the metal field plate 50 in the present application is located in the first etched groove 20 and connects the first doped region 30 and the field oxide layer 40, the metal field plate 50 acts as a floating field plate in the semiconductor device, which can be used to fix the charge to affect the charge distribution on the first surface, thereby changing the electric field distribution in the semiconductor device, so that the peak electric field in the semiconductor device is reduced; and, for a chip integrated with a semiconductor device having the above-mentioned terminal structure, the above-mentioned metal field plate 50 can also reduce the chip's sensitivity to external charges, thereby improving the chip's reliability. In summary, through the present application, the problem of low reliability of semiconductor devices in the prior art is solved.

[0040] In some optional embodiments, in order to adapt to the electric field distribution within the semiconductor device, the terminal structure further includes: at least one second etching groove (not shown in the figure), extending from the first surface into the semiconductor substrate 10, and the first etching groove 20 and the second etching groove are spaced apart along a first direction A, and the first direction A is parallel to the first surface; at least one second doping region (not shown in the figure), extending from the surface of the second etching groove into the semiconductor substrate 10, and the first doping region 30 and the second doping region are spaced apart along the first direction A, and the first doping region 30 and the second doping region have the same conductivity type.

[0041] Specifically, Figure 1 As shown, the terminal structure of the semiconductor device may include two parts. The first part includes at least one first etching groove 20 located on the first surface of the semiconductor substrate 10, extending from the surface of the first etching groove 20 to at least one first doping region 30 in the semiconductor substrate 10, a field oxide layer 40 located on the side of the semiconductor substrate 10 having the first surface, and at least one metal field plate 50 located in the first etching groove 20 and connecting the first doping region 30 and the field oxide layer 40; the second part includes at least one second etching groove (not shown in the figure) located on the first surface of the semiconductor substrate 10, extending from the surface of the second etching groove to at least one second doping region (not shown in the figure) in the semiconductor substrate 10, that is, no metal field plate 50 is etched in the second etching groove.

[0042] Similarly, the second etching grooves in the first surface may be strip-shaped or block-shaped. In the case where there are multiple second etching grooves, the multiple second etching grooves correspond to the multiple second doping regions one by one.

[0043] Optionally, the ion implantation concentration of the first doping region 30 and the second doping region may be the same. Further, a high-energy ion machine may be used for ion implantation, so that the first doping region 30 and the second doping region may have a deeper depth in a direction perpendicular to the first surface, so that the width of the first etching groove 20 and the second etching groove in the first direction A may be further reduced, thereby achieving the effect of further reducing the terminal area.

[0044] Furthermore, in this embodiment, those skilled in the art may reasonably arrange the layout of the first etching groove 20 and the second etching groove in the first surface according to actual conditions, and this application does not make any specific limitation.

[0045] In order to limit the diffusion of the electric field, further improve the voltage resistance of the semiconductor device, and reduce the leakage of the semiconductor device under high voltage, in some optional implementations, such as Figure 1As shown, the terminal structure further includes: at least one third doping region 60, extending from the first surface into the semiconductor substrate 10, and the first doping region 30 and the third doping region 60 are spaced apart along the first direction A, and the third doping region 60 and the semiconductor substrate 10 have the same conductivity type.

[0046] Specifically, Figure 1 As shown, the semiconductor device further includes an active region 70, which extends from the first surface of the semiconductor substrate 10 into the semiconductor substrate 10, and the active region 70 is located on one side of the first doping region 30 and / or the second doping region. On this basis, the third doping region 60 can be located on a side of the first doping region 30 and / or the second doping region away from the active region 70.

[0047] In some optional embodiments, a method for preparing a terminal structure of a semiconductor device is provided, the method comprising: providing a semiconductor substrate 10 having a first surface; forming at least one first etching groove 20 on the first surface; forming at least one first doping region 30 in the semiconductor substrate 10, the first doping region 30 extending from the surface of the first etching groove 20 into the semiconductor substrate 10, the first doping region 30 and the semiconductor substrate 10 having different conductivity types; forming a field oxide layer 40 on a side of the semiconductor substrate 10 having the first surface; forming at least one metal field plate 50 in the first etching groove 20, the metal field plate 50 being respectively arranged in contact with the bottom of the first etching groove 20 and the field oxide layer 40, as shown in FIG. Figure 1 shown.

[0048] Exemplarily, before providing the semiconductor substrate 10, the method for preparing the terminal structure of the semiconductor device may further include: providing a semiconductor substrate; and sequentially growing a buffer layer and a drift layer on a surface of one side of the semiconductor substrate to form the semiconductor substrate 10. The semiconductor substrate may be a silicon carbide substrate.

[0049] In some optional embodiments, such as Figure 1 As shown, in order to reduce the process flow, in the step of forming the first etched groove 20 on the first surface, an alignment mark (not shown in the figure) can also be formed on the first surface, and the alignment mark is used for alignment in subsequent processes.

[0050] The first doping region 30 may be formed by performing high temperature ion implantation into the first etching groove 20 .

[0051] Specifically, the step of forming the above-mentioned field oxide layer 40 may include: forming a silicon oxide layer on the first surface using a thermal oxidation process; removing part of the silicon oxide by photolithography, wet etching or dry etching, and the part of the silicon oxide may be the silicon oxide in the silicon oxide layer except for the surface covering the above-mentioned first doped region 30 and the surface between the adjacent first doped region 30, and the remaining silicon oxide forms the above-mentioned field oxide layer 40.

[0052] Further, in order to form the metal field plate 50 in the first etched groove 20, at least a portion of the field oxide layer 40 covering the bottom surface of the first etched groove 20 may be removed by photolithography, etching, and removing the photoresist, so that at least a portion of the bottom surface of the first etched groove 20 is exposed, and then metal is deposited in the exposed surface of the first etched groove 20 by an alloying process, so as to form the metal field plate 50, and the metal field plate 50 is connected to the first doping region 30 and the field oxide layer 40. The above alloying process may include but is not limited to an evaporation process or a sputtering process.

[0053] Exemplarily, the metal field plate 50 may penetrate the field oxide layer 40 to the bottom of the first etched groove 20. Exemplarily, in addition to the first portion penetrating the oxide layer to the bottom of the first etched groove 20, the metal field plate 50 may also include a second portion located on a side of the field oxide layer 40 away from the semiconductor substrate 10, and the first portion and the second portion are connected.

[0054] In some optional embodiments, such as Figure 1 As shown, the semiconductor substrate 10 further includes an active region 70, which extends from the first surface of the semiconductor substrate 10 into the semiconductor substrate 10, and the active region 70 is located on one side of the first doping region 30. In order to reduce the preparation process, in the step of forming the metal field plate 50, a contact electrode can also be formed on the first surface so that the contact electrode contacts the active region 70. It should be noted that the contact electrode does not contact the metal field plate 50.

[0055] In some optional embodiments, a semiconductor device is provided, such as Figure 1 As shown, as the terminal structure mentioned above; the active area 70 extends from the first surface of the semiconductor substrate 10 in the above-mentioned semiconductor device to the above-mentioned semiconductor substrate 10, and the above-mentioned active area 70 is located on the outside of the above-mentioned terminal structure; the contact electrode (not shown in the figure) includes a first electrode and a second electrode, the above-mentioned semiconductor substrate 10 has a second surface opposite to the above-mentioned first surface, the above-mentioned first electrode is located on the above-mentioned first surface, and the above-mentioned contact electrode is in contact with the above-mentioned active area 70, and the above-mentioned second electrode is located on the above-mentioned second surface.

[0056] Exemplarily, the material of the contact electrode may be metal titanium or metal nickel.

[0057] Furthermore, the semiconductor device may further include a passivation layer, which may be located on a side of the field oxide layer 40 away from the semiconductor substrate 10. Exemplarily, the material of the passivation layer may be selected from at least one of silicon oxide, silicon nitride and polyimide.

[0058] From the above description, it can be seen that the above embodiments of the present invention achieve the following technical effects:

[0059] By applying the technical solution of the present invention, the terminal structure of the semiconductor device includes a semiconductor substrate, at least one first doped region, a field oxide layer and at least one metal field plate. The semiconductor substrate has a first surface, and the first surface has at least one first etched groove; the first doped region extends from the surface of the first etched groove to the semiconductor substrate in a one-to-one correspondence, and the first doped region and the semiconductor substrate have different conductivity types; the field oxide layer is located on the side of the semiconductor substrate having the first surface; at least one metal field plate is located in the first etched groove, and the metal field plate connects the first doped region and the field oxide layer. It can be seen that the terminal structure of the present application forms a field limiting ring structure integrating the first doped region and the metal field plate in the semiconductor device through the above-mentioned first etched groove, thereby improving the withstand voltage and reliability of the silicon carbide device. Furthermore, since the first doped region in the present application extends from the surface of the first etched groove to the semiconductor substrate, compared with the traditional field limiting ring, the field limiting ring structure of the present application can be deeper in the direction perpendicular to the first surface, so that the depletion layer of the semiconductor device can be extended as much as possible into the body of the semiconductor device, thereby saving the terminal area of ​​the semiconductor device. In addition, since the metal field plate in the present application is located in the first etched groove and connects the first doped region and the field oxide layer, the metal field plate serves as a floating field plate in the semiconductor device and can be used to fix the charge to affect the charge distribution on the first surface, thereby changing the electric field distribution in the semiconductor device, thereby reducing the peak electric field in the semiconductor device; and, for a chip integrated with a semiconductor device having the above-mentioned terminal structure, the above-mentioned metal field plate can also reduce the chip's sensitivity to external charges, thereby improving the chip's reliability. In summary, the present application solves the problem of low reliability of semiconductor devices in the prior art.

[0060] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A terminal structure of a semiconductor device, characterized in that: The terminal structure comprises: A semiconductor substrate having a first surface, wherein the first surface has at least one first etched groove; at least one first doped region extending from a surface of the first etched groove into the semiconductor substrate, the first doped region and the semiconductor substrate having different conductivity types; A field oxide layer, located on a side of the semiconductor substrate having the first surface; At least one metal field plate is located in the first etching groove, and the metal field plate connects the first doped region and the field oxide layer.

2. The terminal structure according to claim 1, characterized in that: The terminal structure also includes: at least one second etching groove extending from the first surface into the semiconductor substrate, wherein the first etching groove and the second etching groove are spaced apart along a first direction, and the first direction is parallel to the first surface; At least one second doping region extends from the surface of the second etched groove into the semiconductor substrate, and the first doping region and the second doping region are spaced apart along the first direction, and the first doping region and the second doping region have the same conductivity type.

3. The terminal structure according to claim 1, characterized in that: The terminal structure also includes: At least one third doping region extends from the first surface into the semiconductor substrate, and the first doping region and the third doping region are spaced apart along a first direction, and the third doping region and the semiconductor substrate have the same conductivity type.

4. The terminal structure according to any one of claims 1 to 3, characterized in that: The plurality of first etching grooves are arranged at intervals along a first direction, and an extension length of the plurality of first etching grooves in a second direction is equal to an extension length of the semiconductor substrate, and the second direction is parallel to the first surface.

5. The terminal structure according to any one of claims 1 to 3, characterized in that: A plurality of the first etching grooves are distributed in an array on the first surface.

6. The terminal structure according to any one of claims 1 to 3, characterized in that: The metal field plate fills the first etched groove.

7. The terminal structure according to any one of claims 1 to 3, characterized in that: The first etched groove has a first width in a first direction, and the metal field plate has a second width in the first direction, and the first width is greater than the second width.

8. A method for preparing a terminal structure of a semiconductor device, characterized in that: The preparation method comprises: Providing a semiconductor substrate having a first surface; forming at least one first etched groove on the first surface; forming at least one first doping region in the semiconductor substrate, wherein the first doping region extends from a surface of the first etched groove into the semiconductor substrate, and the first doping region and the semiconductor substrate have different conductivity types; forming a field oxide layer on a side of the semiconductor substrate having the first surface; At least one metal field plate is formed in the first etching groove, and the metal field plate is respectively disposed in contact with the bottom of the first etching groove and the field oxide layer.

9. The preparation method according to claim 8, characterized in that: The preparation method further comprises: In the step of forming the metal field plate, a contact electrode is formed on the first surface so that the contact electrode contacts the active region.

10. A semiconductor device, characterized in that: The semiconductor device comprises: The terminal structure according to any one of claims 1 to 7; an active region extending from a first surface of a semiconductor substrate in the semiconductor device into the semiconductor substrate, and the active region is located outside the terminal structure; The contact electrode comprises a first electrode and a second electrode. The semiconductor substrate has a second surface opposite to the first surface. The first electrode is located on the first surface and the contact electrode contacts the active area. The second electrode is located on the second surface.

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