Micro LED epitaxial wafer, preparation method thereof and Micro LED chip

Abstract

The invention relates to the technical field of photoelectricity, and discloses a Micro LED epitaxial wafer, a preparation method thereof and a Micro LED chip, the Micro LED epitaxial wafer comprises a substrate, and the substrate is sequentially provided with a buffer layer, an N-type GaN layer, a multi-quantum well layer and a P-type GaN layer; the multi-quantum well layer comprises a first multi-quantum well layer, a second multi-quantum well layer and a third multi-quantum well layer which are stacked in sequence, the In component content of the second InGaN quantum well layer is larger than the In component content of the first InGaN quantum well layer, and the In component content of the second InGaN quantum well layer is larger than the In component content of the third InGaN quantum well layer. According to the Micro LED epitaxial wafer provided by the invention, the lighting effect of a Micro LED chip under low working current density can be improved.

Description

Technical Field

[0001] The present invention relates to the field of optoelectronic technology, and in particular to a Micro LED epitaxial wafer and a preparation method thereof, and a Micro LED chip. Background Art

[0002] The development of Micro LED faces challenges in manufacturing technology and materials. For example, as the chip size decreases, the peak EQE of the device decreases and the corresponding current density increases. The efficiency of Micro LED with an operating current density of 0.01A / cm²~0.5A / cm² is still obviously insufficient. In fact, even conventional-sized chips for general lighting and backlight display applications have relatively low efficiency at this current density. The reason is that in order to balance efficiency and cost factors, the operating current density of conventional-sized chips is 20A / cm². 2 Up to 40A / cm 2 The goal of the corresponding epitaxial structure design and material growth is to improve the efficiency under high current density, and its peak EQE is usually in the current density range of 1A / cm²~4A / cm², without paying attention to the device efficiency under low current density. Under different current densities, the dominant reasons for the light-emitting mechanism of LED devices are different, and the corresponding epitaxial layer structure should also change. For example, at the low current density of 0.01A / cm²~0.5A / cm² in the Micro LED working range, the carrier concentration in the quantum well is relatively low, the proportion of Auger recombination is small, and the corresponding quantum well recombination volume can be reduced, which can reduce the number of quantum wells and the number of defects, and improve the EQE of the device under low current density; at the same time, electron leakage has not occurred or the proportion is very low under low current density, and the electron blocking layer structure not only has no effect of blocking electrons, but will block the injection of holes, reducing the quantum efficiency of the device. Therefore, in-depth mechanism research, design and growth of LED epitaxial layer structure under low current density working conditions of Micro LED is a necessary key technology for the research and development of high-efficiency Micro LED devices driven by low working current density. Summary of the invention

[0003] The technical problem to be solved by the present invention is to provide a Micro LED epitaxial wafer, which improves the light efficiency of the Micro LED chip.

[0004] The technical problem to be solved by the present invention is also to provide a method for preparing a Micro LED epitaxial wafer, which has a simple process and can stably produce a Micro LED epitaxial wafer with good luminescence performance.

[0005] In order to solve the above technical problems, the present invention provides a Micro LED epitaxial wafer, comprising a substrate, on which a buffer layer, an N-type GaN layer, a multi-quantum well layer, and a P-type GaN layer are sequentially provided; The multi-quantum well layer includes a first multi-quantum well layer, a second multi-quantum well layer and a third multi-quantum well layer stacked in sequence, the first multi-quantum well layer includes a first quantum barrier layer and a first InGaN quantum well layer stacked alternately, the second multi-quantum well layer includes a second quantum barrier layer and a second InGaN quantum well layer stacked alternately, the third multi-quantum well layer includes a third quantum barrier layer and a third InGaN quantum well layer stacked alternately, the In component content of the second InGaN quantum well layer is greater than the In component content of the first InGaN quantum well layer, and the In component content of the second InGaN quantum well layer is greater than the In component content of the third InGaN quantum well layer.

[0006] In some embodiments, the In component content of the first InGaN quantum well layer is 0.05-0.28; The In component content of the second InGaN quantum well layer is 0.1-0.39; The In component content of the third InGaN quantum well layer is 0.05-0.28.

[0007] In some embodiments, the first quantum barrier layer includes a first GaN layer, an Al layer, and a a Ga 1-a N layer, Al x In y Ga 1-x-y N layer, Al b Ga 1-b N layer and a second GaN layer; The second quantum barrier layer includes a third GaN layer, an Al α Ga 1-α N layer, Al γ In δ Ga 1-γ-δ N layer, Al β Ga 1-β N layer and a fourth GaN layer; The third quantum barrier layer includes a fifth GaN layer, an Al m Ga 1-m N layer, Al j In k Ga 1-j-k N layer, Al n Ga 1-n N layer and a sixth GaN layer.

[0008] In some embodiments, a>m>α; x>j>γ; b>n>β; x>y,γ>δ,j>k.

[0009] In some embodiments, 0.05≤a≤0.3; 0.12≤x≤0.36; 0.01≤y≤0.03; 0.05≤b≤0.3; 0.01≤α≤0.1; 0.01<γ≤0.1; 0.01<δ≤0.03; 0.01≤β≤0.1; 0.03≤m≤0.2; 0.05≤j≤0.2; 0.03≤k≤0.12; 0.03≤n≤0.2.

[0010] In some embodiments, the first GaN layer is a Si-doped GaN layer, and the Al x In y Ga 1-x-y The N layer is Si-doped Al x In y Ga 1-x-y N layer, the second GaN layer is a Si-doped GaN layer; The third GaN layer is a Si-doped GaN layer, and the Al γ In δ Ga 1-γ-δ The N layer is Si-doped Al γ In δ Ga 1-γ-δ N layer, the fourth GaN layer is a Si-doped GaN layer; The fifth GaN layer is a Mg-doped GaN layer, and the Al j In k Ga 1-j-k The N layer is Mg-doped Al j In k Ga 1-j-k N layer, the sixth GaN layer is a Mg-doped GaN layer; The Al a Ga 1-a N layer, Al b Ga 1-b N layer, Al α Ga 1-α N layer, Al β Ga 1-β N layer, Al m Ga 1-m N layer and Al n Ga 1-n The N layer is not intentionally doped.

[0011] In some embodiments, the Si doping concentration of the first GaN layer is 1.15×10 17 atoms / cm 3 ~2.8×10 18 atoms / cm 3 ; The Al x In y Ga 1-x-y The Si doping concentration of the N layer is 1.02×10 17 atoms / cm 3 ~2.3×10 18 atoms / cm 3 ; The Si doping concentration of the second GaN layer is 1.15×10 17 atoms / cm 3 ~2.8×10 18 atoms / cm 3 ; The Si doping concentration of the third GaN layer is 0.8×10 17 atoms / cm 3 ~1.6×10 18 atoms / cm 3 ; The Al γ In δ Ga 1-γ-δ The Si doping concentration of the N layer is 0.5×10 17 atoms / cm 3 ~1.2×10 18 atoms / cm 3 ; The Si doping concentration of the fourth GaN layer is 0.8×10 17 atoms / cm 3 ~1.6×10 18 atoms / cm 3 ; The Mg doping concentration of the fifth GaN layer is 1.6×10 18 atoms / cm 3 ~2.5×10 19 atoms / cm 3 ; The Al j In k Ga 1-j-k The Mg doping concentration of the N layer is 3.2×10 18 atoms / cm 3 ~5.8×10 19 atoms / cm3 ; The Mg doping concentration of the sixth GaN layer is 1.6×10 18 atoms / cm 3 ~2.5×10 19 atoms / cm 3 .

[0012] In order to solve the above problems, the present invention provides a method for preparing a Micro LED epitaxial wafer, comprising the following steps: S1. providing a substrate; S2, depositing a buffer layer, an N-type GaN layer, a multi-quantum well layer, and a P-type GaN layer on the substrate in sequence; The multi-quantum well layer includes a first multi-quantum well layer, a second multi-quantum well layer and a third multi-quantum well layer stacked in sequence, the first multi-quantum well layer includes a first quantum barrier layer and a first InGaN quantum well layer stacked alternately, the second multi-quantum well layer includes a second quantum barrier layer and a second InGaN quantum well layer stacked alternately, the third multi-quantum well layer includes a third quantum barrier layer and a third InGaN quantum well layer stacked alternately, the In component content of the second InGaN quantum well layer is greater than the In component content of the first InGaN quantum well layer, and the In component content of the second InGaN quantum well layer is greater than the In component content of the third InGaN quantum well layer.

[0013] In some embodiments, after the first multi-quantum well layer is grown, a first annealing treatment is performed on the surface, and the first annealing treatment includes: The temperature of the reaction chamber is maintained at 820°C to 1080°C and the pressure is maintained at 50 torr to 390 torr, and a mixed gas of N2 and H2 is introduced into the reaction chamber and maintained for 5s to 50s to complete the first operation; Stop introducing the N2 and H2 mixed gas to complete the second operation; The first operation and the second operation are alternately completed 3 to 15 times to complete the first annealing treatment.

[0014] In some embodiments, after the third multi-quantum well layer is grown, a second annealing treatment is performed on the surface, and the second annealing treatment includes: The temperature of the reaction chamber is maintained at 820°C to 1080°C and the pressure is maintained at 50 torr to 390 torr, and a mixed gas of N2 and H2 is introduced into the reaction chamber and maintained for 10s to 100s to complete the third operation; Stop introducing the N2 and H2 mixed gas to complete the fourth operation; The third operation and the fourth operation are alternately completed 3 to 15 times to complete the second annealing treatment.

[0015] Correspondingly, the present invention further provides a Micro LED chip, which includes the Micro LED epitaxial wafer as described above.

[0016] The implementation of the present invention has the following beneficial effects: In the Micro LED epitaxial wafer provided by the present invention, the multi-quantum well layer includes a first multi-quantum well layer, a second multi-quantum well layer and a third multi-quantum well layer stacked in sequence, the In component content of the second InGaN quantum well layer is greater than the In component content of the first InGaN quantum well layer, and the In component content of the second InGaN quantum well layer is greater than the In component content of the third InGaN quantum well layer. In the present invention, the In component content of the second InGaN quantum well layer is greater than the In component content of the first InGaN quantum well layer and the In component content of the third InGaN quantum well layer, the light emission wavelength of the second InGaN quantum well layer is longer, and the second multi-quantum well layer is the main light-emitting layer. The quantum well layer of the multi-quantum well layer forms a change in which the In component first increases and then decreases. This structure can reduce the lattice mismatch stress between the second InGaN quantum well layer and the second quantum barrier layer in the second multi-quantum well layer, reduce the defects caused by the large mismatch stress, improve the quality of the main light-emitting quantum well region under low working current density, and thus improve the radiation recombination efficiency of the multi-quantum well layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 A schematic diagram of the structure of a Micro LED epitaxial wafer provided by the present invention; Figure 2 A schematic diagram of the structure of the first multi-quantum well layer of the Micro LED epitaxial wafer provided by the present invention; Figure 3 A schematic diagram of the structure of the second multi-quantum well layer of the Micro LED epitaxial wafer provided by the present invention; Figure 4 This is a schematic diagram of the structure of the third multi-quantum well layer of the Micro LED epitaxial wafer provided by the present invention. DETAILED DESCRIPTION

[0018] In order to make the purpose, technical scheme and advantages of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention. In addition, it should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0019] In the description of the present invention, it is necessary to understand that the terms "length", "width", "up", "down", "left", "right", "horizontal", "top", "bottom", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0020] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0021] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or mutual communication; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0022] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being "above", "above" and "above" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below", "below" and "below" a second feature includes that the first feature is directly below and obliquely below the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0023] The disclosure below provides many different embodiments or examples to realize different structures of the present invention. In order to simplify the disclosure of the present invention, the parts and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present invention. In addition, the present invention can repeat reference numbers and / or reference letters in different examples, and this repetition is for the purpose of simplification and clarity, which itself does not indicate the relationship between the various embodiments and / or settings discussed. In addition, the examples of various specific processes and materials provided by the present invention, but those of ordinary skill in the art can be aware of the application of other processes and / or the use of other materials.

[0024] In the present invention, "preferred" and "better" are only used to describe implementation methods or embodiments with better effects, and it should be understood that they do not constitute a limitation on the scope of protection of the present invention. In the present invention, the technical features described in an open manner include closed technical solutions composed of the listed features, and also include open technical solutions containing the listed features. In the present invention, when involving numerical ranges, unless otherwise specified, the two endpoints of the numerical range are included.

[0025] To solve the above problems, the present invention provides a Micro LED epitaxial wafer, such as Figure 1 As shown, it includes a substrate 100, on which a buffer layer 200, an N-type GaN layer 300, a multi-quantum well layer 400, and a P-type GaN layer 500 are sequentially arranged; The multi-quantum well layer 400 includes a first multi-quantum well layer 410, a second multi-quantum well layer 420 and a third multi-quantum well layer 430 stacked in sequence, the first multi-quantum well layer 410 includes a first quantum barrier layer 411 and a first InGaN quantum well layer 412 stacked alternately, the second multi-quantum well layer 420 includes a second quantum barrier layer 421 and a second InGaN quantum well layer 422 stacked alternately, the third multi-quantum well layer 430 includes a third quantum barrier layer 431 and a third InGaN quantum well layer 432 stacked alternately, the In component content of the second InGaN quantum well layer 422 is greater than the In component content of the first InGaN quantum well layer 412, and the In component content of the second InGaN quantum well layer 422 is greater than the In component content of the third InGaN quantum well layer 432.

[0026] In the Micro LED epitaxial wafer provided by the present invention, the In component content of the second InGaN quantum well layer is greater than the In component content of the first InGaN quantum well layer and the In component content of the third InGaN quantum well layer, the second InGaN quantum well layer has a longer luminescent wavelength, and the second multi-quantum well layer is the main luminescent layer. The quantum well layer of the multi-quantum well layer forms a change in which the In component first increases and then decreases. This structure can reduce the lattice mismatch stress between the second InGaN quantum well layer and the second quantum barrier layer in the second multi-quantum well layer, reduce the defects caused by the large mismatch stress, improve the quality of the main luminescent quantum well region at low operating current density, and thus improve the radiation recombination efficiency of the multi-quantum well layer.

[0027] Specifically, the first multi-quantum well layer 410 includes 2 to 6 periods of alternately stacked first quantum barrier layers 411 and first InGaN quantum well layers 412, the second multi-quantum well layer 420 includes 2 to 8 periods of alternately stacked second quantum barrier layers 421 and second InGaN quantum well layers 422, and the third multi-quantum well layer 430 includes 1 to 3 periods of alternately stacked third quantum barrier layers 431 and third InGaN quantum well layers 432.

[0028] like Figure 2~Figure 4 As shown, the quantum well layer in the multi-quantum well layer will be described in detail below: In some embodiments, the In component content of the first InGaN quantum well layer 412 is 0.05-0.28; the In component content of the second InGaN quantum well layer 422 is 0.1-0.39; and the In component content of the third InGaN quantum well layer 432 is 0.05-0.28. More preferably, the In component content of the first InGaN quantum well layer 412 is 0.1-0.2; the In component content of the second InGaN quantum well layer 422 is 0.2-0.35; and the In component content of the third InGaN quantum well layer 432 is 0.1-0.2. In the above embodiment, by adjusting the In component content of the InGaN quantum well layer, the quantum well layer of the multi-quantum well layer forms a change in which the In component first increases and then decreases. This structure can reduce the lattice mismatch stress between the second InGaN quantum well layer 422 and the second quantum barrier layer 421 in the second multi-quantum well layer 420, improve the quality of the main light-emitting quantum well region under low operating current density, and thus improve the radiation recombination efficiency of the multi-quantum well layer.

[0029] In some embodiments, the thickness of the first InGaN quantum well layer 412 is 2.2 nm to 4.6 nm; the thickness of the second InGaN quantum well layer 422 is 2.2 nm to 4.6 nm; and the thickness of the third InGaN quantum well layer 432 is 2.2 nm to 4.6 nm.

[0030] The specific details of the quantum barrier layer of the multi-quantum well layer are as follows: In some embodiments, the first quantum barrier layer 411 includes a first GaN layer 411a, an Al layer 411b, and a GaN layer 411c. a Ga 1- a N layer 411b, Al x In y Ga 1-x-y N layer 411c, Al b Ga 1-b N layer 411d and second GaN layer 411e; The second quantum barrier layer 421 includes a third GaN layer 421a, an Al α Ga 1-α N layer 421b, Al γ In δ Ga 1-γ-δ N layer 421c, Al β Ga 1-β N layer 421d and fourth GaN layer 421e; The third quantum barrier layer 431 includes a fifth GaN layer 431a, an Al m Ga 1-m N layer 431b, Al j In k Ga 1-j-k N layer 431c, Al n Ga 1-n N layer 431d and sixth GaN layer 431e.

[0031] In some embodiments, a>m>α;x>j>γ;b>n>β;x>y,γ>δ,j>k. Preferably, 0.05≤a≤0.3;0.12≤x≤0.36;0.01≤y≤0.03;0.05≤b≤0.3;0.01≤α≤0.1;0.01<γ≤0.1;0.01<δ≤0.03;0.01≤β≤0.1;0.03≤m≤0.2;0.05≤j≤0.2;0.03≤k≤0.12;0.03≤n≤0.2. More preferably, 0.1≤a≤0.25; 0.2≤x≤0.3; 0.015≤y≤0.025; 0.1≤b≤0.25; 0.02≤α≤0.08; 0.02≤γ≤0.08; 0.015≤δ≤0.025; 0.02≤β≤0.08; 0.05≤m≤0.15; 0.01≤j≤0.15; 0.05≤k≤0.1; 0.05≤n≤0.15. In these embodiments, the Al of the first quantum barrier layer a Ga 1-aN layer and Al b Ga 1-b The Al component content of the N layer is respectively greater than that of the Al m Ga 1-m N layer and Al n Ga 1-n The Al content of the N layer and the Al content of the third quantum barrier layer m Ga 1-m N layer and Al n Ga 1-n The Al content of the N layer is greater than that of the Al α Ga 1-α N layer and Al β Ga 1-β The Al content of the N layer and the Al content of the first quantum barrier layer x In y Ga 1-x-y The Al content of N layer is greater than that of Al in the third quantum barrier layer. j In k Ga 1-j-k Al content in N layer > Al content in the second quantum barrier layer γ In δ Ga 1-γ-δ The Al component content of the N layer. The setting of the above Al component content determines the specific barrier height, that is, the barrier layer of the multi-quantum well layer is designed as a multi-layer structure of high barrier layer + low barrier layer + medium barrier layer. This barrier layer design can confine the carrier electron holes in the second multi-quantum well layer, thereby improving the matching degree of the electron hole concentration in the light-emitting area, that is, the second multi-quantum well layer, and improving the light efficiency of the low working current density of the Micro LED.

[0032] In addition, in some embodiments, the thickness of the first GaN layer 411a is 0.5 nm to 6 nm; a Ga 1-a The thickness of the N layer 411b is 0.3nm~2nm; x In y Ga 1-x-y The thickness of the N layer 411c is 1nm~6nm; b Ga 1-b The thickness of the N layer 411d is 0.3nm~2nm; the thickness of the second GaN layer 411e is 0.5nm~6nm. Preferably, the thickness of the first GaN layer 411a is 1nm~5nm; the thickness of the Al a Ga 1-a The thickness of the N layer 411b is 0.5nm~1.5nm; x In y Ga1-x-y The thickness of the N layer 411c is 2nm~4nm; b Ga 1-b The thickness of the N layer 411 d is 0.5 nm to 1.5 nm; the thickness of the second GaN layer 411 e is 1 nm to 5 nm.

[0033] In some embodiments, the thickness of the third GaN layer 421a is 0.5 nm to 6 nm; α Ga 1-α The thickness of the N layer 421b is 0.3nm~2nm; γ In δ Ga 1-γ-δ The thickness of the N layer 421c is 1 nm to 6 nm; β Ga 1-β The thickness of the N layer 421d is 0.3nm~2nm; the thickness of the fourth GaN layer 421e is 0.5nm~6nm. Preferably, the thickness of the third GaN layer 421a is 1nm~5nm; the thickness of the Al α Ga 1-α The thickness of the N layer 421b is 0.5nm~1.5nm; γ In δ Ga 1-γ-δ The thickness of the N layer 421c is 2nm~4nm; β Ga 1-β The thickness of the N layer 421d is 0.5nm-1.5nm; the thickness of the fourth GaN layer 421e is 1nm-5nm.

[0034] In some embodiments, the thickness of the fifth GaN layer 431a is 0.5 nm to 6 nm; m Ga 1-m The thickness of the N layer 431b is 0.3nm~2nm; j In k Ga 1-j-k The thickness of the N layer 431c is 1nm~6nm; n Ga 1-n The thickness of the N layer 431d is 0.3nm~2nm; the thickness of the sixth GaN layer 431e is 0.5nm~6nm. Preferably, the thickness of the fifth GaN layer 431a is 1nm~5nm; the thickness of the Al m Ga 1-m The thickness of the N layer 431b is 0.5nm~1.5nm; j In k Ga 1-j-k The thickness of the N layer 431c is 2nm~4nm;n Ga 1-n The thickness of the N layer 431d is 0.5nm-1.5nm; the thickness of the sixth GaN layer 431e is 1nm-5nm.

[0035] Furthermore, the doping conditions of the quantum barrier layer are as follows: In some embodiments, the first GaN layer 411a is a Si-doped GaN layer. x In y Ga 1-x-y The N layer 411c is Si-doped Al x In y Ga 1-x-y N layer, the second GaN layer 411e is a Si-doped GaN layer; The third GaN layer 421a is a Si-doped GaN layer. γ In δ Ga 1-γ-δ The N layer 421c is Si-doped Al γ In δ Ga 1-γ-δ N layer, the fourth GaN layer 421e is a Si-doped GaN layer; The fifth GaN layer 431a is a Mg-doped GaN layer. j In k Ga 1-j-k The N layer 431c is Mg-doped Al j In k Ga 1-j-k N layer, the sixth GaN layer 431e is a Mg-doped GaN layer; The Al a Ga 1-a N layer 411b, Al b Ga 1-b N layer 411d, Al α Ga 1-α N layer 421b, Al β Ga 1-β N layer 421d, Al m Ga 1- m N layer 431b and Al n Ga 1-n The N layer 431d is not intentionally doped.

[0036] In some embodiments, the Si doping concentration of the first GaN layer 411a is 1.15×10 17 atoms / cm 3 ~2.8×10 18atoms / cm 3 ; The Al x In y Ga 1-x-y The Si doping concentration of the N layer 411c is 1.02×10 17 atoms / cm 3 ~2.3×10 18 atoms / cm 3 ; The Si doping concentration of the second GaN layer 411e is 1.15×10 17 atoms / cm 3 ~2.8×10 18 atoms / cm 3 Preferably, the Si doping concentration of the first GaN layer 411a is 2×10 17 atoms / cm 3 ~1×10 18 atoms / cm 3 ; The Al x In y Ga 1-x-y The Si doping concentration of the N layer 411c is 2×10 17 atoms / cm 3 ~1×10 18 atoms / cm 3 ; The Si doping concentration of the second GaN layer 411e is 2×10 17 atoms / cm 3 ~1×10 18 atoms / cm 3 .

[0037] In some embodiments, the Si doping concentration of the third GaN layer 421a is 0.8×10 17 atoms / cm 3 ~1.6×10 18 atoms / cm 3 ; The Al γ In δ Ga 1-γ-δ The Si doping concentration of the N layer 421c is 0.5×10 17 atoms / cm 3 ~1.2×10 18 atoms / cm 3 The Si doping concentration of the fourth GaN layer 421e is 0.8×10 17 atoms / cm 3 ~1.6×10 18 atoms / cm 3Preferably, the Si doping concentration of the third GaN layer 421a is 1×10 17 atoms / cm 3 ~1×10 18 atoms / cm 3 ; The Al γ In δ Ga 1-γ-δ The Si doping concentration of the N layer 421c is 1×10 17 atoms / cm 3 ~1×10 18 atoms / cm 3 The Si doping concentration of the fourth GaN layer 421e is 1×10 17 atoms / cm 3 ~1×10 18 atoms / cm 3 .

[0038] In some embodiments, the Mg doping concentration of the fifth GaN layer 431a is 1.6×10 18 atoms / cm 3 ~2.5×10 19 atoms / cm 3 ; The Al j In k Ga 1-j-k The Mg doping concentration of the N layer 431c is 3.2×10 18 atoms / cm 3 ~5.8×10 19 atoms / cm 3 The Mg doping concentration of the sixth GaN layer 431e is 1.6×10 18 atoms / cm 3 ~2.5×10 19 atoms / cm 3 Preferably, the Mg doping concentration of the fifth GaN layer 431a is 2×10 18 atoms / cm 3 ~1×10 19 atoms / cm 3 ; The Al j In k Ga 1-j-k The Mg doping concentration of the N layer 431c is 4×10 18 atoms / cm 3 ~4×10 19 atoms / cm 3 The Mg doping concentration of the sixth GaN layer 431e is 2×10 18atoms / cm 3 ~1×10 19 atoms / cm 3 .

[0039] In the above embodiment, the quantum barrier layer is designed as a multilayer structure of doped + non-doped + doped + non-doped + doped. The barrier layer of this structure can improve the current expansibility of the multi-quantum well layer and improve the luminous uniformity and reliability of the product. At the same time, the first multi-quantum well layer 410 and the second multi-quantum well layer 420 are doped with Si elements, and the third multi-quantum well layer 430 is doped with Mg elements, which can provide part of the electrons and holes to the second multi-quantum well layer 420 to participate in the radiation recombination luminescence, so as to improve the matching degree of the electron-hole concentration and improve the light efficiency of Micro LED at low working current density.

[0040] Accordingly, the present invention provides a method for preparing a Micro LED epitaxial wafer, comprising the following steps: S1, providing a substrate 100; In some embodiments, the substrate 100 may be selected from one of a sapphire substrate, a SiO2 sapphire composite substrate, a silicon substrate, a silicon carbide substrate, a gallium nitride substrate, and a zinc oxide substrate. Preferably, the substrate 100 is a sapphire substrate, which is a commonly used GaN-based LED substrate material. The sapphire substrate has a mature preparation process, a low price, is easy to clean and handle, and has good stability at high temperatures.

[0041] S2, sequentially depositing a buffer layer 200, an N-type GaN layer 300, a multi-quantum well layer 400, and a P-type GaN layer 500 on the substrate 100; The multi-quantum well layer 400 includes a first multi-quantum well layer 410, a second multi-quantum well layer 420 and a third multi-quantum well layer 430 stacked in sequence, the first multi-quantum well layer 410 includes a first quantum barrier layer 411 and a first InGaN quantum well layer 412 stacked alternately, the second multi-quantum well layer 420 includes a second quantum barrier layer 421 and a second InGaN quantum well layer 422 stacked alternately, the third multi-quantum well layer 430 includes a third quantum barrier layer 431 and a third InGaN quantum well layer 432 stacked alternately, the In component content of the second InGaN quantum well layer 422 is greater than the In component content of the first InGaN quantum well layer 412, and the In component content of the second InGaN quantum well layer 422 is greater than the In component content of the third InGaN quantum well layer 432.

[0042] Specifically, the above step S2 specifically includes the following steps: S21 , depositing the buffer layer 200 on the substrate 100 .

[0043] In some embodiments, an AlN buffer layer is deposited in an applied material PVD process. The AlN buffer layer provides nucleation centers with the same orientation as the substrate, releases the stress caused by the lattice mismatch between GaN and the substrate and the thermal stress caused by the mismatch in thermal expansion coefficients, provides a flat nucleation surface for further growth, reduces the contact angle of nucleation growth, and enables the island-like grown GaN grains to be connected into a surface within a smaller thickness, thus transforming into two-dimensional epitaxial growth.

[0044] S22 , depositing the N-type GaN layer 300 on the buffer layer 200 .

[0045] In some embodiments, the temperature of the reaction chamber is controlled at 1050° C. to 1200° C., the pressure is controlled at 100 torr to 600 torr, and an N source, a Ga source, and a Si source are introduced to grow the N-type GaN layer.

[0046] S23 , depositing the multi-quantum well layer 400 on the N-type GaN layer 300 .

[0047] In some embodiments, the multi-quantum well layer is prepared by the following method: The first multi-quantum well layer 410 , the second multi-quantum well layer 420 , and the third multi-quantum well layer 430 are grown in sequence to obtain a multi-quantum well layer.

[0048] In some embodiments, the first multi-quantum well layer 410 is prepared by the following method: The first quantum barrier layer 411 and the first InGaN quantum well layer 412 are grown alternately and periodically to obtain the first multi-quantum well layer 410 .

[0049] In some embodiments, the first quantum barrier layer 411 is prepared by the following method: The growth temperature of the reaction chamber is maintained at 820°C to 935°C, the growth pressure is 50 torr to 390 torr, and N source, Ga source, and Si source are introduced to grow the first GaN layer; Then, the growth temperature of the reaction chamber is maintained at 820℃~935℃, the growth pressure is 50torr~390torr, and N source, Ga source, and Al source are introduced to grow Al a Ga 1-a N layers; Then, the growth temperature of the reaction chamber is maintained at 820℃~935℃, the growth pressure is 50torr~390torr, and N source, Ga source, Al source, In source, and Si source are introduced to grow Al x In y Ga 1-x-y N layers; Then, the growth temperature of the reaction chamber is maintained at 820℃~935℃, the growth pressure is 50torr~390torr, and N source, Ga source, and Al source are introduced to grow Al b Ga 1-b N layers; Then, the growth temperature of the reaction chamber is maintained at 820° C. to 935° C., the growth pressure is maintained at 50 torr to 390 torr, and N source, Ga source, and Si source are introduced to grow a second GaN layer.

[0050] In some embodiments, the first InGaN quantum well layer 412 is made by the following method: The growth temperature of the reaction chamber is maintained at 668° C. to 920° C., the growth pressure is maintained at 50 torr to 390 torr, and N source, Ga source, and In source are introduced to grow the first InGaN quantum well layer 412 .

[0051] In some embodiments, the second multi-quantum well layer 420 is prepared by the following method: The second quantum barrier layer 421 and the second InGaN quantum well layer 422 are grown alternately and periodically to obtain the second multi-quantum well layer 420 .

[0052] In some embodiments, the second quantum barrier layer 421 is prepared by the following method: The growth temperature of the reaction chamber is maintained at 820°C to 935°C, the growth pressure is maintained at 50 torr to 390 torr, and N source, Ga source, and Si source are introduced to grow the third GaN layer; Then, the growth temperature of the reaction chamber is maintained at 820℃~935℃, the growth pressure is 50torr~390torr, and N source, Ga source, and Al source are introduced to grow Al α Ga 1-α N layers; Then, the growth temperature of the reaction chamber is maintained at 820℃~935℃, the growth pressure is 50torr~390torr, and N source, Ga source, Al source, In source, and Si source are introduced to grow Al γ In δ Ga 1-γ-δ N layers; Then, the growth temperature of the reaction chamber is maintained at 820℃~935℃, the growth pressure is 50torr~390torr, and N source, Ga source, and Al source are introduced to grow Al β Ga 1-β N layers; Then, the growth temperature of the reaction chamber is maintained at 820° C. to 935° C., the growth pressure is maintained at 50 torr to 390 torr, and an N source, a Ga source, and a Si source are introduced to grow a fourth GaN layer.

[0053] In some embodiments, the second InGaN quantum well layer 422 is made by the following method: The growth temperature of the reaction chamber is maintained at 668° C. to 920° C., the growth pressure is maintained at 50 torr to 390 torr, and N source, Ga source, and In source are introduced to grow the second InGaN quantum well layer 422 .

[0054] In some embodiments, the third multi-quantum well layer 430 is prepared by the following method: The third quantum barrier layer 431 and the third InGaN quantum well layer 432 are grown alternately and periodically to obtain the second multi-quantum well layer 420 .

[0055] In some embodiments, the third quantum barrier layer 431 is prepared by the following method: The growth temperature of the reaction chamber is maintained at 820° C. to 935° C., the growth pressure is maintained at 50 torr to 390 torr, and N source, Ga source, and Mg source are introduced to grow the fifth GaN layer; Then, the growth temperature of the reaction chamber is maintained at 820℃~935℃, the growth pressure is 50torr~390torr, and N source, Ga source, and Al source are introduced to grow Al m Ga 1-m N layers; Then, the growth temperature of the reaction chamber is maintained at 820℃~935℃, the growth pressure is 50torr~390torr, and N source, Ga source, Al source, In source, and Mg source are introduced to grow Al j In k Ga 1-j-k N layers; Then, the growth temperature of the reaction chamber is maintained at 820℃~935℃, the growth pressure is 50torr~390torr, and N source, Ga source, and Al source are introduced to grow Al n Ga 1-n N layers; Then, the growth temperature of the reaction chamber is maintained at 820° C. to 935° C., the growth pressure is maintained at 50 torr to 390 torr, and an N source, a Ga source, and a Mg source are introduced to grow a sixth GaN layer.

[0056] In some embodiments, the third InGaN quantum well layer 432 is made by the following method: The growth temperature of the reaction chamber is maintained at 668° C. to 920° C., the growth pressure is maintained at 50 torr to 390 torr, and N source, Ga source, and In source are introduced to grow the third InGaN quantum well layer 432 .

[0057] In some embodiments, after the first multi-quantum well layer is grown, a first annealing treatment is performed on the surface, and the first annealing treatment includes: The temperature of the reaction chamber is maintained at 820°C to 1080°C and the pressure is maintained at 50 torr to 390 torr, and a mixed gas of N2 and H2 is introduced into the reaction chamber and maintained for 5s to 50s to complete the first operation; Stop introducing the N2 and H2 mixed gas to complete the second operation; The first operation and the second operation are alternately completed 3 to 15 times to complete the first annealing treatment.

[0058] After the deposition of the first multi-quantum well layer is completed, a first annealing treatment is performed to decompose defects such as materials with poor surface crystallization quality and In clusters with a high In component, which is beneficial to improving the crystal quality of the material. At the same time, a slightly rough material surface is formed, which can reduce the in-plane total reflection and light absorption loss of photons in the semiconductor material and improve the light extraction efficiency.

[0059] Further, in some embodiments, after the third multi-quantum well layer is grown, a second annealing treatment is performed on the surface, and the second annealing treatment includes: The temperature of the reaction chamber is maintained at 820°C to 1080°C and the pressure is maintained at 50 torr to 390 torr, and a mixed gas of N2 and H2 is introduced into the reaction chamber and maintained for 10s to 100s to complete the third operation; Stop introducing the N2 and H2 mixed gas to complete the fourth operation; The third operation and the fourth operation are alternately completed 3 to 15 times to complete the second annealing treatment.

[0060] After the deposition of the third multi-quantum well layer is completed, a second annealing treatment is performed to decompose defects such as materials with poor surface crystallization quality and clusters of In with a high In component, which is beneficial to improving the crystal quality of the material. At the same time, a slightly rough material surface is formed, which can reduce the in-plane total reflection and light absorption loss of photons in the semiconductor material and improve the light extraction efficiency.

[0061] S24 , depositing the P-type GaN layer 500 on the multi-quantum well layer 400 .

[0062] In some embodiments, the temperature of the reaction chamber is controlled at 900° C. to 1050° C., the pressure is controlled at 100 torr to 600 torr, and an N source, a Mg source, and a Ga source are introduced to grow the P-type GaN layer.

[0063] Accordingly, the present invention also provides a Micro LED chip, which includes the above-mentioned Micro LED epitaxial wafer. Micro LED epitaxial wafer is the basic material for the manufacture of Micro LED chips, and the quality and characteristics of Micro LED epitaxial wafer directly affect the performance and yield of the final Micro LED chip.

[0064] The present invention is further described below with specific embodiments: Example 1 This embodiment provides a Micro LED epitaxial wafer, including a substrate, on which a buffer layer, an N-type GaN layer, a multi-quantum well layer, and a P-type GaN layer are sequentially provided; The multi-quantum well layer includes a first multi-quantum well layer, a second multi-quantum well layer and a third multi-quantum well layer stacked in sequence, the first multi-quantum well layer includes a first quantum barrier layer and a first InGaN quantum well layer stacked alternately, the second multi-quantum well layer includes a second quantum barrier layer and a second InGaN quantum well layer stacked alternately, the third multi-quantum well layer includes a third quantum barrier layer and a third InGaN quantum well layer stacked alternately, the In component content of the second InGaN quantum well layer is greater than the In component content of the first InGaN quantum well layer, and the In component content of the second InGaN quantum well layer is greater than the In component content of the third InGaN quantum well layer.

[0065] The In component content of the first InGaN quantum well layer is 0.1; the In component content of the second InGaN quantum well layer is 0.25; and the In component content of the third InGaN quantum well layer is 0.1.

[0066] The first quantum barrier layer includes a first Si-doped GaN layer, an Al a Ga 1-a N layer, Si doped Al x In y Ga 1-x-y N layer, Al b Ga 1-b N layer and a second Si-doped GaN layer; The second quantum barrier layer includes a third Si-doped GaN layer, an Al α Ga 1-α N layer, Si doped Al γ In δ Ga 1-γ-δ N layer, Al β Ga 1-β N layer and a fourth Si-doped GaN layer; The third quantum barrier layer includes a fifth Mg-doped GaN layer, an Al m Ga 1-m N layer, Mg doped Al j In k Ga 1-j-k N layer, Al n Ga 1-n N layer and a sixth Mg-doped GaN layer; a: 0.25, x: 0.2, y: 0.02, b: 0.25, α: 0.07, γ: 0.05, δ: 0.02, β: 0.07, m: 0.15, j: 0.1, k: 0.05, n: 0.15.

[0067] The Si doping concentration of the first GaN layer is 5×10 17 atoms / cm 3 ; The Al x In y Ga 1-x-y The Si doping concentration of the N layer is 5×10 17 atoms / cm 3 ; The Si doping concentration of the second GaN layer is 5×10 17 atoms / cm 3 ; The Si doping concentration of the third GaN layer is 2×10 17 atoms / cm 3 ; The Al γ In δ Ga 1-γ-δ The Si doping concentration of the N layer is 2×10 17 atoms / cm 3 ; The Si doping concentration of the fourth GaN layer is 2×10 17 atoms / cm 3 ; The Mg doping concentration of the fifth GaN layer is 5×10 18 atoms / cm 3 ; The Al j In k Ga 1-j-k The Mg doping concentration of the N layer is 5×10 18 atoms / cm 3 ; The Mg doping concentration of the sixth GaN layer is 5×10 18 atoms / cm 3 .

[0068] Example 2 This embodiment provides a Micro LED epitaxial wafer, including a substrate, on which a buffer layer, an N-type GaN layer, a multi-quantum well layer, and a P-type GaN layer are sequentially provided; The multi-quantum well layer includes a first multi-quantum well layer, a second multi-quantum well layer and a third multi-quantum well layer stacked in sequence, the first multi-quantum well layer includes a first quantum barrier layer and a first InGaN quantum well layer stacked alternately, the second multi-quantum well layer includes a second quantum barrier layer and a second InGaN quantum well layer stacked alternately, the third multi-quantum well layer includes a third quantum barrier layer and a third InGaN quantum well layer stacked alternately, the In component content of the second InGaN quantum well layer is greater than the In component content of the first InGaN quantum well layer, and the In component content of the second InGaN quantum well layer is greater than the In component content of the third InGaN quantum well layer.

[0069] The In component content of the first InGaN quantum well layer is 0.15; the In component content of the second InGaN quantum well layer is 0.3; and the In component content of the third InGaN quantum well layer is 0.15.

[0070] The first quantum barrier layer includes a first Si-doped GaN layer, an Al a Ga 1-a N layer, Si doped Al x In y Ga 1-x-y N layer, Al b Ga 1-b N layer and a second Si-doped GaN layer; The second quantum barrier layer includes a third Si-doped GaN layer, an Al α Ga 1-α N layer, Si doped Al γ In δ Ga 1-γ-δ N layer, Al β Ga 1-β N layer and a fourth Si-doped GaN layer; The third quantum barrier layer includes a fifth Mg-doped GaN layer, an Al m Ga 1-m N layer, Mg doped Al j In k Ga 1-j-k N layer, Al n Ga 1-n N layer and a sixth Mg-doped GaN layer; a: 0.3, x: 0.35, y: 0.03, b: 0.3, α: 0.1, γ: 0.1, δ: 0.03, β: 0.1, m: 0.2, j: 0.2, k: 0.12, n: 0.2.

[0071] The Si doping concentration of the first GaN layer is 2×10 17 atoms / cm 3 ; The Al x In y Ga 1-x-y The Si doping concentration of the N layer is 2×10 17 atoms / cm 3 ; The Si doping concentration of the second GaN layer is 2×10 17 atoms / cm 3 ; The Si doping concentration of the third GaN layer is 0.8×10 17 atoms / cm 3 ; The Al γ In δ Ga 1-γ-δ The Si doping concentration of the N layer is 0.5×10 17 atoms / cm 3 ; The Si doping concentration of the fourth GaN layer is 0.8×10 17 atoms / cm 3 ; The Mg doping concentration of the fifth GaN layer is 2×10 18 atoms / cm 3 ; The Al j In k Ga 1-j-k The Mg doping concentration of the N layer is 3.5×10 18 atoms / cm 3 ; The Mg doping concentration of the sixth GaN layer is 2×10 18 atoms / cm 3 .

[0072] Example 3 This embodiment provides a Micro LED epitaxial wafer, including a substrate, on which a buffer layer, an N-type GaN layer, a multi-quantum well layer, and a P-type GaN layer are sequentially provided; The multi-quantum well layer includes a first multi-quantum well layer, a second multi-quantum well layer and a third multi-quantum well layer stacked in sequence, the first multi-quantum well layer includes a first quantum barrier layer and a first InGaN quantum well layer stacked alternately, the second multi-quantum well layer includes a second quantum barrier layer and a second InGaN quantum well layer stacked alternately, the third multi-quantum well layer includes a third quantum barrier layer and a third InGaN quantum well layer stacked alternately, the In component content of the second InGaN quantum well layer is greater than the In component content of the first InGaN quantum well layer, and the In component content of the second InGaN quantum well layer is greater than the In component content of the third InGaN quantum well layer.

[0073] The In component content of the first InGaN quantum well layer is 0.08; the In component content of the second InGaN quantum well layer is 0.15; and the In component content of the third InGaN quantum well layer is 0.09.

[0074] The first quantum barrier layer includes a first Si-doped GaN layer, an Al a Ga 1-a N layer, Si doped Al x In y Ga 1-x-y N layer, Al b Ga 1-b N layer and a second Si-doped GaN layer; The second quantum barrier layer includes a third Si-doped GaN layer, an Al α Ga 1-α N layer, Si doped Al γ In δ Ga 1-γ-δ N layer, Al β Ga 1-β N layer and a fourth Si-doped GaN layer; The third quantum barrier layer includes a fifth Mg-doped GaN layer, an Al m Ga 1-m N layer, Mg doped Al j In k Ga 1-j-k N layer, Al n Ga 1-n N layer and a sixth Mg-doped GaN layer; a: 0.12, x: 0.22, y: 0.01, b: 0.12, α: 0.02, γ: 0.03, δ: 0.01, β: 0.02, m: 0.08, j: 0.09, k: 0.03, n: 0.08.

[0075] The Si doping concentration of the first GaN layer is 2×10 18 atoms / cm 3 ; The Al x In y Ga 1-x-y The Si doping concentration of the N layer is 2×10 18 atoms / cm 3 ; The Si doping concentration of the second GaN layer is 2×10 18 atoms / cm 3 ; The Si doping concentration of the third GaN layer is 1×10 18 atoms / cm 3 ; The Al γ In δ Ga 1-γ-δ The Si doping concentration of the N layer is 1×10 18 atoms / cm 3 ; The Si doping concentration of the fourth GaN layer is 1×10 18 atoms / cm 3 ; The Mg doping concentration of the fifth GaN layer is 2×10 19 atoms / cm 3 ; The Al j In k Ga 1-j-k The Mg doping concentration of the N layer is 5×10 19 atoms / cm 3 ; The Mg doping concentration of the sixth GaN layer is 2×10 19 atoms / cm 3 .

[0076] Comparative Example 1 This comparative example provides a Micro LED epitaxial wafer, which is different from Example 1 in that: its multi-quantum well layer includes alternately stacked GaN quantum barrier layers and InGaN quantum well layers, and the rest is the same as Example 1.

[0077] The Micro LED epitaxial wafers prepared in Example 1 to Example 3 and Comparative Example 1 were prepared into Micro LED chips using the same chip process conditions and tested. The specific test results are shown in Table 1.

[0078] Table 1 Performance test results of Micro LED chips prepared in Examples 1 to 3 and Comparative Example 1

[0079] In the Micro LED epitaxial wafer provided by the present invention, the multi-quantum well layer includes a first multi-quantum well layer, a second multi-quantum well layer and a third multi-quantum well layer stacked in sequence, the In component content of the second InGaN quantum well layer is greater than the In component content of the first InGaN quantum well layer, and the In component content of the second InGaN quantum well layer is greater than the In component content of the third InGaN quantum well layer. In the present invention, the In component content of the second InGaN quantum well layer is greater than the In component content of the first InGaN quantum well layer and the In component content of the third InGaN quantum well layer, the light emission wavelength of the second InGaN quantum well layer is longer, and the second multi-quantum well layer is the main light-emitting layer. The quantum well layer of the multi-quantum well layer forms a change in which the In component first increases and then decreases. This structure can reduce the lattice mismatch stress between the second InGaN quantum well layer and the second quantum barrier layer in the second multi-quantum well layer, reduce the defects caused by the large mismatch stress, improve the quality of the main light-emitting quantum well region under low working current density, and thus improve the radiation recombination efficiency of the multi-quantum well layer.

[0080] In the description of this specification, the description with reference to the terms "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiments or examples are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0081] The above is a preferred embodiment of the invention. It should be pointed out that a person skilled in the art can make several improvements and modifications without departing from the principle of the invention. These improvements and modifications are also considered to be within the scope of protection of the invention.

Claims

1. A Micro LED epitaxial wafer, characterized in that: It comprises a substrate, on which a buffer layer, an N-type GaN layer, a multi-quantum well layer, and a P-type GaN layer are sequentially arranged; The multi-quantum well layer includes a first multi-quantum well layer, a second multi-quantum well layer and a third multi-quantum well layer stacked in sequence, the first multi-quantum well layer includes a first quantum barrier layer and a first InGaN quantum well layer stacked alternately, the second multi-quantum well layer includes a second quantum barrier layer and a second InGaN quantum well layer stacked alternately, the third multi-quantum well layer includes a third quantum barrier layer and a third InGaN quantum well layer stacked alternately, the In component content of the second InGaN quantum well layer is greater than the In component content of the first InGaN quantum well layer, and the In component content of the second InGaN quantum well layer is greater than the In component content of the third InGaN quantum well layer.

2. The Micro LED epitaxial wafer according to claim 1, wherein: The In component content of the first InGaN quantum well layer is 0.05-0.28; The In component content of the second InGaN quantum well layer is 0.1-0.39; The In component content of the third InGaN quantum well layer is 0.05-0.

28.

3. The Micro LED epitaxial wafer according to claim 1, wherein: The first quantum barrier layer includes a first GaN layer, an Al a Ga 1-a N layer, Al x In y Ga 1-x-y N layer, Al b Ga 1-b N layer and a second GaN layer; The second quantum barrier layer includes a third GaN layer, an Al α Ga 1-α N layer, Al γ In δ Ga 1-γ-δ N layer, Al β Ga 1-β N layer and a fourth GaN layer; The third quantum barrier layer includes a fifth GaN layer, an Al m Ga 1-m N layer, Al j In k Ga 1-j-k N layer, Al n Ga 1-n N layer and a sixth GaN layer.

4. The Micro LED epitaxial wafer according to claim 3, wherein: a>m>α; x>j>γ; b>n>β; x>y,γ>δ,j>k.

5. The Micro LED epitaxial wafer according to claim 4, wherein: 0.05≤a≤0.3; 0.12≤x≤0.36; 0.01≤y≤0.03; 0.05≤b≤0.3; 0.01≤α≤0.1; 0.01<γ≤0.1; 0.01<δ≤0.03; 0.01≤β≤0.1; 0.03≤m≤0.2; 0.05≤j≤0.2; 0.03≤k≤0.12; 0.03≤n≤0.

2.

6. The Micro LED epitaxial wafer according to claim 3, wherein: The first GaN layer is a Si-doped GaN layer, and the Al x In y Ga 1-x-y The N layer is Si-doped Al x In y Ga 1-x-y N layer, the second GaN layer is a Si-doped GaN layer; The third GaN layer is a Si-doped GaN layer, and the Al γ In δ Ga 1-γ-δ The N layer is Si-doped Al γ In δ Ga 1-γ-δ N layer, the fourth GaN layer is a Si-doped GaN layer; The fifth GaN layer is a Mg-doped GaN layer, and the Al j In k Ga 1-j-k The N layer is Mg-doped Al j In k Ga 1-j-k N layer, the sixth GaN layer is a Mg-doped GaN layer; The Al a Ga 1-a N layer, Al b Ga 1-b N layer, Al α Ga 1-α N layer, Al β Ga 1-β N layer, Al m Ga 1-m N layer and Al n Ga 1-n The N layer is not intentionally doped.

7. The Micro LED epitaxial wafer according to claim 6, wherein: The Si doping concentration of the first GaN layer is 1.15×10 17 atoms / cm 3 ~2.8×10 18 atoms / cm 3 ; The Al x In y Ga 1-x-y The Si doping concentration of the N layer is 1.02×10 17 atoms / cm 3 ~2.3×10 18 atoms / cm 3 ; The Si doping concentration of the second GaN layer is 1.15×10 17 atoms / cm 3 ~2.8×10 18 atoms / cm 3 ; The Si doping concentration of the third GaN layer is 0.8×10 17 atoms / cm 3 ~1.6×10 18 atoms / cm 3 ; The Al γ In δ Ga 1-γ-δ The Si doping concentration of the N layer is 0.5×10 17 atoms / cm 3 ~1.2×10 18 atoms / cm 3 ; The Si doping concentration of the fourth GaN layer is 0.8×10 17 atoms / cm 3 ~1.6×10 18 atoms / cm 3 ; The Mg doping concentration of the fifth GaN layer is 1.6×10 18 atoms / cm 3 ~2.5×10 19 atoms / cm 3 ; The Al j In k Ga 1-j-k The Mg doping concentration of the N layer is 3.2×10 18 atoms / cm 3 ~5.8×10 19 atoms / cm 3 ; The Mg doping concentration of the sixth GaN layer is 1.6×10 18 atoms / cm 3 ~2.5×10 19 atoms / cm 3 .

8. A method for preparing a Micro LED epitaxial wafer according to any one of claims 1 to 7, characterized in that: The following steps are involved: S1. providing a substrate; S2, depositing a buffer layer, an N-type GaN layer, a multi-quantum well layer, and a P-type GaN layer on the substrate in sequence; The multi-quantum well layer includes a first multi-quantum well layer, a second multi-quantum well layer and a third multi-quantum well layer stacked in sequence, the first multi-quantum well layer includes a first quantum barrier layer and a first InGaN quantum well layer stacked alternately, the second multi-quantum well layer includes a second quantum barrier layer and a second InGaN quantum well layer stacked alternately, the third multi-quantum well layer includes a third quantum barrier layer and a third InGaN quantum well layer stacked alternately, the In component content of the second InGaN quantum well layer is greater than the In component content of the first InGaN quantum well layer, and the In component content of the second InGaN quantum well layer is greater than the In component content of the third InGaN quantum well layer.

9. The method for preparing a Micro LED epitaxial wafer according to claim 8, wherein: After the growth of the first multi-quantum well layer is completed, a first annealing treatment is performed on the surface, and the first annealing treatment includes: The temperature of the reaction chamber is maintained at 820°C to 1080°C and the pressure is maintained at 50 torr to 390 torr, and a mixed gas of N2 and H2 is introduced into the reaction chamber and maintained for 5s to 50s to complete the first operation; Stop introducing the N2 and H2 mixed gas to complete the second operation; The first operation and the second operation are alternately completed 3 to 15 times to complete the first annealing treatment.

10. The method for preparing a Micro LED epitaxial wafer according to claim 8, wherein: After the third multi-quantum well layer is grown, a second annealing treatment is performed on the surface, and the second annealing treatment includes: The temperature of the reaction chamber is maintained at 820°C to 1080°C and the pressure is maintained at 50 torr to 390 torr, and a mixed gas of N2 and H2 is introduced into the reaction chamber and maintained for 10s to 100s to complete the third operation; Stop introducing the N2 and H2 mixed gas to complete the fourth operation; The third operation and the fourth operation are alternately completed 3 to 15 times to complete the second annealing treatment.

11. A Micro LED chip, characterized in that: The Micro LED chip includes the Micro LED epitaxial wafer as described in any one of claims 1 to 7.

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