Display device and method for setting the same

Abstract

A display device and a method for setting the same are provided. The display device includes: an emission area; a light emitting element in the emission region; a first bank layer having a side surface exposed to the emission region opening; a second bank layer protruding more than a side surface of the first bank layer at the emission area opening, and including an upper surface; a first inorganic pattern in the first emission region opening and spaced apart from an upper surface of the second bank layer; a second inorganic pattern in the second emission region opening and spaced apart from each of the first inorganic pattern and an upper surface of the second bank layer; and a dam on the second bank layer between the first inorganic pattern and the second inorganic pattern, and spaced apart from the first inorganic pattern and the second inorganic pattern.

Description

[0001] This application claims priority to and all benefits derived from Korean Patent Application No. 10-2023-0088853, filed on Jul. 10, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present disclosure relates to a display device and a method for setting the display device. Background Art

[0003] With the development of the information society, the demand for display devices for displaying images has increased and diversified. For example, display devices have been applied to various electronic devices such as smart phones, digital cameras, laptop computers, navigation devices, and smart TVs. The display device may be a flat panel display device such as a liquid crystal display device, a field emission display device, or an organic light emitting display device. Among such flat panel display devices, since each of the pixels of the display panel includes a light emitting element that can emit light by itself, the light emitting display device can display an image without a backlight unit that provides light to the display panel.

[0004] The display device has been applied to a glasses-type device for providing virtual reality and augmented reality. The display device of such a glasses-type device is implemented in a very small size of about 2 inches or less to be applied to the glasses-type device, but should have a high pixel integration so as to be implemented with a high resolution. For example, the display device of a relatively small electronic device may have a high pixel integration of 400 pixels per inch (PPI) or more. Summary of the invention

[0005] When the display device of an electronic device is implemented in a very small size but with a relatively high pixel integration, the plane area of ​​the light emitting region in which the light emitting element of the display device is arranged is reduced or minimized. Therefore, it is difficult to implement light emitting elements separated from each other for each emission region through a mask process.

[0006] One or more embodiments of the present disclosure provide a display device capable of forming light emitting elements separated from each other for each emission region without a mask process.

[0007] Aspects of the present disclosure also provide a display device in which emission deviation of each pixel that may occur due to penetration of an etchant into a light emitting element in an etching process performed during a process for manufacturing the display device is reduced.

[0008] However, aspects of the present disclosure are not limited to those set forth herein. The above and other aspects of the present disclosure will become more apparent to those skilled in the art to which the present disclosure pertains by referring to the detailed description of the present disclosure given below.

[0009] According to aspects of the present disclosure, a display device includes: a first pixel electrode and a second pixel electrode, which are arranged on a substrate and are spaced apart from each other; a pixel defining film, which is arranged on the substrate and exposes the first pixel electrode and the second pixel electrode; a first light-emitting layer and a first common electrode, the first light-emitting layer is arranged on the first pixel electrode, and the first common electrode is arranged on the first light-emitting layer; a second light-emitting layer and a second common electrode, the second light-emitting layer is arranged on the second pixel electrode, and the second common electrode is arranged on the second light-emitting layer; a first embankment layer, which is arranged on the pixel defining film; a second embankment layer, which is arranged on the first embankment layer and has a side surface that protrudes much more than a side surface of the first embankment layer; a first inorganic layer, which is arranged on the first common electrode and the second embankment layer and is spaced apart from an upper surface of the second embankment layer; a second inorganic layer, which is arranged on the second common electrode and the second embankment layer, is spaced apart from an upper surface of the second embankment layer and is spaced apart from the first inorganic layer; and a dam, which is arranged on the second embankment layer and is spaced apart from the first inorganic layer and the second inorganic layer.

[0010] The dam may not overlap the first inorganic layer and the second inorganic layer in a thickness direction of the substrate.

[0011] The display device may further include an organic encapsulation layer disposed in a space between the first inorganic layer and an upper surface of the second bank layer spaced apart from each other and in a space between the second inorganic layer and an upper surface of the second bank layer spaced apart from each other.

[0012] A distance between the first inorganic layer and the dam may be about 0.75 to about 1.25 times the thickness of the first light emitting layer.

[0013] The distance between the first inorganic layer and the bank may be about 1000 angstroms (Å) to about 3000 Å.

[0014] The thickness of the first light emitting layer may be from about 1500Å to about 2500Å.

[0015] A maximum vertical distance from the substrate to the dam may be smaller than a maximum vertical distance from the substrate to the first inorganic layer.

[0016] The thickness of the dam may be from about 1000Å to about 3000Å.

[0017] The first common electrode and the second common electrode may be spaced apart from each other, and the first common electrode and the second common electrode may contact a side surface of the first bank layer.

[0018] The dam may be made of a material different from that of the organic encapsulation layer.

[0019] The dam may include one or more selected from polyimide, polyamide, benzocyclobutene, phenolic resin, acrylic resin, methacrylic resin, polyisoprene, vinyl-based resin, epoxy-based resin, urethane-based resin, cellulose-based resin, and perylene-based resin.

[0020] The first inorganic layer may contact a lower surface of the second bank layer adjacent to the first common electrode, and the second inorganic layer may contact a lower surface of the second bank layer adjacent to the second common electrode.

[0021] The pixel defining film may be spaced apart from an upper surface of the first pixel electrode.

[0022] The display device may further include a residual pattern disposed in a space between the pixel defining film and an upper surface of the first pixel electrode that are spaced apart from each other.

[0023] According to aspects of the present disclosure, a method for setting up a display device includes: forming (or setting) a plurality of pixel electrodes and a sacrificial layer on a substrate; forming a pixel defining material layer on the sacrificial layer; forming a first embankment material layer on the pixel defining material layer; and forming a second embankment material layer on the first embankment material layer, wherein a plurality of pixel electrodes are spaced apart from each other, and the sacrificial layer is disposed on the pixel electrodes; exposing the pixel defining material layer by etching the first embankment material layer and the second embankment material layer in an area overlapping with the pixel electrodes; etching the side surface of the first embankment material layer so that a portion of the lower surface of the second embankment material layer is exposed; forming a dam on the second embankment layer; exposing the pixel electrode by etching the exposed pixel defining material layer and the sacrificial layer; and forming a first light emitting layer on the first pixel electrode of the pixel electrodes; forming a first common electrode on the first light emitting layer; and forming a first inorganic material layer on the first common electrode.

[0024] In the step of forming the dam on the second bank layer, a material of the dam may be applied onto the second bank layer by slit coating, spin coating, or inkjet printing, and the dam may be patterned by photolithography.

[0025] In the steps of forming a first light-emitting layer on the first pixel electrode of the pixel electrode and forming a first common electrode on the first light-emitting layer, a first light-emitting material layer separated from the first light-emitting layer can be formed on the second bank layer and the dam, and a first electrode material layer separated from the first common electrode can be formed on the first light-emitting material layer, and in the step of forming a first inorganic material layer on the first common electrode, a first inorganic material layer connected without disconnection can be formed on the first common electrode and the first electrode material layer.

[0026] The method for manufacturing a display device may also include: etching a portion of the first inorganic material layer; exposing the dam by etching the first electrode material layer and the first light-emitting material layer; and forming a second light-emitting layer on a second pixel electrode of the pixel electrode; forming a second common electrode on the second light-emitting layer; and forming a second inorganic material layer on the second common electrode.

[0027] In the step of forming the second light emitting layer on the second pixel electrode, a second light emitting material layer including the same material as the second light emitting layer may be formed between the first inorganic material layer and the dam.

[0028] In the step of etching a portion of the first inorganic material layer, a portion of the first inorganic material layer may be removed by a dry etching process, and in the step of exposing the dam by etching the first electrode material layer and the first light-emitting material layer, the first electrode material layer and the first light-emitting material layer may be removed by a wet etching process.

[0029] With the display device and the method for manufacturing the display device according to the embodiment, a dam can be included between the light-emitting elements to prevent the free radicals of the etchant from penetrating between the second bank layer and the first inorganic encapsulation layer during the etching process. The damage of the light-emitting element due to the etchant or moisture is prevented, and thus the brightness difference between the light-emitting elements can be reduced.

[0030] The effects of the present disclosure are not limited to the above-mentioned effects, and various other effects are included in the present specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The above and other aspects and features of the present disclosure will become more apparent by describing in detail embodiments of the present disclosure with reference to the accompanying drawings, in which: Figure 1 is a perspective view showing a display device according to an embodiment; Figure 2 yes Figure 1 A cross-sectional view of a display device; Figure 3 is a top plan view showing an arrangement of a light emitting element of a display device according to an embodiment relative to a first inorganic encapsulation layer, a second bank layer, and a dam; Figure 4 is a cross-sectional view showing a portion of a display device according to an embodiment; Figure 5 is a diagram showing the first emission region and the second emission region (specifically, Figure 4 An enlarged cross-sectional view of area A1); Figure 6 is a cross-sectional view showing a process in which an etchant penetrates into a light emitting element in the absence of a dam structure; Figure 7is a cross-sectional view illustrating a process of blocking penetration of an etchant in a display device according to an embodiment; and Figures 8 to 18 are cross-sectional views sequentially illustrating a process for providing a display device according to an embodiment. DETAILED DESCRIPTION

[0032] The invention will now be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are shown. However, the invention may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of the invention to those skilled in the art.

[0033] It will also be understood that when a layer is referred to as being associated with another element (such as “on” another layer or substrate), the layer can be directly on the other layer or substrate, or intervening layers may also be present. Conversely, when a layer is referred to as being associated with another element (such as “directly on” another layer or substrate), there are no intervening layers therebetween.

[0034] Throughout the specification, the same reference numerals refer to the same components. For example, a reference numeral identifying a singular element in the drawings may be used to refer to multiple singular elements in the disclosure.

[0035] It will be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the teachings of the invention, the first element discussed below may be referred to as the second element. Similarly, the second element may also be referred to as the first element.

[0036] The terms used herein are only used for the purpose of describing specific embodiments and are not intended to be limiting. As used herein, unless the context clearly indicates otherwise, "one", "one (kind / person)", "the (described)" and "at least one (kind / person)" do not represent the limitation of quantity, and are intended to include both the singular and the plural. Therefore, in the claims, citing "one (kind / person)" element followed by citing "described" element includes one element and multiple elements. For example, unless the context clearly indicates otherwise, "element" has the same meaning as "at least one element". "At least one (kind / person)" should not be interpreted as being limited to "one" or "one (kind / person)". "Or" means "and / or". As used herein, the term "and / or" includes any combination and all combinations of one or more related listed items. It will also be understood that when used in this specification, the term "comprises" and its variations or "includes" and its variations indicate the presence of stated features, regions, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components and / or groups thereof.

[0037] In addition, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe the relationship of one element to another element as shown in the accompanying drawings. It will be understood that relative terms are intended to cover different orientations of the device in addition to the orientation depicted in the accompanying drawings. For example, if the device in one drawing is turned over, the element described as being on the "lower" side of the other elements will subsequently be oriented to be on the "upper" side of the other elements. Therefore, the term "lower" may include both "lower" and "upper" orientations depending on the specific orientation of the drawing. Similarly, if the device in one drawing is turned over, the element described as being "below" or "under" the other elements will subsequently be oriented to be "above" the other elements. Therefore, the term "below..." or "under..." may cover both upper and lower orientations.

[0038] As used herein, "about" or "approximately" is inclusive of the stated value and means within an acceptable range of deviation for a particular value as determined by one of ordinary skill in the art, taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., measurement system limitations). For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0039] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will also be understood that terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and in the present disclosure, and will not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0040] Embodiments are described herein with reference to schematically illustrated cross-sectional views as idealized embodiments. Therefore, variations in the shapes of the illustrations due to, for example, manufacturing techniques and / or tolerances are expected. Therefore, the embodiments described herein should not be interpreted as being limited to the specific shapes of the regions as shown here, but will include deviations in shapes due to, for example, manufacturing. For example, a region shown or described as flat may typically have rough and / or nonlinear features. In addition, the sharp angles shown may be rounded. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shape of the regions, and are not intended to limit the scope of the claims.

[0041] Hereinafter, embodiments will be described with reference to the accompanying drawings.

[0042] Figure 1 is a perspective view showing a display device 10 according to the embodiment.

[0043] Reference Figure 1 The display device 10 according to the embodiment may be included in an electronic device to provide a display screen for displaying an image in the electronic device. The electronic device may refer to all electronic devices that provide a display screen for displaying an image. For example, a television, a laptop computer, a monitor, a billboard, an Internet of Things (IoT) device, a mobile phone, a smart phone, a tablet personal computer (PC), an electronic watch, smart glasses, a smart watch, a watch phone, a head-mounted display, a mobile communication terminal, an electronic notebook, an electronic book, a portable multimedia player (PMP), a navigation device, a game console, a digital camera, a video camera, etc. that provide a display screen may be included in the electronic device.

[0044] The shape of the display device 10 may be modified variously. For example, the planar shape of the display device 10 may have a shape similar to a rectangular shape having short sides in the first direction DR1 and long sides in the second direction DR2 intersecting the first direction DR1 to define a plane. In a plan view, corners where the short sides in the first direction DR1 and the long sides in the second direction DR2 meet each other may be rounded with a curvature, but are not limited thereto, and may also be right angles. The planar shape of the display device 10 in a plan view is not limited to a rectangular shape, and may be a shape similar to other polygonal shapes, a circular shape, or an elliptical shape.

[0045] The display device 10 may include a display panel 100, a display driver 200, a circuit board 300, and a touch driver 400 (see Figure 2 ).

[0046] The display panel 100 may include a main area MA and a sub area SBA adjacent to each other.

[0047] The main area MA may include a display area DA including pixels displaying an image and a non-display area NDA adjacent to the display area DA (such as being arranged around the display area DA in a plan view). The display area DA may emit light from a plurality of light-emitting areas and / or a plurality of opening areas. For example, the display panel 100 may include a pixel circuit including a switching element, a pixel defining film defining a light-emitting area and / or an opening area, and a self-luminous element.

[0048] For example, the self-luminous element may include at least one of an organic light emitting diode (LED) including an organic light emitting layer, a quantum dot LED including a quantum dot light emitting layer, an inorganic LED including an inorganic semiconductor, and a micro LED, but is not limited thereto.

[0049] A plurality of pixels, a plurality of scan lines, a plurality of data lines, and a plurality of power lines may be provided in the display area DA. Each of the plurality of pixels may be defined as a minimum unit of light emission, and each of the self-luminous elements described above may be in each of the pixels. The plurality of scan lines may supply a scan signal received from a scan driver (not shown) to the plurality of pixels. The plurality of data lines may supply a data voltage received from the display driver 200 to the plurality of pixels. The plurality of power lines may supply a source voltage received from the display driver 200 to the plurality of pixels.

[0050] The non-display area NDA may be an area (e.g., a plane area) outside the display area DA or closer to the outer edge of the display device 10 than the display area DA. The non-display area NDA may be defined as an edge area of ​​the main area MA of the display panel 100. The non-display area NDA may include a scan driver supplying a scan signal to a scan line and a fan-out line connecting the display driver 200 and the display area DA to each other.

[0051] The sub-area SBA may be an area extending from one side of the main area MA. The sub-area SBA may include a flexible material that can be bent, folded, and rolled. That is, the display device 10 and its various components or layers at the sub-area SBA may be bendable, foldable, rollable, etc. For example, when the display device 10 is bent at the sub-area SBA, the sub-area SBA may be arranged to overlap with the main area MA in (or along) the thickness direction (e.g., a third direction DR3 intersecting both the first direction DR1 and the second direction DR2). The sub-area SBA may include a pad (or pad) portion of the display driver 200 and the display panel 100, and the display panel 100 is connected to the circuit board 300 at the pad portion. In another embodiment, the sub-area SBA may be omitted, and the display driver 200 and the pad portion may be arranged in the non-display area NDA.

[0052] The display driver 200 may output signals and voltages as electrical signals for driving the display panel 100 to activate pixels, generate and / or emit light, display images, etc. The display driver 200 may supply data voltages to the data lines. The display driver 200 may supply source voltages to the power lines and supply scan control signals to the scan driver. The display driver 200 may be formed as an integrated circuit (IC) and mounted on the display panel 100 in a chip on glass (COG) manner, a chip on plastic (COP) manner, or an ultrasonic bonding manner. As an example, the display driver 200 may be connected to the display panel 100 at the sub-area SBA, and may be overlapped with the main area MA in the thickness direction (third direction DR3) by bending the display panel 100 at the sub-area SBA. As another example, the display driver 200 may be mounted on the circuit board 300.

[0053] The circuit board 300 may be attached or connected to the display panel 100 at a pad portion of the display panel 100, such as by using an anisotropic conductive film (ACF). Leads of the circuit board 300 may be electrically connected to the pad portion of the display panel 100. The circuit board 300 may be a flexible printed circuit board, a printed circuit board, or a flexible film such as a chip on film.

[0054] Figure 2 Viewed from the side Figure 1 10 is a cross-sectional view of a display device 10. Specifically, Figure 2 Shows Figure 1 A side surface of the display device 10 when the display device 10 is folded.

[0055] Reference Figure 2 , the display panel 100 may include a substrate SUB, a thin film transistor layer TFTL as a circuit layer, a light emitting element layer EML, a thin film encapsulation layer TFEL as an encapsulation layer, and a color filter layer CFL.

[0056] The substrate SUB may be a base substrate or a base member. The substrate SUB may be a flexible substrate that can be bent, folded, and rolled. For example, the substrate SUB may include a polymer resin such as polyimide (PI), but is not limited thereto. In another embodiment, the substrate SUB may include a glass material or a metal material.

[0057] The thin film transistor layer TFTL may be disposed on the substrate SUB. The thin film transistor layer TFTL may include a plurality of thin film transistors constituting a pixel circuit of a pixel. The thin film transistor layer TFTL may also include a scan line, a data line, a power line, a scan control line, a fan-out line connecting the display driver 200 and the data line to each other, and a lead connecting the display driver 200 and the pad portion to each other. Each of the thin film transistors may include a semiconductor region, a source electrode, a drain electrode, and a gate electrode. For example, when a scan driver is formed on one side of the non-display area NDA of the display panel 100, the scan driver may include a thin film transistor of a circuit layer.

[0058] The thin film transistor layer TFTL may be disposed in the display area DA, the non-display area NDA, and the sub-area SBA. The thin film transistor, the scan line, the data line, and the power line of each pixel of the thin film transistor layer TFTL may be disposed in the display area DA. The scan control line and the fan-out line of the thin film transistor layer TFTL may be disposed in the non-display area NDA. The lead line of the thin film transistor layer TFTL may be disposed in the sub-area SBA.

[0059] The light emitting element layer EML may be disposed on the thin film transistor layer TFTL. The light emitting element layer EML may include a plurality of light emitting elements and a pixel defining film, each light emitting element including a first electrode, a second electrode and a light emitting layer to emit light, and the pixel defining film defines the area of ​​the pixel. The plurality of light emitting elements of the light emitting element layer EML may be disposed in the display area DA. The light emitting element layer EML may be connected to a circuit layer for activating pixels, generating and / or emitting light, displaying images, and the like.

[0060] In an embodiment, the light emitting layer may be an organic light emitting layer including an organic material. The light emitting layer may include a hole transport layer, an organic light emitting layer, and an electron transport layer. When the first electrode of the light emitting element layer EML receives a voltage through the thin film transistor of the thin film transistor layer TFTL and the second electrode receives a cathode voltage, holes and electrons may move to the organic light emitting layer through the hole transport layer and the electron transport layer, respectively, and may be combined with each other in the organic light emitting layer to emit light.

[0061] In another embodiment, the light emitting element may include a quantum dot light emitting diode including a quantum dot light emitting layer, an inorganic light emitting diode including an inorganic semiconductor, or a micro light emitting diode.

[0062] The thin film encapsulation layer TFEL may cover the upper surface and the side surface of the light emitting element layer EML and may protect the light emitting element layer EML. The thin film encapsulation layer TFEL may include at least one inorganic film and at least one organic film for encapsulating the light emitting element layer EML.

[0063] The color filter layer CFL may be disposed on the thin film encapsulation layer TFEL. The color filter layer CFL may include a plurality of color filters, each corresponding to a plurality of emission regions. Each of the color filters may selectively transmit light of a specific wavelength therethrough and block or absorb light of other wavelengths. The color filter layer CFL may absorb a portion of the light introduced from outside the display device 10 to reduce reflected light caused by external light. Therefore, the color filter layer CFL may prevent color distortion caused by external light reflection.

[0064] Since the color filter layer CFL is directly disposed on the thin film encapsulation layer TFEL, the display device 10 may not require a separate substrate for the color filter layer CFL. Therefore, the thickness of the display device 10 may be relatively small. The color filter layer CFL may contact the thin film encapsulation layer TFEL to form an interface therebetween.

[0065] In some embodiments, the display device 10 may further include an optical device that provides functions to the display device 10. The optical device may emit or receive light in infrared, ultraviolet, and visible light bands to provide functions. For example, the optical device may be an optical sensor (such as a proximity sensor, an illumination sensor, a camera sensor, a fingerprint sensor, or an image sensor) that senses light incident on the display device 10.

[0066] Figure 3 is a plan view showing a part of the display device 10 according to the embodiment. Figure 3 is a plan view showing a regional arrangement of light emitting elements ED1 , ED2 , and ED3 , first inorganic encapsulation layers TL1 , TL2 , and TL3 as a plurality of inorganic patterns, a second bank layer BN2 , and a dam DAM in a display area DA of the display device 10 .

[0067] Reference Figure 3 The second bank layer BN2 may cover the display area DA, but expose a portion of the display area DA (eg, the lower layer) outside the second bank layer BN2. An opening ( Figure 3 The light emitting elements ED1, ED2 and ED3 may be disposed in the corresponding openings.

[0068] The first inorganic encapsulation layers TL1, TL2, and TL3 may cover the light emitting elements ED1, ED2, and ED3 in the corresponding openings, and may partially cover the boundary portion of the second bank layer BN2 defining the openings. The dam DAM may be disposed on the second bank layer BN2 to be spaced apart from the first inorganic encapsulation layers TL1, TL2, and TL3 by a predetermined distance d1. Figure 3 It has been shown that the exposed area not covered by the second bank layer BN2 has a circular shape in a plan view, but the exposed area not covered by the second bank layer BN2 may have a polygonal shape such as a triangular shape, a quadrilateral shape or a hexagonal shape, and the shapes of the first inorganic encapsulation layers TL1, TL2 and TL3 covering the exposed area and the peripheral portion of the exposed area may also be changed.

[0069] The first inorganic encapsulation layers TL1, TL2, and TL3 extend from within the volume of the opening to outside the overlapping peripheral portion of the opening and the second bank layer BN2 defining the opening, respectively. The extended portions of the first inorganic encapsulation layers TL1, TL2, and TL3 may extend further from the light-emitting elements ED1, ED2, and ED3 than the overlapping peripheral portion of the second bank layer BN2 defining the opening. The extended portions (wings) of the first inorganic encapsulation layers TL1, TL2, and TL3 may be disposed at a level (or plane) above the second bank layer BN2, and the light-emitting elements ED1, ED2, and ED3 may be disposed at a level below the second bank layer BN2.

[0070] Along a plane defined by the first direction DR1 and the second direction DR2, the exposed regions not covered by the second bank layer BN2 may be disposed to be spaced apart from each other in the first direction DR1, and may also be disposed to be spaced apart from each other in the second direction DR2. The shape and arrangement of the exposed regions not covered by the second bank layer BN2 are not limited to Figure 3 and the exposed area not covered by the second bank layer BN2 can be formed in the shape and arrangement shown in PENTILE ® Type settings.

[0071] Figure 4 is a cross-sectional view showing a portion of the display device 10 according to the embodiment. Specifically, Figure 4 It is along Figure 3 A sectional view taken along the line BB', and showing the Figure 3 An organic encapsulating layer TFE2, a second inorganic encapsulating layer TFE3, color filters CF1, CF2, and CF3, a light blocking layer BM including a plurality of light blocking patterns spaced apart from each other, and an overcoat layer OC are provided on the plan view of FIG. Figure 4 The cross sections of the substrate SUB, the thin film transistor layer TFTL, the light emitting element layer EML, the thin film encapsulation layer TFEL, and the color filter layer CFL are shown.

[0072] The thin film transistor layer TFTL may include a first buffer layer BF1, a bottom metal layer BML including solid material portions spaced apart from each other, a second buffer layer BF2, a thin film transistor TFT, a gate insulating layer GI, a first interlayer insulating layer ILD1, a capacitor electrode CPE, a second interlayer insulating layer ILD2, a first connection electrode CNE1, a first passivation layer PAS1, a second connection electrode CNE2, and a second passivation layer PAS2.

[0073] The first buffer layer BF1 may be disposed on the substrate SUB. The first buffer layer BF1 may include an inorganic film capable of preventing air or moisture from penetrating. For example, the first buffer layer BF1 may include a plurality of stacked inorganic films.

[0074] The bottom metal layer BML may be disposed on the first buffer layer BF1. For example, the bottom metal layer BML may be formed as a single material layer or a plurality of material layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), and alloys thereof.

[0075] The second buffer layer BF2 may cover the first buffer layer BF1 and the bottom metal layer BML. The second buffer layer BF2 may include an inorganic film capable of preventing air or moisture from penetrating. For example, the second buffer layer BF2 may include a plurality of stacked inorganic films.

[0076] The thin film transistor TFT may be disposed on the second buffer layer BF2 and may constitute a pixel circuit of each of the plurality of pixels. For example, the thin film transistor TFT may be a driving transistor and / or a switching transistor of the pixel circuit. The thin film transistor TFT may include a semiconductor layer ACT, a source electrode SE, a drain electrode DE, and a gate electrode GE.

[0077] The semiconductor layer ACT may be disposed on the second buffer layer BF2. The semiconductor layer ACT may overlap the bottom metal layer BML and the gate electrode GE in the thickness direction (eg, the third direction DR3), and may be insulated from the gate electrode GE by the gate insulating layer GI. The material of the semiconductor layer ACT in a portion of the semiconductor layer ACT may be conductive to form a source electrode SE and a drain electrode DE.

[0078] The gate electrode GE may be disposed on the gate insulating layer GI. The gate electrode GE may overlap the semiconductor layer ACT in a thickness direction (eg, the third direction DR3) with the gate insulating layer GI interposed therebetween.

[0079] The gate insulating layer GI may be disposed on the semiconductor layer ACT. For example, the gate insulating layer GI may cover the semiconductor layer ACT and the second buffer layer BF2 and may insulate the semiconductor layer ACT and the gate electrode GE from each other. The gate insulating layer GI may include (or define) a contact hole through which the first connection electrode CNE1 penetrates.

[0080] The first interlayer insulating layer ILD1 may cover the gate electrode GE and the gate insulating layer GI. The first interlayer insulating layer ILD1 may include a contact hole through which the first connection electrode CNE1 penetrates. The contact hole of the first interlayer insulating layer ILD1 may be connected to the contact hole of the gate insulating layer GI and the contact hole of the second interlayer insulating layer ILD2, respectively, or aligned with the contact hole of the gate insulating layer GI and the contact hole of the second interlayer insulating layer ILD2 to define a single contact hole that penetrates the insulating layers IL2, IL1, and GI together.

[0081] The capacitor electrode CPE may be disposed on the first interlayer insulating layer ILD1 . The capacitor electrode CPE may overlap the gate electrode GE in a thickness direction (eg, the third direction DR3 ). The capacitor electrode CPE and the gate electrode GE may form a capacitor.

[0082] The second interlayer insulating layer ILD2 may cover the capacitor electrode CPE and the first interlayer insulating layer ILD1. The second interlayer insulating layer ILD2 may include a contact hole through which the first connection electrode CNE1 penetrates. The contact hole of the second interlayer insulating layer ILD2 may be connected to the contact hole of the first interlayer insulating layer ILD1 and the contact hole of the gate insulating layer GI.

[0083] The first connection electrode CNE1 may be disposed on the second interlayer insulating layer ILD2. The first connection electrode CNE1 may electrically connect the drain electrode DE of the thin film transistor TFT and the second connection electrode CNE2 to each other. The first connection electrode CNE1 may be inserted into or pass through a contact hole formed in the second interlayer insulating layer ILD2, the first interlayer insulating layer ILD1, and the gate insulating layer GI to contact the drain electrode DE of the thin film transistor TFT within a corresponding single contact hole.

[0084] The first passivation layer PAS1 may cover the first connection electrode CNE1 and the second interlayer insulating layer ILD2. The first passivation layer PAS1 may protect the thin film transistor TFT. The first passivation layer PAS1 may include a contact hole through which the second connection electrode CNE2 penetrates.

[0085] The second connection electrode CNE2 may be disposed on the first passivation layer PAS1. The second connection electrode CNE2 may electrically connect the first connection electrode CNE1 and the pixel electrodes AE1, AE2, and AE3 of the light emitting element ED to each other. The second connection electrode CNE2 may be inserted into a contact hole formed in the first passivation layer PAS1 to contact the first connection electrode CNE1.

[0086] The second passivation layer PAS2 may cover the second connection electrode CNE2 and the first passivation layer PAS1. The second passivation layer PAS2 may include contact holes through which the pixel electrodes AE1, AE2, and AE3 of the light emitting element ED penetrate.

[0087] The light emitting element layer EML may be disposed on the thin film transistor layer TFTL. The light emitting element layer EML may include a light emitting element ED, a pixel defining film PDL, a capping layer CAP as a capping pattern, and a dam structure BNS including a dam pattern. The light emitting element ED may include pixel electrodes AE1, AE2, and AE3, light emitting layers EL1, EL2, and EL3, and common electrodes CE1, CE2, and CE3, respectively.

[0088] Figure 5 1 is a diagram showing the first emission area EA1 and the second emission area EA2 (specifically, Figure 4 Magnified view of area A1). Figure 6 is a cross-sectional view showing a process in which an etchant penetrates into a light emitting element ED in the absence of a dam DAM structure, Figure 7 is a cross-sectional view illustrating a process of blocking penetration of an etchant in the display device 10 according to an embodiment.

[0089] Apart from Figure 4 In addition, refer to Figure 5 , the display device 10 may include a plurality of emission areas EA1, EA2, and EA3 disposed in the display area DA. The emission areas EA1, EA2, and EA3 may include or define a plane area where light is emitted from the light emitting elements ED1, ED2, and ED3 and is transferred to the color filter layer CFL in the third direction DR3. The emission areas EA1, EA2, and EA3 may include a first emission area EA1, a second emission area EA2, and a third emission area EA3 that are spaced apart from each other and emit light of the same or different colors.

[0090] In an embodiment, the areas or sizes of the first emission area EA1, the second emission area EA2, and the third emission area EA3 may be the same as each other. For example, in the display device 10, the first emission area EA1, the second emission area EA2, and the third emission area EA3 may have the same plane area. However, the present disclosure is not limited to this. In the display device 10, the areas or sizes of the first emission area EA1, the second emission area EA2, and the third emission area EA3 may be different from each other. For example, the plane area of ​​the second emission area EA2 may be larger than the plane areas of the first emission area EA1 and the third emission area EA3, and the plane area of ​​the third emission area EA3 may be larger than the plane area of ​​the first emission area EA1. The intensity of light emitted from the emission areas EA1, EA2, and EA3 can be changed according to the plane areas of the emission areas EA1, EA2, and EA3, and the color sense of the picture displayed on the display device 10 can be controlled by adjusting the plane areas of the emission areas EA1, EA2, and EA3. Figure 4 In the embodiment of FIG. 5 , it has been illustrated that the plane areas of the emission areas EA1 , EA2 , and EA3 are the same as each other, but the present disclosure is not limited thereto.

[0091] In the display device 10, one first emission area EA1, one second emission area EA2, and one third emission area EA3 disposed adjacent to each other may form one pixel group. One pixel group may include each of the emission areas EA1, EA2, and EA3 that emit light of different colors to express a white grayscale. However, the present disclosure is not limited thereto, and the combination of the emission areas EA1, EA2, and EA3 constituting one pixel group may be modified differently according to the arrangement of the emission areas EA1, EA2, and EA3, the color of the light emitted by the emission areas EA1, EA2, and EA3, and the like.

[0092] A plurality of openings formed in the embankment structure BNS of the light emitting element layer EML are defined along the boundary of the embankment structure BNS. That is, the sidewalls or side surfaces of the material portion of the embankment structure BNS may define the openings. The first embankment layer BN1 and the second embankment layer BN2 of the embankment structure BNS may have a planar shape extending along the boundary of the emission areas EA1, EA2, and EA3 to surround the emission areas EA1, EA2, and EA3. The planar size or shape of the opening may include the planar size or shape of the first emission area EA1, the second emission area EA2, and the third emission area EA3 disposed therein.

[0093] The display device 10 may include a plurality of light emitting elements ED1, ED2, and ED3 disposed in different emission areas EA1, EA2, and EA3, respectively. The light emitting elements ED1, ED2, and ED3 may include a first light emitting element ED1 disposed in a first emission area EA1, a second light emitting element ED2 disposed in a second emission area EA2, and a third light emitting element ED3 disposed in a third emission area EA3.

[0094] The light-emitting elements ED1, ED2, and ED3 may include pixel electrodes AE1, AE2, and AE3, light-emitting layers EL1, EL2, and EL3, and common electrodes CE1, CE2, and CE3, respectively. The light-emitting elements ED1, ED2, and ED3 disposed in different emission areas EA1, EA2, and EA3 may emit light of different colors, respectively, according to the materials of the light-emitting layers EL1, EL2, and EL3. For example, the first light-emitting element ED1 disposed in the first emission area EA1 may emit a first light (which is red light) having a peak wavelength in the range of about 610 nanometers (nm) to about 650 nm, the second light-emitting element ED2 disposed in the second emission area EA2 may emit a second light (which is green light) having a peak wavelength in the range of about 510 nm to about 550 nm, and the third light-emitting element ED3 disposed in the third emission area EA3 may emit a third light (which is blue light) having a peak wavelength in the range of about 440 nm to about 480 nm. The first emission area EA1, the second emission area EA2, and the third emission area EA3 constituting one pixel (or one pixel group) may include light-emitting elements ED1, ED2, and ED3 that emit light of different colors to express a white grayscale at one pixel. Optionally, the light-emitting layers EL1, EL2, and EL3 may include two or more materials that emit light of different colors, so that one light-emitting layer may emit mixed light. For example, the light-emitting layers EL1, EL2, and EL3 may include both a red light-emitting material and a green light-emitting material to emit yellow light, or include all of a red light-emitting material, a green light-emitting material, and a blue light-emitting material to emit white light.

[0095] The pixel electrodes AE1, AE2, and AE3 may be disposed on the second passivation layer PAS2. The pixel electrodes AE1, AE2, and AE3 may be disposed in a plurality of emission areas EA1, EA2, and EA3, respectively. The pixel electrodes AE1, AE2, and AE3 may include a first pixel electrode AE1 disposed in a first emission area EA1, a second pixel electrode AE2 disposed in a second emission area EA2, and a third pixel electrode AE3 disposed in a third emission area EA3. The first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 may be disposed to be spaced apart from each other along the second passivation layer PAS2. Figure 4It has been shown that the first pixel electrode AE1, the second pixel electrode AE2 and the third pixel electrode AE3 are spaced apart from each other in the first direction DR1, but the present disclosure is not limited thereto, and the first pixel electrode AE1, the second pixel electrode AE2 and the third pixel electrode AE3 may be spaced apart from each other in any direction within a plane formed by the first direction DR1 and the second direction DR2 intersecting each other.

[0096] The pixel electrodes AE1, AE2, and AE3 may be electrically connected to the drain electrode DE of the corresponding thin film transistor TFT through the first connection electrode CNE1 and the second connection electrode CNE2. Outer edges of the pixel electrodes AE1, AE2, and AE3 spaced apart from each other are partially covered by the material of the pixel definition film PDL, so that the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 may be insulated from each other.

[0097] The pixel electrodes AE1, AE2, and AE3 may include a transparent electrode material and / or a conductive metal material. The conductive metal material may be one or more of silver (Ag), copper (Cu), aluminum (Al), nickel (Ni), lanthanum (La), titanium (Ti), and titanium nitride (TiN). The transparent electrode material may be one or more of indium tin oxide (ITO), indium zinc oxide (IZO), and indium tin zinc oxide (ITZO). The pixel electrodes AE1, AE2, and AE3 may have a multilayer structure of a transparent electrode material and a conductive metal material.

[0098] The pixel defining film PDL may be disposed on the second passivation layer PAS2, the residual pattern RP, and the pixel electrodes AE1, AE2, and AE3. The pixel defining film PDL may be disposed entirely on the second passivation layer PAS2, but portions of the upper surfaces of the pixel electrodes AE1, AE2, and AE3 may be exposed to the outside of the pixel defining film PDL by covering the outer surfaces of the pixel electrodes AE1, AE2, and AE3 and the outer surface of the residual pattern RP. For example, the pixel defining film PDL may expose the first pixel electrode AE1 to the outside of the pixel defining film PDL in the first emission area EA1, and the first light emitting layer EL1 may be directly disposed on the first pixel electrode AE1 exposed by the pixel defining film PDL.

[0099] The pixel defining film PDL as a pixel defining layer may include an inorganic insulating material. The pixel defining film PDL may include at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, a tantalum oxide layer, a hafnium oxide layer, a zinc oxide layer, and an amorphous silicon layer, but is not limited thereto. Material portions of the pixel defining film PDL may be spaced apart from each other to define a pixel opening in the pixel defining film PDL.

[0100] According to an embodiment, the pixel defining film PDL may be disposed on the pixel electrodes AE1, AE2, and AE3, but may be spaced apart from the upper surfaces of the pixel electrodes AE1, AE2, and AE3. Within the opening of the bank structure BNS, the pixel defining film PDL may not be in direct contact with the upper surfaces of the pixel electrodes AE1, AE2, and AE3, but may partially overlap with the upper surfaces of the pixel electrodes AE1, AE2, and AE3 in the thickness direction (e.g., the third direction DR3) of the substrate SUB, and the residual pattern RP may be disposed between the pixel defining film PDL and the upper surfaces of the pixel electrodes AE1, AE2, and AE3. However, the pixel defining film PDL may be in direct contact with the outer side surfaces of the pixel electrodes AE1, AE2, and AE3.

[0101] Each of the pixel defining film PDL and the second bank layer BN2 may have a side surface defining an opening at the corresponding emission region. The side surface of the pixel defining film PDL may protrude more toward the emission regions EA1, EA2, and EA3 than the side surface of the second bank layer BN2. That is, the pixel defining film PDL extends further toward the emission region than the second bank layer BN2, so that the side surface of the pixel defining film PDL is closer to the corresponding emission layer than the side surface of the second bank layer BN2. Each of the pixel defining film PDL and the second bank layer BN2 may extend further than the side surface of the first bank layer BN1.

[0102] The residual pattern RP may be disposed on or along the outer edges of the pixel electrodes AE1, AE2, and AE3, respectively. Due to the residual pattern RP, the pixel defining film PDL may not be in direct contact with the upper surfaces of the pixel electrodes AE1, AE2, and AE3. As used herein, non-contact may exclude edge contact or point contact. For example, within the opening of the embankment structure BNS, the pixel defining film PDL is spaced apart from the corresponding pixel electrode by the residual pattern RP.

[0103] The sacrificial layer SFL (see FIG. 1 ) disposed on the pixel electrodes AE1 , AE2 , and AE3 may be removed during the manufacturing process of the display device 10 . Figure 8 ) is used to form a residual pattern RP, so that the residual pattern RP is the remaining portion of the material of the sacrificial layer SFL. The residual pattern RP may include a metal, an oxide semiconductor, or a transparent conductive oxide (TCO). The accompanying drawings only show the case where the inner surface of the residual pattern RP facing the emission areas EA1, EA2, and EA3 is aligned with the inner surface of the pixel defining film PDL, but the present disclosure is not limited thereto. The inner surface of the residual pattern RP may protrude much more toward the emission areas EA1, EA2, and EA3 than the inner surface of the pixel defining film PDL, or may be much more recessed than the inner surface of the pixel defining film PDL.

[0104] The light-emitting layers EL1, EL2 and EL3 may be disposed on the pixel electrodes AE1, AE2 and AE3, respectively. The light-emitting layers EL1, EL2 and EL3 may be organic light-emitting layers or organic light-emitting patterns made of organic materials, and may be formed on the pixel electrodes AE1, AE2 and AE3, respectively, by a deposition process. The light-emitting layers EL1, EL2 and EL3 may have a multilayer structure, and hole injection materials, hole transport materials, light-emitting materials, electron transport materials and / or electron injection materials may constitute the layers of the light-emitting layers EL1, EL2 and EL3, respectively. When the thin film transistor TFT applies a predetermined voltage to the pixel electrodes AE1, AE2 and AE3 of the light-emitting elements ED1, ED2 and ED3 and the common electrodes CE1, CE2 and CE3 of the light-emitting elements ED1, ED2 and ED3 receive a common voltage or a cathode voltage, holes and electrons may be injected and transported, respectively, and may be combined with each other in the light-emitting layers EL1, EL2 and EL3 to emit light.

[0105] The light-emitting layers EL1, EL2, and EL3 may include a first light-emitting layer EL1, a second light-emitting layer EL2, and a third light-emitting layer EL3, each of which is disposed in different emission areas EA1, EA2, and EA3. The first light-emitting layer EL1 may be disposed on the first pixel electrode AE1 in the first emission area EA1, the second light-emitting layer EL2 may be disposed on the second pixel electrode AE2 in the second emission area EA2, and the third light-emitting layer EL3 may be disposed on the third pixel electrode AE3 in the third emission area EA3. The plurality of light-emitting layers EL1, EL2, and EL3 may emit light of different colors, respectively, or one light-emitting layer EL1, EL2, or EL3 may emit mixed light. In an embodiment, the first light-emitting layer EL1 may emit red light, the second light-emitting layer EL2 may emit green light, and the third light-emitting layer EL3 may emit blue light. In another embodiment, the first light-emitting layer EL1 may emit yellow light as a mixture of red light and green light, and the second light-emitting layer EL2 may emit blue light. In yet another embodiment, the first light-emitting layer EL1 may emit white light as a mixture of red light, green light, and blue light.

[0106] In an embodiment, the second thickness h2 of the light emitting layers EL1, EL2, and EL3 may be about 1500 angstroms (Å) to about 2500 Å. The thickness of the light emitting layers EL1, EL2, and EL3 may be changed according to the color of the light emitted from the light emitting layers EL1, EL2, and EL3. The second thickness h2 of the corresponding light emitting layer may be defined along the third direction DR3 by the thickness portion of the light emitting layer within the pixel opening of the pixel defining film PDL. The second thickness h2 may also be defined in a direction perpendicular to the surface to which the light emitting layer extends (such as the side surface or the upper surface of the pixel defining film PDL).

[0107] The light-emitting layers EL1, EL2, and EL3 may be disposed on the upper surface of the pixel defining film PDL. The light-emitting layers EL1, EL2, and EL3 may be disposed in a space defined between the pixel electrodes AE1, AE2, and AE3 and the inner surface of the pixel defining film PDL. The light-emitting layers EL1, EL2, and EL3 may contact the pixel defining film PDL, the residual pattern RP, and the pixel electrodes AE1, AE2, and AE3.

[0108] The common electrodes CE1, CE2, and CE3 may be disposed on the light emitting layers EL1, EL2, and EL3, respectively. The common electrodes CE1, CE2, and CE3 may include a transparent conductive material to emit light generated from the light emitting layers EL1, EL2, and EL3. The common electrodes CE1, CE2, and CE3 may receive a common voltage or a low potential voltage. When the pixel electrodes AE1, AE2, and AE3 receive a voltage corresponding to the data voltage and the common electrodes CE1, CE2, and CE3 receive a low potential voltage, a potential difference is formed between the pixel electrodes AE1, AE2, and AE3 and the common electrodes CE1, CE2, and CE3, so that the light emitting layers EL1, EL2, and EL3 may emit light.

[0109] The common electrodes CE1, CE2, and CE3 may include a first common electrode CE1, a second common electrode CE2, and a third common electrode CE3, each of which is disposed in different emission areas EA1, EA2, and EA3. The first common electrode CE1 may be disposed on the first light emitting layer EL1 in the first emission area EA1, the second common electrode CE2 may be disposed on the second light emitting layer EL2 in the second emission area EA2, and the third common electrode CE3 may be disposed on the third light emitting layer EL3 in the third emission area EA3. The first common electrode CE1, the second common electrode CE2, and the third common electrode CE3 may be spaced apart from each other.

[0110] The cover layer CAP may be disposed on the common electrodes CE1, CE2, and CE3. The cover layer CAP may include an organic or inorganic insulating material and is a cover pattern disposed on the light emitting elements ED1, ED2, and ED3. The cover layer CAP may prevent the light emitting elements ED1, ED2, and ED3 from being damaged by external air. In an embodiment, the cover layer CAP may include an organic material (such as α-NPD, NPB, TPD, m-MTDATA, Alq 3 , LiF and / or CuPc) or an inorganic material (such as aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride and / or silicon oxynitride).

[0111] The display device 10 may include a plurality of embankment structures BNS of embankment layers respectively disposed on a material portion of the pixel defining film PDL. The embankment structure BNS may have a structure in which embankment layers BN1 and BN2 including materials different from each other are sequentially stacked in a direction away from the pixel defining film PDL. The material portion of the embankment structure BNS may define a plurality of openings having an area (including an area of ​​the emission areas EA1, EA2, and EA3), and may be disposed to overlap with the light blocking layer BM to be described later. The light emitting elements ED1, ED2, and ED3 of the display device 10 may be disposed to overlap with the openings of the embankment structure BNS.

[0112] The bank structure BNS may include a first bank layer BN1 and a second bank layer BN2 sequentially stacked on the pixel defining layer PDL.

[0113] The first bank layer BN1 may be disposed on the pixel defining film PDL. The inner surface of the first bank layer BN1 may be recessed from the inner surface of the pixel defining film PDL in a direction away from the emission areas EA1, EA2, and EA3. The inner surface of the first bank layer BN1 may be recessed from the inner surface of the second bank layer BN2 to be described later in a direction away from the emission areas EA1, EA2, and EA3.

[0114] According to an embodiment, the first bank layer BN1 may include a metal material. In an embodiment, the first bank layer BN1 may include aluminum (Al) or an alloy of aluminum (Al).

[0115] In an embodiment, the thickness of the first bank layer BN1 may be in the range of about 4000 Å to about 7000 Å. When the thickness of the first bank layer BN1 is within the above range, the light emitting layers EL1, EL2, and EL3 and the common electrodes CE1, CE2, and CE3 spaced apart from each other may be formed by a deposition and etching process instead of a mask process.

[0116] According to an embodiment, the common electrodes CE1, CE2 and CE3 may be in direct contact with the inner surface of the first bank layer BN1. The common electrodes CE1, CE2 and CE3 of different light emitting elements ED1, ED2 and ED3 may be in direct contact with the first bank layer BN1, respectively, and the first bank layer BN1 may include a metal material so that the common electrodes CE1, CE2 and CE3 may be electrically connected to each other through the first bank layer BN1.

[0117] The light emitting layers EL1, EL2, and EL3 may be in direct contact with the inner surface of the first bank layer BN1. The contact area between the common electrodes CE1, CE2, and CE3 and the inner surface of the first bank layer BN1 may be greater than the contact area between the light emitting layers EL1, EL2, and EL3 and the inner surface of the first bank layer BN1. Figure 5, for example, the contact area may be a plane area along a plane defined along the second direction DR2 and the third direction DR3. The common electrodes CE1, CE2, and CE3 may be arranged to have a larger contact area with respect to the inner side surface of the first bank layer BN1 than the light emitting layers EL1, EL2, and EL3. The common electrodes CE1, CE2, and CE3 may extend farther than the light emitting layers EL1, EL2, and EL3 along the inner side surface of the first bank layer BN1 in the third direction DR3 to be arranged to a height higher than the light emitting layers EL1, EL2, and EL3 along the inner side surface of the first bank layer BN1. Since the common electrodes CE1, CE2, and CE3 of different light emitting elements ED1, ED2, and ED3 are electrically connected to each other through the first bank layer BN1, it may be advantageous for the common electrodes CE1, CE2, and CE3 to contact the first bank layer BN1 with a larger plane area.

[0118] The second bank layer BN2 may be disposed on the first bank layer BN1. The second bank layer BN2 may include a tip TIP as an extension of the second bank layer BN2 protruding from the inner side surface of the first bank layer BN1. The inner side surface of the distal end of the second bank layer BN2 defining the tip TIP may be closer to the emission areas EA1, EA2, and EA3 than the inner side surface of the first bank layer BN1.

[0119] The side surfaces of the second bank layer BN2 have a shape in which they protrude more than the side surfaces of the first bank layer BN1 in a direction toward the emission areas EA1, EA2, and EA3. Therefore, an undercut structure of the first bank layer BN1 may be formed under the tip TIP of the second bank layer BN2.

[0120] In the display device 10 according to the embodiment, the embankment structure BNS includes a tip TIP protruding toward the emission areas EA1, EA2, and EA3. Therefore, the light-emitting layers EL1, EL2, and EL3 and the common electrodes CE1, CE2, and CE3 can be formed in separate patterns by deposition and etching processes instead of mask processes. In addition, even by a deposition process, different layers or patterns can be formed separately in different emission areas EA1, EA2, and EA3. For example, even if the light-emitting layers EL1, EL2, and EL3 and the common electrodes CE1, CE2, and CE3 of the light-emitting elements ED1, ED2, and ED3 are formed by a deposition process without using a mask, the deposited materials can be disconnected from each other by the tip TIP of the second embankment layer BN2 and the embankment structure BNS is interposed therebetween, rather than being connected to each other between the emission areas EA1, EA2, and EA3. By forming a material layer for forming a specific layer on the entire display device 10, and then etching and removing the layer formed in the unnecessary area, different layers can be formed separately in different emission areas EA1, EA2, and EA3 as separate patterns. In the display device 10, different light-emitting elements ED1, ED2, and ED3 may be formed for each of the emission areas EA1, EA2, and EA3 through deposition and etching processes without using a mask process, unnecessary components may be omitted from the display device 10, and the area of ​​the non-display area NDA may be minimized.

[0121] The side surface shape of the bank structure BNS having an undercut may be a structure formed by a difference in etching rates between materials of the first bank layer BN1 and the second bank layer BN2 in an etching process due to the first bank layer BN1 and the second bank layer BN2 including different materials. According to an embodiment, the second bank layer BN2 may include a material having an etching rate that is slower or lower than that of the first bank layer BN1, and the first bank layer BN1 may be etched more than the second bank layer BN2 in the etching process, so that a lower surface of a tip TIP of the second bank layer BN2 may be exposed at an opening in the bank structure BNS, and an undercut may be formed by the tip TIP of the second bank layer BN2 together with an inner side surface of the first bank layer BN1.

[0122] The second bank layer BN2 may include a metal material different from the metal material of the first bank layer BN1. The metal material of the second bank layer BN2 may be any material that is removed together with the metal material of the first bank layer BN1 by dry etching but has an etching rate much slower than that of the first bank layer BN1 or is not etched relative to wet etching. In an embodiment, the first bank layer BN1 may include aluminum (Al), and the second bank layer BN2 may include titanium (Ti).

[0123] The tip TIP of the second bank layer BN2 may overlap with the common electrodes CE1, CE2, and CE3 in a third direction DR3 perpendicular to the substrate SUB. In addition, the tip TIP of the second bank layer BN2 may overlap with the light-emitting layers EL1, EL2, and EL3 in a third direction DR3 perpendicular to the substrate SUB. In addition, the tip TIP of the second bank layer BN2 may overlap with the pixel defining film PDL in a third direction DR3 perpendicular to the substrate SUB. The common electrodes CE1, CE2, and CE3 may be formed as a pattern below the lower surface of the tip TIP of the second bank layer BN2. Along the thickness direction of the display panel 100, the maximum distance from the substrate SUB to each of the common electrodes CE1, CE2, and CE3 may be less than the minimum distance from the substrate SUB to the second bank layer BN2.

[0124] The thin film encapsulation layer TFEL may be disposed on the light emitting elements ED1, ED2, and ED3 and the embankment structure BNS, and may cover the plurality of light emitting elements ED1, ED2, and ED3 and the embankment structure BNS. The thin film encapsulation layer TFEL may include at least one inorganic film to prevent oxygen or moisture from penetrating into the light emitting element layer EML. The thin film encapsulation layer TFEL may include at least one organic film to protect the light emitting element layer EML from foreign matter such as dust.

[0125] In an embodiment, the thin film encapsulation layer TFEL may include a first inorganic encapsulation layer TFE1 , an organic encapsulation layer TFE2 , and a second inorganic encapsulation layer TFE3 which are sequentially stacked.

[0126] Each of the first inorganic encapsulation layer TFE1 and the second inorganic encapsulation layer TFE3 may include one or more inorganic insulating materials. The inorganic insulating material may be any one of silicon oxide, silicon nitride and silicon oxynitride, and may be, for example, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride and / or silicon oxynitride.

[0127] The organic encapsulation layer TFE2 may include a polymer material. The polymer material may include acrylic resin, epoxy resin, polyimide, polyethylene, etc. For example, the organic encapsulation layer TFE2 may include an acrylic resin such as polymethyl methacrylate or polyacrylic acid. The organic encapsulation layer TFE2 may be formed by curing a monomer or applying a polymer.

[0128] The first inorganic encapsulation layer TFE1 may be disposed on the light emitting elements ED1, ED2, and ED3 and the embankment structure BNS. The first inorganic encapsulation layer TFE1 may include a first inorganic layer (also referred to as a first inorganic pattern) TL1, a second inorganic layer (also referred to as a second inorganic pattern) TL2, and a third inorganic layer (also referred to as a second inorganic pattern) TL3, which are respectively disposed to correspond to different emission areas EA1, EA2, and EA3. The first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3 may include an inorganic insulating material and cover the light emitting elements ED1, ED2, and ED3, respectively. The first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3 may prevent the light emitting elements ED1, ED2, and ED3 from being damaged by external air.

[0129] The first inorganic encapsulation layer TFE1 may be formed by chemical vapor deposition (CVD) and thus may be formed along the steps or contours of the layers on which they are deposited. For example, the first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3 may even form a thin film along the lower surface of the tip TIP of the defining bank structure BNS of the second bank layer BN2. Figures 4 to 6 It has been shown that the first inorganic encapsulation layers TL1, TL2 and TL3 seal the light emitting elements ED1, ED2 and ED3 with uneven thickness along the outer surfaces of the light emitting elements ED1, ED2 and ED3, but the first inorganic encapsulation layers TL1, TL2 and TL3 can be set with uniform thickness along the upper surface, side surface and lower surface of the second bank layer BN2, the inner surface of the first bank layer BN1 and the upper surface of the common electrodes CE1, CE2 and CE3.

[0130] The first inorganic layer TL1 may not overlap with the second emission area EA2 and the third emission area EA3, and may be disposed only in the first emission area EA1 and on a portion of the embankment structure BNS that is closest to the first emission area EA1 and extends around the first emission area EA1. The second inorganic layer TL2 may not overlap with the first emission area EA1 and the third emission area EA3, and may be disposed only in the second emission area EA2 and on a portion of the embankment structure BNS that is closest to the second emission area EA2 and extends around the second emission area EA2. The third inorganic layer TL3 may not overlap with the first emission area EA1 and the second emission area EA2, and may be disposed only in the third emission area EA3 and on the embankment structure BNS that is closest to the second emission area EA2 and extends around the third emission area EA3.

[0131] The first inorganic layer TL1 may be formed after forming the first common electrode CE1, the second inorganic layer TL2 may be formed after forming the second common electrode CE2, and the third inorganic layer TL3 may be formed after forming the third common electrode CE3. The first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3 may be disposed to be spaced apart from each other on the bank structure BNS.

[0132] The first inorganic encapsulation layers TL1, TL2, and TL3 may include main portions TL1_M, TL2_M, and TL3_M surrounded by the bank structure BNS and wing portions TL1_W, TL2_W, and TL3_W protruding from the main portions TL1_M, TL2_M, and TL3_M, respectively. Figure 5 The wing portions protruding from the first inorganic encapsulation layer TL1, TL2 and TL3 (the dotted line boundary shown in FIG) may form a single integral (integral) pattern. The main portions TL1_M, TL2_M and TL3_M of the first inorganic encapsulation layer TL1, TL2 and TL3 may contact the lower surface of the second bank layer BN2 and the side surface (e.g., inner sidewall) of the first bank layer BN1, and may cover the cover layer CAP and the common electrodes CE1, CE2 and CE3. The wing portions TL1_W, TL2_W and TL3_W of the first inorganic encapsulation layer TL1, TL2 and TL3 may have a wing shape in a cross-sectional view. The wing portions TL1_W, TL2_W and TL3_W of the first inorganic encapsulation layer TL1, TL2 and TL3 may be disposed on the second bank layer BN2, but may be spaced apart from the upper surface of the second bank layer BN2 and have an undercut structure. The wing portions TL1_W, TL2_W and TL3_W may overlap with the second bank layer BN2 in the thickness direction (e.g., the third direction DR3) of the substrate SUB. The space between the wing portions TL1_W, TL2_W, and TL3_W of the first inorganic encapsulation layers TL1, TL2, and TL3 spaced apart from each other and the second bank layer BN2 may be a space or gap in which the light emitting material and the electrode material are deposited and then removed.

[0133] The dam DAM may be disposed on the second bank layer BN2 and between the first inorganic encapsulation layers TL1, TL2, and TL3 spaced apart from each other. The dam DAM may be disposed in a space between the first and second inorganic layers TL1 and TL2 spaced apart from each other and in a space between the second and third inorganic layers TL2 and TL3 spaced apart from each other.

[0134] In the method of setting the display device 10, after forming the first light emitting layer EL1, the first common electrode CE1 and the first inorganic layer TL1 in the first emission area EA1 (e.g., the first (or previous) emission area structure), the second light emitting layer EL2, the second common electrode CE2 and the second inorganic layer TL2 may be formed in the second emission area EA2 (e.g., the second (or next) emission area structure). In this case, the materials for the subsequent structures are deposited on the entire substrate SUB including the previous structure, and thus, the second light emitting material layer ELL2, the second electrode material layer CEL2 and the second inorganic material layer TLL2 (see Fig.15 ) may be formed on the previous structure of the first inorganic layer TL1 covering the first emission region EA1 and the periphery of the first emission region EA1. The second light emitting material layer ELL2 may be made of the same material as the second light emitting layer EL2, and the second electrode material layer CEL2 may be made of the same material as the second common electrode CE2.

[0135] When there is no dam DAM on the second bank layer BN2, due to the undercut structure of the wing portion TL1_W of the first inorganic layer TL1, as shown Figure 6 As shown in , at the outer boundary of the first inorganic layer TL1, portions of the second light emitting material layer ELL2 and the second electrode material layer CEL2 are disconnected from each other by such an undercut structure and a gap is formed therebetween. After the second inorganic material layer TLL2 is formed over the disconnected portions of the second light emitting material layer ELL2 and the second electrode material layer CEL2, only the second inorganic layer TL2 disposed in and around the second emission area EA2 is left, and the second inorganic material layer TLL2 disposed in the remaining area is removed by an etching process. In this case, as Figure 6 As shown in , free radicals of the etchant used to remove the second inorganic material layer TLL2 may penetrate into the gap between the second light emitting material layer ELL2 and the second electrode material layer CEL2 disconnected from each other. The free radicals penetrated into the gap remove a portion of the first inorganic layer TL1 and weaken the adhesion or encapsulation between the dam structure BNS and the first inorganic layer TL1. This may cause damage to the first light emitting element ED1 and become a dark spot when the display device 10 is driven to display an image.

[0136] When Figure 7As shown in the method of setting the display device 10, when the dam DAM is set on the second bank layer BN2, the second light-emitting material layer ELL2 and the second electrode material layer CEL2 can cover the first inorganic layer TL1 and the dam DAM without being disconnected by the wing of the previous structure. Since the dam DAM is set to occupy a position adjacent to the outer edge of the first inorganic layer TL1, the step coverage of the second light-emitting material layer ELL2 and the second electrode material layer CEL2 can be improved. The first inorganic layer TL1 is surrounded by the second light-emitting material layer ELL2 and is therefore not exposed to the etchant during the removal of a portion of the second inorganic material layer TLL2. Since the first inorganic layer TL1 is covered by the second light-emitting material layer ELL2 and the second electrode material layer CEL2, damage to the first light-emitting element ED1 can be prevented, and the brightness difference between the light-emitting elements ED1, ED2, and ED3 can be reduced.

[0137] The dam DAM may not overlap with the first inorganic encapsulation layers TL1, TL2, and TL3 in the thickness direction (e.g., the third direction DR3) of the substrate SUB. Due to the non-overlapping, the dam DAM and the corresponding inorganic encapsulation patterns among the first inorganic encapsulation layers TL1, TL2, and TL3 may be adjacent to or spaced apart from each other along the second bank layer BN2. The dam DAM is coplanar with the first inorganic encapsulation layers TL1, TL2, and TL3 (that is, the dam DAM may be spaced apart from the first inorganic encapsulation layers TL1, TL2, and TL3, but may be located on the same line in a direction parallel to the substrate SUB). The first inorganic encapsulation layers TL1, TL2, and TL3 may be spaced apart from the dam DAM by a predetermined distance d1 along the second bank layer BN2. The distance d1 between the first inorganic encapsulation layers TL1, TL2, and TL3 and the dam DAM may be defined as the minimum distance between the first inorganic encapsulation layers TL1, TL2, and TL3 and the dam DAM.

[0138] The distance d1 between the first inorganic encapsulation layers TL1, TL2 and TL3 and the dam DAM may be about 0.75 to about 1.25 times the second thickness h2 of the light-emitting layers EL1, EL2 and EL3. When the distance d1 is within the above range, the coverage of the light-emitting material layers ELL2 and ELL3 deposited on the first inorganic encapsulation layers TL1, TL2 and TL3 is improved, so that the light-emitting material layers ELL2 and ELL3 can respectively fill the space between the first inorganic encapsulation layers TL1, TL2 and TL3 and the dam DAM closest to the outer edge of such encapsulation pattern. In an embodiment, the distance d1 between the first inorganic encapsulation layers TL1, TL2 and TL3 and the dam DAM may be about 1000Å to about 3000Å.

[0139] The maximum vertical distance h3 from the substrate SUB to the upper surface of the dam DAM may be less than the maximum vertical distance h4 from the substrate SUB to the upper surfaces of the first inorganic encapsulation layers TL1, TL2, and TL3. The vertical distance may be the maximum distance or height of a particular element relative to a reference. The upper surface may be farthest from a reference (such as the substrate SUB, the second bank layer BN2, etc.). The height of the dam or wing portion may be defined at the farthest point or upper surface relative to the reference. When the height of the dam DAM is greater than the height of the wing portions TL1_W, TL2_W, and TL3_W of the first inorganic encapsulation layers TL1, TL2, and TL3, the coverage of the light-emitting material layers ELL2 and ELL3 deposited on the first inorganic encapsulation layers TL1, TL2, and TL3 may be insufficient. In an embodiment, the first thickness h1 of the dam DAM may be about 1000Å to about 3000Å.

[0140] The dam DAM may include an organic material. In an embodiment, the dam DAM may include one or more selected from the group consisting of polyimide, polyamide, benzocyclobutene, phenolic resin, acrylic resin, methacrylic resin, polyisoprene, vinyl resin, epoxy resin, urethane resin, cellulose resin and perylene resin. The dam DAM may include an opaque material and a transparent material. The dam DAM may be made of an organic material different from the organic material of the organic encapsulation layer TFE2.

[0141] The organic encapsulation layer TFE2 is disposed on the second bank layer BN2, the first inorganic encapsulation layers TL1, TL2, and TL3, and the dam DAM. A portion of the organic encapsulation layer TFE2 may be disposed in a space between the wing portions TL1_W, TL2_W, and TL3_W of the first inorganic encapsulation layers TL1, TL2, and TL3, which are spaced apart from each other, and the upper surface of the second bank layer BN2. A portion of the second bank layer BN2 may not overlap with the first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3, and the dam DAM, and may be in direct contact with the organic encapsulation layer TFE2.

[0142] The second inorganic encapsulation layer TFE 3 may be disposed on the organic encapsulation layer TFE 2. The second inorganic encapsulation layer TFE 3 may include aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0143] The light blocking layer BM may be disposed on the thin film encapsulation layer TFEL. The light blocking layer BM may include a plurality of holes OPT1, OPT2, and OPT3 defined therein to overlap with the emission areas EA1, EA2, and EA3, respectively. For example, the first hole OPT1 may be disposed to overlap with the first emission area EA1. The second hole OPT2 may be disposed to overlap with the second emission area EA2, and the third hole OPT3 may be disposed to overlap with the third emission area EA3. The area or size of each of the holes OPT1, OPT2, and OPT3 may be larger than the area or size of each of the emission areas EA1, EA2, and EA3. The holes OPT1, OPT2, and OPT3 of the light blocking layer BM are formed to be larger than the emission areas EA1, EA2, and EA3, and therefore, the light emitted from the emission areas EA1, EA2, and EA3 may be viewed not only from the front surface of the display device 10 (e.g., in the third direction DR3) but also from the side surface of the display device 10, such as by a user from outside the display device 10.

[0144] The light blocking layer BM may include a light absorbing material. For example, the light blocking layer BM may include an inorganic black pigment or an organic black pigment. The inorganic black pigment may be carbon black, and the organic black pigment may include at least one of lactam black, perylene black, and aniline black, but the present disclosure is not limited thereto. The light blocking layer BM may prevent color mixing caused by penetration of visible light between the first emission area EA1, the second emission area EA2, and the third emission area EA3, thereby improving the color gamut of the display device 10.

[0145] The display device 10 may include a plurality of color filters CF1, CF2, and CF3 disposed in the emission areas EA1, EA2, and EA3. The plurality of color filters CF1, CF2, and CF3 may be disposed to correspond to the emission areas EA1, EA2, and EA3, respectively. For example, the color filters CF1, CF2, and CF3 may be disposed on a light blocking layer BM including a plurality of holes OPT1, OPT2, and OPT3, and the plurality of holes OPT1, OPT2, and OPT3 are disposed to correspond to the emission areas EA1, EA2, and EA3. The holes OPT1, OPT2, and OPT3 of the light blocking layer BM may be formed to overlap with the openings of the emission areas EA1, EA2, and EA3 and / or the embankment structure BNS and the pixel defining film PDL, and a light emitting area may be formed, and light emitted from the emission areas EA1, EA2, and EA3 is emitted to the outside of the display panel 100 through the light emitting area. Each of the color filters CF1 , CF2 , and CF3 may have a larger area than each of the holes OPT1 , OPT2 , and OPT3 of the light blocking layer BM, and may completely cover the light emitting region formed by each of the holes OPT1 , OPT2 , and OPT3 .

[0146] The color filters CF1, CF2, and CF3 may include a first color filter CF1, a second color filter CF2, and a third color filter CF3 that are arranged to correspond to different emission areas EA1, EA2, and EA3, respectively. The color filters CF1, CF2, and CF3 may include a colorant such as a dye or a pigment that absorbs light of a wavelength band other than light of a specific wavelength band, and may be arranged to correspond to the color of the light emitted from the emission areas EA1, EA2, and EA3. For example, the first color filter CF1 may be a red color filter that is arranged to overlap with the first emission area EA1 and allows only the first light as red light to be transmitted therethrough. The second color filter CF2 may be a green color filter that is arranged to overlap with the second emission area EA2 and allows only the second light as green light to be transmitted therethrough, and the third color filter CF3 may be a blue color filter that is arranged to overlap with the third emission area EA3 and allows only the third light as blue light to be transmitted therethrough.

[0147] A plurality of color filters CF1, CF2 and CF3 may be spaced apart from other adjacent color filters CF1, CF2 and CF3 along a solid portion of the light blocking layer BM. The color filters CF1, CF2 and CF3 may have an area larger than the holes OPT1, OPT2 and OPT3 of the light blocking layer BM, while covering the holes OPT1, OPT2 and OPT3 of the light blocking layer BM, respectively, but may have an area sufficient to be spaced apart from other color filters CF1, CF2 and CF3 on the light blocking layer BM. However, the present disclosure is not limited thereto. A plurality of color filters CF1, CF2 and CF3 may be arranged to partially overlap with other adjacent color filters CF1, CF2 and CF3. Different color filters CF1, CF2 and CF3 may overlap each other on a solid portion of the light blocking layer BM, and the solid portion is an area that is not overlapped with the emission areas EA1, EA2 and EA3. In the display device 10, the color filters CF1, CF2 and CF3 are arranged to overlap each other, so that the intensity of the reflected light caused by the external light can be reduced. In addition, the color sense of the reflected light caused by the external light can be controlled by adjusting the arrangement, shape, area, etc. of the color filters CF1, CF2 and CF3 in the plan view.

[0148] An overcoat layer OC may be disposed on the color filters CF1, CF2, and CF3 to flatten the upper ends of the color filters CF1, CF2, and CF3. The overcoat layer OC may be a colorless light-transmitting layer having no color in the visible light band. For example, the overcoat layer OC may include a colorless light-transmitting organic material such as an acrylic resin.

[0149] Hereinafter, a process for setting the display device 10 according to an embodiment will be described with reference to other drawings.

[0150] Figures 8 to 18are detailed cross-sectional views sequentially illustrating a process for disposing the display device 10 according to an embodiment.

[0151] exist Figures 8 to 18 , a process of forming or setting a dam structure BNS and a light emitting element ED in a light emitting element layer EML and a thin film encapsulation layer TFEL on the light emitting element layer EML of a display device 10 is schematically shown. Hereinafter, a description of a process of forming each layer in a process for manufacturing the display device 10 will be omitted, and an order of forming each layer will be described.

[0152] Reference Figure 8 A plurality of pixel electrodes AE1, AE2 and AE3 spaced apart from each other in the first electrode layer, a sacrificial layer SFL spaced apart from each other, a pixel defining material layer PDLL and a plurality of embankment material layers BNL1 and BNL2 are formed on the entire second passivation layer PAS2.

[0153] Despite Figure 8 1. However, a thin film transistor layer TFTL may be provided on the substrate SUB, and the structure of the thin film transistor layer TFTL is the same as that of the above reference. Figure 4 The structures described are the same. A detailed description thereof will be omitted.

[0154] Then, refer to Fig. 9 A photoresist (not shown) is formed on the second bank material layer BNL2, and a first etching process (first etching, Fig. 9 ). The holes HOL in the first and second bank material layers BNL1 and BNL2 may be formed by a first etching process. The photoresist patterns of the photoresist may be disposed to be spaced apart from each other on the second bank material layer BNL2 and may be disposed to expose regions of the second bank material layer BNL2 overlapping the plurality of pixel electrodes AE1, AE2, and AE3.

[0155] In an embodiment, anisotropic dry etching may be performed as the first etching process (first etching). The hole HOL may be formed in a region overlapping the plurality of pixel electrodes AE1 , AE2 , and AE3 , and may form an opening of the bank structure BNS.

[0156] Next, refer to Fig.10 , can be processed by a second etching process (second etching, Fig.10The first bank material layer BNL1 may have an etching rate faster than the second bank material layer BNL2, and the inner side surface of the second bank layer BN2 may be formed to protrude from the inner side surface of the first bank layer BN1. The inner side surface of the second bank layer BN2 protrudes more than the side surface of the first bank layer BN1 in the direction toward the hole HOL to form a tip TIP. The lower surface of the second bank layer BN2 may be exposed at the tip TIP to define the undercut structure.

[0157] In an embodiment, the second etching process may be isotropic wet etching. In the second etching process, an alkali etchant may be used. A dam structure BNS including a first dam layer BN1 and a second dam layer BN2 may be obtained by the second etching process. A portion of the pixel defining material layer PDLL is exposed outside the dam structure BNS at the hole HOL.

[0158] Then, if Fig.11 As shown in, a dam DAM can be formed on the second bank layer BN2. The step of forming the dam DAM may include applying the dam material to the second bank layer BN2 by slit coating, spin coating or inkjet printing, and patterning the dam material by photolithography. In the step of patterning the dam material, the width of the dam DAM can be adjusted according to the mask. The organic material as described above can be used as the dam material. In the plan view, the dam DAM can be set as a discrete pattern.

[0159] Next, if Fig.12 As shown in FIG. , by the third etching process (third etching, Fig.12 ), a portion of the pixel defining material layer PDLL may be removed, and a portion of the sacrificial layer SFL may also be removed. The third etching process may include a dry etching process for removing the pixel defining material layer PDLL and a wet etching process for removing the sacrificial layer SFL. The step of removing the pixel defining material layer PDLL in the dry etching process may expose a portion of the sacrificial layer SFL outside the pixel defining material layer PDLL at the hole HOL. The wet etching process may remove the portion of the sacrificial layer SFL exposed to the hole HOL.

[0160] The sacrificial layer SFL may protect the pixel electrodes AE1, AE2, and AE3 from plasma in the dry etching process. Portions of the sacrificial layer SFL exposed to the hole HOL and portions of the sacrificial layer SFL respectively between the first bank layer BN1 and each of the pixel electrodes AE1, AE2, and AE3 may be removed. However, the sacrificial layer SFL may not be completely removed, and a residual portion may remain as a partial residual pattern RP between the pixel definition film PDL and each of the pixel electrodes AE1, AE2, and AE3, respectively.

[0161] Through the third etching process, the pixel electrodes AE1, AE2, and AE3 may be exposed outside the pixel defining layer. Thereafter, the photoresist (not shown) may be removed.

[0162] Then, if Fig.13 As shown in , a first light emitting layer EL1, a first common electrode CE1 and a capping layer CAP are deposited on the first pixel electrode AE1 to form a first light emitting element ED1 in the corresponding hole HOL. In this case, the corresponding materials of the first light emitting layer EL1, the first common electrode CE1 and the capping layer CAP are formed on the entire surface of the substrate SUB having the dam DAM. Therefore, the first light emitting material layer ELL1, the first electrode material layer CEL1 and the capping material layer CAPL may also be formed on the second bank layer BN2 and the dam DAM.

[0163] The first light emitting layer EL1 and the first light emitting material layer ELL1, which are parts of the same material layer, may be separated from each other by the tip TIP of the second bank layer BN2, the first common electrode CE1 and the first electrode material layer CEL1, which are parts of the same material layer, may be separated from each other by the tip TIP of the second bank layer BN2, and the capping layer CAP and the capping material layer CAPL, which are parts of the same material layer, may be separated from each other by the tip TIP of the second bank layer BN2. The first light emitting layer EL1 is formed on the first pixel electrode AE1, and at the same time, the remaining part of the first light emitting material layer ELL1 may be formed on the second bank layer BN2. The first common electrode CE1 is formed on the first light emitting layer EL1, and at the same time, the remaining part of the first electrode material layer CEL1 may be formed on the first light emitting material layer ELL1. That is, the first light emitting layer EL1 and the first light emitting material layer ELL1 are at the same layer with each other, the first common electrode CE1 and the first electrode material layer CEL1 are at the same layer with each other, and the capping layer CAP and the capping material layer CAPL are at the same layer with each other. When in the same layer, the elements may be formed in the same process and / or include the same material as each other, the elements may be corresponding parts of the same material layer, the elements may be in the same layer by forming an interface with the same underlying layer or overlying layer, etc., but is not limited thereto.

[0164] The first light emitting layer EL1 and the first common electrode CE1 may be formed by a deposition process. The material for the first light emitting layer EL1 and the first common electrode CE1 may not be smoothly deposited in the hole HOL due to the tip TIP of the second bank layer BN2. However, the material of the first light emitting layer EL1 and the first common electrode CE1 is deposited in a direction inclined relative to the upper surface of the substrate SUB, rather than in a direction perpendicular to the upper surface of the substrate SUB, and thus may be deposited in a region and on a surface effectively hidden by the tip TIP of the second bank layer BN2.

[0165] Compared with the deposition process for forming the light-emitting layers EL1, EL2, and EL3, the deposition process for forming the common electrodes CE1, CE2, and CE3 may be performed in an inclined direction relatively closer to the horizontal direction with respect to the DR1-DR2 plane. Therefore, the common electrodes CE1, CE2, and CE3 may contact the side surface of the first bank layer BN1 in which the opening is defined with a larger contact area than the light-emitting layers EL1, EL2, and EL3. Alternatively, the common electrodes CE1, CE2, and CE3 may be deposited along the side surface of the first bank layer BN1 in which the opening is defined to a position higher than the light-emitting layers EL1, EL2, and EL3. Different common electrodes CE1, CE2, and CE3 may contact the first bank layer BN1 having high conductivity to be electrically connected to each other via the solid portion of the first bank layer BN1.

[0166] Subsequently, a first inorganic material layer TLL1 is formed to cover the first light emitting element ED1 and the capping layer CAP. The first inorganic material layer TLL1 may be formed (e.g., continuously) to completely cover the outer surfaces of the first light emitting element ED1, the bank layers BN1 and BN2, the capping layer CAP, the first light emitting material layer ELL1, the first electrode material layer CEL1, and the capping material layer CAPL without any disconnected portions. Specifically, the first inorganic material layer TLL1 is formed on the upper surface of the first common electrode CE1, the upper surface of the capping layer CAP, the side surface of the first bank layer BN1, the lower surface and the upper surface of the second bank layer BN2, and the upper surfaces of the first electrode material layer CEL1 and the capping material layer CAPL.

[0167] Next, refer to Fig.14 , a fourth etching process (fourth etching, Fig.14 ). In an embodiment, the fourth etching process may include a dry etching process to remove a portion of the first inorganic material layer TLL1 and a wet etching process to remove a portion of each of the first electrode material layer CEL1 and the first light emitting material layer ELL1.

[0168] In the dry etching process, a portion of the first inorganic material layer TLL1 may be removed in an area other than an area overlapping with the first emission area EA1 and an edge area surrounding or extending from the first emission area EA1. The first inorganic layer TL1 remains in an area overlapping with the first emission area EA1 and extending from the first emission area EA1 to an edge area surrounding the first emission area EA1. A portion of the capping material layer CAPL is also removed to expose the first electrode material layer CEL1.

[0169] In the wet etching process as isotropic etching, a portion of each of the first light emitting material layer ELL1 and the first electrode material layer CEL1 of the second emission area EA2 and the third emission area EA3 that is not covered by the first inorganic layer TL1 and the first electrode material layer CEL1 and the first light emitting material layer ELL1 disposed on the second bank layer BN2 and the dam DAM may be removed. Therefore, the first light emitting material layer ELL1 and the first electrode material layer CEL1 disposed between the wing portion TL1_W of the first inorganic layer TL1 and the second bank layer BN2 may also be removed.

[0170] Then, if Fig.15 As shown in FIG. 1 , a second light emitting layer EL2, a second common electrode CE2 and a capping layer CAP are deposited on the second pixel electrode AE2 to form a second light emitting element ED2 on the substrate SUB having the previous emission structure of the first inorganic layer TL1 and the first light emitting element ED1. Thereafter, a second inorganic material layer TLL2 is formed to cover the second light emitting element ED2 and the capping layer CAP. In this process, as shown in FIG. Fig.15 The material layers are deposited on the entire surface of the substrate SUB as shown in the figure, and the second light-emitting material layer ELL2, the second electrode material layer CEL2 and the covering material layer CAPL can cover the first inorganic layer TL1 and the dam DAM without disconnection. In particular, the second light-emitting material layer ELL2 can also be arranged in the space or gap between the first inorganic layer TL1 and the dam DAM which are spaced apart from each other. The second light-emitting material layer ELL2 can be made of or include the same material as the second light-emitting layer EL2.

[0171] exist Fig.15 In the embodiment, the second light emitting material layer ELL2 extends along the dam DAM closest to the first inorganic layer TL1 and along the outer surface of the first inorganic layer TL1. The second light emitting material layer ELL2 may remain outside the gap between the first wing portion TL1_W and the tip TIP of the second bank layer BN2. The empty space or gap may be defined by the first inorganic layer TL1 together with the second bank layer BN2 and the second light emitting material layer ELL2.

[0172] Next, if Fig.16 As shown in FIG. 1 , the second inorganic layer TL2 overlapping the second emission area EA2 and the edge around the second emission area EA2 may be formed by removing a portion of the second inorganic material layer TLL2. Fig.14The dry etching process for removing the first inorganic material layer TLL1 is similarly performed. A portion of the capping material layer CAPL is also removed to expose the second electrode material layer CEL2. Due to the second light emitting material layer ELL2 disposed in the space between the first inorganic layer TL1 and the dam DAM spaced apart from each other and blocking the gap between the first wing portion TL1_W and the tip TIP of the second bank layer BN2, the outer surface of the first inorganic layer TL1 may not be exposed to the etchant plasma, and the first light emitting element ED1 may be protected during the removal of a portion of the second inorganic material layer TLL2.

[0173] Then, if Fig.17 As shown in FIG. 1 , the second bank layer BN2 and the dam DAM can be exposed by removing the second electrode material layer CEL2 and the second light emitting material layer ELL2 to set the second inorganic layer TL2 and the second light emitting element ED2. Fig.14 The wet etching process of removing the first electrode material layer CEL1 and the first light emitting material layer ELL1 is similarly performed.

[0174] Thereafter, when similarly executing Fig.17 and Fig.18 During the process shown in , a third light emitting element ED3 and a third inorganic layer TL3 together as another latter emission structure can be formed on the stacked structure having both the former emission structure at the first emission area EA1 and the latter emission structure at the second emission area EA2.

[0175] Subsequently, although not shown in the drawings, the display device 10 is further provided by forming an organic encapsulation layer TFE2 and a second inorganic encapsulation layer TFE3 of a thin film encapsulation layer TFEL, a light blocking layer BM, a color filter layer CFL, and an overcoat layer OC on the light emitting elements ED1, ED2, and ED3 and the dam structure BNS. The structures of the thin film encapsulation layer TFEL, the light blocking layer BM, the color filter layer CFL, and the overcoat layer OC are the same as those described above, and thus a detailed description thereof will be omitted.

[0176] In one or more embodiments, the display device 10 includes a pixel defining layer, a light-emitting element, a bank layer BNS, a first inorganic pattern TL1, a second inorganic pattern TL2, and a dam DAM, the pixel defining layer defines an emission area including a first emission area EA1 and a second emission area EA2 spaced apart from each other, the light-emitting element includes a first light-emitting element ED1 in the first emission area EA1 and a second light-emitting element ED2 in the second emission area EA2, the bank layer BNS is on the pixel defining layer and defines openings (e.g., holes HOL) corresponding to the emission areas, respectively, the bank layer BNS includes a first bank layer BN1 and a second bank layer BN2 in sequence from the pixel defining layer, the first bank layer BN1 has a side surface exposed to the opening, the second bank layer BN2 protrudes much more than the side surface of the first bank layer BN1 in a corresponding direction toward the emission area, and includes an upper surface, the first inorganic pattern TL1 is on the bank layer BNS, and the second inorganic pattern TL2 protrudes more than the side surface of the first bank layer BN1 in a corresponding direction toward the emission area, and includes an upper surface. In the first opening of NS corresponding to the first emission area EA1, the first inorganic pattern TL1 extends out of the first opening and overlaps with the first part of the second bank layer BN2 adjacent to the first emission area EA1, and is spaced from the upper surface of the second bank layer BN2 at the first part of the second bank layer BN2. In the second opening of the bank layer BNS corresponding to the second emission area EA2, the second inorganic pattern TL2 is spaced from the first inorganic pattern TL1, extends out of the second opening, overlaps with the second part of the second bank layer BN2 adjacent to the second emission area EA2, and is spaced from the upper surface of the second bank layer BN2 at the second part of the second bank layer BN2. The dam DAM is on the second bank layer BN2, the dam DAM is between the first inorganic pattern TL1 and the second inorganic pattern TL2, and is spaced from both the first inorganic pattern TL1 and the second inorganic pattern TL2.

[0177] In a method of setting a display device 10, the method includes: setting pixel electrodes spaced apart from each other ( Figure 8 AE1, AE2, AE3) layers and sacrificial layers ( Figure 8 a pixel defining material layer PDLL ( Figure 8 ); bank material layers BNL1 and BNL2 are provided on the pixel definition material layer PDLL ( Figure 8 ); etching the bank material layers BNL1 and BNL2 at the region overlapping the pixel electrode to provide a bank layer BNS defining an emission region opening, wherein the emission region opening exposes the pixel defining material layer PDLL outside the bank layer BNS ( Fig. 9 and Fig.10), the bank layer BNS includes a first bank layer BN1 and a second bank layer BN2, the first bank layer BN1 having a side surface exposed to the emission region opening, the second bank layer BN2 being on the first bank layer BN1 and defining a tip TIP of the second bank layer BN2 extending further than the side surface of the first bank layer BN1 ( Fig.10 ); A dam DAM is provided on the second bank layer BN2 and spaced apart from the emission region opening ( Fig.11 ); The pixel electrode is exposed at the opening of the emission region by etching the pixel definition material layer PDLL exposed at the opening of the emission region and etching the sacrificial layer SFL corresponding to the pixel electrode ( Fig.12 ); a first light emitting element ED1 is disposed in a first emission area opening (a hole HOL at a first emission area EA1) among the emission area openings, and the first light emitting element ED1 includes a first pixel electrode AE1, a first light emitting layer EL1 and a first common electrode CE1 among the pixel electrodes ( Fig.13 ); and disposing a first inorganic pattern TL1 on the first light emitting element ED1 in the first emission region opening ( Fig.13 and Fig.14 ).

[0178] Reference Fig.13 The step of setting the first light-emitting layer EL1 includes setting the first light-emitting material layer ELL1, the first light-emitting material layer ELL1 is on the first pixel electrode AE1, the second bank layer BN2 and the dam DAM, and defines the first light-emitting layer EL1, the first light-emitting layer EL1 is in the first emission region opening and is disconnected from the rest of the first light-emitting material layer ELL1 by the tip TIP of the second bank layer BN2; the step of setting the first common electrode CE1 includes setting the first electrode material layer CEL1, the first electrode material layer CEL1 is on the first light-emitting material layer ELL1 (that is, the first light-emitting material layer ELL1) The step of setting the first inorganic pattern TL1 includes setting a first inorganic material layer TLL1, the first inorganic material layer TLL1 is on the first electrode material layer CEL1 (that is, the rest of the first electrode material layer CEL1 and the first common electrode CE1), and defines a first common electrode CE1, the first common electrode CE1 is in the first emission area opening, and is disconnected from the rest of the first electrode material layer CEL1 by the tip TIP of the second bank layer BN2; the step of setting the first inorganic pattern TL1 includes setting a first inorganic material layer TLL1, the first inorganic material layer TLL1 is on the first electrode material layer CEL1 (that is, the rest of the first electrode material layer CEL1 and the first common electrode CE1), and continuously extends from the first common electrode CE1 in the first emission area opening to the dam DAM.

[0179] Reference Fig.13 and Fig.14 The method includes: etching a portion of the first inorganic material layer TLL1 corresponding to the remaining portion of the first electrode material layer CEL1; and exposing the dam DAM by etching the remaining portion of the first electrode material layer CEL1 and the remaining portion of the first light emitting material layer ELL1. Figures 14 to 16 The method includes: setting a second light-emitting element ED2 in a second emission area opening among the emission area openings, the second emission area opening is spaced apart from the first emission area opening, and a dam DAM is therebetween, the second light-emitting element ED2 includes a second pixel electrode AE2, a second light-emitting layer EL2 and a second common electrode CE2 among the pixel electrodes; and setting a second inorganic pattern TL2 on the second light-emitting element ED2 in the second emission area opening.

[0180] Reference Fig.15 The step of setting the second light-emitting layer EL2 includes setting a second light-emitting material layer ELL2, the second light-emitting material layer ELL2 is on the first inorganic pattern TL1, the second pixel electrode AE2, the second bank layer BN2 and the dam DAM, and defines the second light-emitting layer EL2, the second light-emitting layer EL2 is in the second emission area opening, and is disconnected from the rest of the second light-emitting material layer ELL2 by the tip TIP of the second bank layer BN2; the step of setting the second common electrode CE2 includes setting a second electrode material layer CEL2, the second electrode material layer CEL2 is on the first inorganic pattern TL1, the second light-emitting material layer ELL2 (that is, the second light-emitting material layer ELL2 The step of setting the second inorganic pattern TL2 includes setting a second inorganic material layer TLL2, the second inorganic material layer TLL2 is on the first inorganic pattern TL1, the second electrode material layer CEL2 (that is, the rest of the second electrode material layer CEL2 and the second common electrode CE2), and continuously extends from the second common electrode CE2 in the opening of the second emission area to the dam DAM.

[0181] In summarizing the detailed description, it will be appreciated by those skilled in the art that many changes and modifications may be made to the embodiments without departing substantially from the principles of the invention. Therefore, the embodiments of the disclosed invention are used in a general and descriptive sense only and not for the purpose of limitation.

Claims

1. A display device, comprising: a pixel defining layer defining an emission region, wherein the emission region includes a first emission region and a second emission region spaced apart from each other; Light-emitting elements, including a first light-emitting element in the first emission region and a second light-emitting element in the second emission region; a bank layer on the pixel defining layer and defining openings respectively corresponding to the emission regions, the bank layer comprising, in order from the pixel defining layer: a first bank layer including side surfaces exposed to the openings; and a second bank layer protruding more than the side surfaces of the first bank layer in a corresponding direction toward the emission regions and including an upper surface; a first inorganic pattern, in a first opening of the bank layer corresponding to the first emission region, the first inorganic pattern extending out of the first opening, overlapping a first portion of the second bank layer adjacent to the first emission region, and spaced apart from the upper surface of the second bank layer at the first portion of the second bank layer; a second inorganic pattern, in a second opening of the bank layer corresponding to the second emission region, the second inorganic pattern being spaced apart from the first inorganic pattern, extending out of the second opening, overlapping a second portion of the second bank layer adjacent to the second emission region, and spaced apart from the upper surface of the second bank layer at the second portion of the second bank layer; and A dam is formed on the second bank layer, the dam being between the first inorganic pattern and the second inorganic pattern and spaced apart from both the first inorganic pattern and the second inorganic pattern.

2. The display device according to claim 1, wherein: The dam is coplanar with the first inorganic pattern and the second inorganic pattern.

3. The display device according to claim 1, further comprising an organic encapsulation layer on the bank layer, in, A first space is defined between the upper surface of the second bank layer at the first portion thereof and the first inorganic pattern, and a second space is defined between the upper surface of the second bank layer at the second portion thereof and the second inorganic pattern, and The organic encapsulation layer extends into the first space and the second space.

4. The display device according to claim 1, wherein: Each of the light emitting elements includes a light emitting layer having a thickness, and The dam is spaced apart from the first inorganic pattern by a distance that is 0.75 to 1.25 times the thickness of the light emitting layer.

5. The display device according to claim 1, wherein: The dam is spaced apart from the first inorganic pattern by a distance of 1000 angstroms to 3000 angstroms.

6. The display device according to claim 1, wherein: Each of the light emitting elements includes a light emitting layer having a thickness of 1500 angstroms to 2500 angstroms.

7. The display device according to claim 1, wherein: In a direction away from the pixel defining layer, along a thickness direction of the display device, the first inorganic pattern protrudes more than the dam.

8. The display device according to claim 1, wherein: The thickness of the dam is 1000 angstroms to 3000 angstroms.

9. The display device according to claim 1, wherein: The first light emitting element comprises a first common electrode, The second light emitting element includes a second common electrode spaced apart from the first common electrode, A portion of the first bank layer is between the first opening and the second opening and includes a first side surface exposed to the first opening and a second side surface exposed to the second opening, and The first common electrode and the second common electrode are in contact with the first side surface and the second side surface of the first bank layer, respectively.

10. The display device according to claim 3, wherein: The dam includes a material different from that of the organic encapsulation layer.

11. The display device according to claim 1, wherein: The dam includes one or more selected from the group consisting of polyimide, polyamide, benzocyclobutene, phenolic resin, acrylic resin, methacrylic resin, polyisoprene, vinyl-based resin, epoxy-based resin, urethane-based resin, cellulose-based resin, and perylene-based resin.

12. The display device according to claim 1, wherein: The second bank layer protruding more than the side surface of the first bank layer defines a tip, the tip including a lower surface exposed to the first opening and the second opening, The first light emitting element comprises a first common electrode, The second light emitting element includes a second common electrode spaced apart from the first common electrode, The first inorganic pattern contacts the lower surface of the second bank layer in the first opening, and The second inorganic pattern contacts the lower surface of the second bank layer in the second opening.

13. The display device according to claim 1, wherein: Each of the light emitting elements includes a pixel electrode having an upper surface, and The pixel defining layer is spaced apart from the upper surface of the pixel electrode.

14. The display device according to claim 13, further comprising: a space between the pixel defining layer and the upper surface of the pixel electrode, and The residual pattern, in said space.

15. A method for setting a display device, the method comprising the following steps: A layer of pixel electrodes spaced apart from each other and a sacrificial layer respectively on the pixel electrodes are provided, A pixel defining material layer is provided on the sacrificial layer, the pixel electrode and the space between the sacrificial layer and the pixel electrode, Disposing a bank material layer on the pixel definition material layer; The bank material layer is etched at a region overlapping the pixel electrode to provide a bank layer defining an emission region opening, the emission region opening exposing the pixel defining material layer outside the bank layer, the bank layer comprising: a first bank layer having a side surface exposed to the emission region opening, and a second bank layer on the first bank layer and defining a tip of the second bank layer extending more than the side surface of the first bank layer; providing a dam on the second bank layer and spaced apart from the emission area opening; exposing the pixel electrode at the emission area opening by etching the pixel definition material layer exposed at the emission area opening and etching the sacrificial layer corresponding to the pixel electrode; A first light emitting element is disposed in a first emission area opening among the emission area openings, wherein the first light emitting element includes a first pixel electrode, a first light emitting layer and a first common electrode among the pixel electrodes, and A first inorganic pattern is disposed on the first light emitting element in the first emission region opening.

16. The method according to claim 15, wherein: The steps of setting up the dam include: providing the material of the dam onto the second bank layer by slit coating, spin coating or inkjet printing, and The material of the dam is patterned by photolithography.

17. The method according to claim 15, wherein: The step of providing the first light emitting layer includes providing a first light emitting material layer, the first light emitting material layer is on the first pixel electrode, the second bank layer and the dam, and defines the first light emitting layer, the first light emitting layer is in the first emission region opening, and is disconnected from the rest of the first light emitting material layer by the tip of the second bank layer, The step of providing the first common electrode includes providing a first electrode material layer, the first electrode material layer is on the first light emitting material layer and defines the first common electrode, the first common electrode is in the first emission region opening and is disconnected from the rest of the first electrode material layer by the tip of the second bank layer, and The step of providing the first inorganic pattern includes providing a first inorganic material layer on the first electrode material layer and continuously extending from the first common electrode in the first emission region opening to the dam.

18. The method according to claim 17, further comprising the steps of: etching a portion of the first inorganic material layer corresponding to the remaining portion of the first electrode material layer; exposing the dam by etching the remaining portion of the first electrode material layer and the remaining portion of the first light emitting material layer; A second light emitting element is disposed in a second emission area opening among the emission area openings, the second emission area opening is spaced apart from the first emission area opening, and the dam is between the first emission area opening and the second emission area opening, and the second light emitting element includes a second pixel electrode among the pixel electrodes, a second light emitting layer, and a second common electrode; as well as A second inorganic pattern is disposed on the second light emitting element in the second emission region opening.

19. The method according to claim 18, wherein: The step of providing the second light emitting layer includes providing a second light emitting material layer, the second light emitting material layer is on the first inorganic pattern, the second pixel electrode, the second bank layer and the dam, and defines the second light emitting layer, the second light emitting layer is in the second emission region opening, and is disconnected from the rest of the second light emitting material layer by the tip of the second bank layer, The step of providing the second common electrode includes providing a second electrode material layer, the second electrode material layer is on the first inorganic pattern, the second light emitting material layer, the second bank layer and the dam, and defines the second common electrode, the second common electrode is in the second emission region opening, and is disconnected from the rest of the second electrode material layer by the tip of the second bank layer, and The step of providing the second inorganic pattern includes providing a second inorganic material layer on the first inorganic pattern and the second electrode material layer and continuously extending from the second common electrode in the second emission region opening to the dam.

20. The method according to claim 18, wherein: The step of etching the portion of the first inorganic material layer comprises a dry etching process, and The step of etching the remaining portion of the first electrode material layer and the remaining portion of the first light emitting material layer comprises a wet etching process.

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