NAND memory with different pass voltage ramp rates for binary and polymorphic memories

Abstract

To reduce spikes in the current used by a NAND memory die, different ramp rates are used during a program operation for pass voltages applied to unselected word lines, depending on whether data is stored in a multi-level cell (MLC) format or in a single-level cell (SLC) format. The ramp rates may be determined by device characterization and stored on the memory die as parameter values. Depending on whether the data is stored in the MLC format or the SLC format, different ramp rate interval values may also be used for the pass voltage applied to unselected word lines during a program operation.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] For all purposes, this application claims the benefit of the entire contents of U.S. Non-Provisional Application No. 17 / 897,993, filed on August 29, 2022, and entitled “NAND MEMORY WITH DIFFERENT PASSVOLTAGE RAMP RATES FOR BINARY AND MULTI-STATE MEMORY,” and is hereby incorporated by reference into this application. Background Art

[0003] The present disclosure relates to techniques for non-volatile storage devices.

[0004] Semiconductor memory is widely used in various electronic devices, such as cellular phones, digital cameras, personal digital assistants, medical electronics, mobile computing devices, servers, solid-state drives, non-mobile computing devices and other devices. Semiconductor memory can include non-volatile memory or volatile memory. Non-volatile memory allows information to be stored and retained even when the non-volatile memory is not connected to a power source (e.g., a battery). Examples of non-volatile memory are flash memory (e.g., NAND-type and NOR-type flash memory). Users of non-volatile memory generally want the memory to operate at high speeds so that they do not need to wait for storage operations to complete, and also want the memory to consume less power. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Like numbered elements refer to common parts in different figures.

[0006] Figure 1A is a block diagram of one embodiment of a storage system connected to a host.

[0007] Figure 1B is a block diagram of one embodiment of a front end processor circuit.

[0008] Figure 2A is a block diagram of one embodiment of a back-end processor circuit.

[0009] Figure 2B is a block diagram of one embodiment of a memory package.

[0010] Figure 3A is a functional block diagram of an implementation of a memory die.

[0011] Figure 3B is a functional block diagram of an embodiment of an integrated memory component.

[0012] Figure 4 is a block diagram of an individual sensing block divided into a core part and a common part.

[0013] Figure 5A Depicted is a side view of an embodiment of an integrated memory component stacked on a substrate.

[0014] Figure 5B Depicted is a side view of an embodiment of an integrated memory component stacked on a substrate.

[0015] Fig. 6A is a perspective view of a portion of one example embodiment of a monolithic three dimensional memory array that may include a memory structure.

[0016] Figure 6B is a block diagram explaining one example organization of the memory structure.

[0017] Figure 6C is a block diagram depicting a top view of a portion of one block from a memory structure.

[0018] Fig.6D Depicted is a portion of an embodiment of a three-dimensional memory structure showing Figure 6C A cross-sectional view of line AA.

[0019] Fig. 6E Describes a portion of a vertical column Fig.6D A cross-sectional view of the area.

[0020] Fig. 6F is a schematic diagram of multiple NAND strings, showing multiple sub-blocks.

[0021] Fig. 7A Depicted are threshold voltage distributions for memory cells in a binary implementation.

[0022] Figure 7B Depicted are threshold voltage distributions for memory cells in a multi-level cell (MLC) implementation.

[0023] Figure 7C is a table describing one example of assigning data values ​​to data states.

[0024] Figure 8 is a flow chart describing one embodiment of a process for programming non-volatile memory.

[0025] Fig. 9 A series of programming voltage pulses is depicted.

[0026] Fig.10 Two program voltage pulses and one verify voltage pulse are depicted.

[0027] Fig.11Two programming voltage pulses and a set of verify voltage pulses are depicted.

[0028] Fig.12 is a flow chart describing one embodiment of a process for program verifying non-volatile memory.

[0029] Fig.13 is an implementation of a collective programming waveform for NAND memory.

[0030] Fig.14 Reducing the Icc peak on the unselected word lines by using a slower ramp rate for the Vpass voltage is illustrated.

[0031] Fig.15 Depicts the Vpass voltage levels that can be generated for Fig.13 The WL_unsel waveform uses an example implementation of a multi-stage charge pump for the word line driver.

[0032] FIG. 16A to FIG. 16C The plot shows the relationship between the Fig.13 Region 1314 of VWL_unsel is consistent with the example voltage signal.

[0033] Fig.17A and Fig. 17B Describes the methods that can be used to implement Fig.13 Different ramp rates of the charge pump (such as Fig.16A Two exemplary clock signals in ).

[0034] Fig.18 is an example of the variation of RC values ​​across a word line of a NAND memory array having a center union region.

[0035] Fig.19 is a flow chart of an embodiment of determining and using a nonvolatile memory device having a wordline dependent ramp rate of a pass voltage.

[0036] Fig. 20 An implementation of differential ramp rates and timing for biasing the MLC and SLC of unselected word lines during a programming operation is illustrated.

[0037] Fig.21 A flow chart of an embodiment of determining and using a nonvolatile memory device having independently configurable ramp rates and ramp rate timing values ​​through voltage for MLC and SLC operation.

[0038] Fig. 22 is a flow chart of an embodiment for incorporating the use of differential pass voltage ramp rates and ramp rate interval values ​​for MLC and SLC operations. DETAILED DESCRIPTION

[0039] In NAND memory architecture, in order to access a selected memory cell for programming or reading operations, a programming or sensing voltage is applied to the corresponding selected word line. In order to be able to accurately write or read the data of the selected memory cell, the other unselected memory cells of the NAND string need to be fully turned on by applying a programming pass voltage (Vpass) or a read pass voltage (Vread) to the corresponding unselected word line so as not to interfere with the write or read operation. Since the number of word lines in a NAND memory device can be very large, biasing all unselected word lines to Vread or specifically to Vpass at the same time can result in a very large spike in the current Icc drawn by the memory die.

[0040] To reduce these Icc spikes, different pass voltage ramp rates are used for different regions or zones of the word line below. The properties of the word line, such as its resistance and capacitance (RC) values, vary across the NAND memory array. By determining the RC values ​​of the word lines across the array, the word lines can be divided into multiple zones based on these properties. The zones can then be individually assigned different ramp rates for applying the pass voltage to the unselected word lines, where the parameters of the ramp rates can be stored as register values ​​on the memory die. In other techniques for reducing such Icc spikes while maintaining performance, differential Vpass ramp rates can be used for multi-level (MLC) and binary (SLC) operations. Differential Vpass ramp rate interval values ​​can also be used for MLC and SLC operations.

[0041] Figures 1A to 6F One example of a storage system that can be used to implement the techniques disclosed herein is described.

[0042] Figure 1A1 is a block diagram of one embodiment of a storage system 100 connected to a host system 120. The storage system 100 can implement the techniques disclosed herein. Many different types of storage systems can be used with the techniques disclosed herein. One exemplary storage system is a solid state drive (“SSD”); however, other types of storage systems can also be used. The storage system 100 includes a memory controller 102, a memory package 104 for storing data, and a local memory (e.g., MRAM / DRAM / ReRAM) 106. The memory controller 102 includes a front end processor circuit (FEP) 110 and one or more back end processor circuits (BEP) 112. In one embodiment, the FEP circuit 110 is implemented on an ASIC. In one embodiment, each BEP circuit 112 is implemented on a separate ASIC. The ASIC for each of the BEP circuit 112 and the FEP circuit 110 is implemented on the same semiconductor, so that the memory controller 102 is manufactured as a system on a chip (“SoC”). The FEP 110 and the BEP 112 each include their own processor. In one embodiment, the FEP 110 and the BEP 112 operate in a master-slave configuration, where the FEP 110 is a master device and each BEP 112 is a slave device. For example, the FEP circuit 110 implements a flash translation layer that performs memory management (e.g., garbage collection, wear leveling, etc.), logical to physical address translation, communication with the host, management of DRAM (local volatile memory), and management of the overall operation of the SSD (or other non-volatile storage system). The BEP circuit 112 manages memory operations in the memory package 104 according to the request of the FEP circuit 110. For example, the BEP circuit 112 can perform read, erase, and program processes. In addition, the BEP circuit 112 can perform buffer management, set specific voltage levels required by the FEP circuit 110, perform error correction (ECC), control the switching mode interface to the memory package, etc. In one embodiment, each BEP circuit 112 is responsible for its own set of memory packages. The memory controller 102 is an example of a control circuit.

[0043] In one embodiment, there are multiple memory packages 104. Each memory package 104 may include one or more memory dies. In one embodiment, each memory die in the memory package 104 utilizes NAND flash memory (including two-dimensional NAND flash memory and / or three-dimensional NAND flash memory). In other embodiments, the memory package 104 may include other types of memory; for example, the memory package may include phase change memory (PCM) memory.

[0044] In one embodiment, the memory controller 102 communicates with the host system 120 using an interface 130 that implements NVM Express (NVMe) over PCI Express (PCIe). To work with the storage system 100, the host system 120 includes a host processor 122, a host memory 124, and a PCIe interface 126 that communicate on a bus 128. The host memory 124 is the physical memory of the host and can be DRAM, SRAM, non-volatile memory, or another type of storage device. The host system 120 is external to and separate from the storage system 100. In one embodiment, the storage system 100 is embedded in the host system 120. In other embodiments, the controller 102 can communicate with the host 120 via various types of communication buses and / or links, including, for example, NVMe over Fabrics architecture, or cache / memory coherent architectures based on Cache Coherent Interconnect for Accelerators (CCIX), Compute for Fast Links (CXL), Open Coherent Accelerator Processor Interface (OpenCAPI), Gen-Z, etc. For simplicity, the following example embodiments will be described with respect to the PCIe example.

[0045] Figure 1B is a block diagram of one embodiment of the FEP circuit 110 . Figure 1BA PCIe interface 150 is shown that communicates with a host system 120, and a host processor 152 that communicates with the PCIe interface. The host processor 152 can be any type of processor known in the art that is suitable for implementation. The host processor 152 communicates with a network on chip (NOC) 154. NOC is a communication subsystem on an integrated circuit, usually between cores in a SoC. NOC can span synchronous and asynchronous clock domains, or use non-clocked asynchronous logic. NOC technology applies network theory and methods to on-chip communication, and brings significant improvements compared to conventional bus and crossbar switch interconnections. Compared with other designs, NOC improves the scalability of SoCs and the power efficiency of complex SoCs. The wires and links of NOC are shared by many signals. Since all links in NOC can run simultaneously on different data packets, a high degree of parallelism is achieved. Therefore, as the complexity of integrated subsystems continues to increase, NOC provides enhanced performance (such as throughput) and scalability compared to previous communication architectures (e.g., dedicated point-to-point signal lines, shared buses, or segmented buses with bridges). Connected to and in communication with the NOC 154 are a memory processor 156, SRAM 160, and a DRAM controller 162. The DRAM controller 162 is used to operate and communicate with the local memory 106 (e.g., DRAM / MRAM / ReRAM). The SRAM 160 is a local RAM memory used by the memory processor 156. The memory processor 156 is used to run the FEP circuits and perform various memory operations. Also in communication with the NOC are two PCIe interfaces 164 and 166. Figure 1B In the embodiment of the present invention, the memory controller 102 includes two BEP circuits 112; therefore, there are two PCIe interfaces 164 / 166. Each PCIe interface communicates with one of the BEP circuits 112. In other embodiments, there may be more or less than two BEP circuits 112; therefore, there may be more than two PCIe interfaces.

[0046] Figure 2A is a block diagram of one embodiment of the BEP circuit 112 . Figure 2A A method for communicating with the FEP circuit 110 (e.g., Figure 1BThe PCIe interface 200 communicates with two NOCs 202 and 204. In one embodiment, the two NOCs can be combined into one large NOC. Each NOC (202 / 204) is connected to SRAM (230 / 260), buffer (232 / 262), processor (220 / 250) and data path controller (222 / 252) through an XOR engine (224 / 254), an ECC engine (226 / 256).

[0047] The ECC engine 226 / 256 is used to perform error correction, as known in the art. In this article, the ECC engine 226 / 256 may be referred to as a controller ECC engine. The XOR engine 224 / 254 is used to perform an XOR on the data so that the data can be combined and stored in a recoverable manner in the presence of programming errors. In one embodiment, the XOR engine 224 / 254 can recover data that cannot be decoded using the ECC engine 226 / 256.

[0048] The data path controller 222 is connected to the memory interface 228 for communicating with the integrated memory component via four channels. Therefore, the top NOC 202 is associated with the memory interface 228 of the four channels for communicating with the integrated memory component, and the bottom NOC 204 is associated with the memory interface 258 of the four additional channels for communicating with the integrated memory component. In one embodiment, each memory interface 228 / 258 includes four switching mode interfaces (TM interfaces), four buffers and four schedulers. There is a scheduler, buffer and TM interface for each of the channels. The processor can be any standard processor known in the art. The data path controller 222 / 252 can be a processor, FPGA, microprocessor or other type of controller. The XOR engine 224 / 254 and the ECC engine 226 / 256 are dedicated hardware circuits, referred to as hardware accelerators. In other embodiments, the XOR engine 224 / 254 and the ECC engine 226 / 256 can be implemented in software. The scheduler, buffer and TM interface are hardware circuits. In other embodiments, the memory interface (circuitry used to communicate with the memory die) can be Figure 2A In addition, there is a different structure than that depicted. Figure 1B and Figure 2A Controllers of different configurations may also be used with the techniques described herein.

[0049] Figure 2B1 is a block diagram of one embodiment of a memory package 104 including multiple memory dies 300 connected to a memory bus (data lines and chip enable lines) 318. The memory bus 318 is connected to the switch mode interface 228 for communicating with the TM interface of the BEP circuit 112 (see, e.g. Figure 2A ). In some embodiments, the memory package may include a small controller connected to the memory bus and the TM interface. In summary, the memory package 104 may have eight or sixteen memory dies; however, other numbers of memory dies may also be implemented. The techniques described herein are not limited to any particular number of memory dies. In some embodiments, the memory package may also include a processor, a CPU device, such as a RISC-V CPU, and an amount of RAM to help implement some of the capabilities described below. The techniques described herein are not limited to any particular number of memory dies.

[0050] Figure 3A is a block diagram depicting one example of a memory die 300 that may implement the techniques described herein. Figure 2B The memory die 300 of one of the memory dies 300 includes a memory array 302, which may include any memory cell described below. The array terminal lines of the memory array 302 include individual word line layers organized into rows, and individual bit line layers organized into columns. However, other orientations may also be implemented. The memory die 300 includes a row control circuit 320, the output 308 of which is connected to the corresponding word line of the memory array 302. The row control circuit 320 receives a set of M row address signals and one or more various control signals from the system control logic circuit 360, and may generally include circuits such as a row decoder 322, an array terminal driver 324, and a block selection circuit 326 for both read operations and write operations. The row control circuit 320 may also include a read / write circuit. The memory die 300 also includes a column control circuit 310, which includes a sense amplifier 330, the input / output 306 of which is connected to the corresponding bit line of the memory array 302. Although only a single block is shown for array 302, a memory die may include multiple arrays that may be accessed separately. Column control circuitry 310 receives a set of N column address signals and one or more various control signals from system control logic 360, and may generally include circuits such as column decoders 312, array terminal receivers or drivers 314, block select circuitry 316, and read / write circuits and I / O multiplexers.

[0051] System control logic 360 receives data and commands from the host and provides output data and status to the host. In other embodiments, system control logic 360 receives data and commands from a separate controller circuit and provides output data to the controller circuit, wherein the controller circuit communicates with the host. In some embodiments, system control logic 360 may include a state machine 362 that provides die-level control of memory operations. In one embodiment, state machine 362 can be programmed by software. In other embodiments, state machine 362 does not use software and is fully implemented in hardware (e.g., electronic circuits). In another embodiment, state machine 362 is replaced by a microcontroller or microprocessor that is on or outside the memory chip. System control logic 360 may also include a power control module 364 that controls the power and voltage supplied to the rows and columns of memory 302 during memory operation, and may include a charge pump and a regulator circuit for generating a regulated voltage. System control logic 360 includes a storage device 366 that can be used to store parameters for operating memory array 302.

[0052] Commands and data are passed between the controller 102 and the memory die 300 via a memory controller interface 368 (also referred to as a "communication interface"). The memory controller interface 368 is an electrical interface for communicating with the memory controller 102. Examples of the memory controller interface 368 include a switch mode interface and an open NAND flash interface (ONFI). Other I / O interfaces may also be used. For example, the memory controller interface 368 may implement a switch mode interface that is connected to the switch mode interface of the memory interface 228 / 258 of the memory controller 102. In one embodiment, the memory controller interface 368 includes a set of input and / or output (I / O) pins connected to the controller 102.

[0053] In some embodiments, all elements of memory die 300, including system control logic 360, may be formed as part of a single die. In other embodiments, some or all of system control logic 360 may be formed on different dies.

[0054] For purposes of this document, the phrase "one or more control circuits" may include a controller, state machine, microcontroller, microprocessor, and / or other control circuitry represented by system control logic 360, or other similar circuitry for controlling non-volatile memory.

[0055] In one embodiment, the memory structure 302 includes a three-dimensional memory array of non-volatile memory cells, where multiple memory levels are formed over a single substrate (such as a wafer). The memory structure may include any type of non-volatile memory integrally formed in one or more physical levels of memory cells having active regions disposed over a silicon (or other type) substrate. In one example, the non-volatile memory cells include vertical NAND strings with charge trapping.

[0056] In another embodiment, the memory structure 302 includes a two-dimensional memory array of non-volatile memory cells. In one example, the non-volatile memory cells are NAND flash memory cells that utilize floating gates. Other types of memory cells (e.g., NOR-type flash memory) may also be used.

[0057] The exact type of memory array architecture or memory cell included in the memory structure 302 is not limited to the above examples. Many different types of memory array architectures or memory technologies can be used to form the memory structure 302. No specific non-volatile memory technology is required to implement the claimed new embodiments presented herein. Other examples of suitable technologies for the memory cells of the memory structure 302 include ReRAM memory (resistive random access memory), magnetoresistive memory (e.g., MRAM, spin transfer torque MRAM, spin orbit torque MRAM), FeRAM, phase change memory (e.g., PCM), etc. Examples of suitable technologies for the memory cell architecture of the memory structure 302 include two-dimensional arrays, three-dimensional arrays, cross-point arrays, stacked two-dimensional arrays, vertical bit line arrays, etc.

[0058] An example of a ReRAM crosspoint memory includes a reversible resistance switching element arranged in a crosspoint array accessed by an X line and a Y line (e.g., a word line and a bit line). In another embodiment, the memory cell may include a conductive bridge memory element. The conductive bridge memory element may also be referred to as a programmable metallization unit. Based on the physical relocation of ions within a solid electrolyte, the conductive bridge memory element may be used as a state change element. In some cases, the conductive bridge memory element may include two solid metal electrodes, one relatively inert (e.g., tungsten) and the other electrochemically active (e.g., silver or copper), with a thin film of a solid electrolyte between the two electrodes. As the temperature increases, the mobility of the ions also increases, which causes the programming threshold of the conductive bridge memory cell to decrease. Therefore, the conductive bridge memory element may have a wide range of programming thresholds over the entire temperature range.

[0059] Another example is a magnetoresistive random access memory (MRAM) that stores data via magnetic storage elements. These elements are formed by two ferromagnetic layers separated by a thin insulating layer, each of which can maintain magnetization. One of the two layers is a permanent magnet set to a specific polarity; the magnetization of the other layer can be changed to match the magnetization of the storage memory by the external magnetic field. The memory device is built from a grid of such memory cells. In one embodiment for programming, each memory cell is located between a pair of write lines that are arranged at right angles to each other, parallel to the cells, one above the cell and one below the cell. When current passes through them, an induced magnetic field is generated.

[0060] Phase change memory (PCM) takes advantage of the unique properties of chalcogenide glass. One embodiment uses a GeTe-Sb2Te3 superlattice to achieve non-thermal phase change by changing the coordination state of germanium atoms using only laser pulses (or light pulses from another source). Therefore, the programming dose is a laser pulse. The memory cell can be disabled by preventing the memory cell from receiving light. In other PCM embodiments, the memory cell is programmed by a current pulse. It should be noted that the use of "pulse" in this document does not require a rectangular pulse, but includes (continuous or discontinuous) vibrations or pulse trains of sound, current, voltage light or other waves. These memory elements within each selectable memory cell or bit can include additional series elements as selectors, such as a bidirectional threshold switch or a metal insulator substrate.

[0061] Those of ordinary skill in the art will recognize that the technology described herein is not limited to a single particular memory structure, memory configuration, or material composition, but encompasses many related memory structures within the spirit and scope of the technology as described herein and as understood by those of ordinary skill in the art.

[0062] Can Figure 3A The components of the memory system 100 are grouped into two parts: the memory structure 302 of the memory cells; and the peripheral circuitry, including all other components. An important characteristic of the memory circuit is its capacity, which can be increased by increasing the area of ​​the memory die of the memory system 100 reserved for the memory structure 302; however, this reduces the area of ​​the memory die available for the peripheral circuitry. This can impose quite severe limitations on these peripheral components. For example, the need to fit the sense amplifier circuitry within the available area can be a significant limitation on the sense amplifier design architecture. The reduction in available area relative to the system control logic 360 may limit the available functions that can be implemented on the chip. Therefore, in the design of the memory die of the memory system 100, a basic trade-off needs to be made between the amount of dedicated area for the memory structure 302 and the amount of dedicated area for the peripheral circuitry.

[0063] Another area where the memory structure 302 and the peripheral circuits often conflict is in the processing involved in forming these areas, as these areas often involve different processing technologies and trade-offs when implementing different technologies on a single die. For example, when the memory structure 302 is a NAND flash memory, this is an NMOS structure, while the peripheral circuits are often CMOS based. For example, elements such as sense amplifier circuits, charge pumps, logic elements in state machines, and other peripheral circuits in the system control logic 360 often employ PMOS devices. The processing operations used to manufacture CMOS dies will differ in many ways from those optimized for NMOS flash NAND memory or other memory cell technologies.

[0064] To improve these limitations, the embodiments described below can Figure 3A The components of the memory structure 302 can be separated into separately formed dies, and then these dies are bonded together. More specifically, the memory structure 302 can be formed on one die, and some or all of the peripheral circuit elements (including one or more control circuits) can be formed on a separate die. For example, the memory die can be formed only by memory elements, such as a memory cell array of a flash NAND memory, an MRAM memory, a PCM memory, a ReRAM memory, or other memory types. Then some or all of the circuit systems in the peripheral circuit system (even including elements such as decoders and sense amplifiers) can be moved to a separate die. This allows each die in the memory die to be optimized separately according to its technology. For example, a NAND memory die can be optimized for an NMOS-based memory array structure without worrying about CMOS elements that have now been moved to an independent peripheral circuit system die that can be optimized for CMOS processing. This provides more room for peripheral elements, and if the peripheral elements are restricted to the edge of the same die that houses the memory cell array, additional capabilities that may not be easily bonded can now be combined. The two dies can then be bonded together in a bonded multi-die memory circuit, where the array on one die is connected to the peripheral elements on the other memory circuit. For example, although the following description will focus on bonded memory circuits of one memory die and one peripheral circuit die, other implementations may use more dies, such as two memory dies and one peripheral circuit die.

[0065] Figure 3B Shows Figure 3A An alternative arrangement to the arrangement of may be achieved using wafer-to-wafer bonding to provide bonded die pairs. Figure 3BA functional block diagram of one embodiment of an integrated memory component 307 is depicted. The integrated memory component 307 can be used in a memory package 104 in a memory system 100. The integrated memory component 307 includes two types of semiconductor dies (or more succinctly, "dies"). The memory structure die 301 includes a memory structure 302. The memory structure 302 can include non-volatile memory cells. The control die 311 includes control circuits 360, 310, 320. In some embodiments, the control die 311 is configured to connect to the memory structure 302 in the memory structure die 301. In some embodiments, the memory structure die 301 and the control die 311 are bonded together.

[0066] Figure 3B An example of peripheral circuits is shown, including control circuits formed in a peripheral circuit or control die 311 coupled to a memory structure 302 formed in a memory structure die 301. Common components are shown in a similar manner to Figure 3A As can be seen, system control logic 360, row control circuitry 320, and column control circuitry 310 are located in control die 311. In some embodiments, all or a portion of column control circuitry 310 and all or a portion of row control circuitry 320 are located on memory structure die 301. In some embodiments, a portion of the circuitry in system control logic 360 is located on memory structure die 301.

[0067] The system control logic 360, the row control circuit 320, and the column control circuit 310 may be formed by conventional processes (e.g., CMOS processes), so that adding elements and functions more commonly found on the memory controller 102, such as ECC, may require few or no additional process steps (i.e., the same process steps used to manufacture the controller 102 may also be used to manufacture the system control logic 360, the row control circuit 320, and the column control circuit 310). Therefore, while moving such circuits in a die (such as the memory structure die 301) may reduce the number of steps required to manufacture such a die, adding such circuits to a die (such as the control die 311) may not require any additional process steps. Since some or all of the control circuits 360, 310, 320 are implemented using CMOS technology, the control die 311 may also be referred to as a CMOS die.

[0068] Figure 3BColumn control circuitry 310 including sense amplifiers 350 on control die 311 is shown coupled to memory structures 302 on memory structure die 301 via electrical paths 306. For example, electrical paths 306 may provide electrical connections between column decoders 312, driver circuits 314, block selectors 316, and bit lines of memory structures 302. Electrical paths may extend from column control circuitry 310 in control die 311 through pads on control die 311 that are bonded to corresponding pads of memory structure die 301 that are connected to bit lines of memory structures 302. Each bit line of memory structures 302 may have a corresponding electrical path in electrical paths 306 connected to column control circuitry 310, including a pair of bond pads. Similarly, row control circuitry 320 (including row decoders 322, array drivers 324, and block selectors 326) is coupled to memory structures 302 via electrical paths 308. Each of the electrical paths 308 may correspond to a word line, a dummy word line, or a select gate line. Additional electrical paths may also be provided between the control die 311 and the memory structure die 301 .

[0069] For the purposes of this document, the phrase "one or more control circuits" may include one or more of the controller 102, system control logic 360, column control circuit 310, row control circuit 320, microcontroller, state machine, and / or other control circuits, or other similar circuits for controlling non-volatile memory. The one or more control circuits may include only hardware or a combination of hardware and software (including firmware). For example, a controller programmed by firmware to perform the functions described herein is an example of a control circuit. The control circuit may include a processor, FGA, ASIC, integrated circuit, or other type of circuit.

[0070] Figure 4 4 is a block diagram of a separate sense block of sense amplifiers 350 divided into a core portion (referred to as sense modules 480) and a common portion 480. In one embodiment, there will be a separate sense module 450 for each bit line and one common portion 480 for a group of multiple sense modules 450. In one example, a sense block will include one common portion 480 and eight, twelve, or sixteen sense modules 450. Each sense module in the group will communicate with the associated common portion via a data bus 454.

[0071] The sensing module 450 includes a sensing circuit 460 that determines whether the conduction current in the connected bit line is above or below a predetermined level, or in voltage-based sensing, determines whether the voltage level in the connected bit line is above or below a predetermined level. The sensing circuit 460 will receive a control signal from the state machine via an input line 471. In some embodiments, the sensing module 450 includes a circuit commonly referred to as a sense amplifier. The sensing module 450 also includes a bit line latch 468, which is used to set the voltage condition on the connected bit line. For example, a predetermined state latched in the bit line latch 468 will cause the connected bit line to be pulled to a state (e.g., Vdd) that specifies program inhibition.

[0072] The common portion 480 includes a processor 468, a set of data latches 484, and an I / O interface 488 coupled between the set of data latches 484 and the data bus 318. The processor 468 performs calculations. For example, one of its functions is to determine the data stored in the sensed memory cell and store the determined data in the set of data latches. The set of data latches 484 is used to store the data bits determined by the processor 468 during the read operation. The set of data latches can also be used to store the data bits imported from the data bus 318 during the programming operation. The imported data bits represent the write data intended to be programmed into the memory. The I / O interface 488 provides an interface between the data latches 484 and the data bus 318.

[0073] During reading or sensing, the operation of the system is under the control of the state machine 362, which controls the supply of different control gate or other bias voltages to the addressed memory cells (using power control 364). As it steps through the various predefined control gate voltages corresponding to the various memory states supported by the memory, the sense module 450 may trip at one of these voltages, and the output will be provided from the sense module 450 to the processor 482 via bus 454. At this point, the processor 482 determines the resulting memory state by considering the trip event of the sense module and the information about the control gate voltage applied from the state machine via input line 490. It then calculates the binary encoding of the memory state and stores the resulting data bits into the data latch 484. In another embodiment of the core portion, the bit line latch 468 plays a dual role, acting as both a latch for latching the output of the sense module 450 and a bit line latch as described above.

[0074] Data latch stack 484 includes a stack of data latches corresponding to the sense module. In one embodiment, each sense module 450 has three, four or another number of data latches. In one embodiment, the latch is a respective one. In this document, the latch in an embodiment of data latch stack 484 will be referred to as SDL, XDL, ADL, BDL and CDL. In the embodiment discussed here, latch XDL is a transmission latch for exchanging data with I / O interface 488. In addition to the first sense amplifier data latch SDL, additional latches ADL, BDL and CDL can be used to maintain multi-state data, wherein the number of such latches typically reflects the number of bits stored in the memory cell. For example, in a multi-level cell (MLC) memory format of 3 bits per cell, three groups of latches ADL, BDL, CDL can be used for upper page data, middle page data, lower page data. In an embodiment of 2 bits per cell, only ADL and BDL can be used, and an MLC embodiment of 4 bits per cell can include another group of DDL latches. In other embodiments, XDL latches may be used to hold additional data pages, such as a 4-bit per cell MLC embodiment that uses XDL latches in addition to the three sets of latches ADL, BDL, CDL for four data pages. The following discussion will focus primarily on the 3-bit per cell embodiment, as this illustrates the main features without becoming overly complex, but the discussion may also apply to embodiments with formats having more or fewer bits per cell. Some embodiments may also include additional latches for specific functions, such as represented by TDL latches, where, for example, this may be used for a "fast write" operation, where it is used for programming operations when a memory cell is approaching its target state and is partially inhibited to slow down its programming rate.

[0075] For example, in some embodiments, the data read from the memory cell or the data to be programmed into the memory cell will first be stored in the XDL. In the case where the data will be programmed into the memory cell, the system can program the data from the XDL into the memory cell. In one embodiment, before the next operation is performed, the data is completely programmed from the XDL into the memory cell. In other embodiments, when the system begins to program the memory cell through the XDL, the system also transfers the data stored in the XDL to the ADL in order to reset the XDL. Before the data is transferred from the XDL to the ADL, the data retained in the ADL is transferred to the BDL, thereby clearing any data (if any) retained in the BDL, and the same is true for the BDL and CDL. Once the data has been transferred from the XDL to the ADL, the system continues (if necessary) to program the memory cell through the ADL, while loading the data to be programmed into the memory cell on the next word line into the reset XDL. By performing data loading and programming operations simultaneously, the system can save time and therefore perform a sequence of such operations faster.

[0076] During programming or verification, the data to be programmed is stored in the set of data latches 484 from the data bus 318. During the verification process, the processor 482 monitors the verified memory state relative to the desired memory state. When the two are consistent, the processor 482 sets the bit line latch 468 to cause the bit line to be pulled to a state that specifies programming inhibition. This inhibits the memory cell from further programming even if the memory cell coupled to the bit line is subjected to a programming pulse on its control gate. In other embodiments, the processor initially loads the bit line latch 468, and the sensing circuit sets it to an inhibit value during the verification process.

[0077] In some implementations (but not necessarily), the data latches are implemented as shift registers so that parallel data stored therein is converted to serial data for the data bus 318, and vice versa. In one embodiment, all data latches corresponding to a read / write block of m memory cells may be connected together to form a block shift register so that a block of data may be input or output via serial transmission. Specifically, the read / write module group is adjusted so that each of its data latch groups shifts data into or out of the data bus in sequence, just as if they were part of a shift register for the entire read / write block.

[0078] In some embodiments, there is more than one control die 311 and more than one memory structure die 301 in the integrated memory component 307. In some embodiments, the integrated memory component 307 includes a stack of multiple control dies 311 and multiple memory structure dies 301. Figure 5AA side view of an embodiment of an integrated memory component 307 (e.g., including a stack of control dies 311 and memory structure dies 301) stacked on a substrate 502 is depicted. The integrated memory component 307 has three control dies 311 and three memory structure dies 301. In some embodiments, there are more than three memory structure dies 301 and more than three control dies 311.

[0079] Each control die 311 is attached (e.g., bonded) to at least one of the memory structure dies 301. Some of the bonding pads 570, 574 are depicted. There may be more bonding pads. The space between the two dies 301, 311 bonded together is filled with a solid layer 548, which can be formed of epoxy or other resins or polymers. The solid layer 548 protects the electrical connection between the dies 301, 311 and further fixes the dies together. Various materials can be used as the solid layer 548, but in an embodiment, the material can be a Hysol epoxy resin from Henkel Corporation (the company has offices in California, USA).

[0080] The integrated memory components 307 may be stacked, for example, in a stepped offset manner so that the bonding pads at each level are uncovered and accessible from above. Wire bonds 506 connected to the bonding pads connect the control die 311 to the substrate 502. Multiple such wire bonds may be formed across the entire width of each control die 311 (i.e., formed to Figure 5A ).

[0081] Memory structure die through silicon vias (TSVs) 512 may be used to route signals through the memory structure die 301. Control die through silicon vias (TSVs) 514 may be used to route signals through the control die 311. TSVs 512, 514 may be formed before, during, or after the formation of integrated circuits in the semiconductor die 301, 311. TSVs 512, 514 may be formed by etching holes through the wafer. These holes may then be lined with a barrier to prevent metal diffusion. The barrier layer may in turn be lined with a seed layer, and the seed layer may be plated with an electrical conductor, such as copper, although other suitable materials may be used, such as aluminum, tin, nickel, gold, doped polysilicon, and alloys or combinations thereof.

[0082] Solder balls 508 may optionally be attached to contact pads 510 on the lower surface of substrate 502. Solder balls 508 may be used to electrically and mechanically couple integrated memory component 307 to a host device, such as a printed circuit board. Solder balls 508 may be omitted in the event that integrated memory component 307 is to be used as an LGA package. Solder balls 508 may form part of the interface between integrated memory component 307 and memory controller 102.

[0083] Figure 5B A side view of an embodiment of an integrated memory component 307 stacked on a substrate 502 is depicted. The integrated memory component 307 has three control dies 311 and three memory structure dies 301. In some embodiments, there are far more than three memory structure dies 301 and far more than three control dies 311. In this example, each control die 311 is bonded to at least one memory structure die 301. Optionally, a control die 311 can be bonded to two memory structure dies 301.

[0084] Some of the bonding pads 570, 574 are depicted. There may be more bonding pads. The space between the two dies 301, 311 bonded together is filled with a solid layer 548, which may be formed of epoxy or other resins or polymers. Figure 5A Compared to the example in Figure 5B The integrated memory component 307 in FIG. 3 has no step offset. The memory structure die through silicon vias (TSVs) 512 may be used to route signals through the memory structure die 301. The control die through silicon vias (TSVs) 514 may be used to route signals through the control die 311.

[0085] As briefly discussed above, the control die 311 and the memory structure die 301 can be bonded together. The bonding pads on each die 301, 311 can be used to bond the two dies together. In some embodiments, in the so-called Cu-Cu bonding process, the bonding pads are directly bonded to each other without solder or other additional materials. In the Cu-Cu bonding process, the bonding pads are controlled to be highly flat and formed in a highly controlled environment, which is substantially free of environmental particles, otherwise the environmental particles may be deposited on the bonding pads and prevent close bonding. Under such properly controlled conditions, the bonding pads are aligned and pressed against each other to form mutual bonding based on surface tension. This bonding can be formed at room temperature, although heat can also be applied. In the embodiment using Cu-Cu bonding, the bonding pads can be about 5 μm square and spaced apart from each other at a spacing of 5 μm to 5 μm. Although the process is referred to as Cu-Cu bonding in this article, the term can also be applied to the case where the bonding pads are formed by materials other than copper.

[0086] When the area of ​​the bonding pad is small, it may be difficult to bond the semiconductor die together. By providing a film layer on the surface of the semiconductor die including the bonding pad, the size and spacing of the bonding pad can be further reduced. The film layer is arranged around the bonding pad. When the dies are put together, the bonding pads can be bonded to each other, and the film layers on each die can be bonded to each other. This bonding technology can be called hybrid bonding. In an embodiment using hybrid bonding, the bonding pads can be about 5 μm square and spaced apart from each other at a spacing of 1 μm to 5 μm. Bonding technology can be used to provide bonding pads with smaller size and spacing.

[0087] Some embodiments may include a film on the surface of the die 301, 311. If such a film is not initially provided, the space between the die can be filled at the bottom with epoxy or other resin or polymer. The bottom fill material can be applied as a liquid and then hardened into a solid layer. This bottom filling step protects the electrical connection between the die 301, 311 and further secures the die together. Various materials can be used as the bottom fill material, but in an embodiment, the bottom fill material can be a Hysol epoxy resin from Henkel Corporation, which has offices in California, USA.

[0088] Fig. 6A is a perspective view of a portion of an example embodiment of a monolithic three-dimensional memory array including a memory structure 302 that includes a plurality of non-volatile memory cells. For example, Fig. 6A A portion of a block including a memory is shown. The depicted structure includes a set of bit lines BL located above a stack of alternating dielectric layers and conductive layers, wherein vertical column materials extend through the dielectric layers and the conductive layers. For example, one of the dielectric layers is marked as D, and one of the conductive layers (also referred to as word line layers) is marked as W. The word line layer includes one or more word lines connected to the memory cell. For example, the word line can be connected to the control gate of the memory cell. The number of alternating dielectric layers and conductive layers can vary based on specific implementation requirements. One set of embodiments includes between 108 and 304 alternating dielectric layers and conductive layers. An example embodiment includes 96 data word line layers, 8 selection layers, 6 dummy word line layers, and 110 dielectric layers. More or less than 108 to 304 layers may also be used. In one embodiment, the alternating dielectric layers and conductive layers are divided into four "fingers" or sub-blocks by local interconnects LI. Fig. 6A Two fingers and two local interconnects LI are shown. A source line layer SL is located below the alternating dielectric and word line layers. Vertical columns of material (also called memory holes) are formed in the stack of alternating dielectric and conductive layers. For example, one of the vertical columns / memory holes is labeled MH. Note that in Fig. 6AIn the , the dielectric layers are depicted as see-through so that the reader can see the memory holes located in the stack of alternating dielectric and conductive layers. In one embodiment, a NAND string is formed by filling the vertical columns / memory holes with a material including a charge trapping material to create a vertical column of memory cells. Each memory cell can store one or more data bits.

[0089] Figure 6B 604. It is a block diagram illustrating an example organization of a memory structure 302, which is divided into two planes 602 and 604. Then, each plane is divided into M blocks. In one example, each plane has about 2000 blocks. However, different numbers of blocks and planes can also be used. In one embodiment, for two plane memories, the block ID is usually such that even blocks belong to one plane and odd blocks belong to another plane; therefore, plane 602 includes blocks 0, 2, 4, 6..., and plane 604 includes blocks 1, 3, 5, 7... In one embodiment, a block of memory cells is an erase unit. That is, all memory cells of a block are erased together. In other embodiments, memory cells may be grouped into blocks for other reasons, such as to organize the memory structure 302 to enable signaling and selection circuits.

[0090] FIG. 6C to FIG. 6E An example 3D NAND structure is depicted. Figure 6C is a block diagram depicting a top view of a portion of one block from the memory structure 302 . Figure 6C The portion of the box depicted in corresponds to Figure 6B of block 2 in section 606. From Figure 6C It can be seen that Figure 6C The blocks depicted in FIG. extend in the direction 633. In one embodiment, the memory array will have 60 layers. Other embodiments have fewer or more than 60 layers. However, Figure 6C Only the top layer is shown.

[0091] Figure 6C A plurality of circles representing vertical columns are depicted. Each of the vertical columns includes a plurality of select transistors and a plurality of memory cells. In one embodiment, each vertical column implements a NAND string. For example, Figure 6C Vertical columns 622, 632, 642, and 652 are depicted. Vertical column 622 implements NAND string 682. Vertical column 632 implements NAND string 684. Vertical column 642 implements NAND string 686. Vertical column 652 implements NAND string 688. More details of these vertical columns are provided below. Figure 6C The block depicted in FIG. 6 extends in the direction of arrow 633 and in the direction of arrow 633, so the block includes more Figure 6C More vertical columns depicted in

[0092] Figure 6C Also depicted is a set of bit lines 615 , including bit lines 611 , 612 , 613 , 614 , . . . , 619 . Figure 6C Twenty-four bit lines are shown because only a portion of the block is depicted. It is contemplated that more than twenty-four bit lines are connected to the vertical columns of the block. Each circle representing a vertical column has an "x" to indicate that it is connected to a bit line. For example, bit line 614 is connected to vertical columns 622, 632, 642, and 652.

[0093] Figure 6C The block depicted in includes a set of local interconnects 662, 664, 666, 668, and 669 that connect the various layers to the source lines below the vertical columns. Local interconnects 662, 664, 666, 668, and 669 are also used to divide each layer of the block into four regions; for example, Figure 6C The top layer depicted in is divided into regions 620, 630, 640 and 650, which are called fingers or sub-blocks. In the layer of the block implementing the memory cell, these four regions are called word line sub-blocks, which are separated by local interconnects. In one embodiment, the word line sub-blocks located on the common level of the block are connected together at the end of the block to form a single word line. In another embodiment, the word line sub-blocks located on the same level are not connected together. In an example implementation, the bit line is connected to only one vertical column in each of regions 620, 630, 640 and 650. In this implementation, each block has sixteen rows of active columns, and each bit line is connected to four rows in each block. In one embodiment, all four rows connected to the common bit line are connected to the same word line (via different word line sub-blocks connected together on the same level). Therefore, the system uses source side selection lines and drain side selection lines to select one (or another subset) of the four to be performed memory operations (programming, verification, reading and / or erasing).

[0094] although Figure 6C Shown in blocks with four vertical columns per region, four regions and sixteen vertical columns, but these exact numbers are exemplary implementations. Other implementations may include more or fewer regions per block, more or fewer vertical columns per region, and more or fewer vertical columns per block.

[0095] Figure 6C It is also shown that the vertical columns are staggered. In other embodiments, different staggered patterns can be used. In some embodiments, the vertical columns are not staggered.

[0096] Fig.6D A portion of an embodiment of a three-dimensional memory structure 302 is depicted, showing Figure 6C The cross-sectional view cuts through vertical columns 632 and 634 and region 630 (see Figure 6C ). Fig.6D The structure includes: four drain side selection layers SGD0, SGD1, SGD2 and SGD3; four source side selection layers SGS0, SGS1, SGS2 and SGS3; four dummy word line layers DD0, DD1, DS0 and DS1; and forty-eight data word line layers WLL0-WLL47 for connecting to data memory cells. Other embodiments may implement more or less than four drain side selection layers, more or less than four source side selection layers, more or less than four dummy word line layers, and more or less than forty-eight word line layers (e.g., 96 word line layers). Vertical columns 632 and 634 are depicted as protruding through the drain side selection layers, source side selection layers, dummy word line layers and word line layers. In one embodiment, each vertical column includes a NAND string. For example, vertical column 632 includes NAND string 684. Below the vertical columns and the layers listed below are substrate 601, an insulating film 654 on the substrate, and source lines SL. The NAND strings of vertical column 632 have source terminals at the bottom of the stack and drain terminals at the top of the stack. Figure 6C Consistent, Fig.6D A vertical column 632 is shown connected to a bit line 614 via a connector 617. Local interconnects 664 and 666 are also depicted.

[0097] For ease of reference, the following items are collectively referred to as conductive layers: drain side selection layers SGD0, SGD1, SGD2, and SGD3; source side selection layers SGS0, SGS1, SGS2, and SGS3; dummy word line layers DD0, DD1, DS0, and DS1; and word line layers WLL0-WLL47. In one embodiment, the conductive layers are made of a combination of TiN and tungsten. In other embodiments, other materials may be used to form the conductive layers, such as doped polysilicon, metals (such as tungsten), or metal silicides. In some embodiments, different conductive layers may be formed of different materials. Between the conductive layers are dielectric layers DL0-DL59. For example, dielectric layer DL49 is above word line layer WLL43 and below word line layer WLL44. In one embodiment, the dielectric layers are made of SiO 2 In other embodiments, other dielectric materials may be used to form the dielectric layer.

[0098] The non-volatile memory cells are formed along vertical columns that extend through alternating conductive layers and dielectric layers in the stack. In one embodiment, the memory cells are arranged in NAND strings. Word line layers WLL0 to WLL47 are connected to memory cells (also referred to as data memory cells). Dummy word line layers DD0, DD1, DS0, and DS1 are connected to dummy memory cells. Dummy memory cells do not store user data, while data memory cells are eligible to store user data. Drain side selection layers SGD0, SGD1, SGD2, and SGD3 are used to electrically connect and disconnect the NAND string to the bit line. Source side selection layers SGS0, SGS1, SGS2, and SGS3 are used to electrically connect and disconnect the NAND string to the source line SL.

[0099] In some embodiments, the word lines are read sequentially, which means reading the word lines from low to high (e.g., WLL0 to WLL47) or from high to low (e.g., WLL47 to WLL0). When reading sequentially, the entire group of word lines need not be read. Disclosed herein are techniques for providing compensation for disturbances caused by neighboring memory cells on a target memory cell during a sequential read.

[0100] In some embodiments, the reading of a single word line is broken down into separate readings of sub-blocks. Figure 6C , the block is divided into four sub-blocks 620, 630, 640, 650. Therefore, before reading the four sub-blocks on the adjacent word line layer, the four sub-blocks on one word line layer can be read. In some embodiments, the data state information is used to provide compensation on a sub-block basis. For example, for each of the four sub-blocks 620 to 650, the data state information of the memory cells at WLL35 is retained. Then, when reading the sub-block 620 of WLL36, the data state information of the sub-block 620 at WLL35 is used to compensate for the interference from the adjacent memory cells in the sub-block 620 at WLL35, and when reading the sub-block 630 of WLL36, the data state information of the sub-block 630 at WLL35 is used to compensate for the interference from the adjacent memory cells in the sub-block 620 at WLL35, and so on.

[0101] For a three-dimensional NAND memory array with a large number of word lines, one or more union regions may be included. The use of a union portion may simplify the manufacturing process and, in some embodiments, allow sub-block level operations by accessing word lines only above or below the union portion. The union region will typically have a thicker dielectric region DLJ than between other word lines. As with the source and drain terminals, one or more dummy lines may be included above the union portion (DU) and below the union portion (DL).

[0102] Fig. 6E A portion of a vertical column 632 is depicted. Fig.6D629. In one embodiment, the vertical columns are circular and include four layers; however, in other embodiments, more or less than four layers may be included, and other shapes may be used. In one embodiment, the vertical columns 632 include a material such as SiO 2 An inner core layer 670 made of a dielectric of. Other materials may also be used. Surrounding the inner core 670 is a polysilicon channel 671. Materials other than polysilicon may also be used. Note that the channel 671 is connected to the bit line. Surrounding the channel 671 is a tunneling dielectric 672. In one embodiment, the tunneling dielectric 672 has an ONO structure. Surrounding the tunneling dielectric 672 is a charge trapping layer 673, such as (for example) silicon nitride. Other memory materials and structures may also be used. The technology described herein is not limited to any particular material or structure.

[0103] Fig. 6E Dielectric layers DLL49, DLL50, DLL51, DLL52, and DLL53 are depicted, as well as word line layers WLL43, WLL44, WLL45, WLL46, and WLL47. Each of the word line layers includes a word line region 676 surrounded by an aluminum oxide layer 677 composed of a blocking oxide (SiO 2 ) layer 678. The physical interaction of the word line layer and the vertical column forms a memory cell. Therefore, in one embodiment, the memory cell includes a channel 671, a tunnel dielectric 672, a charge trapping layer 673, a blocking oxide layer 678, an aluminum oxide layer 677, and a word line region 676. For example, word line layer WLL47 and a portion of vertical column 632 constitute memory cell MC1. Word line layer WLL46 and a portion of vertical column 632 constitute memory cell MC2. Word line layer WLL45 and a portion of vertical column 632 constitute memory cell MC3. Word line layer WLL44 and a portion of vertical column 632 constitute memory cell MC4. Word line layer WLL43 and a portion of vertical column 632 constitute memory cell MC5. In other architectures, the memory cell may have a different structure; however, the memory cell will still still be a storage cell.

[0104] It should be noted that the charge trapping layer 673 may extend from one end of the NAND string to the other end, and therefore may be referred to herein as a continuous charge trapping layer. When programming a memory cell, electrons are stored in a portion of the charge trapping layer 673 associated with the memory cell. In response to an appropriate voltage on the word line region 676, these electrons are attracted from the channel 671 into the charge trapping layer 673 through the tunneling dielectric 672. The Vt of the memory cell increases in proportion to the amount of stored charge. In one embodiment, programming is achieved by Fowler-Nordheim tunneling of electrons into the charge trapping layer. During an erase operation, electrons return to the channel or holes are injected into the charge trapping layer to recombine with electrons. In one embodiment, erasure is achieved using holes injected into the charge trapping layer via a physical mechanism such as gate induced drain leakage (GIDL).

[0105] Fig. 6F yes FIG. 6A to FIG. 6E A schematic diagram of a portion of a memory is depicted in FIG. Fig. 6F Physical word lines WLL0 to WLL95 are shown extending across the entire block. Fig. 6F The structure corresponds to FIG. 6A to FIG. 6E Portion 606 in block 2 of includes bit lines 611, 612, 613, 614, ..., 619. Within the block, each bit line is connected to four NAND strings. Drain side selection lines SGD0, SGD1, SGD2, and SGD3 are used to determine which of the four NAND strings is connected to the associated bit line. Source side selection lines SGS0, SGS1, SGS2, and SGS3 are used to determine which of the four NAND strings is connected to a common source line. It can also be considered that the block is divided into four sub-blocks SB0, SB1, SB2, and SB3. Sub-block SB0 corresponds to those vertical NAND strings controlled by SGD0 and SGS0, sub-block SB1 corresponds to those vertical NAND strings controlled by SGD1 and SGS1, sub-block SB2 corresponds to those vertical NAND strings controlled by SGD2 and SGS2, and sub-block SB3 corresponds to those vertical NAND strings controlled by SGD3 and SGS3.

[0106] Although 6A to 6F An example memory system of is a three-dimensional memory structure including vertical NAND strings with charge trapping material, but other (2D and 3D) memory structures (eg, MRAM, ReRAM, PCM) may also be used with the techniques described herein.

[0107] The memory system discussed above can be erased, programmed, and read. At the end of a successful programming process (with verification), the threshold voltage of the memory cell should be within one or more distributions of threshold voltages for programmed memory cells or within the distribution of threshold voltages for erased memory cells, as appropriate.

[0108] Fig. 7A is a graph of threshold voltage versus number of memory cells and illustrates example threshold voltage distributions for a memory array when each memory cell stores one bit of data. Fig. 7A Two threshold voltage distributions are shown: E and P. Threshold voltage distribution E corresponds to an erased data state. Threshold voltage distribution P corresponds to a programmed data state. Therefore, memory cells having threshold voltages in threshold voltage distribution E are in an erased data state (e.g., they are erased). Therefore, memory cells having threshold voltages in threshold voltage distribution P are in a programmed data state (e.g., they are programmed). In one embodiment, erased memory cells store data "1" and programmed memory cells store data "0". Memory cells that store one bit of data are referred to as single-level cells ("SLC").

[0109] Figure 7B is a graph of threshold voltage versus number of memory cells and illustrates example threshold voltage distributions for a memory array when each memory cell stores three bits of data. However, other embodiments may use other data capacities per memory cell (e.g., such as one bit of data, two bits of data, four bits of data, or five bits of data per memory cell). Memory cells that store more than one bit of data are referred to as multi-level cells ("MLCs"). Figure 7B Eight threshold voltage distributions are shown, corresponding to eight data states. For data state N, the data state N has a higher threshold voltage than data state N-1 and a lower threshold voltage than data state N+1. The first threshold voltage distribution (data state) S0 represents an erased memory cell. The other seven threshold voltage distributions (data states) S1 to S7 represent programmed memory cells and are therefore also referred to as programmed data states. In some embodiments, data states S1 to S7 may overlap, where the controller 122 relies on error correction to identify the correct data being stored.

[0110] Figure 7B Seven read reference voltages Vr1, Vr2, Vr3, Vr4, Vr5, Vr6, and Vr7 are shown for reading data from memory cells. By testing (e.g., performing a sensing operation) whether the threshold voltage of a given memory cell is above or below the seven read reference voltages, the system can determine the data state (i.e., S0, S1, S2, S3, ...) that the memory cell is in. Fig. 7AIn the example, the reference voltage Vr is used to test whether the memory cell is erased or programmed.

[0111] Figure 7B Also shown are seven verification reference voltages Vv1, Vv2, Vv3, Vv4, Vv5, Vv6, and Vv7 (also referred to as verification target voltages). When programming memory cells to data state S1, the system will test whether these memory cells have a threshold voltage greater than or equal to Vv1. When programming memory cells to data state S2, the system will test whether the memory cells have a threshold voltage greater than or equal to Vv2. When programming memory cells to data state S3, the system will determine whether the memory cells have a threshold voltage greater than or equal to Vv3. When programming memory cells to data state S4, the system will test whether these memory cells have a threshold voltage greater than or equal to Vv4. When programming memory cells to data state S5, the system will test whether these memory cells have a threshold voltage greater than or equal to Vv5. When programming memory cells to data state S6, the system will test whether these memory cells have a threshold voltage greater than or equal to Vv6. When programming memory cells to data state S7, the system will test whether these memory cells have a threshold voltage greater than or equal to Vv7.

[0112] In one embodiment, referred to as full sequence programming, memory cells may be programmed directly from erased data state S0 to any of programmed data states S1 to S7. For example, a population of memory cells to be programmed may first be erased so that all memory cells in the population are in erased data state S0. Then, a programming process is used to program the memory cells directly into data states S1, S2, S3, S4, S5, S6, and / or S7. For example, while some memory cells are being programmed from data state S0 to data state S1, other memory cells are being programmed from data state S0 to data state S2 and / or from data state S0 to data state S3, and so on. Figure 7B The arrows represent full sequence programming. In addition to full sequence programming, the techniques described herein can also be used with other types of programming (including but not limited to multi-level programming / multi-phase programming).

[0113] Figure 7B Each threshold voltage distribution (data state) corresponds to a predetermined value for a set of data bits stored in the memory cell. The specific relationship between the data programmed into the memory cell and the threshold voltage level of the memory cell depends on the data encoding scheme employed by the memory cell. In one embodiment, data values ​​are assigned to threshold voltage ranges using a Gray code assignment so that if the threshold voltage of the memory is erroneously shifted to its adjacent physical state, only one bit will be affected.

[0114] Figure 7C is a table describing an example of assigning data values ​​to data states. Figure 7B In the table, S0=111 (erased state), S1=110, S2=100, S3=000, S4=010, S5=011, S6=001, and S7=101. Other encodings of data may also be used. The techniques disclosed herein do not require a specific data encoding. In one embodiment, when a block is subjected to an erase operation, all memory cells are moved to data state S0, i.e., the erased state. Return to reference Figure 4 In one embodiment, during a programming operation, the ADL, BDL, and CDL data latches may be used for lower, middle, and upper page data values ​​of a memory cell, respectively.

[0115] Generally speaking, during a verification operation and a read operation, the selected word line is connected to a voltage (an example of a reference signal) whose level is specified for each read operation (e.g., see the read reference voltages Vr1, Vr2, Vr3, Vr4, Vr5, Vr6, and Vr7 of FIG. 6 ) or verification operation (e.g., see the verification reference voltages Vv1, Vv2, Vv3, Vv4, Vv5, Vv6, and Vv7 of FIG. 6 ) in order to determine whether the threshold voltage of the associated memory cell has reached this level. After the word line voltage is applied, the conduction current of the memory cell is measured to determine whether the memory cell is turned on (conducted current) in response to the voltage applied to the word line. If the conduction current is measured to be greater than a specific value, it is assumed that the memory cell is turned on and the voltage applied to the word line is greater than the threshold voltage of the memory cell. If the conduction current is not measured to be greater than a specific value, it is assumed that the memory cell is not turned on and the voltage applied to the word line is not greater than the threshold voltage of the memory cell. During a read or verify process, unselected memory cells are provided with one or more read pass voltages (also called bypass voltages) at their control gates so that these memory cells will operate as pass gates (e.g., conduct current regardless of whether these memory cells are being programmed or erased).

[0116] There are many ways to measure the conduction current of a memory cell during a read or verify operation. In one example, the conduction current of a memory cell is measured at the rate at which the memory cell discharges or charges a dedicated capacitor in a sense amplifier. In another example, the conduction current of a selected memory cell allows (or does not allow) the NAND string including the memory cell to discharge the corresponding bit line. The voltage on the bit line is measured after a certain period of time to see if it has been discharged. It should be noted that the techniques described herein can be used with different methods known in the art for verification / reading. Other reading and verification techniques known in the art can also be used.

[0117] Figure 8 is a flow chart describing one embodiment of a process for programming performed by memory die 300 / 307. In one example embodiment, Figure 8 The process is executed on the memory die 300 / 307 under the direction of the state machine 362 using the control circuits discussed above. Figure 8 process to achieve Fig. 7A Programming, Figure 7B Full sequence programming or other programming schemes including multi-level programming. When multi-level programming is implemented, Figure 8 The process is used to implement any / each stage of the multi-level programming process.

[0118] Typically, during a programming operation, a programming signal Vpgm is applied to the control gate (via a selected word line) as a series of programming voltage pulses, such as Fig. 9 As shown. Between the programming pulses are a set of verify pulses to perform verification. In many implementations, the magnitude of the programming pulses increases with each successive pulse by a predetermined step size ΔVpgm (eg, 0.2v to 0.5v). Figure 8 In step 870, a programming voltage (Vpgm) is initialized to a starting value (e.g., about 12V to 16V or another suitable level), and a programming counter PC maintained by the state machine 362 is initialized to 1. In step 872, a programming pulse of the programming signal Vpgm is applied to the selected word line (the word line selected for programming). In one embodiment, a group of memory cells that are programmed simultaneously are all connected to the same word line (the selected word line). Unselected word lines receive one or more boost voltages (e.g., about 7 volts to 11 volts) to implement a boost scheme known in the art. In one embodiment, if a memory cell should be programmed, the corresponding bit line is grounded. On the other hand, if the memory cell should remain at its current threshold voltage, the corresponding bit line is connected to Vdd (e.g., 1 volt to 3.5 volts) to inhibit programming. In step 872, a programming voltage pulse is simultaneously applied to all memory cells connected to the selected word line, so that all memory cells connected to the selected word line are programmed simultaneously. That is, they are programmed at the same time or during overlapping time (both are considered to be simultaneous). In this way, all memory cells connected to a selected word line will have their threshold voltage changed simultaneously unless they have been locked out from programming.

[0119] In step 874, one or more verify operations are performed using a set of appropriate verify reference voltages to verify the appropriate memory cells. In one embodiment, the verify process is performed by testing whether the threshold voltage of the memory cells selected for programming has reached the appropriate verify reference voltages.

[0120] In step 876, it is determined whether all memory cells have reached their target threshold voltage (PASS). If so, then the programming process is complete and successful because all selected memory cells have been programmed and verified to their target states. In step 878, a "PASS" (or success) status is reported. If it is determined in 876 that not all memory cells have reached their target threshold voltage (FAIL), then the programming process will continue to step 880.

[0121] In step 880, the system counts the number of memory cells that have not yet reached their corresponding target threshold voltage distribution. That is, the system counts the number of memory cells that have failed the verification process so far. This count can be done by the state machine 362, the controller 102, or other logic. In one specific implementation, each sense block in the sense block will store the state (pass / fail) of its corresponding memory cell. In one embodiment, there is a total count that reflects the total number of memory cells currently being programmed that have failed the last verification step. In another embodiment, a separate count is maintained for each data state.

[0122] In step 882, it is determined whether the count from step 880 is less than or equal to a predetermined limit. In one embodiment, the predetermined limit is the number of bits that can be corrected by an error correction code (ECC) during the read process of a page of memory cells. If the number of failed cells is less than or equal to the predetermined limit, the programming process can stop and report a "pass" status in step 878. In this case, enough memory cells are programmed correctly so that the remaining few memory cells that have not been fully programmed can be corrected using ECC during the read process. In some embodiments, step 880 will calculate the number of failed cells for each sector, each target data state or other cell, and compare these counts individually or collectively to one or more thresholds in step 882.

[0123] In one embodiment, the predetermined limit may be less than the total number of bits that can be corrected by the ECC during the read process to account for future errors. When programming less than all memory cells of a page, or comparing counts of only one data state (or less than all states), the predetermined limit may be a fraction (proportional or not) of the number of bits that can be corrected by the ECC during the read process of the page of memory cells. In some embodiments, the limit is not predetermined. Instead, it changes based on the number of errors that have been counted for the page, the number of program-erase cycles performed, or other criteria.

[0124] If the number of failed memory cells is not less than the predetermined limit, the programming process continues at step 884 and checks the programming counter PC against the programming limit value (PL). Examples of programming limit values ​​include 6, 20, and 30; however, other values ​​may be used. If the programming counter PC is not less than the programming limit value PL, the programming process is considered to have failed and a "failed" status is reported in step 888. If the programming counter PC is less than the programming limit value PL, the process continues at step 886, during which the programming counter PC is incremented by 1 and the programming voltage Vpgm is stepped to the next magnitude. For example, the next pulse will have a magnitude that is one step larger (e.g., a step of 0.1 volts to 0.4 volts) than the previous pulse. After step 886, the process loops back to step 872 and another programming pulse is applied to the selected word line to cause execution. Figure 8 Another iteration of the programming process (steps 872 to 886).

[0125] Since errors may occur when programming or reading, and errors may occur when storing data (e.g., due to electronic drift, data retention problems, or other phenomena), error correction is used with data programming. Memory systems typically use error correction codes (ECC) to protect data from corruption. Many ECC encoding schemes are well known in the art. These conventional error correction codes are particularly useful in large-capacity memories including flash (and other non-volatile) memories, because such encoding schemes can have a significant impact on manufacturing yields and device reliability, making devices with a small number of unprogrammable or defective cells available. Of course, there is a trade-off between yield savings and the cost of providing additional memory cells to store code bits (i.e., encoding "rate"). Therefore, some ECC codes are more suitable for flash memory devices than other ECC codes. Generally speaking, the ECC codes of flash memory devices tend to have a higher encoding rate (i.e., a lower code bit / data bit ratio) than the codes used in data communication applications (which can have an encoding rate as low as 1 / 2). Examples of well-known ECC codes commonly used in conjunction with flash memory storage devices include Reed-Solomon codes, other BCH codes, Hamming codes, and the like. Sometimes, error correction codes used in conjunction with flash memory storage devices are "systematic" in that the data portion of the final codeword is unchanged from the actual data being encoded, with code or parity bits appended to the data bits to form the complete codeword.

[0126] The specific parameters of a given error correction code include the type of code, the size of the block of actual data from which the codeword is derived, and the total length of the codeword after encoding. For example, if at least 60 ECC or parity bits are used, a typical BCH code applied to a 512-byte (4096-bit) data sector can correct up to four error bits. Reed-Solomon codes are a subset of BCH codes and are also commonly used for error correction. For example, a typical Reed-Solomon code can correct up to four errors in a 512-byte data sector using approximately 72 ECC bits. In the case of flash memory, error correction coding provides significant improvements in manufacturing yield and the reliability of flash memory over time.

[0127] In some embodiments, the controller 102 receives host data (also referred to as user data or data from an entity external to the memory system), also referred to as information bits, to be stored in the non-volatile memory structure 302. The information bits are represented by the matrix i = [1 0] (note that two bits are used for exemplary purposes only, and many embodiments have codewords longer than two bits). An error correction decoding process (such as any of the processes mentioned above or below) is implemented by the ECC engine 226 / 256 of the controller 102, where parity bits are added to the information bits to provide data represented by the matrix or codeword v = [1 0 1 0], indicating that two parity bits have been attached to the data bits. Other techniques that map input data to output data in a more complex manner may be used. For example, a low-density parity check (LDPC) code, also referred to as a Gallager code, may be used. More details about LDPC codes can be found in RG Gallager, "Low-density parity-check codes", IRE Trans. Inform. Theory, vol. IT-8, pp. 21-28, Jan. 1962; and D. MacKay, Information Theory, Inference and Learning Algorithms, Cambridge University Press 2003, chapter 47. In implementation, such LDPC codes are typically applied (e.g., by ECC engine 226 / 256) to multiple pages decoded across multiple storage elements, but they need not be applied across multiple pages. Data bits can be mapped to logical pages and stored in memory structure 302 by programming one or more memory cells to one or more programming states corresponding to v.

[0128] In one implementation, programming is used to raise the threshold voltage of a memory cell to one of the programmed data states S1, S7. Erasing is used to lower the threshold voltage of a memory cell to the erased data state SO.

[0129] One technique to erase memory cells in some memory devices is to bias the p-well (or other type) substrate to a high voltage to charge the NAND channel. When the NAND channel is at a high voltage, an erase enable voltage is applied to the control gate of the memory cell to erase the non-volatile storage element (memory cell). Another method to erase a memory cell is to generate a gate induced drain leakage (GIDL) current to charge the NAND string channel. An erase enable voltage is applied to the control gate of the memory cell while maintaining the string channel potential to erase the memory cell.

[0130] In one embodiment, a GIDL current is generated by causing a drain-to-gate voltage at a select transistor. The transistor drain-to-gate voltage that generates the GIDL current is referred to herein as the GIDL voltage. When the select transistor drain voltage is significantly higher than the select transistor control gate voltage, a GIDL current may be generated. The GIDL current is the result of carrier generation, i.e., electron-hole pair generation and / or trap-assisted generation due to band-to-band tunneling. In one embodiment, the GIDL current may cause one type of carrier (e.g., hole) to move primarily into the NAND channel, thereby raising the potential of the channel. Another type of carrier (e.g., electron) is extracted from the channel by an electric field in the direction of the bit line or in the direction of the source line. During erase, holes may tunnel from the channel to the charge storage region of the memory cell and recombine with the electrons therein to reduce the threshold voltage of the memory cell.

[0131] A GIDL current may be generated at either end of a NAND string. A first GIDL voltage may be generated between two terminals of a select transistor (e.g., a drain-side select transistor) connected to a bit line to generate a first GIDL current. A second GIDL voltage may be generated between two terminals of a select transistor (e.g., a source-side select transistor) connected to a source line to generate a second GIDL current. Erasing based on GIDL current at only one end of a NAND string is referred to as single-sided GIDL erasing. Erasing based on GIDL current at both ends of a NAND string is referred to as double-sided GIDL erasing.

[0132] As mentioned above, Fig. 9 The programming signal Vpgm is depicted as a series of programming voltage pulses. These programming voltage pulses are an example of a programming dose applied to a plurality of non-volatile memory cells being programmed to a data state. Figure 8 As described, the system performs program verification between programming doses, such as Fig.10 and Fig.11 shown. Fig.10 An embodiment in which each memory cell stores one bit of data is illustrated, depicting Fig. 9 In both of the programming voltage pulses 902 and 904. Between the programming voltage pulses 902 and 904 is a verify voltage pulse 910. In one embodiment, the verify voltage pulse 910 has a magnitude of Vv (see Fig. 7A ) and represents a system that performs program verification (step 874) between programming doses (successive iterations of step 872).

[0133] Fig.11 An embodiment of storing three bits of data per memory cell is illustrated, depicting Fig. 9 Two of the programming voltage pulses 902 and 904 are provided. Between the programming voltage pulses 902 and 904 are verification voltage pulses v1, v2, v3, v4, v5, v6, and v7. In one embodiment, the verification voltage pulse v1 has a magnitude of Vv1 (see Figure 7B ), verify voltage pulse v2 has a magnitude of Vv2, verify voltage pulse v3 has a magnitude of Vv3, verify voltage pulse v4 has a magnitude of Vv4, verify voltage pulse v5 has a magnitude of Vv5, verify voltage pulse v6 has a magnitude of Vv6, and verify voltage pulse v7 has a magnitude of Vv7. Verify voltage pulses v1, v2, v3, v4, v5, v6, and v7 represent the system performing program verification (step 874) between programming doses (consecutive iterations of step 872).

[0134] Fig.12 1 is a flow chart describing one embodiment of a process for performing program verification on a non-volatile memory. That is, Fig.12 The process is Figure 8 The process performed during an example implementation of step 874 is for an embodiment storing three bits of data per memory cell. Fig.12 The process uses Fig. 9 and Fig.11 The waveform is used to execute. Fig.12 In step 960, the system performs verification on data state S1. For example, the system tests whether the memory cell being programmed to data state S1 has a threshold voltage greater than Vv1 (e.g., Fig.11 A verify voltage pulse v1 is applied to the control gate of the memory cell being programmed to data state S1).

[0135] In step 962, the system performs verification on data state S2. For example, the system tests whether the memory cell being programmed to data state S2 has a threshold voltage greater than Vv2 (e.g., Fig.11A verify voltage pulse v2 is applied to the control gate of the memory cell being programmed to data state S2).

[0136] In step 964, the system performs verification on data state S3. For example, the system tests whether the memory cell being programmed to data state S3 has a threshold voltage greater than Vv3 (e.g., Fig.11 A verify voltage pulse v3 is applied to the control gate of the memory cell being programmed to data state S3).

[0137] In step 966, the system performs verification on data state S4. For example, the system tests whether the memory cell being programmed to data state S4 has a threshold voltage greater than Vv4 (e.g., Fig.11 A verify voltage pulse v4 is applied to the control gate of the memory cell being programmed to data state S4).

[0138] In step 968, the system performs verification on data state S5. For example, the system tests whether the memory cell being programmed to data state S5 has a threshold voltage greater than Vv5 (e.g., Fig.11 A verify voltage pulse v5 is applied to the control gate of the memory cell being programmed to data state S5).

[0139] In step 970, the system performs verification on data state S6. For example, the system tests whether the memory cell being programmed to data state S6 has a threshold voltage greater than Vv6 (e.g., Fig.11 A verify voltage pulse v6 is applied to the control gate of the memory cell being programmed to data state S6).

[0140] In step 972, the system performs verification on data state S7. For example, the system tests whether the memory cell being programmed to data state S7 has a threshold voltage greater than Vv7 (e.g., Fig.11 A verify voltage pulse v7 of 1 is applied to the control gate of the memory cell being programmed to data state S7). Note that in one embodiment, steps 960 to 972 are performed between programming doses (e.g., between programming voltage pulses). In some embodiments, one or more of steps 960 to 972 may be skipped between certain programming voltage pulses. In one embodiment, steps 960 to 972 are performed sequentially (in any order or in the order depicted), while in other embodiments, steps 960 to 972 are performed in parallel (e.g., simultaneously).

[0141] Fig.12The flow illustrates verification of all target data states, but to speed up the verification phase of the programming operation, a "smart verify" operation can be used. In a smart verify, not all target data state levels are checked. Initially, for the first few programming pulses, only the lower data states need to be checked. As the programming operation continues, and as the lower target data state begins verification, additional higher data states are included; and when the lower state ends, the lower target state verification can be discarded.

[0142] The programming operation may include a single programming pass or multiple programming passes, where each pass is programmed using, for example, incremental step pulses. The verify voltage (including Fig.11 The example verify signals v1-v7 in ) may encompass lower assigned data states, and then intermediate assigned data states, and then higher assigned data states as the programming operation progresses. Fig.11 The use of all v1-v7 between pulses 902 and 904 is shown, but in a smart verify operation, only a subset is typically used. The verify voltage is part of the sensing operation. The memory cell is sensed during the application of the verify signal to determine its programming progress. The verify voltage is used to determine the programming progress of the memory cell. For example, as discussed in the following paragraphs, Fig.13 Verify voltages Vv1 and Vv2 are used for the S1 and S2 states, respectively (curves 1307 and 1308).The result of sensing Vth relative to its verify voltage can be used to inhibit further programming of the memory cell.

[0143] Fig.13 is an implementation of a collective programming waveform for NAND memory. Fig.13 , the vertical dimension represents voltage and the horizontal dimension represents time, where the time points are t0-t13. The depicted time period corresponds to one programming loop and includes a precharge phase 1390 (t0-t2), a programming phase 1391 (t2-t4), a recovery phase 1392 (t4-t9), and a verification phase 1393 (t9-t13). The voltages shown are examples.

[0144] The top waveform depicts the voltage applied to the selected word line WLn in the first programming loop of a programming operation, as shown relative to FIG. 7A to FIG. 12 Curve 1301 represents 1V, curve 1302 represents the programming pass voltage Vpass, curve 1303 represents the programming voltage Vpgm, curve 1304 represents the positive recovery voltage Vcc=3V, curve 1305 represents the voltage pulse at Vread, curve 1306 represents 0V, and curves 1307 and 1308 represent example verification voltages VvA and VvB, respectively, where in the first programming loop, these may correspond to Fig.11During each verification voltage application, a sensing operation occurs for a selected memory cell assigned to the data state being verified. The selected memory cell is connected to a selected word line and may be in a selected sub-block. The programming pulses include curves 1302 and 1303.

[0145] The second waveform depicts the voltage VWL_unsel applied to the unselected word lines. When programming or reading memory cells on a selected word line, it is necessary to fully turn on the unselected memory cells along the NAND string to allow the selected memory cells to be programmed or sensed. Curve 1310 represents 0V, curve 1311 represents Vpass=10V, and curve 1312 represents the positive recovery or transition voltage Vpass2Vread. This refers to the voltage applied in the transition from the program pass voltage to the read pass voltage. Region 1314 represents the increase of VWL_unsel from 0V to Vpass. This will be discussed below with respect to FIG. 16A to FIG. 16C This ramp region 1314 to the Vpass voltage level is discussed in more detail. Curve 1313 represents Vread, where the Vread value used in a verify operation may be the same as the Vread value used in a sense operation for data reading, depending on the implementation.

[0146] Fig.13 The third row of depicts the voltage Vbl_pgm, which is applied to the bit lines of the program selected NAND string, enabling them to generate sufficient channel voltage to increase the stored change level of the memory cells on the selected bit line and the selected word line. Curve 1320 represents IV and curve 1321 represents 0.5V.

[0147] Fig.13 The fourth row of depicts the voltage Vbl_inh applied to the non-selected bit lines of the NAND strings to inhibit programming. These are the inhibited NAND strings in the selected sub-block. Curve 1330 represents 2V, and curve 1331 represents 0V at t7-t9 in the recovery phase. Curve 1332 represents 2V in the verification phase.

[0148] Fig.13 The fifth row of depicts the voltage Vsgd_sel applied to the drain side select gate SGD transistors of the selected sub-block. Curve 1340 represents 8V, curve 1341 represents 2.5V, curve 1342 represents 0V, and curve 1343 represents 8V.

[0149] Fig.13The sixth row of FIG. 1 depicts the voltages Vsgd_unsel and Vsgs applied to the SGD transistors and SGS transistors of the unselected sub-blocks. For Vsgd_unsel and Vsgs, curve 1350 represents 8V, and curve 1351 represents 2.5V. Curve 1352 represents Vsgs of 8V, and curve 1353 represents Vsgd_unsel of 0V.

[0150] Fig.13 The bottom line of depicts the voltage Vsl applied to the source line. Curve 1360 represents 1V, curve 1361 represents 0V, and curve 1362 represents 1V. In the pre-charge phase, positive Vbl_inh (curve 1330) is provided to the drain side channel of the disabled NAND string to remove residual electrons and provide a small amount of boost (such as 1V-2V). At this time, the SGD transistors of the selected and unselected sub-blocks are in a conductive state, for example, at a voltage of 8V. This allows the bit line voltage to be transmitted to the drain end channel. At this time, the SGS transistors of the selected and unselected sub-blocks may also be in a conductive state, for example, at a voltage of 8V to allow Vsl to pass to the source end of the channel. For example, curve 1331 represents Vbl_inh returning to 0V at t7-t9 in part of the recovery phase, and curve 1332 represents Vbl_inh at 2V during the verification phase.

[0151] In the programming phase, VWLn and Vwl_unsel are ramped up, for example, starting from t2, to provide capacitive coupling of the channels of the inhibited NAND strings. Then, at t3, VWLn is further ramped up to the peak level of Vpgm and maintained at Vpgm until t4. After applying the programming pulse, the word line voltage is ramped down in the recovery phase. Subsequently, in the verification phase, one or more verification tests are performed by applying one or more verification voltages on WLn and, for each verification voltage, sensing the conductive state of the memory cells in the programmed NAND strings of the selected sub-block. Prior to the verification test, VWLn is ramped up with VWL_unsel to equalize the channel potential.

[0152] During a programming pulse, Vsgd_sel is high enough to provide the selected SGD transistor with a conductive state for the programmed NAND string receiving Vbl_pgm = 0 V, but low enough to provide the selected SGD transistor with a non-conductive state for the inhibited NAND string receiving Vbl_inh = 2 V. During the verify phase, the SGD and SGS transistors are in a strongly conductive state to allow sensing of the selected memory cell.

[0153] consider Fig.13During interval t2-t3 of t3-t4, all word lines (both selected and unselected) are ramped up to Vpass before a programming pulse is applied to the selected word line. Since the size of the NAND array can be very large, with many blocks of memory cells (each with many word lines and many NAND strings), the resulting current Icc drawn by the die when all of these word lines are ramped up simultaneously can cause large spikes in current consumption. It is generally desirable to reduce the Icc level on the memory device, and in particular, to reduce large spikes in current because these peaks can place higher demands on the power control circuits and driver circuits of the control circuitry of the memory die. The following discussion presents techniques for smoothing these peaks by using different ramp rates for the Vpass voltage for different groups of word lines when biasing the NAND memory for programming operations.

[0154] Embodiments of non-volatile NAND memory may include a Vpass ramp rate parameter, RRC_VPASS, which controls how quickly or slowly the Vpass voltage will reach its peak Vpass applied on unselected word lines during a programming operation. Fig.13 The ramp rate also affects the peak current Icc and the corresponding power consumption during the Vpass ramp period of t2-t3 of . Typically, a faster Vpass ramp rate increases the Icc peak, while a slower ramp rate reduces the Icc peak; however, the impact of the RRC_VPASS parameter depends on the specific word line, because the electrical properties (specifically the RC (resistance-capacitance) values) of different word lines are different. Although having a slower ramp rate will reduce the peak Icc value, if a common RRC_VPASS value is used for all word lines, the programming performance (i.e., write time or Tprog) will be adversely affected. In order to be able to reduce the Icc peak and at the same time minimize the impact on the write time, a word line dependent Vpass ramp rate is used.

[0155] More specifically, because the RC properties of the word lines of a memory device typically vary relatively smoothly across NAND strings (except for defects such as open word lines or shorts), the word lines can be broken down into several regions with individually settable Vpass ramp rate values. For a device or device type, the number of word line regions, their sizes, and boundary locations can be determined as part of the device characterization process. For example, the end word lines near the source side or drain side select transistors may behave differently from the middle word lines, such that the middle word lines may have one RRC_VPASS value and the end word lines may have another value, where the end word lines all have the same RRC_VPASS value or each end word line has a different individual value. In a NAND memory embodiment having one or more center union regions (see Fig.6D), additional RRC_VPASS may be used for word lines near the union region, where regions above and below the union (and away from the end regions) may have a common RRC_VPASS or separate values. Depending on the implementation, the RCC_VPASS value may be determined and set as a parameter value on the memory die for all instances of a particular device design, for a batch of designs, or trimmed for individual devices, where this option may be based on the amount of process variation during the manufacturing process for the circuit design. The RCC_VPASS value may then be set along with other register values ​​for the operating parameters of the die, such as Figure 3A or Figure 3B The memory device 366 on the memory die or control die of the die pair. Typically, these parameters can be set along with other parameters as part of the test and die sorting process of the die.

[0156] Fig.14 Reducing the Icc peak on the unselected word lines by using a slower ramp rate for the Vpass voltage is illustrated. Fig.14 Two traces of the current Icc drawn by a single unselected word line during a programming operation are shown for both the standard Vpass ramp rate and the lower ramp rate. The two waveforms mostly overlap, except for the region 1314 corresponding to VWL_unsel. Fig.13 The ramp-up period of Vpass during the interval t2-t3. Fig.14 In the center region of , trace 1403 is Icc for the standard ramp rate for Vpass and shows an initial peak value when ramping up and then falling to a low value. Trace 1401 corresponds to a lower ramp rate, for example about half the rate, and is initially lower than 1403, but is higher than 1403 as 1401 falls. The integrated amount of current Icc is similar for both cases, but the peak current during the ramp up of Vpass is reduced by an amount ΔIcc. For Fig.14 For example, the peak Icc reduction ΔIcc is about 30%, but the amount will vary from wordline to wordline depending on the RC value of the wordline, so that the peak Icc impact relative to the RRC_VPASS change is wordline dependent and does not affect all wordlines equally in terms of peak Icc reduction. For example, on wordlines with lower RC values, a lower slope will have a greater impact on reducing peak Icc during Vpass ramp-up, but this may require Fig.13 The amount of ramp rate reduction for the fastest word line can be selected to balance the amount of Icc peak reduction and its impact on programming performance.

[0157] Back to Figure 3A and Figure 3B, the voltages VWLn and VWL_unsel are applied to the word lines by the array driver 324 of the row control circuit 320, as selected by the circuits of the row decoder 322 and the block selector 326 using the voltages provided from the power control 364. Many of these voltages applied to the word lines are higher than the on-die supply level Vcc. Fig.13 For example values ​​on , Vcc = 3V, while Vpass and Vread applied to the unselected word lines are both higher than this value. To generate these higher voltage levels from Vcc, a charge pump may be used.

[0158] Fig.15 Depicts the Vpass voltage levels that can be generated for Fig.13 The WL_unsel waveform of 1560 uses an example implementation of a multi-stage charge pump for a word line driver. A charge pump is an example of a voltage driver that can provide an output voltage higher than its input voltage. Vin is provided at input node 1562, and Vout is obtained at output node 1586. For example, Vin can be a fixed power supply voltage in a semiconductor chip, sometimes referred to as Vcc or Vdd. For example, Vout can be a word line voltage.

[0159] For example, three poles 1568, 1576 and 1584 are provided. Each stage 1568, 1576 and 1584 may include a switch and one or more fast capacitors Cf1, Cf2 and Cf3, such as MOS (metal oxide semiconductor) capacitors, respectively. At node 1562, the charge from the input voltage is maintained in the input capacitor Cin connected to the ground node. At node 1570 between the first stage 1568 and the second stage 1576, the capacitor Ca is connected to the ground node. At node 1578 between the second stage 1576 and the third stage 1584, the capacitor Cb is connected to the ground node. Finally, at the output node 1586, the output capacitor Cout is connected to the ground node. Compared with a single-stage charge pump, a multi-stage charge pump can provide greater flexibility in providing a high output voltage and a wider range of output voltages. In addition, each stage may include one or more capacitors to provide even greater flexibility.

[0160] The multi-stage charge pump 1548 is operated by a control circuit 1577, which controls switching in each stage. The switch may be, for example, a MOSFET, a bipolar junction transistor, or a relay switch. Based on the switching operation, charge is transferred from the input node 1562 of the first stage to Cf1, and from Cf1 to node 1570. The charge is then transferred from the node 1570 of the second stage to Cf2 of the second stage, and from Cf2 to node 1578. The charge is then transferred from the node 1578 of the third stage to Cf3, and from Cf3 to the output node 1586.

[0161] Generally speaking, each stage of charge pump operation includes two main phases: charging the flying capacitor from the input node, and discharging the flying capacitor into the output node. During each phase, some switches are closed (conductive), thereby connecting the flying capacitor to the input node, the output node, or the ground node. The control circuit 1577 may also communicate with the output node 1586, such as to detect its level and make adjustments in the charge pump. For example, if Vout is above the target voltage, the switching frequency may be reduced, or if Vout is below the target voltage, the switching frequency may be increased. As shown in conjunction with Fig.17A and Fig. 17B As discussed further, Vout is proportional to the switching frequency. Note that the circuit shown is only an example, as various modifications can be made. There are many different charge pump designs, and other types of voltage driver circuits can also be used.

[0162] FIG. 16A to FIG. 16C The plot shows the relationship between the Fig.13 Region 1314 of VWL_unsel is consistent with the example voltage signal. Fig.16A Depicted with Fig.13 An example voltage signal consistent with region 1314 of , wherein there is a continuous increase in the voltage signal (curves 1670-1672), and the example increase rates are Rhigh (high rate), Rint (intermediate rate between Rhigh and Rlow), and Rlow (low rate), respectively. The peak current consumption is believed to be due to the voltage driver for the unselected word lines, and the peak current consumption can be reduced by reducing the ramp rate. For example, the peak current consumption is highest at Rhigh, lower at Rint, and even lower at Rlow. Although this example illustrates three ramp rates, in general, two or more ramp rates can be used, such as the eight values ​​of Table 1 below. As Fig.17A and Fig. 17B As discussed, the clock rate of the voltage driver can be adjusted to adjust the ramp rate. When the ramp rate is reduced, the time period in which the voltage increases from 0V to Vpass increases. For example, for Rhigh, Rint, and Rlow, the time period is a, b, or c, respectively. In this example, each voltage signal may begin to increase at the same time at t2, but will require different amounts of time to reach Vpass.

[0163] Fig. 16B Depicted with Fig.131670, wherein there is a continuous increase in the voltage signal (curve 1670), a step-wise increase in the voltage signal (curves 1673 and 1674), and the example increase rates are Rhigh, Rint and Rlow, respectively. This is another example of reducing the ramp rate. As an alternative to the continuous increase, a step-wise increase can be used, such as in curves 1673 and 1674. Typically, one or more step sizes can be used. The voltage signal (curve 1673) includes a first increase from 0V to an intermediate level Vint between 0V and Vpass, followed by a period in which the voltage output is constant at Vint, followed by a second increase from Vint to Vpass. The voltage signal 1674 includes a first increase from 0V to a first intermediate level Vint1, followed by a period in which the voltage output is constant at Vint1, followed by a second increase from Vint1 to a second intermediate level Vint2, followed by a period in which the voltage output is constant at Vint2, followed by a third increase from Vint2 to Vpass. Each voltage signal starts to increase simultaneously at t2.

[0164] Fig. 16C Depicted with Fig.13 Another alternative embodiment of the example voltage signal consistent with region 1314 of , wherein the start of the increase of voltage signals 1675 and 1676 is delayed by d1 and d2, respectively, relative to the start of the increase of voltage signal 1675. By offsetting the voltage signals of different groups of unselected word lines, the peak current consumption can be reduced because the load on the voltage driver is dispersed in time. In addition, the capacitance between the word line and the memory hole is reduced. In general, offset voltage signals for two or more groups of word lines can be used. This example includes three groups of word lines. In this example, each voltage signal has a continuous increase from 0V to Vpass, but other options are possible, such as a step-by-step increase. The voltage signal (curve 1670) begins to increase at t2. After a delay of d1 relative to t2, voltage signal 1675 begins to increase. After a delay of d2 relative to t2, voltage signal 1676 begins to increase.

[0165] In the embodiments presented here, the same Vpass voltage level is used for all unselected word lines, but in other embodiments, different Vpass levels are sometimes used for different word lines, based on their position along the NAND string or based on their position relative to the selected word line. In these cases, the parameters used to determine the different ramp rates can be independent of the final Vpass voltage level of the word line.

[0166] Fig.17A and Fig. 17B Describes the methods that can be used to implement Fig.13 Different ramp rates of the charge pump (such as Fig.16A Two exemplary clock signals in ). Fig.17A depicts an example clock signal 1788 and an output voltage 1791 of a charge pump that uses a lower ramp rate (Rlow) (e.g., lower relative to Fig.16A the example shown). Fig.13 The clock signal is provided by a control circuit 1577 to activate switches in stages of the charge pump. The output voltage increases with each charging cycle, starting from 0V, for example, and ending at Vpass (e.g., 8V - 10V). Due to the repeated charging and discharging of capacitors in the charge pump, the output voltage has a ripple shape. The clock signal has a period CLK1a during a time period 1789 when the output voltage is rising. The clock signal then changes to have a period CLK1b > CLK1a during a time period 1790 when the output voltage reaches Vpass, and the output voltage then remains at Vpass. The output voltage can return to 0V or other initial levels at a specified time.

[0167] Fig. 17B depicts an example clock signal 1792 and an output voltage 1796 of a charge pump that uses a higher ramp rate (Rhigh) (relative to Fig.17A the example shown). Fig.15 The output voltage increases with each charging cycle, starting from 0V, for example, and ending at Vpass. The clock signal has a period CLK2 < CLK1a during a time period 1793 when the output voltage is rising. The clock signal then changes to have a period CLK1b > CLK2 during a time period 1794 when the output voltage reaches Vpass, as Fig.17A shown, and the output voltage then remains at Vpass.

[0168] To reduce the Icc peak level during the biasing of word lines in a NAND memory array during a programming operation while avoiding large programming time losses, the embodiments presented herein implement a word - line - related Vpass ramp rate (RRC_VPASS). The word lines of the array are divided into several adjacent zones based on the word - line RC values, where the ramp rate of the zones can be trimmed during the die sorting process for a given set of devices. The electrical properties of the word lines (i.e., word - line RC values) are generally quite consistent across a range of word lines, except near the source or drain extremes or near the junction regions within the structure (see Fig.6D ). This can be illustrated with respect to Fig.18 the example shown.

[0169] Fig.18 is an example of the variation of the RC values of word lines across a NAND memory array with a central junction region. In the Fig.18 curve, the horizontal axis is the word - line number of an embodiment of approximately 160 word lines with a central junction (as illustrated in Fig.6D ) and (as illustrated in 6A to 6FThe horizontal axis is the RC value of the word line, where it should be noted that the bottom of the graph does not start at 0; instead, for example, the fluctuations in region 1 are about 2-3% change, and the larger drop in region 3 is about 25% change. Fig.18 The wordline RC data in FIG. 1 are from test data of an actual device manufactured according to an implementation for a set of process parameters. The RC values ​​of the parameters in this example are divided into 5 regions of similar RC values: 1 / 4 Region 1 on the source end of the word lines of the NAND string; Region 2 for approximately one eighth of the word lines in the center region between Region 1 and the word lines near the union region; Region 3 for a group of word lines surrounding the center union; Region 4 for the word lines above the union region (but not the last few word lines near the drain side select gate); and Region 5 for several word lines on the drain end. The number of RC value regions will depend on the die design and processing, but a typical result will be one region near each of the drain side and source side, a region around any intermediate union regions, and an intermediate region away from the ends and union of the NAND string. The Vpass ramp rate (RRC_VPASS) value can then be selected based on the RC value of the region, with higher RC regions having higher ramp rates and lower RC regions having lower ramp rates. Therefore, not all regions require higher RRC_VPASS values, which can save programming time loss.

[0170] The Vpass ramp rate (RRC_VPASS) for a given die may be stored along with other operating parameters that are set as part of the test / die sorting / initialization operations performed on the device before it is assembled into a package or otherwise shipped from a manufacturer or test center. Back to Reference Figure 3A and 3B , these parameters may be set in registers of the storage device 366 of the system control logic. In one embodiment, the RRC_VPASS parameter may be a three-bit value corresponding to different ramp rate scaling factors that increase or decrease the ramp rate relative to the base rate (i.e., x1.00). Table 1 illustrates an example of one embodiment. Return to Reference Fig.18 For example, region 1 may be (011), region 2 may be (110), region 3 may be (000), region 4 may be (010), and region 5 may be (111).

[0171]

[0172] Table 1

[0173] The above implementation scheme has taken into account Fig.13The ramp rate of the unselected word lines from 0V to Vpass between t2 and t3 of FIG. 1314 is indicated. These techniques may be similarly applied when the unselected word lines are ramped up to Vread during t9-t10. In some embodiments, the ramp starts at an intermediate voltage ( Fig.13 Instead of discharging to 0V, the Vread may be slightly lower than this Vpass, so that the amplitude of the voltage change during the ramp is less than that in the Vpass case, but a significant spike in Icc may still occur given the large number of word lines ramping up simultaneously. Thus, more generally, when accessing a selected word line in a NAND architecture, whether for a programming operation pulse or for a sensing operation (both verify and data access read), the word line dependent ramp rate for the unselected word lines can reduce the spike in the current used by the memory die.

[0174] Fig.19 1 is a flow chart of an embodiment of determining and using a non-volatile memory device having a word line dependent ramp rate through a voltage. Beginning at step 1901, a plurality of NAND memory dies are manufactured, wherein the NAND memory dies may be Figure 3A The memory die 300 or Figure 3B Memory dies 301 are fabricated according to a specific set of design and process parameter values ​​used during fabrication. At step 1903, the memory dies are tested to characterize device properties, where this is typically done for a representative subset of devices. Based on the device characterization testing, at step 1905, electrical properties of the test die (including RC values ​​of the word lines) are determined.

[0175] Once the RC values ​​for the word lines are determined for a sample set of devices, at step 1907, the number of word line regions, the boundaries of those regions, and the resulting sizes of those regions are determined, which can be a manual process, an automated process, or a combination of these processes depending on the implementation. Fig.18, approximately 5-10% of the word lines in the central region around the union structure are assigned to one zone (Zone 3), with one or more additional zones assigned to either side. Above the union, the range of RC values ​​is fairly well contained until close to the drain side select gate and the word lines are assigned to one zone (Zone 4), with the last few high RC value word lines assigned to their own zone (Zone 5). Below the union, two zones are used, with a larger zone (Zone 1) on the source end, and a slightly smaller zone (Zone 2) between Zones 1 and 3 for a slightly higher RC value region. The number and boundaries of zones may be selected differently for different device designs and sets of production runs. For example, in a NAND architecture with a single central union region, it may be found that five zones are typically required, although the boundaries on these zones may be different for different manufacturing runs or changes in processing parameters. A word line zone will typically be a collection of multiple contiguous word lines, as in the five zone example here, but in some cases a zone may be a single word line or include more than one range of contiguous word lines. For example, in a NAND structure with a central union, in some cases, the central word lines on either side of the union (similar to Fig.18 For regions 2 and 4 in FIG. 1 , a single ramp rate parameter may be used for both regions.

[0176] Once the zones are established in step 1907, the ramp rate for each zone may be determined at step 1909. At step 1911, based on the mean or other average of the RC values ​​of the word lines of the zones, a Vpass ramp rate parameter may be determined and set in a device register of the memory die, such as in a register of the storage device 366 of the system control logic 360. These values ​​may be used for examples of devices manufactured simultaneously at the examples for steps 1903, 1905, and 1907, or for examples of devices manufactured subsequently according to the same manufacturing process and parameters. In the embodiment of Table 1 above, the RRC_VPASS parameter is a three-bit value, but other embodiments may use other numbers of bits. Table 1 also shows a specific set of ramp rate scale factor values, but other embodiments may determine or use other sets of scale factors. The setting of the ramp rate scale factor values ​​in the device register may be performed during the die sorting process when other operating parameters of the device are set. In some embodiments, the ramp rate scale factor values ​​of individual devices may be individually trimmed.

[0177] Once the memory die have their operating parameters set and other pre-shipping preparations of the individual die have been completed, the memory die may be assembled into a package, such as with respect to FIG. Figure 5A and Figure 5BIn such a package, there may be memory dies from different manufacturing runs that will have different sets of regions and / or ramp rate scale factor values ​​for the regions. At step 1915, the end user can then put the multi-die memory package into operation with each of the dies using its corresponding set of ramp rate scale factor values.

[0178] As above relative to Fig. 7A and Figure 7B As discussed, NAND memory can operate in both a binary (single-level cell, or SLC) format or a multi-level cell (MLC) format, where each memory cell stores multiple bits of data, such as 3 or 4 bits per cell. The algorithms used to perform SLC and MLC programming can differ in many ways. For example, referring to Figures 9 to 13 In MLC write operations, there are usually multiple verification operations between programming pulses. The step size between programming pulses ( Fig. 9 The ΔVpgm in (Vpass) can be different between MLC and SLC because MLC will typically use a finer resolution of the threshold voltage distribution. MLC writes typically require more programming cycles. Therefore, for several reasons, the amplitude and timing of the Icc peak in an SLC write operation will typically be different from the amplitude and timing of an MLC write operation. To address this issue, the use of different ramp rates for applying Vpass to the unselected word lines can be applied to MLC and SLC programming of NAND memory. In addition, differential timing can be applied to the Vpass ramp time duration (i.e., Fig.13 t2-t3 in ( t2-t3 in ) for MLC and SLC programming.

[0179] More specifically, as discussed above, the parameter RRC_VPASS can be used to control how quickly or slowly the Vpass voltage will reach its peak Vpass applied on the unselected word lines, but this ramp rate also affects power consumption because faster ramp rates generally increase the Icc peak, while slower ramp rates decrease the Icc peak. However, relaxing the RRC_VPASS parameter value can degrade programming performance (write time of tPROG), and to maintain the same reliability (Vt margin), the timing may also need to be relaxed, where the impact of this tPROG degradation may be different between MLC and SLC. The following discussion presents the use of separate RRC_VPASS and timing parameters for MLC and SLC so that the ICC / tPROG tradeoff between TLC and SLC can be evaluated separately. Fig. 20 The use of different parameters for MLC and SLC programming is illustrated.

[0180] Fig. 20 An implementation of differential ramp rates and timing for biasing the MLC and SLC of unselected word lines during a programming operation is illustrated. Fig. 20 Similar to Fig.16A 2070 and Rmlc 2072 for programming unselected word lines. This example uses a more relaxed waveform for MLC than SLC, since SLC programming will typically have less significant Icc peaks, but this may vary based on design and manufacturing details. As with the differential ramp rates for the word lines, an alternative implementation for the MLC / SLC case may be based on something like Fig. 16B , Fig. 16C implementation plan or Fig.16A , Fig. 16B and Fig. 16C Additionally, although the use of different ramp rates for MLC / SLC operation and for different word line groups are presented separately, in some embodiments, they may be combined.

[0181] like Fig. 20 As illustrated in , the ramp rates for MLC operation and SLC operation may be determined separately and stored as parameter value pairs (RRC_VPASS_MLC, RRC_VPASS_SLC). Depending on the implementation, a single parameter set may be used for all arrays of a die or each array may have its own parameter set. Examples of parameter values ​​are illustrated in Table 2, where the selection of parameter values ​​may again be made at the time of device characterization. In the example of Table 2, 3-bit values ​​are again used for both MLC and SLC values. In Table 2, the ramp rate scaling factor for a given parameter value is the same for both MLC and SLC, but in other implementations, these may be different. If it is known that the memory die will be configured for one of the SLC or MLC operating modes and only operate in that operating mode, then in some implementations, only the appropriate parameter value needs to be determined and set in the register.

[0182]

[0183]

[0184] Table 2

[0185] Fig. 20 The separation of the timing of MLC and SLC is also illustrated, where different values ​​of ΔT=(t3-t2) are used. Fig.13, time t2 to t3 should be long enough to allow the unselected word lines, or at least non-defective word lines, to be at or close to Vpass, and other bias levels to be set and reasonably stabilized before Vpgm is applied to the selected word line WLn. Using a longer ΔT may allow for a full ramp up to Vpass and stabilization of the voltage levels, but increases programming time, while a shorter ΔT may affect programming accuracy.

[0186] To illustrate the different ramp times between MLC and SLC operation and the differences in algorithms and behaviors, in addition to the settable ramp rate, some embodiments may additionally or alternatively have a settable parameter for ΔT for MLC relative to SLC operation. For SLC operation with a ramp rate Rslc at 2070, t3 can be used because Vpass is reached with margin for stable and slower word lines. However, for an MLC ramp rate Rmlc of 2072, the unselected word lines only reach the bias level 2074 at t3, which may adversely affect write accuracy or require additional programming cycles. Conversely, for an MLC ramp rate Rmlc of 2072, a value t3' (or even t3") may be used to allow for stable and slower word lines. Table 3 illustrates an example of setting a parameter value pair (ΔT_mlc, ΔT_slc) for a value of t3 relative to t2, where MLC and SLC operation are independently settable. As with the ramp rate parameters, these interval values ​​may be stored in Figure 3A or Figure 3B In a register of a storage device 366 of the system control logic 360 .

[0187] Table 3 again uses a 3-bit implementation for both MLC and SLC, and uses the same scaling factor for both, but other implementations may use different values ​​for these. If it is known that the memory die will be configured for one of the SLC or MLC operating modes and only operate in that operating mode, then in some implementations, only the appropriate parameter value needs to be determined and set in the register.

[0188]

[0189]

[0190] Table 3

[0191] Fig.21 A flow chart of an embodiment of determining and using a nonvolatile memory device having independently configurable ramp rates and ramp rate timing values ​​through voltage for MLC and SLC operation. Fig.21 The process is similar to Fig.19The process of and in an embodiment that also combines word line related ramp rates, the two processes can be combined. Starting from step 2101, a number of NAND memory dies are manufactured, wherein these NAND memory dies can be Figure 3A The memory die 300 or Figure 3B 301 of memory dies. These dies are manufactured according to a set of values ​​of specific design and processing parameters used in the manufacturing process. At step 2103, the memory dies are tested to characterize the device properties, where this is typically performed for a representative subset of devices. Based on the device characterization test, the behavior of the memory dies when programming operations are performed in MLC and SLC configurations can be determined and used to determine the Vpass ramp rate for the two configurations in step 2105 and the Vpass ramp interval timing for the two configurations in step 2107. Steps 2105 and 2107 can be performed sequentially or simultaneously. In addition, in some embodiments, only one of the two parameter sets may be settable, so that one of the two steps will be omitted accordingly.

[0192] Once the Vpass ramp rate and ramp interval timing values ​​for SLC and MLC operations are determined in steps 2105 and 2107, at step 2109, parameter values ​​may be set in registers for the memory die, such as in registers of the storage device 366 of the system control logic 360. These values ​​may be used for examples of devices manufactured simultaneously with the examples for steps 2103, 2105, and 2107, or for examples of devices manufactured subsequently according to the same manufacturing process and parameters. In the embodiments of Tables 2 and 3 above, the RRC_VPASS_MLC, RRC_VPASS_SLC, ΔT_mlc, and ΔT_slc parameter values ​​are three-bit values, but other embodiments may use other numbers of bits. Tables 2 and 3 also show a specific set of scaling factor values, but other embodiments may determine or use other sets of scaling factors. The setting of parameter values ​​in device registers may be performed during the die sorting process when other operating parameters of the device are set. In some embodiments, the parameter values ​​of individual devices may be individually trimmed.

[0193] Once the memory die has had its operating parameters set and other pre-shipping preparations of the individual die completed, the die may be assembled into a package at step 2011, such as with respect to Figure 5A and Figure 5BAs illustrated. In such a package, there may be memory dies from different manufacturing runs. At step 2013, the end user can then put the multi-die memory package into operation, where each of the dies uses its corresponding set of ramp rate scale factor values ​​and ramp rate interval factor values. Depending on the implementation, a single die may be operated only as an SLC device using SLC operating parameters; operated only as an MLC device using MLC operating parameters; have an array configured to operate in either mode using corresponding operating parameters; or have a portion (such as one or more planes) operating in MLC mode and other portions (such as one or more planes) operating in SLC mode using corresponding operating parameters. A multi-die package may include various combinations of these different die configurations; for example, a multi-die package may include multiple dies of the same type, but some of the dies are configured to operate in SLC mode using SLC operating parameters (such as in a "binary cache" arrangement) and other dies are configured to operate in MLC mode using MLC operating parameters.

[0194] Fig. 22 is a flow diagram of an embodiment for incorporating the use of differential Vpass ramp rates and ramp rate interval values ​​for MLC and SLC operations. Fig. 22 The elements are additional elements that can be incorporated into the write operation to combine the SLC and MLC Vpass ramp rate and Vpass ramp rate interval values ​​that can be set separately. Beginning at step 2201, a program command is received. The write command may be a host data write command from the host 120 or generated on the memory controller 102, such as for housekeeping operations (garbage collection, rewriting data cached in the SLC to MLC format, and other controller generated writes). Once the program command is received or generated on the memory controller, at step 2203, the program command is received at the system control logic 360, where it is determined whether it is an MLC write or an SLC write. For MLC writes, at step 2205, the system control logic 360 reads the MLC programming parameters from registers of the storage device 366, where, depending on the implementation, this may be one or both of the MLC Vpass ramp rate parameter value and the Vpass ramp rate interval parameter value, as well as other programming parameters. These parameters are then used at step 2207 to perform polymorphic programming, as described above with respect to Figure 8 , Fig. 9 and Figures 11 to 13Conversely, if the program command is for an SLC write, then at step 2209, the system control logic 360 reads the SLC programming parameters from the registers of the storage device 366, where, depending on the implementation, this may be one or both of the SLC Vpass ramp rate parameter value and the Vpass ramp rate interval parameter value, as well as other programming parameters. These parameters are then used at step 2211 to perform binary programming, as described above with respect to Figure 8 , Fig. 9 , Fig.10 and Fig.13 described.

[0195] One embodiment includes a nonvolatile memory device including a control circuit configured to connect to one or more arrays of nonvolatile memory cells, each of the one or more arrays having a NAND architecture and configurable to store data in a single-level cell (SLC) format or a multi-level cell (MLC) format for the memory cells. The control circuit includes a register configured to store operating parameters of the one or more memory arrays, the operating parameters including a ramp rate value for applying an unselected word line voltage level for memory access operations for an array configured to operate in the SLC format and a ramp rate value for applying an unselected word line voltage level for memory access operations for an array configured to operate in the MLC format. The control circuit is configured to: receive a command for accessing one or more memory cells along a selected word line corresponding to one or more NAND strings; determine whether the memory cells along the selected word line store data in the SLC format or in the MLC format; and access the one or more memory cells along the selected word line, wherein to access the one or more memory cells, the control circuit is configured to bias an unselected word line of the corresponding NAND string to the unselected word line voltage level at the ramp rate value corresponding to the determined one of the SLC format and the MLC format.

[0196] One embodiment includes a method comprising: receiving a plurality of replicas of a nonvolatile memory die fabricated according to a design and a set of process parameter values, the memory die having a NAND architecture; performing a device characterization test on a sample set of the replicas of the memory die; determining, based on the device characterization test, a ramp rate value for a word line of an array of memory cells for the memory die when the array is not selected to store data in a multi-level cell format; determining, based on the device characterization test, a ramp rate value for a word line of the array when the array of memory cells for the memory die is not selected to store data in a single-level cell format; and storing a parameter value corresponding to the determined ramp rate value in each of the plurality of replicas of the memory die when the array is storing data in the multi-level cell format, and storing a parameter value corresponding to the determined ramp rate value in each of the plurality of replicas of the memory die when the array is storing data in the single-level cell format, wherein when performing the access operation, the replica of the memory die is configured to ramp word lines of the array that are not selected for the access operation to an unselected word line voltage at a ramp rate based on the ramp rate parameter value corresponding to whether the array is storing data in the multi-level cell format or in the single-level cell format.

[0197] One embodiment includes a nonvolatile memory device, comprising: an array of nonvolatile memory cells configured to store data in a single-level cell (SLC) format or a multi-level cell format (MLC); and one or more control circuits connected to the array. The array of nonvolatile memory cells includes: a plurality of word lines; and a plurality of NAND strings, each of the plurality of NAND strings having a plurality of memory cells, each of the plurality of memory cells having a control gate connected to a corresponding one of the word lines. The one or more control circuits include: a register configured to store operating parameters of the array of non-volatile memory cells, the operating parameters including a ramp rate value for applying an unselected word line voltage level for a memory access operation when the array is configured to store data in the SLC format and a ramp rate value for applying the unselected word line voltage level for the memory access operation when the array is configured to store data in the MLC format; and a plurality of word line drivers configured to bias an unselected word line to the unselected word line voltage at the ramp rate value corresponding to the ramp rate parameter value corresponding to whether the array stores data in the MLC format or in the SLC format when accessing one or more memory cells along a selected word line.

[0198] For the purposes of this document, references in the specification to "an embodiment," "one embodiment," "some embodiments," or "another embodiment" may be used to describe different embodiments or the same embodiment.

[0199] For the purposes of this document, a connection may be a direct connection or an indirect connection (e.g., via one or more other parts). In some cases, when an element is referred to as being connected or coupled to another element, the element may be directly connected to the other element, or indirectly connected to the other element via an intervening element. When an element is referred to as being directly connected to another element, there are no intervening elements between the element and the other element. Two devices are "in communication" if they are directly connected or indirectly connected, such that they are able to communicate electronic signals between them.

[0200] For the purposes of this document, the term "based on" may be understood as "based, at least in part, on."

[0201] For the purposes of this document, the use of numerical terms such as a "first" object, a "second" object, and a "third" object without additional context may not imply an ordering of the objects, but may be used for identification purposes to identify different objects.

[0202] For the purposes of this document, the term "group" of objects may refer to a "group" of one or more objects.

[0203] The above detailed description has been provided for the purpose of illustration and description. It is not intended to be exhaustive or to limit the precise form disclosed by the invention. Many modifications and variations are possible in light of the above teachings. The described embodiments are selected to best explain the principles of the proposed technology and its practical application, thereby enabling others skilled in the art to best utilize it in various embodiments and in various modifications suitable for the specific use contemplated. The scope of the invention is intended to be defined by the appended claims.

Claims

1. A non-volatile memory device, comprising: A control circuit configured to be connected to one or more arrays of non-volatile memory cells, each of the one or more arrays having a NAND architecture and configurable to store data in a single-level cell (SLC) format or a multi-level cell (MLC) format for the memory cells, the control circuit comprising: registers configured to store operating parameters of the one or more memory arrays, the operating parameters including a ramp rate value for applying unselected word line voltage levels for memory access operations for arrays configured to operate in the SLC format and a ramp rate value for applying unselected word line voltage levels for memory access operations for arrays configured to operate in the MLC format, The control circuit is configured to: receiving a command to access one or more memory cells along a selected word line corresponding to one or more NAND strings; determining whether memory cells along the selected word line store data in the SLC format or in the MLC format; and accessing the one or more memory cells along the selected word line, wherein to access the one or more memory cells, the control circuit is configured to: Unselected word lines of the corresponding NAND string are biased to the unselected word line voltage level at the ramp rate value corresponding to the determined one of the SLC format and the MLC format.

2. The nonvolatile memory device of claim 1 , wherein the control circuit is formed on a control die, the nonvolatile memory device further comprising: A memory die includes the one or more arrays, the memory die being formed separately from the control die and bonded to the control die.

3. The nonvolatile memory device of claim 1, wherein the one or more memory cells along the selected word line are accessed for a programming operation.

4. The nonvolatile memory device of claim 1, wherein the one or more memory cells along the selected word line are accessed for a program verify operation.

5. The nonvolatile memory device of claim 1, wherein the one or more memory cells along the selected word line are accessed for a data read operation.

6. The non-volatile memory device according to claim 1, wherein: The operating parameters also include a ramp rate interval parameter value for applying the unselected word line voltage levels for memory access operations for an array configured to operate in the SLC format and a ramp rate interval parameter value for applying the unselected word line voltage levels for memory access operations for an array configured to operate in the MLC format, and To access the one or more memory cells, the control circuit is configured to bias unselected word lines of the corresponding NAND string to the unselected word line voltage level for the ramp rate interval parameter value corresponding to the determined one of the SLC format and the MLC format.

7. The non-volatile memory device of claim 6, wherein the operational parameter for applying the ramp rate interval parameter value for the unselected word line voltage level is a multi-bit value.

8. The non-volatile memory device of claim 1, wherein the operating parameter for applying the ramp rate value of the unselected word line voltage level is a multi-bit value.

9. The nonvolatile memory device according to claim 1, wherein the control circuit further comprises: One or more charge pump circuits are configured to drive the unselected word lines, wherein different ramp rate values ​​correspond to different clock rates of the charge pump circuits.

10. The non-volatile memory device according to claim 1, further comprising: The one or more arrays, wherein the arrays have a three-dimensional NAND architecture.

11. A method comprising: receiving a plurality of replicas of a non-volatile memory die manufactured according to a design and a set of process parameter values, the memory die having a NAND architecture; performing device characterization testing on a sample set of replicas of the memory die; determining, based on the device characterization test, a ramp rate value for a word line of an array of memory cells for the memory die when the array is not selected to store data in a multi-level cell format; determining, based on the device characterization test, a ramp rate value for the word line of the array when the array of memory cells for the memory die is not selected to store data in a single level cell format; and storing a parameter value corresponding to the determined ramp rate value in each of the plurality of the replicas of the memory die when the array stores data in the multi-level cell format, and storing a parameter value corresponding to the determined ramp rate value in each of the plurality of the replicas of the memory die when the array stores data in the single-level cell format, wherein when performing the access operation, the replicas of the memory die are configured to ramp word lines of the array that are not selected for the access operation to an unselected word line voltage at a ramp rate based on the ramp rate parameter value corresponding to whether the array stores data in the multi-level cell format or in the single-level cell format.

12. The method according to claim 11, further comprising: determining, based on the device characterization test, a ramp rate interval value for the word lines of the array when an array of memory cells for the memory die is not selected to store data in the multi-level cell format; determining, based on the device characterization test, a ramp rate interval value for the word lines of the array when the array of memory cells for the memory die is not selected to store data in the single level cell format; and storing a parameter value corresponding to the determined ramp rate interval value in each of the plurality of the replicas of the memory die when the array is storing data in the multi-level cell format, and storing a parameter value corresponding to the determined ramp rate interval value in each of the plurality of the replicas of the memory die when the array is storing data in the single-level cell format, wherein when performing the access operation, the replicas of the memory die are configured to ramp word lines of the array that are not selected for the access operation to an unselected word line voltage for an interval based on the ramp rate interval parameter value corresponding to whether the array is storing data in the multi-level cell format or in the single-level cell format.

13. The method of claim 11, wherein receiving the plurality of copies of the non-volatile memory die comprises manufacturing the memory die according to the design and the set of processing parameter values.

14. The method of claim 11, wherein the plurality of the memory dies storing the parameter values ​​include memory dies that are not in the sample set.

15. The method according to claim 11, further comprising: After storing the parameter values ​​corresponding to the determined ramp rate values ​​in the memory dies, one or more of the memory dies are assembled into a package.

16. The method of claim 15, wherein the package further comprises one or more memory dies different from the plurality of memory dies.

17. The method according to claim 11, further comprising: After storing the parameter value corresponding to the determined ramp rate value, performing the access operation includes determining whether the access is to an array storing data in the multi-level cell format or in the single-level cell format, and ramping the word lines not selected for the access operation of the array to an unselected word line voltage at the rate based on the corresponding ramp rate parameter value.

18. The method of claim 11, wherein the access operation is a program operation, and the unselected word line voltage is a pass voltage of the program operation.

19. A non-volatile memory device, the non-volatile memory device comprising: An array of non-volatile memory cells configured to store data in a single-level cell (SLC) format or a multi-level cell format (MLC), comprising: a plurality of word lines; and a plurality of NAND strings, each of the plurality of NAND strings having a plurality of memory cells, each of the plurality of memory cells having a control gate connected to a corresponding one of the word lines; and One or more control circuits connected to the array, the one or more control circuits comprising: a register configured to store operating parameters of the array of nonvolatile memory cells, the operating parameters including a ramp rate value for applying an unselected word line voltage level for a memory access operation when the array is configured to store data in the SLC format and a ramp rate value for applying the unselected word line voltage level for the memory access operation when the array is configured to store data in the MLC format; and a plurality of word line drivers configured to bias unselected word lines to the unselected word line voltage at the ramp rate values ​​corresponding to the ramp rate parameter values ​​corresponding to whether the array stores data in the MLC format or the SLC format when accessing one or more memory cells along a selected word line.

20. The nonvolatile memory device of claim 19, wherein the operating parameters further include a ramp rate interval value for applying the unselected word line voltage level for memory access operations when the array is configured to store data in the SLC format, and a ramp rate interval value for applying the unselected word line voltage level for memory access operations when the array is configured to store data in the MLC format, and The plurality of word line drivers are further configured to bias unselected word lines to the unselected word line voltage when accessing one or more memory cells along the selected word line, wherein each of the unselected word lines is ramped to the unselected word line voltage for a ramp rate interval corresponding to the operating parameter value corresponding to whether the array stores data in the MLC format or in the SLC format.

Images