Semiconductor device

Abstract

This semiconductor device (1) is provided with a semiconductor base (10), a first electrode (20), and an insulating layer (30). Semiconductor base (10) having a first semiconductor region (12) of a first conductivity type (n-type), a second semiconductor region (16) of a second conductivity type (p-type) formed at a position in contact with a first electrode (20) and an insulating layer (30), and a first conductivity type (n-type) formed in contact with the second semiconductor region (16) so as to surround the second semiconductor region (16) in plan view and a third semiconductor region 18. In the semiconductor device (1), when the sum of impurities in the second semiconductor region (16) is S1 and the sum of impurities in the third semiconductor region (18) is S2, the relationship S1 < S2 is satisfied, and the combination of the second semiconductor region (16) and the third semiconductor region (18) has the function of a Zener diode. This semiconductor device (1) has a higher breakdown tolerance than conventional semiconductor devices.

Description

Technical Field

[0001] The present invention relates to semiconductor devices. Background Art

[0002] Conventionally, there is known a semiconductor device including a so-called guard ring for the purpose of improving the withstand voltage (for example, refer to Patent Document 1).

[0003] Figure 4 900 is a diagram for explaining a conventional semiconductor device. Figure 4 (a) is a plan view of a semiconductor device 900. Figure 4 (b) Yes Figure 4 (a) AA cross-section view. Figure 4 (b) can also be said to be a cross-sectional view of a corner C in the semiconductor device 900. Figure 4 In (a), in order to show the shapes of the first semiconductor region 912 and the guard ring 916 as seen from above, the first electrode 920 , the insulating layer 930 , and the field electrode 940 arranged on the first main surface of the semiconductor substrate 910 are not shown.

[0004] like Figure 4 As shown, a conventional semiconductor device 900 includes: a semiconductor substrate 910; a first electrode 920 disposed on a first main surface of the semiconductor substrate 910; an insulating layer 930 disposed on the first main surface so as to surround the first electrode 920 when viewed from a planar surface; a field plate 940 connected to the first electrode 920 and disposed on the insulating layer 930; and a second electrode 950 disposed on a second main surface opposite to the first main surface. The semiconductor substrate 910 includes an n-type first semiconductor region 912 (an n-type semiconductor region 913 and an n++ type semiconductor region 914); a p-type guard ring 916; and an n+ type channel stopper 918 disposed on the outer end side separated from the guard ring 916. In the conventional semiconductor device 900, when viewed from above, the outer edge of the corner C of the guard ring 916 is usually made to be arc-shaped (see FIG. 1 ). Figure 4 (a)).

[0005]

Prior technical literature

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 5-75100

[0007] In the conventional semiconductor device 900 , the contact edge E (a portion near the boundary between the first electrode 920 and the insulating layer 930 in the semiconductor substrate 910 ) tends to be easily broken down when reverse biased, and there is a problem that it is difficult to improve the breakdown resistance.

[0008] The present invention is proposed to solve the above-mentioned problems, and an object of the present invention is to provide a semiconductor device having a higher breakdown resistance than conventional semiconductor devices. Summary of the invention

[0009] The semiconductor device of the present invention is characterized in that it includes: a semiconductor substrate; a first electrode arranged on a first main surface of the semiconductor substrate; and an insulating layer arranged on the first main surface in a manner of surrounding the first electrode when viewed from a plane, wherein the semiconductor substrate has: a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type formed at a position in contact with the first electrode and the insulating layer; and a third semiconductor region of a first conductivity type formed in contact with the second semiconductor region in a manner of surrounding the second semiconductor region when viewed from a plane, when the total impurity sum of the second semiconductor region is set to S1 and the total impurity sum of the third semiconductor region is set to S2, the relationship S1<S2 is satisfied, and the combination of the second semiconductor region and the third semiconductor region has the function of a Zener diode.

[0010] Effects of the Invention

[0011] According to the semiconductor device of the present invention, since the semiconductor substrate has a third semiconductor region of the first conductivity type formed in contact with the second semiconductor region in a manner of surrounding the second semiconductor region in a planar view, and when the total impurity of the second semiconductor region is set to S1 and the total impurity of the third semiconductor region is set to S2, the relationship S1<S2 is satisfied, and the combination of the second semiconductor region and the third semiconductor region has the function of a Zener diode, the electric field intensity between the second semiconductor region and the third semiconductor region can be made higher than that near the contact edge when reverse biased, thereby generating avalanche breakdown between the second semiconductor region and the third semiconductor region before the contact edge is broken down. Therefore, as a result, the semiconductor device of the present invention is a semiconductor device that can have a higher breakdown tolerance than conventional semiconductor devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 This is a diagram showing a semiconductor device 1 according to Embodiment 1.

[0013] Figure 2 This is a diagram showing a semiconductor device 2 according to a second embodiment.

[0014] Figure 3 It is a diagram for explaining the extension of a depletion layer at a corner of a semiconductor device.

[0015] Figure 4 This is a diagram for explaining a conventional semiconductor device 900 . DETAILED DESCRIPTION

[0016] The semiconductor device of the present invention is described below based on the embodiments shown in the drawings. The embodiments described below do not limit the invention involved in the present invention. The elements and their combinations described in the embodiments are not all essential to the solution means of the present invention.

[0017] [Implementation method 1]

[0018] Figure 1 1 is a diagram showing a semiconductor device 1 according to Embodiment 1. Figure 1 (a) is a plan view of the semiconductor device 1, Figure 1 (b) Yes Figure 1 (a) A1-A1 cross-sectional view. Figure 1 (b) can also be said to be a cross-sectional view of a corner C1 in the semiconductor device 1. Figure 1 In (a), the first electrode 20, the insulating layer 30 and the field electrode 40 arranged on the first main surface of the semiconductor substrate 10 are not shown in order to show the shapes of the first semiconductor region 12, the second semiconductor region 16 and the third semiconductor region 18 when viewed from a plane.

[0019] like Figure 1 As shown, the semiconductor device 1 of embodiment 1 includes: a semiconductor substrate 10; a first electrode 20 arranged on a first main surface of the semiconductor substrate 10; an insulating layer 30 arranged on the first main surface in a manner of surrounding the first electrode 20 when viewed from a plane; a field plate 40 connected to the first electrode 20 and arranged on the insulating layer 30; and a second electrode 50 arranged on a second main surface on the opposite side of the first main surface of the semiconductor substrate 10. Figure 1 The semiconductor device 1 shown may further include components other than those described above. In addition, the semiconductor device 1 is a Schottky barrier diode.

[0020] The semiconductor substrate 10 includes a first semiconductor region 12 of a first conductivity type (n-type in the first embodiment); a second semiconductor region 16 of a second conductivity type (p-type in the first embodiment); and a third semiconductor region 18 of a first conductivity type (n-type in the first embodiment). In addition, since the impurity concentration of the third semiconductor region 18 is higher than that of the n-type semiconductor region 13 described later and lower than that of the n++ type semiconductor region 14, Figure 1 The third semiconductor region 18 is represented as “n+” in FIG. 1 . In the semiconductor device 1 , the second semiconductor region 16 may be referred to as a guard ring, and the third semiconductor region 18 may be referred to as a channel stop layer.

[0021] The first semiconductor region 12 includes an n-type semiconductor region 13 disposed on the first main surface side and an n++ type semiconductor region 14 disposed on the second main surface side. The wafer resistivity of the n-type semiconductor region 13 may be, for example, 0.6 to 25 ω·cm. The thickness of the n-type semiconductor region 13 may be, for example, 4 to 65 μm. The surface impurity concentration of the n++ type semiconductor region 14 may be, for example, 1×10 20 m -3 The thickness of the n++ type semiconductor region 14 may be, for example, 100 to 400 μm.

[0022] The second semiconductor region 16 is formed at a position in contact with the first electrode 20 and the insulating layer 30. In the semiconductor device 1, when viewed from a plane, the corner C1 ( Figure 1 The outer edge of (a) is arc-shaped. The total amount of impurities in the second semiconductor region 16 can be, for example, 3×10 12 ~8×10 12 cm -2 The second semiconductor region 16 may have a depth of, for example, 0.4 to 4.0 μm.

[0023] The "total amount of impurities" in this specification refers to the value obtained by integrating the concentration distribution from the surface to the depth direction. The total amount of impurities is also a value associated with the doping amount (the amount of impurities injected), but the appropriate correlation between the withstand voltage and the doping amount may not always be obtained. This is because heat treatment, etc., can change the amount of impurities.

[0024] The third semiconductor region 18 is formed to be in contact with the second semiconductor region 16 so as to surround the second semiconductor region 16 in a plan view. The third semiconductor region 18 is formed to the end of the semiconductor device 1 in a plan view. The third semiconductor region 18 is formed from the first main surface to a depth position deeper than the deepest part of the second semiconductor region 16. The total amount of impurities in the third semiconductor region 18 may be, for example, 3×10 12 ~1×10 15 cm -2 The depth of the third semiconductor region 18 may be, for example, 0.5 to 5.0 μm.

[0025] In the semiconductor device 1, when the total impurity of the second semiconductor region 16 is set to S1 and the total impurity of the third semiconductor region 18 is set to S2, the relationship S1<S2 is satisfied. In the semiconductor device 1, it is preferable to satisfy the relationship 0.15<(S1 / S2)<1. In the semiconductor device 1, the combination of the second semiconductor region 16 and the third semiconductor region 18 has the function of a Zener diode.

[0026] The "Zener diode" in this specification includes not only a diode that only undergoes Zener breakdown at a pn junction, but also a diode that undergoes avalanche breakdown depending on conditions.

[0027] Next, effects of the semiconductor device 1 according to the first embodiment will be described.

[0028] According to the semiconductor device 1 of the first embodiment, the semiconductor substrate 10 includes: the first semiconductor region 12 of the first conductivity type; the second semiconductor region 16 of the second conductivity type formed at a position in contact with the first electrode 20 and the insulating layer 30; and the third semiconductor region 18 of the first conductivity type formed in contact with the second semiconductor region 16 so as to surround the second semiconductor region 16 in a plan view, and when the total impurity of the second semiconductor region 16 is set to S1 and the total impurity of the third semiconductor region 18 is set to S2, the relationship S1<S2 is satisfied, and the combination of the second semiconductor region 16 and the third semiconductor region 18 has the function of a Zener diode, so that when reverse biased, the electric field intensity between the second semiconductor region 16 and the third semiconductor region 18 can be made higher than that near the contact edge E1, so that avalanche breakdown occurs between the second semiconductor region 16 and the third semiconductor region 18 before the contact edge E1 is broken down. Therefore, as a result, the semiconductor device 1 of the present invention is a semiconductor device that can have a higher breakdown tolerance than conventional semiconductor devices.

[0029] According to the semiconductor device 1 of the first embodiment, the third semiconductor region 18 is formed from the first main surface to a depth position deeper than the deepest portion of the second semiconductor region 16 . Therefore, sufficient contact between the second semiconductor region 16 and the third semiconductor region 18 can be ensured.

[0030] In addition, according to the semiconductor device 1 of embodiment 1, since the relationship 0.15<(S1 / S2)<1 is satisfied, by increasing the ratio of the total impurity S1 of the second semiconductor region 16 to the total impurity S2 of the third semiconductor region 18 to a certain extent, the reduction in withstand voltage caused by too few impurities in the second semiconductor region 16 can be suppressed.

[0031] Furthermore, the semiconductor device 1 according to the first embodiment is a Schottky barrier diode capable of having a higher breakdown withstand capability than conventional devices.

[0032] [Implementation method 2]

[0033] Figure 2 2 is a diagram for explaining a semiconductor device 2 according to a second embodiment. Figure 2 (a) is a plan view of the semiconductor device 2, Figure 2 (b) Yes Figure 2 (a) A2-A2 cross-sectional view. Figure 2(b) can also be said to be a cross-sectional view of a corner C2 in the semiconductor device 2. Figure 2 In (a), the first electrode 20a, the insulating layer 30a, and the field electrode 40a arranged on the first main surface of the semiconductor substrate 10a are not shown in order to show the shapes of the first semiconductor region 12a, the second semiconductor region 16a, and the third semiconductor region 18a in a plan view.

[0034] The semiconductor device 2 of the second embodiment has basically the same structure as the semiconductor device 1 of the first embodiment, but the shape of the outer edge of the second semiconductor region when viewed from a plane is different from that of the semiconductor device 1 of the first embodiment. In the semiconductor device 2 of the second embodiment, when viewed from a plane, the outer edge of the second semiconductor region 16a is in a rectangular shape (square). That is, when viewed from a plane, the outer edge of the corner C2 of the second semiconductor region 16a is in an angular shape.

[0035] Here, use Figure 3 A phenomenon that occurs when the outer edge of the second semiconductor region 16 a is formed into a rectangular shape will be described. Figure 3 1 is a diagram for explaining the extension of the depletion layer at the corner of a semiconductor device. Figure 3 (a) is a plan view of a corner C of a conventional semiconductor device 900. Figure 3 (b) is a bottom plan view of the corner C2 of the semiconductor device 2 according to the second embodiment. Figure 2 (a) and Figure 4 As in (a), Figure 3 The first electrode, the insulating layer, and the field electrode arranged on the first main surface of the semiconductor substrate are not shown.

[0036] First, in the conventional semiconductor device 900, Figure 3 As shown in (a), when viewed from a plane, the outer edge of the corner C of the guard ring 916 is formed in an arc shape. The outer edge of the guard ring 916 contacts the n-type semiconductor region 913 having a lower impurity concentration than the guard ring 916. Therefore, when reverse biased, the depletion layer easily extends from the outer edge boundary of the guard ring 916 to the n-type semiconductor region 913 side (outside) (refer to Figure 3 (a) dashed line D1). At this time, due to the charge balance, the point corresponding to the 45° arc (refer to Figure 3 The extension of the depletion layer at point P1 in (a) tends to be narrowed (refer to Figure 3 (a) double arrow). Therefore, in the conventional semiconductor device 900, the electric field intensity tends to be concentrated near this point.

[0037] On the other hand, in the semiconductor device 2 of the second embodiment, as Figure 3As shown in (b), when viewed from a plane, the outer edge of the second semiconductor region 16a (guard ring) is rectangular. The outer edge of the second semiconductor region 16a is connected to the third semiconductor region 18a, which has a larger total impurity than the second semiconductor region 16a (usually also a higher impurity concentration). Therefore, when reverse biased, the depletion layer easily extends from the outer edge of the second semiconductor region 16a to the side (inside) of the second semiconductor region 16a (refer to Figure 3 (b) The dashed line D2). In this case, due to the charge balance at the interface, the vertex of the second semiconductor region 16a (corresponding to the portion at 45°, see Figure 3 The depletion layer at point P2 in (b) tends to expand (refer to Figure 3 (b) Double-headed arrow). Therefore, in the semiconductor device 2 of the second embodiment, the electric field intensity near this point can be relaxed.

[0038] In the semiconductor device 1 of the first embodiment, the outer edge of the corner C1 of the second semiconductor region 16 is in an arc shape, but unlike the conventional semiconductor device 900, the outer edge of the second semiconductor region 16 is in contact with the third semiconductor region 18 having a larger total amount of impurities than the second semiconductor region 16a. In this case, since the depletion layer easily extends from the outer edge boundary of the second semiconductor region 16 to the second semiconductor region 16 side (inside), unlike the conventional semiconductor device 900, the extension of the depletion layer is not hindered even at a point corresponding to 45° of the arc.

[0039] In addition, in the semiconductor device 2, the outer edge (the boundary between the n-type semiconductor region 13a and the second semiconductor region 16a) of the first semiconductor region 12a (n-type semiconductor region 13a) is also rectangular. Since the outer edge of the second semiconductor region 16a is the boundary between the second semiconductor region 16a and the third semiconductor region 18a, the shape of the inner edge of the third semiconductor region 18a corresponds to the second semiconductor region 16a. Although the illustration from the plane is omitted, the shapes of the first electrode 20a, the insulating layer 30a, and the field electrode 40a arranged on the first main surface also correspond to the second semiconductor region 16a (the outer edge is rectangular when viewed from the plane).

[0040] In the semiconductor device 2 of the second embodiment, although the shape of the outer edge of the second semiconductor region when viewed from the plane is different from that of the semiconductor device 1 of the first embodiment, according to the semiconductor device 2, since the semiconductor base 10a has: a first semiconductor region 12a of the first conductivity type; a second semiconductor region 16a of the second conductivity type formed at a position in contact with the first electrode 20a and the insulating layer 30a; and a third semiconductor region 18a of the first conductivity type formed in contact with the second semiconductor region 16a in a manner of surrounding the second semiconductor region 16a when viewed from the plane, and when the total amount of impurities in the second semiconductor region 16a is set to S1 and the total amount of impurities in the third semiconductor region 18a is set to S2, the relationship S1<S2 is satisfied, and the combination of the second semiconductor region 16a and the third semiconductor region 18a has the function of a Zener diode, it is possible to make the electric field intensity between the second semiconductor region 16a and the third semiconductor region 18a higher than that near the contact edge E2 when reverse biased, and it is possible to induce avalanche breakdown between the second semiconductor region 16a and the third semiconductor region 18a before the contact edge E2 is broken down. Therefore, as a result, the semiconductor device 2 of the second embodiment is similar to the semiconductor device 1 of the first embodiment, and is a semiconductor device having a higher breakdown resistance than conventional semiconductor devices.

[0041] In addition, according to the semiconductor device 2 of the second embodiment, since the outer edge of the second semiconductor region 16a is rectangular (square) when viewed from a plane, it is easy to extend the depletion layer from the corner of the second semiconductor region 16a when reverse biased, so that the electric field intensity at the vertex (equivalent to the 45° portion) of the second semiconductor region 16a can be alleviated. Therefore, in the semiconductor device 2 of the second embodiment, compared with the corner C2 of the outer edge of the second semiconductor region 16a, it is easier to induce avalanche breakdown at the side, thereby further improving the breakdown resistance.

[0042] Furthermore, the semiconductor device 2 according to the second embodiment has the effects possessed by the semiconductor device 1 according to the first embodiment other than those described above.

[0043] As mentioned above, although the present invention has been described based on the above-mentioned embodiments, the present invention is not limited to the above-mentioned embodiments, and can be implemented in various forms within the scope of the concept, and for example, the following modifications are also possible.

[0044] (1) The positions, sizes, etc. described in the above-mentioned embodiments (including the following modifications, the same applies hereinafter) are merely examples and may be changed within a range that does not impair the effects of the present invention.

[0045] (2) Although the semiconductor devices 1 and 2 in the above embodiments are Schottky barrier diodes, the present invention is not limited thereto. The present invention may also be applied to diodes other than Schottky barrier diodes, transistors, or thyristors. In the above embodiments, the first conductivity type is set to n-type and the second conductivity type is set to p-type, but depending on the type of semiconductor device, the first conductivity type may be set to p-type and the second conductivity type may be set to n-type.

[0046] (3) In the semiconductor device 2 of the second embodiment, the outer edge of the second semiconductor region 16a is a square when viewed from above, but the present invention is not limited to this. The outer edge of the second semiconductor region may be a rectangle.

[0047]

Explanation of symbols

[0048] 1, 2…semiconductor device; 10, 10a…semiconductor substrate; 12, 12a…first semiconductor region; 13, 13a…n-type semiconductor region; 14…n+ type semiconductor region; 16, 16a…second semiconductor region; 18, 18a…third semiconductor region; 20, 20a…first electrode; 30, 30a…insulating layer; 40, 40a…field plate; 50…second electrode; C1, C2…corner; E1, E2…contact edge.

Claims

1. A semiconductor device, characterized in that: include: Semiconductor substrate; A first electrode disposed on a first main surface of the semiconductor substrate; as well as an insulating layer disposed on the first main surface so as to surround the first electrode in a plan view, Wherein, the semiconductor substrate comprises: a first semiconductor region of a first conductivity type; a second semiconductor region of the second conductivity type formed at a position in contact with the first electrode and the insulating layer; and a third semiconductor region of the first conductivity type formed in contact with the second semiconductor region in a manner surrounding the second semiconductor region when viewed from a plane, When the total amount of impurities in the second semiconductor region is set to S1 and the total amount of impurities in the third semiconductor region is set to S2, the relationship S1<S2 is satisfied. A combination of the second semiconductor region and the third semiconductor region has a function of a Zener diode.

2. The semiconductor device according to claim 1, wherein: in, The third semiconductor region is formed from the first main surface to a depth position deeper than the deepest portion of the second semiconductor region.

3. The semiconductor device according to claim 1, wherein: The relationship of 0.15<(S1 / S2)<1 is satisfied.

4. The semiconductor device according to claim 1, wherein: in, When viewed from a plane, the outer edge of the second semiconductor region is formed of a rectangular shape.

5. The semiconductor device according to claim 1, wherein: The semiconductor device is a Schottky barrier diode.

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