Display device

Abstract

The display device includes: a substrate; a via layer disposed on the substrate; a first electrode and a second electrode disposed on the via layer and spaced apart from each other; a first insulating layer disposed on the first electrode and the second electrode; a bank layer disposed on the first insulating layer and including a partition wall portion and a bank portion having a thickness greater than a thickness of the partition wall portion; a second insulating layer disposed on the bank layer and the first insulating layer; a light emitting element disposed on the second insulating layer and disposed on the first electrode and the second electrode; and a first connection electrode and a second connection electrode, the first connection electrode being in contact with one end of each of the light emitting elements, the second connection electrode being in contact with the other end of each of the light emitting elements, in which the second insulating layer overlaps the partition wall portion and does not overlap the bank portion.

Description

Technical Field

[0001] The present disclosure relates to a display device. Background Art

[0002] As multimedia develops, display devices are becoming more and more important. Therefore, various types of display devices such as organic light emitting displays (OLEDs) and liquid crystal displays (LCDs) are being used.

[0003] As a device for displaying an image of a display device, there is a self-luminous display device including a light-emitting element. The self-luminous display device may be an organic light-emitting display using an organic material as a light-emitting material or an inorganic light-emitting display using an inorganic material as a light-emitting material. Summary of the invention

[0004] Technical issues

[0005] Aspects of the present disclosure provide a display device that can prevent electrodes from being damaged during a process.

[0006] However, aspects of the present disclosure are not limited to those set forth herein. The above and other aspects of the present disclosure will become more apparent to those of ordinary skill in the art to which the present disclosure pertains by referring to the detailed description of the present disclosure given below.

[0007] Technical Solution

[0008] According to aspects of the present disclosure, a display device includes: a substrate; a via layer disposed on the substrate; a first electrode and a second electrode disposed on the via layer and spaced apart from each other; a first insulating layer disposed on the first electrode and the second electrode; a dam layer disposed on the first insulating layer and including a blocking portion and a dam portion having a thickness greater than that of the blocking portion; a second insulating layer disposed on the dam layer and the first insulating layer; a light-emitting element disposed on the second insulating layer and on the first electrode and the second electrode; and a first connecting electrode and a second connecting electrode, the first connecting electrode contacting one end of each light-emitting element and the second connecting electrode contacting the other end of each light-emitting element, wherein the second insulating layer overlaps the blocking portion and does not overlap the dam portion.

[0009] The first insulating layer is directly disposed on the via layer, the first electrode, and the second electrode.

[0010] The thickness of the first insulating layer is smaller than the thickness of the second insulating layer.

[0011] The thickness of the first insulating layer is in the range of 30% to 70% of the thickness of the second insulating layer.

[0012] The thickness of the first insulating layer is to

[0013] The first insulating layer and the second insulating layer are in contact with each other in a region overlapping the light emitting element.

[0014] The first insulating layer and the second insulating layer include the same material.

[0015] The barrier portion includes a first barrier portion overlapping the first electrode and a second barrier portion spaced apart from the first barrier portion and overlapping the second electrode, and the bank portion surrounds the first barrier portion and the second barrier portion.

[0016] The bank layer includes a first opening disposed between the first blocking portion and the second blocking portion, and the light emitting element is disposed in the first opening.

[0017] The bank layer separates an emission region in which the light emitting element is disposed and a sub-region spaced apart from the emission region, and includes a second opening spaced apart from a first opening, wherein the first opening is disposed in the emission region and the second opening is disposed in the sub-region.

[0018] According to the disclosed embodiment, the display device includes: a substrate; a via layer, which is arranged on the substrate; a first electrode and a second electrode, which are arranged on the via layer and are spaced apart from each other; a first insulating layer, which is arranged on the via layer, the first electrode and the second electrode; a dam layer, which is arranged on the first insulating layer and separates an emission region and a sub-region spaced apart from the emission region; a second insulating layer, which is arranged on the dam layer and the first insulating layer; a light-emitting element, which is arranged on the second insulating layer in the emission region and on the first electrode and the second electrode; and a first connecting electrode and a second connecting electrode, the first connecting electrode contacts one end of each light-emitting element, and the second connecting electrode contacts the other end of each light-emitting element, wherein the second insulating layer does not overlap with a region other than the emission region and the sub-region.

[0019] The bank layer includes a barrier portion and a bank portion having a thickness greater than a thickness of the barrier portion, wherein the barrier portion overlaps the emission region and the bank portion does not overlap the emission region and the sub-region.

[0020] The second insulating layer does not overlap the bank portion but overlaps the barrier portion.

[0021] The first insulating layer overlaps the bank portion and the barrier portion.

[0022] The barrier portion and the bank portion are integrally formed.

[0023] The first insulating layer and the second insulating layer are in contact with each other in a region overlapping the light emitting element.

[0024] The display device also includes: a first contact portion and a second contact portion, which penetrate the first insulating layer and the second insulating layer and are arranged in the sub-region spaced apart from each other, the first connection electrode is connected to the first electrode through the first contact portion, and the second connection electrode is connected to the second electrode through the second contact portion.

[0025] The display device also includes: a first conductive layer, which is arranged on the substrate and includes a bottom metal layer, a first power line, a second power line and a first pad electrode; a semiconductor layer, which is arranged on the first conductive layer and includes an active layer stacked with the bottom metal layer; a second conductive layer, which is arranged on the semiconductor layer and includes a source electrode contacting a portion of the semiconductor layer, a drain electrode contacting the first power line, a gate electrode stacked with the semiconductor layer, a first conductive pattern contacting the second power line, and a second pad electrode stacked with the first pad electrode; and a third pad electrode, which is arranged on the second pad electrode.

[0026] The first electrode is electrically connected to the first power line through the source electrode, and the second electrode is electrically connected to the second power line through the first conductive pattern.

[0027] The first connection electrode, the second connection electrode and the third pad electrode include the same material.

[0028] Specific details of other embodiments are included in the detailed description and accompanying drawings.

[0029] Beneficial Effects

[0030] In the display device according to the embodiment, the first insulating layer completely covering the electrode is formed to prevent a developer in a subsequent process from reaching the electrode, thereby preventing lift-up or breakage of the electrode.

[0031] The effects according to the embodiments are not limited to the above-exemplified contents, and more various effects are included in the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 is a schematic plan view of a display device according to an embodiment.

[0033] Figure 2 is a plan view showing the arrangement of a plurality of wirings included in the display device according to the embodiment.

[0034] Figure 3 is an equivalent circuit diagram of a sub-pixel according to an embodiment.

[0035] Figure 4 is a plan view of a pixel of a display device according to an embodiment.

[0036] Figure 5 is a cross-sectional view of the pad portion and along Figure 4 A cross-sectional view taken along line E1-E1'.

[0037] Figure 6 It is along Figure 4 A cross-sectional view taken along line E2-E2'.

[0038] Figure 7 is a plan view of a first insulating layer disposed in a sub-pixel.

[0039] Figure 8 is a plan view of a bank layer provided in a sub-pixel.

[0040] Fig. 9 is a plan view of a second insulating layer disposed in a sub-pixel.

[0041] Fig.10 yes Figure 5 Magnified view of area A.

[0042] Fig.11 is a schematic diagram of a light emitting element according to an embodiment.

[0043] Figures 12 to 22 are cross-sectional views sequentially illustrating a process of manufacturing a display device according to an embodiment.

[0044] Fig.23 is a cross-sectional view of a sub-pixel and a pad portion of a display device according to an embodiment. DETAILED DESCRIPTION

[0045] The present invention will now be described more fully hereinafter with reference to the accompanying drawings in which preferred embodiments of the invention are shown. However, the present invention may be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. Instead, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of the invention to those skilled in the art.

[0046] It will also be understood that when a layer is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. Throughout the specification, the same reference numerals refer to the same components.

[0047] It will be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, the first element discussed below may be referred to as the second element without departing from the teachings of the present invention. Similarly, the second element may also be referred to as the first element.

[0048] Each of the features of the various embodiments of the present disclosure can be partially or fully combined with each other, and various interlocks and drives are technically possible. Each embodiment can be implemented independently of each other, or can be implemented together in association.

[0049] Hereinafter, specific embodiments will be described with reference to the accompanying drawings.

[0050] Figure 1 is a schematic plan view of a display device 10 according to the embodiment.

[0051] Reference Figure 1 , the display device 10 displays a moving image or a still image. The display device 10 may refer to any electronic device that provides a display screen. Examples of the display device 10 may include a television, a notebook computer, a monitor, a billboard, an Internet of Things (IoT) device, a mobile phone, a smart phone, a tablet personal computer (PC), an electronic watch, a smart watch, a watch phone, a head-mounted display, a mobile communication terminal, an electronic notebook, an electronic book, a portable multimedia player (PMP), a navigation device, a game console, a digital camera, and a camcorder, all of which provide a display screen.

[0052] The display device 10 includes a display panel that provides a display screen. Examples of the display panel include an inorganic light emitting diode display panel, an organic light emitting display panel, a quantum dot light emitting display panel, a plasma display panel, and a field emission display panel. The following will describe a case where an inorganic light emitting diode display panel is applied as an example of a display panel, but the present disclosure is not limited to this case, and other display panels may also be applied as long as the same technical spirit is applicable.

[0053] The shape of the display device 10 may be variously changed. For example, the display device 10 may have various shapes such as a horizontally long rectangle, a vertically long rectangle, a square, a quadrilateral with rounded (chamfered) corners (vertices), other polygons, or a circle. The shape of the display area DPA of the display device 10 may also be similar to the overall shape of the display device 10. Figure 1 , a display device 10 having a shape similar to a rectangle long in the second direction DR2 is shown.

[0054] The display device 10 may include a display area DPA and a non-display area NDA. The display area DPA may be an area where a picture may be displayed, and the non-display area NDA may be an area where a picture is not displayed. The display area DPA may also be referred to as an active area, and the non-display area NDA may also be referred to as an inactive area. The display area DPA may generally occupy the center of the display device 10.

[0055] The display area DPA may include a plurality of pixels PX. The pixels PX may be arranged in a matrix form. Each of the pixels PX may be rectangular or square in a plan view. However, the present disclosure is not limited thereto, and each of the pixels PX may also have a rhombus planar shape having each side inclined relative to a direction. The pixels PX may be arranged in a stripe type or an island type. In addition, each of the pixels PX may include one or more light-emitting elements that emit light of a specific wavelength band to display a specific color.

[0056] The non-display area NDA may be located around the display area DPA. The non-display area NDA may completely or partially surround the display area DPA. The display area DPA may be rectangular, and the non-display area NDA may be disposed adjacent to four sides of the display area DPA. The non-display area NDA may form a frame of the display device 10. In each non-display area NDA, a wiring or circuit driver included in the display device 10 may be positioned, or an external device may be installed.

[0057] Figure 2 is a plan view showing the arrangement of a plurality of wirings included in the display device 10 according to the embodiment.

[0058] Reference Figure 2 , the display device 10 may include a plurality of wirings. The display device 10 may include a plurality of scan lines SL (SL1, SL2, SL3), a plurality of data lines DTL (DTL1, DTL2, DTL3), an initialization voltage wiring VIL, and a plurality of voltage wirings VL (VL1, VL2, VL3, VL4). Although not shown in the drawings, other wirings may be further provided in the display device 10.

[0059] The first scan line SL1 and the second scan line SL2 may extend in the first direction DR1. The first scan line SL1 and the second scan line SL2 may be disposed adjacent to each other and may be spaced apart from the other first scan lines SL1 and the other second scan lines SL2 in the second direction DR2. The first scan line SL1 and the second scan line SL2 may be connected to each scan wiring pad (or referred to as a "pad") WPD_SC connected to a scan driver (not shown). For example, each pair of the first scan line SL1 and the second scan line SL2 may be connected to the same scan wiring pad WPD_SC. The first scan line SL1 and the second scan line SL2 may extend from a pad area PDA disposed in the non-display area NDA to the display area DPA.

[0060] Each third scan line SL3 may extend in the second direction DR2 and may be spaced apart from other third scan lines SL3 in the first direction DR1. One third scan line SL3 may be connected to one or more first scan lines SL1 or one or more second scan lines SL2. In an embodiment, the first scan line SL1 and the second scan line SL2 may be made of a conductive layer disposed at a different layer from the third scan line SL3. The scan line SL may have a mesh structure in the entire display area DPA, but the present disclosure is not limited thereto.

[0061] In this specification, the term "connected" may mean that any one component and another component are connected to each other not only by physical contact but also by other components. In addition, it is understood that any one part and another part are connected to each other as an integral component. In addition, the connection between any one component and another component may be interpreted as including an electrical connection through another component in addition to the connection through direct contact.

[0062] The data line DTL may extend in the first direction DR1. The data line DTL may include a first data line DTL1, a second data line DTL2, and a third data line DTL3. Each of the first to third data lines DTL1 to DTL3 may form a group and may be disposed adjacent to each other. The data lines DTL1 to DTL3 may extend from a pad area PDA disposed in a non-display area NDA to a display area DPA. However, the present disclosure is not limited thereto, and the data lines DTL may also be disposed at equal intervals between a first voltage wiring VL1 and a second voltage wiring VL2 to be described later.

[0063] The initialization voltage wiring VIL may extend in the first direction DR1. Each of the initialization voltage wirings VIL may be disposed between the data line DTL and the first and second scan lines SL1 and SL2. The initialization voltage wiring VIL may extend from the pad area PDA disposed in the non-display area NDA to the display area DPA.

[0064] The first voltage wiring VL1 and the second voltage wiring VL2 extend in the first direction DR1, and the third voltage wiring VL3 and the fourth voltage wiring VL4 extend in the second direction DR2. The first voltage wiring VL1 and the second voltage wiring VL2 may be alternately arranged in the second direction DR2, and the third voltage wiring VL3 and the fourth voltage wiring VL4 may be alternately arranged in the first direction DR1. The first voltage wiring VL1 and the second voltage wiring VL2 may extend in the first direction DR1 to cross the display area DPA. Among the third voltage wiring VL3 and the fourth voltage wiring VL4, some wirings may be arranged in the display area DPA, and other wirings may be arranged in the non-display area NDA located on both sides of the display area DPA in the first direction DR1. The first voltage wiring VL1 and the second voltage wiring VL2 may be made of a conductive layer arranged in a layer different from the third voltage wiring VL3 and the fourth voltage wiring VL4. Each of the first voltage wirings VL1 may be connected to at least one third voltage wiring VL3, and each of the second voltage wirings VL2 may be connected to at least one fourth voltage wiring VL4. Therefore, the voltage wiring VL may have a mesh structure in the entire display area DPA. However, the present disclosure is not limited thereto.

[0065] The first scan line SL1, the second scan line SL2, the data line DTL, the initialization voltage wiring VIL, the first voltage wiring VL1 and the second voltage wiring VL2 may be electrically connected to at least one wiring pad WPD. Each wiring pad WPD may be arranged in the non-display area NDA. In an embodiment, each wiring pad WPD may be arranged in a pad area PDA located at the lower side of the display area DPA as the second side in the first direction DR1. The first scan line SL1 and the second scan line SL2 are connected to each scan wiring pad WPD_SC arranged in the pad area PDA, and the data line DTL is respectively connected to different data wiring pads WPD_DT. Each of the initialization voltage wirings VIL is connected to the initialization wiring pad WPD_Vint, the first voltage wiring VL1 is connected to the first voltage wiring pad WPD_VL1, and the second voltage wiring VL2 is connected to the second voltage wiring pad WPD_VL2. An external device may be mounted on the wiring pad WPD. The external device may be mounted on the wiring pad WPD by an anisotropic conductive film, ultrasonic bonding, or the like. Although each wiring pad WPD is disposed in the pad area PDA located at the lower side of the display area DPA in the drawings, the present disclosure is not limited thereto. Some of the wiring pads WPD may also be disposed in an area located at the upper side or any one of the left and right sides of the display area DPA.

[0066] Each pixel PX or sub-pixel SPXn (where n is an integer from 1 to 3) of the display device 10 includes a pixel driving circuit. The above wiring can transmit a driving signal to each pixel driving circuit while passing through or surrounding each pixel PX. The pixel driving circuit may include a transistor and a capacitor. The number of transistors and capacitors in each pixel driving circuit may be changed differently. According to an embodiment, each sub-pixel SPXn of the display device 10 may have a 3T1C structure in which the pixel driving circuit includes three transistors and one capacitor. Although the 3T1C structure will be used as an example to describe the pixel driving circuit below, the present disclosure is not limited thereto, and various other modified structures such as a 2T1C structure, a 7T1C structure, and a 6T1C structure are also applicable.

[0067] Figure 3 is an equivalent circuit diagram of a sub-pixel SPXn according to an embodiment.

[0068] Reference Figure 3 , each sub-pixel SPXn of the display device 10 according to the embodiment includes three transistors T1 to T3 and one storage capacitor Cst in addition to the light emitting diode EL.

[0069] The light emitting diode EL emits light according to the current supplied by the first transistor T1. The light emitting diode EL includes a first electrode, a second electrode and at least one light emitting element disposed therebetween. The light emitting element can emit light of a specific wavelength band in response to an electrical signal received from the first electrode and the second electrode.

[0070] A first end of the light emitting diode EL can be connected to the source electrode of the first transistor T1, and a second end of the light emitting diode EL can be connected to a second voltage wiring VL2 supplied with a low potential voltage (hereinafter referred to as a second power supply voltage) lower than a high potential voltage of the first voltage wiring VL1 (hereinafter referred to as a first power supply voltage).

[0071] The first transistor T1 adjusts the current flowing from the first voltage wiring VL1 supplied with the first power supply voltage to the light emitting diode EL according to the voltage difference between the gate electrode and the source electrode. For example, the first transistor T1 may be a driving transistor for driving the light emitting diode EL. The first transistor T1 may have a gate electrode connected to the source electrode of the second transistor T2, a source electrode connected to the first electrode of the light emitting diode EL, and a drain electrode connected to the first voltage wiring VL1 to which the first power supply voltage is applied.

[0072] The second transistor T2 is turned on by the scan signal of the first scan line SL1 to connect the data line DTL to the gate electrode of the first transistor T1. The second transistor T2 may have a gate electrode connected to the first scan line SL1, a source electrode connected to the gate electrode of the first transistor T1, and a drain electrode connected to the data line DTL.

[0073] The third transistor T3 is turned on by the scan signal of the second scan line SL2 so that the initialization voltage wiring VIL is connected to the first end of the light emitting diode EL. The third transistor T3 may have a gate electrode connected to the second scan line SL2, a drain electrode connected to the initialization voltage wiring VIL, and a source electrode connected to the first end of the light emitting diode EL or the source electrode of the first transistor T1.

[0074] In the embodiment, the source electrode and the drain electrode of each of the transistors T1 to T3 are not limited to the above description, and may also be the opposite. In addition, each of the transistors T1 to T3 may be formed as a thin film transistor. In addition, although Figure 3 Each of the transistors T1 to T3 is mainly described as an N-type metal oxide semiconductor field effect transistor (MOSFET), but the present disclosure is not limited thereto. That is, each of the transistors T1 to T3 may also be formed as a P-type MOSFET, or some of the transistors T1 to T3 may be formed as an N-type MOSFET, while the other transistors may be formed as a P-type MOSFET.

[0075] The storage capacitor Cst is formed between the gate electrode and the source electrode of the first transistor T1. The storage capacitor Cst stores a difference between the gate voltage and the source voltage of the first transistor T1.

[0076] The structure of the pixel PX of the display device 10 according to the embodiment will now be described in detail with further reference to other drawings.

[0077] Figure 4 is a plan view of a pixel PX of the display device 10 according to the embodiment.

[0078] Figure 4 The planar arrangement of the electrodes RME ( RME1 and RME2 ), the bank layer BNL, the plurality of light emitting elements ED, and the connection electrodes CNE ( CNE1 and CNE2 ) in the pixel PX of the display device 10 is shown.

[0079] Reference Figure 4, each of the pixels PX of the display device 10 may include a plurality of sub-pixels SPXn. For example, one pixel PX may include a first sub-pixel SPX1, a second sub-pixel SPX2, and a third sub-pixel SPX3. The first sub-pixel SPX1 may emit light of a first color, the second sub-pixel SPX2 may emit light of a second color, and the third sub-pixel SPX3 may emit light of a third color. For example, the first color may be blue, the second color may be green, and the third color may be red. However, the present disclosure is not limited thereto, and the sub-pixels SPXn may also emit light of the same color. In an embodiment, the sub-pixel SPXn may emit blue light. Although one pixel PX includes three sub-pixels SPXn in the accompanying drawings, the present disclosure is not limited thereto, and the pixel PX may also include a greater number of sub-pixels SPXn.

[0080] Each sub-pixel SPXn of the display device 10 may include an emission area EMA and a non-emission area. The emission area EMA may be an area in which a light-emitting element ED is disposed to emit light of a specific wavelength band. The non-emission area may be an area in which a light-emitting element ED is not disposed and no light is output therefrom because light emitted from the light-emitting element ED does not reach the area.

[0081] The emission area EMA may include a region in which the light emitting element ED is disposed and a region adjacent to the light emitting element ED and from which light emitted from the light emitting element ED is output. For example, the emission area EMA may also include a region from which light emitted from the light emitting element ED is output after being reflected or refracted by other members. A plurality of light emitting elements ED may be disposed in each sub-pixel SPXn, and a region in which the light emitting element ED is positioned and a region adjacent to the region may form the emission area EMA.

[0082] Although the emission areas EMA of the subpixels SPXn have substantially the same area in the drawings, the present disclosure is not limited thereto. In some embodiments, the emission area EMA of each subpixel SPXn may have different areas according to the color or wavelength band of light emitted from the light emitting element ED disposed in the subpixel SPXn.

[0083] Each sub-pixel SPXn may further include a sub-region SA disposed in a non-emission region. The sub-region SA of each sub-pixel SPXn may be disposed on a lower side of the emission region EMA as a second side in the first direction DR1. The emission region EMA and the sub-region SA may be alternately arranged along the first direction DR1, and the sub-region SA may be disposed between the emission regions EMA of different sub-pixels SPXn spaced apart from each other along the first direction DR1. For example, the emission region EMA and the sub-region SA may be alternately arranged in the first direction DR1, and may both be repeatedly arranged in the second direction DR2. However, the present disclosure is not limited thereto, and the arrangement of the emission region EMA and the sub-region SA in a plurality of pixels PX may also be different from the arrangement of the emission region EMA and the sub-region SA in the plurality of pixels PX. Figure 4 The layout is different.

[0084] Since the light emitting element ED is not disposed in the sub-region SA, light may not be emitted from the sub-region SA, but a portion of each of the electrodes RME disposed in each sub-pixel SPXn may be disposed in the sub-region SA. The electrodes RME disposed in different sub-pixels SPXn may be separated from each other by the separation portion ROP of the sub-region SA.

[0085] The display device 10 may include electrodes RME ( RME1 and RME2 ), a bank layer BNL, a light emitting element ED, and connection electrodes CNE ( CNE1 and CNE2 ).

[0086] The electrode RME extends in one direction and is disposed in each sub-pixel SPXn. The electrode RME may extend in the first direction DR1 to be located in the emission area EMA and the sub-area SA of each sub-pixel SPXn, and may be spaced apart from each other in the second direction DR2. The electrode RME may be electrically connected to the light emitting element ED to be described later. However, the present disclosure is not limited thereto, and the electrode RME may not be electrically connected to the light emitting element ED.

[0087] The electrode RME may include a first electrode RME1 and a second electrode RME2 disposed in each sub-pixel SPXn. The first electrode RME1 is disposed on the left side of the center of the emission area EMA, and the second electrode RME2 is spaced apart from the first electrode RME1 in the second direction DR2 and disposed on the right side of the center of the emission area EMA. The first electrode RME1 and the second electrode RME2 of different sub-pixels SPXn may be spaced apart from each other by a separation portion ROP located in the sub-region SA of any one sub-pixel SPXn.

[0088] Although the two electrodes RME in each sub-pixel SPXn extend in the first direction DR1 in the drawing, the present disclosure is not limited thereto. For example, in the display device 10, a greater number of electrodes RME may be provided in one sub-pixel SPXn, or the electrode RME may be partially bent and may have different widths according to positions.

[0089] The bank layer BNL may be disposed throughout the entire display area DPA and may partially expose or surround the sub-pixel SPXn. The bank layer BNL may include a first opening OP1 and a second opening OP2 spaced apart from the first opening OP1. The first opening OP1 may be disposed in the emission area EMA of each sub-pixel SPXn, and the second opening OP2 may be disposed in a sub-area SA located on one side of the emission area EMA. The sub-area SA may be defined as the second opening OP2 of the bank layer BNL.

[0090] As will be described later, the bank layer BNL may include a bank portion BNP (see Figure 6 ) and the barrier portions BP1 and BP2 having a lower height than the bank portion BNP (see Figure 6 ).

[0091] The bank portion BNP may be disposed at a boundary between sub-pixels SPXn adjacent to each other in the first direction DR1 and the second direction DR2, and may also be disposed at a boundary between the emission area EMA and the sub-area SA. The sub-pixel SPXn, the emission area EMA, and the sub-area SA of the display device 10 may be regions separated by the bank portion BNP. The distance between the sub-pixel SPXn, the emission area EMA, and the sub-area SA may vary according to the width of the bank portion BNP. The bank portion BNP may overlap with the boundary of the sub-pixel SPXn, the sub-area SA, and the electrode RME between the emission area EMA and the sub-area SA.

[0092] The bank portion BNP of the bank layer BNL may also be disposed in the sub-region SA of each sub-pixel SPXn. The bank portion BNP may surround the second opening OP2 disposed in the sub-region SA. The second opening OP2 formed by the bank portion BNP may be the same as the separation portion ROP, and the electrode RME and the connection electrode CNE are not disposed in the second opening OP2.

[0093] The blocking portions BP1 and BP2 of the bank layer BNL may be integrated with the bank portion BNP and disposed in the emission area EMA of each sub-pixel SPXn. The blocking portions BP1 and BP2 may be spaced apart from each other, and the first opening OP1 in the emission area EMA is disposed therebetween. The light emitting element ED may be disposed in the first opening OP1 formed by the blocking portions BP1 and BP2. The blocking portions BP1 and BP2 may overlap the electrodes RME1 and RME2 in the emission area EMA of each sub-pixel SPXn, respectively.

[0094] The light emitting element ED may be disposed in the emission area EMA. The light emitting element ED may be disposed in the first opening OP1 of the bank layer BNL and may be spaced apart from each other in the first direction DR1. In an embodiment, the light emitting element ED may extend in one direction, and both ends of the light emitting element ED may be respectively disposed on different electrodes RME. For example, the first end of the light emitting element ED may be disposed on the first electrode RME1, and the second end of the light emitting element ED may be disposed on the second electrode RME2. The length of each light emitting element ED may be greater than the distance between the electrodes RME spaced apart in the second direction DR2. The direction along which the light emitting element ED extends may be substantially perpendicular to the first direction DR1 along which the electrode RME extends. However, the present disclosure is not limited thereto, and the direction along which the light emitting element ED extends may also be the second direction DR2 or a direction inclined relative to the second direction DR2.

[0095] The connection electrode CNE may be disposed on the light emitting element ED, the second insulating layer PAS2 (see Figure 5 ) and the bank layer BNL. The connection electrodes CNE may extend in a direction and may be spaced apart from each other. Each of the connection electrodes CNE may contact the light emitting element ED and may be electrically connected to the electrode RME.

[0096] The connection electrode CNE may include a first connection electrode CNE1 and a second connection electrode CNE2 disposed in each subpixel SPXn. The first connection electrode CNE1 may extend in the first direction DR1 and may be disposed on the first electrode RME1. The first connection electrode CNE1 may partially overlap the first electrode RME1 and may extend from the emission area EMA to the subarea SA. The second connection electrode CNE2 may extend in the first direction DR1 and may be disposed on the second electrode RME2. The second connection electrode CNE2 may partially overlap the second electrode RME2 and may extend from the emission area EMA to the subarea SA. The first connection electrode CNE1 may contact a first end of the light emitting element ED, and the second connection electrode CNE2 may contact a second end of the light emitting element ED.

[0097] According to an embodiment, in the display device 10, the connection electrode CNE may contact the electrodes RME respectively through the contact portions CT1 and CT2 provided in the sub-area SA. The first connection electrode CNE1 may contact the first electrode RME1 through the first contact portion CT1 in the sub-area SA. The second connection electrode CNE2 may contact the second electrode RME2 through the second contact portion CT2 in the sub-area SA. Power supply voltages may be applied to the connection electrodes CNE respectively through the electrodes RME. The first power supply voltage may be applied to the first connection electrode CNE1 through the first electrode RME1, and the second power supply voltage may be applied to the second connection electrode CNE2 through the second electrode RME2. Each connection electrode CNE may contact the light emitting element ED in the emission area EMA to transmit the power supply voltage to the light emitting element ED.

[0098] Figure 5 is a cross-sectional view of the pad portion and along Figure 4 A cross-sectional view taken along line E1-E1'. Figure 6 It is along Figure 4 A cross-sectional view taken along line E2-E2'. Figure 7 is a plan view of a first insulating layer PAS1 disposed in a sub-pixel SPXn. Figure 8 is a plan view of the bank layer BNL provided in the sub-pixel SPXn. Fig. 9 is a plan view of a second insulating layer PAS2 disposed in the sub-pixel SPXn. Fig.10 yes Figure 5 Magnified view of area A.

[0099] Figure 5 A cross section across both ends of the light emitting element ED provided in the first sub-pixel SPX1 , the electrode contact holes CTD and CTS and the contact portions CT1 and CT2 , and a cross section of a pad portion are shown. Figure 6 A cross section spanning both ends of the light emitting element ED provided in the first sub-pixel SPX1 and a portion of the bank layer BNL is shown. Figure 7 A planar arrangement of a first insulating layer PAS1 disposed under the bank layer BNL is shown. Figure 8 A planar arrangement of a bank layer BNL disposed under the second insulating layer PAS2 is shown. Fig. 9 A planar layout of the second insulating layer PAS2 is shown.

[0100] Reference Figures 5 to 10 The display device 10 may include a substrate SUB and a semiconductor layer, a plurality of conductive layers, and a plurality of insulating layers disposed on the substrate SUB. In addition, the display device 10 may include an electrode RME, a light emitting element ED, and a connecting electrode CNE. The semiconductor layer, the conductive layer, and the insulating layer may constitute a circuit element layer and a display element layer of the display device 10.

[0101] The substrate SUB may be an insulating substrate. The substrate SUB may be made of an insulating material such as glass, quartz or a polymer resin. In addition, the substrate SUB may be a rigid substrate, but may also be a flexible substrate that can be bent, folded, rolled, etc.

[0102] The circuit element layer may be disposed on the substrate SUB and may include a first conductive layer 100, a buffer layer BL, a semiconductor layer 200, a gate insulating layer GI, a second conductive layer 300, a passivation layer PV, and a via layer VIA.

[0103] The first conductive layer 100 is disposed on the substrate SUB. The first conductive layer 100 may include a first voltage wiring VL1, a second voltage wiring VL2, a bottom metal layer CAS, and a first pad electrode PE1. The first voltage wiring VL1, the second voltage wiring VL2, and the bottom metal layer CAS disposed in the display area DPA and the first pad electrode PE1 disposed in the pad area PDA may be made of the first conductive layer 100. The first conductive layer 100 may also include the above-mentioned data line DTL extending in the second direction DR2 (see Figure 3 ), initialization voltage wiring VIL (see Figure 3 ) or scanning line SL (see Figure 3 ).

[0104] The first voltage wiring VL1 may overlap at least a portion of a drain electrode DE of a transistor to be described later in the thickness direction of the substrate SUB. The first voltage wiring VL1 may be electrically connected to the drain electrode DE of the transistor through a fourth contact hole CNT4. A high potential voltage (or a first power supply voltage) supplied to the transistor may be applied to the first voltage wiring VL1.

[0105] The second voltage wiring VL2 may overlap at least a portion of the first conductive pattern CDP1 in the thickness direction of the substrate SUB. The second voltage wiring VL2 may be electrically connected to the first conductive pattern CDP1 through the fifth contact hole CNT5. A low potential voltage (or a second power supply voltage) lower than the high potential voltage supplied to the first voltage wiring VL1 may be applied to the second voltage wiring VL2. The high potential voltage supplied to the transistor may be applied to the first voltage wiring VL1, and a low potential voltage lower than the high potential voltage supplied to the first voltage wiring VL1 may be applied to the second voltage wiring VL2.

[0106] The bottom metal layer CAS may be disposed below the active layer ACT of the transistor to cover at least the channel region of the active layer ACT. The bottom metal layer CAS may be a light blocking layer that protects the active layer ACT of the transistor from external light. In addition, the bottom metal layer CAS may be electrically connected to the active layer ACT to stabilize the electrical characteristics of the transistor. However, the present disclosure is not limited thereto, and the bottom metal layer CAS may also be omitted.

[0107] The first pad electrode PE1 may form any one of the above-mentioned wiring pads WPD. For example, the first pad electrode PE1 may be the first pad electrode PE1 of any one of the scan wiring pad WPD_SC, the data wiring pad WPD_DT, the initialization wiring pad WPD_Vint, the first voltage wiring pad WPD_VL1, and the second voltage wiring pad WPD_VL2.

[0108] The first conductive layer 100 may be made of a light blocking material (i.e., an opaque metal material that blocks the transmission of light). In some embodiments, the first conductive layer 100 may be, but is not limited to, a single layer or a multilayer made of any one or more selected from molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and alloys thereof. For example, the first conductive layer 100 may be a Ti / Cu double layer in which a titanium layer and a copper layer are stacked.

[0109] The buffer layer BL may be disposed on the first conductive layer 100 and the substrate SUB. The buffer layer BL may be disposed in the display area DPA and the non-display area NDA (see Figure 1 ). The buffer layer BL may form a third contact hole CNT3 and a fourth contact hole CNT4 partially exposing the first conductive layer 100 together with the gate insulating layer GI in the display area DPA. The buffer layer BL may form a first pad contact hole CTP1 together with the gate insulating layer GI in the pad area PDA.

[0110] The buffer layer BL can protect the plurality of transistors from moisture introduced through the substrate SUB which is easily permeable to moisture. In some embodiments, the buffer layer BL can include, but is not limited to, silicon oxide (SiO x ), Silicon Nitride (SiN x ) or silicon oxynitride (SiO x N y ) of inorganic insulating materials.

[0111] The semiconductor layer 200 may be disposed on the buffer layer BL. The semiconductor layer 200 may include an active layer ACT of a transistor disposed in the display area DPA. The active layer ACT of the transistor may overlap the bottom metal layer CAS as described above.

[0112] The semiconductor layer 200 may include polycrystalline silicon, monocrystalline silicon, or an oxide semiconductor, etc. In an embodiment, the semiconductor layer 200 may include polycrystalline silicon or an oxide semiconductor. The oxide semiconductor may include indium (In). For example, the oxide semiconductor may be at least one of indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium oxide (IGO), indium zinc tin oxide (IZTO), indium gallium tin oxide (IGTO), indium gallium zinc oxide (IGZO), and indium gallium zinc tin oxide (IGZTO).

[0113] The gate insulating layer GI may be disposed on the buffer layer BL on which the semiconductor layer 200 is disposed. The gate insulating layer GI may be formed in the same pattern as the second conductive layer 300 to be described later. In some embodiments, the side surface of the gate insulating layer GI may be aligned or substantially aligned with the side surface of the second conductive layer 300, but the present disclosure is not limited thereto. The gate insulating layer GI may be made of a material including, for example, silicon oxide (SiO x ), Silicon Nitride (SiN x ) and silicon oxynitride (SiO x N y ) may be a single layer made of an inorganic layer of at least any one of the inorganic materials of ), or may be a multilayer in which inorganic layers are alternately stacked.

[0114] The second conductive layer 300 may be disposed on the gate insulating layer GI. The second conductive layer 300 may include a first conductive pattern CDP1, a second pad electrode PE2, and a gate electrode GE, a drain electrode DE, and a source electrode SE of a transistor disposed in the display area DPA.

[0115] The gate electrode GE may overlap the channel region of the active layer ACT in the third direction DR3 which is a thickness direction of the substrate SUB. Although not shown in the drawings, the second conductive layer 300 may further include an electrode of a storage capacitor.

[0116] The drain electrode DE may be spaced apart from the gate electrode GE. The drain electrode DE may be electrically connected to the portion of the active layer ACT by contacting the portion of the active layer ACT through a second contact hole CNT2 penetrating the gate insulating layer GI to expose the portion of the active layer ACT. In addition, the drain electrode DE may be electrically connected to the first voltage wiring VL1 by contacting the first voltage wiring VL1 through a fourth contact hole CNT4 penetrating the gate insulating layer GI and the buffer layer BL to expose the portion of the first voltage wiring VL1. A portion of the active layer ACT may be electrically connected to the first voltage wiring VL1 through the drain electrode DE.

[0117] The source electrode SE may be spaced apart from the drain electrode DE and the gate electrode GE. The source electrode SE may be electrically connected to the other portion of the active layer ACT by contacting the other portion of the active layer ACT through a first contact hole CNT1 penetrating the gate insulating layer GI to expose the other portion of the active layer ACT. The source electrode SE may also be electrically connected to the bottom metal layer CAS disposed below the source electrode SE by contacting the bottom metal layer CAS through a third contact hole CNT3 penetrating the gate insulating layer GI and the buffer layer BL.

[0118] The first conductive pattern CDP1 may overlap the second voltage wiring VL2. The first conductive pattern CDP1 may be electrically connected to the second voltage wiring VL2 by contacting the second voltage wiring VL2 through a fifth contact hole CNT5 penetrating the gate insulating layer GI and the buffer layer BL to expose a portion of the second voltage wiring VL2. The first conductive pattern CDP1 may be a connection pattern that electrically connects the second voltage wiring VL2 made of the first conductive layer 100 to a second electrode RME2 to be described later.

[0119] The second pad electrode PE2 may be disposed in the pad area PDA of the non-display area NDA. The second pad electrode PE2 may be disposed on the gate insulating layer GI. The second pad electrode PE2 may overlap the first pad electrode PE1 in the third direction DR3. The second pad electrode PE2 may have substantially the same width as the first pad electrode PE1, but the present disclosure is not limited thereto. The second pad electrode PE2 may be electrically connected to the first pad electrode PE1 through a first pad contact hole CTP1 that penetrates the gate insulating layer GI and the buffer layer BL to expose a portion of the first pad electrode PE1.

[0120] As will be described later, the first, second, third, fourth, and first pad contact holes CNT1, CNT2, CNT3, CNT4, and CTP1 penetrating the buffer layer BL and the gate insulating layer GI may be contact holes simultaneously formed through a single mask process.

[0121] The second conductive layer 300 may be a single layer or multiple layers made of any one or more selected from molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu) and alloys thereof.

[0122] The passivation layer PV may be disposed on the buffer layer BL on which the second conductive layer 300 is formed. The passivation layer PV may cover and protect the second conductive layer 300. For example, during the manufacturing process of the display device 10, the passivation layer PV may be disposed on the second pad electrode PE2 of the pad area PDA to protect the second pad electrode PE2 from a process of etching the electrode RME to be described later. The passivation layer PV may be disposed on the second pad electrode PE2 in the pad area PDA to form a second pad contact hole CTP2 exposing the second pad electrode PE2 in the third direction DR3 so that the third pad electrode PE3 and the second pad electrode PE2 to be described later may be electrically connected by contacting each other.

[0123] In some embodiments, the passivation layer PV may include, but is not limited to, silicon oxide (SiO x ), Silicon Nitride (SiN x ) or silicon oxynitride (SiO x N y ) of inorganic insulating materials.

[0124] The via layer VIA may be disposed on the passivation layer PV. The via layer VIA may cover the upper surface of the passivation layer PV in the display area DPA. The via layer VIA may be disposed in the display area DPA, but may not be disposed in the pad area PDA of the non-display area NDA at least. This may be caused by the via material layer disposed in the pad area PDA being removed during the manufacturing process of the display device 10.

[0125] The via layer VIA may include an organic insulating material such as polyimide (PI), and may form a flat upper surface by compensating for a step difference caused by a conductive layer under the via layer VIA. However, in some embodiments, the via layer VIA may be omitted.

[0126] The display device 10 may include an electrode RME, a bank layer BNL, a light emitting element ED, and a connection electrode CNE as a display element layer disposed on the via layer VIA. In addition, the display device 10 may include insulating layers PAS1 and PAS2.

[0127] The electrodes RME (RME1 and RME2) may be disposed on the via layer VIA. For example, the electrodes RME may be directly disposed on the via layer VIA and may be spaced apart to face each other. The electrodes RME may include a first electrode RME1 and a second electrode RME2. The first electrode RME1 and the second electrode RME2 may overlap with a bank portion BNP and barrier portions BP1 and BP2 of a bank layer BNL to be described later. The first electrode RME1 may overlap with the bank portion BNP and the first barrier portion BP1, and the second electrode RME2 may overlap with the bank portion BNP and the second barrier portion BP2.

[0128] Each of the first and second electrodes RME1 and RME2 may be disposed in the emission area EMA and the sub-area SA. The electrodes RME of different sub-pixels SPXn adjacent to each other in the first direction DR1 may be spaced or separated from each other in a separation portion ROP disposed in the sub-area SA.

[0129] The first electrode RME1 and the second electrode RME2 may be spaced apart from each other, and a space between the first electrode RME1 and the second electrode RME2 may overlap with the first opening OP1 of the bank layer BNL. In an embodiment, a distance between the first electrode RME1 and the second electrode RME2 spaced apart from each other may be smaller than a width of the first opening OP1 of the bank layer BNL or a distance between the first blocking portion BP1 and the second blocking portion BP2. The first opening OP1 may have a width sufficient to allow the light emitting element ED to be disposed in the first opening OP1, and the first electrode RME1 and the second electrode RME2 may be spaced apart by a distance such that both ends of the light emitting element ED are placed on the first electrode RME1 and the second electrode RME2.

[0130] Each of the electrodes RME may directly contact the second conductive layer 300 through an electrode contact hole CTD or CTS in a portion overlapping the bank layer BNL between the emission region EMA and the sub-region SA. The first electrode contact hole CTD may be formed in a region where the bank layer BNL and the first electrode RME1 overlap, and the second electrode contact hole CTS may be formed in a region where the bank layer BNL and the second electrode RME2 overlap. The first electrode RME1 may contact the source electrode SE through a first electrode contact hole CTD penetrating the via layer VIA and the passivation layer PV. The second electrode RME2 may contact the first conductive pattern CDP1 through a second electrode contact hole CTS penetrating the via layer VIA and the passivation layer PV. The first electrode RME1 may be electrically connected to the transistor through the source electrode SE to receive a first power supply voltage, and the second electrode RME2 may be electrically connected to the second voltage wiring VL2 through the first conductive pattern CDP1 to receive a second power supply voltage. However, the present disclosure is not limited thereto.

[0131] The electrode RME may include a conductive material with high reflectivity. For example, each of the electrode RMEs may include a metal such as silver (Ag), copper (Cu), or aluminum (Al), may be an alloy including aluminum (Al), nickel (Ni), or lanthanum (La), or may have a structure in which a metal layer such as titanium (Ti), molybdenum (Mo), or niobium (Nb) and the above alloy are stacked. In some embodiments, each of the electrode RMEs may be a double layer or multilayer in which an alloy including aluminum (Al) and at least one metal layer made of titanium (Ti), molybdenum (Mo), or niobium (Nb) are stacked.

[0132] However, the present disclosure is not limited thereto, and each electrode RME may also include a transparent conductive material. For example, each electrode RME may include a material such as ITO, IZO or ITZO. In some embodiments, each electrode RME may have a structure in which a transparent conductive material and a metal layer having a high reflectivity are stacked in one or more layers, or may be formed into a structure including a single layer thereof. For example, each electrode RME may have a stacked structure of ITO / Ag / ITO, ITO / Ag / IZO or ITO / Ag / ITZO / IZO. The electrode RME may be electrically connected to the light emitting element ED, and may reflect some of the light emitted from the light emitting element ED in an upward direction above the substrate SUB.

[0133] The first insulating layer PAS1 may be disposed in the pad area PDA of the display area DPA and the non-display area NDA. The first insulating layer PAS1 may be disposed on the via layer VIA on which the electrode RME is formed, and may be disposed on the passivation layer PV in the pad area PDA. The first insulating layer PAS1 may overlap the blocking portions BP1 and BP2 and the bank portion BNP of the bank layer BNL to be described later.

[0134] like Figure 7 As shown in FIG, the first insulating layer PAS1 may be disposed in the entire subpixel SPXn except a portion of the subregion SA. For example, the first insulating layer PAS1 may be disposed in the entire subpixel SPXn except the first contact portion CT1, the second contact portion CT2, and the separation portion ROP of the subregion SA.

[0135] The first insulating layer PAS1 may be directly disposed on the via layer VIA, the first electrode RME1, and the second electrode RME2 in the display area DPA to cover them. The first insulating layer PAS1 may protect the first electrode RME1 while insulating the first electrode RME1 and the second electrode RME2 from each other. As will be described later, a developer for forming a bank layer BNL may be applied on the electrode RME. However, since the first insulating layer PAS1 protects the electrode RME, the first insulating layer PAS1 may prevent the electrode RME from being electrically corroded by the developer. In addition, the first insulating layer PAS1 may prevent the light emitting element ED on the first insulating layer PAS1 from directly contacting other components, thereby preventing damage to the light emitting element ED.

[0136] In an embodiment, the first insulating layer PAS1 may have a predetermined thickness to protect the electrode RME from the developer. The first insulating layer PAS1 may have a predetermined thickness. to Thickness TT1 (see Fig.10 ), preferably, having to In addition, the thickness TT1 of the first insulating layer PAS1 may be greater than the thickness TT2 of the second insulating layer PAS2 to be described later (see Fig.10 ). For example, the thickness TT1 of the first insulating layer PAS1 may be in the range of 30% to 70% of the thickness TT2 of the second insulating layer PAS2. The thickness TT1 of the first insulating layer PAS1 may be smaller than the thickness TT2 of the second insulating layer PAS2, thereby preventing an increase in the total thickness of the insulating layer disposed on the display element layer.

[0137] The first insulating layer PAS1 may include first and second contact portions CT1 and CT2 penetrating the first insulating layer PAS1 and at least partially exposing the first and second electrodes RME1 and RME2 in the sub-region SA of the display region DPA. The first connection electrode CNE1 and the first electrode RME1, which will be described later, may be electrically connected to each other by the first contact portion CT1 penetrating the first insulating layer PAS1, and the second connection electrode CNE2 and the second electrode RME2 may be electrically connected to each other by the second contact portion CT2 penetrating the first insulating layer PAS1.

[0138] The first insulating layer PAS1 may be disposed on the passivation layer PV in the pad area PDA. The first insulating layer PAS1 may be disposed directly on the upper surface of the passivation layer PV in the pad area PDA. The first insulating layer PAS1 may form a second pad contact hole CTP2 exposing the second pad electrode PE2 together with the passivation layer PV and the second insulating layer PAS2 in the pad area PDA. Side surfaces of the passivation layer PV, the first insulating layer PAS1, and the second insulating layer PAS2 forming the second pad contact hole CTP2 may be aligned with each other, but the present disclosure is not limited thereto.

[0139] The first insulating layer PAS1 may include silicon oxide or silicon nitride. In an embodiment, the first insulating layer PAS1 may be made of silicon oxide so that the gas degassed from the via layer VIA may be released to the outside. However, the present disclosure is not limited thereto.

[0140] The bank layer BNL may be disposed on the first insulating layer PAS1. The bank layer BNL may include a bank portion BNP and blocking portions BP1 and BP2 having heights different from the bank portion BNP. The bank layer BNL may be disposed in the entire sub-pixel SPXn except for a portion of the emission region EMA and a portion of the sub-region SA. The blocking portions BP1 and BP2 and the bank portion BNP may be integrated with each other and may be referred to as portions of the bank layer BNL according to their placement positions and heights.

[0141] Further references Figure 8, the blocking portions BP1 and BP2 of the bank layer BNL may overlap the emission area EMA of each sub-pixel SPXn. The blocking portions BP1 and BP2 may extend in the first direction DR1, and may be spaced apart from each other and the first opening OP1 in the emission area EMA may be placed between the blocking portions BP1 and BP2. For example, the blocking portions BP1 and BP2 may include a first blocking portion BP1 and a second blocking portion BP2 spaced apart from each other in the second direction DR2 by the first opening OP1. The first blocking portion BP1 may be disposed on the left side of the center of the emission area EMA as the first side in the second direction DR2, and the second blocking portion BP2 may be spaced apart from the first blocking portion BP1 and disposed on the right side of the center of the emission area EMA as the second side in the second direction DR2. The bank portion BNP may be disposed between the first blocking portion BP1 and the second blocking portion BP2 of different sub-pixels SPXn. A plurality of light emitting elements ED may be disposed in the first opening OP1 between the first blocking portion BP1 and the second blocking portion BP2.

[0142] The first blocking portion BP1 and the second blocking portion BP2 may extend in the first direction DR1 and may be integrated with a portion of the bank portion BNP of the bank layer BNL surrounding the emission area EMA. The length of each of the blocking portions BP1 and BP2 in the first direction DR1 may be the same as the length of the emission area EMA in the first direction DR1. The first blocking portion BP1 and the second blocking portion BP2 may have the same width in the second direction DR2. However, the present disclosure is not limited thereto, and the first blocking portion BP1 and the second blocking portion BP2 may also have different widths. For example, any one blocking portion may have a greater width than the other blocking portion. Although two blocking portions BP1 and BP2 having the same width are provided in the sub-pixel SPXn in the drawings, the present disclosure is not limited thereto. The number and shape of the blocking portions BP1 and BP2 may vary according to the number or arrangement structure of the electrodes RME.

[0143] The blocking portions BP1 and BP2 may be disposed on the first insulating layer PAS1. For example, the blocking portions BP1 and BP2 may be disposed directly on the first insulating layer PAS1, and at least a portion of each of the blocking portions BP1 and BP2 may protrude from the upper surface of the first insulating layer PAS1. The protruding portion of each of the blocking portions BP1 and BP2 may have an inclined side surface or a curved side surface having a predetermined curvature. Different from the drawings, each of the blocking portions BP1 and BP2 may also have a shape having an outer surface curved with a predetermined curvature in cross section, for example, may have a semicircular shape or a semi-elliptical shape.

[0144] The bank portion BNP of the bank layer BNL may be disposed on the first insulating layer PAS1. The bank portion BNP may include a portion extending in the first direction DR1 and the second direction DR2, and may surround each sub-pixel SPXn. The bank portion BNP may surround the emission area EMA and the sub-region SA of each sub-pixel SPXn to separate them, and may be integrated with the blocking portions BP1 and BP2 disposed in the emission area EMA. The bank portion BNP of the bank layer BNL may surround the outermost periphery of the display area DPA to separate the display area DPA from the non-display area NDA. The bank portion BNP may not overlap with the emission area EMA and the sub-region SA. The bank layer BNL may be disposed in the entire display area DPA, and may be formed in a grid shape. The area exposed by the bank layer BNL in the display area DPA may be a first opening OP1 disposed in the emission area EMA and a second opening OP2 disposed in the sub-region SA. The portion of the bank layer BNL in which the blocking portions BP1 and BP2 are disposed may be the emission area EMA.

[0145] The bank portion BNP of the bank layer BNL may have a thickness greater than that of the blocking portions BP1 and BP2. The upper surface of the bank portion BNP may be at a height greater than that of the blocking portions BP1 and BP2. The bank portion BNP may prevent ink from overflowing to adjacent sub-pixels SPXn in an inkjet printing process during a manufacturing process of the display device 10. The bank layer BNL may include, but is not limited to, an organic insulating material such as polyimide (PI).

[0146] The second insulating layer PAS2 may be disposed in the pad area PDA of the display area DPA and the non-display area NDA. The second insulating layer PAS2 may be disposed on the bank layer BNL and the first insulating layer PAS1 in the display area DPA, and may be disposed on the first insulating layer PAS1 in the pad area PDA.

[0147] like Fig. 9 As shown in , the second insulating layer PAS2 may be disposed in the emission area EMA and the sub-area SA of the sub-pixel SPXn. Specifically, the second insulating layer PAS2 may be disposed in the entire emission area EMA, and may be disposed in the sub-area SA except the first contact portion CT1, the second contact portion CT2, and the separation portion ROP. For example, the second insulating layer PAS2 may not overlap with the area of ​​the display area DPA except the emission area EMA and the sub-area SA, and may not be disposed in the area of ​​the display area DPA except the emission area EMA and the sub-area SA.

[0148] The second insulating layer PAS2 may cover the first insulating layer PAS1 exposed by the first opening OP1 of the bank layer BNL in the emission area EMA. In the emission area EMA, the second insulating layer PAS2 may be directly disposed on the blocking portions BP1 and BP2 of the bank layer BNL, and may overlap and cover the blocking portions BP1 and BP2. The second insulating layer PAS2 may not be disposed on the bank portion BNP of the bank layer BNL, and may not overlap the bank portion BNP.

[0149] In an embodiment, the emission area EMA defined by the bank portion BNP of the bank layer BNL may be coated with ink in which the light emitting elements ED are dispersed in a process of aligning the light emitting elements ED. In this case, the surface of the bank portion BNP may be hydrophobic so that the ink does not overflow to the adjacent sub-pixel SPXn. Since the second insulating layer PAS2 does not cover the bank portion BNP, the bank portion BNP may prevent the ink from overflowing when the ink is applied.

[0150] In an embodiment, the second insulating layer PAS2 may have to The thickness TT2 of the second insulating layer PAS2 may be greater than the thickness TT1 of the first insulating layer PAS1. The sum of the respective thicknesses of the first insulating layer PAS1 and the second insulating layer PAS2 (TT1+TT2) may be to Preferably, the sum of the respective thicknesses of the first insulating layer PAS1 and the second insulating layer PAS2 (TT1+TT2) can be within the range of to Since the first insulating layer PAS1 and the second insulating layer PAS2 have a thickness within the above range, it is possible to prevent an increase in the total thickness of the insulating layer provided on the display element layer.

[0151] The second insulating layer PAS2 may be disposed under the light emitting element ED. In a region overlapping with the light emitting element ED, the second insulating layer PAS2 may directly contact the first insulating layer PAS1. Here, the region overlapping with the light emitting element ED may be disposed in the first opening OP1 of the bank layer BNL. In an embodiment, the lower surface of the second insulating layer PAS2 may directly contact the upper surface of the first insulating layer PAS1.

[0152] The second insulating layer PAS2 may form, together with the first insulating layer PAS1, in the sub-area SA, the first contact portion CT1 and the second contact portion CT2 that at least partially expose the first electrode RME1 and the second electrode RME2. The second insulating layer PAS2 may be disposed on the first insulating layer PAS1 in the pad area PDA. The second insulating layer PAS2 may be directly disposed on the first insulating layer PAS1 in the pad area PDA. The second insulating layer PAS2 may form, together with the first insulating layer PAS1 in the pad area PDA, a second pad contact hole CTP2 that exposes the second pad electrode PE2.

[0153] The second insulating layer PAS2 may include the same material as the first insulating layer PAS1. The second insulating layer PAS2 may include silicon oxide or silicon nitride. In an embodiment, the second insulating layer PAS2 may be made of silicon oxide so that the gas degassed from the via layer VIA can be released to the outside. However, the present disclosure is not limited thereto.

[0154] The light emitting element ED may be disposed in the emission area EMA. The light emitting element ED may not be disposed in the sub-area SA. As described above, since the bank layer BNL is formed to separate the emission area EMA and the sub-area SA of each sub-pixel SPXn, the ink in which the light emitting element ED is dispersed may be ejected only into the emission area EMA. Therefore, the light emitting element ED may be disposed in the emission area EMA, but not in the sub-area SA.

[0155] The light emitting element ED may be disposed between the first blocking portion BP1 and the second blocking portion BP2 of the bank layer BNL in the emission region EMA. In some embodiments, each of the light emitting elements ED may extend in a direction, and the direction along which each of the light emitting elements ED extends may be substantially perpendicular to the direction along which the first electrode RME1 and the second electrode RME2 extend. However, the present disclosure is not limited thereto, and the direction along which the light emitting element ED extends may also be inclined relative to the direction along which the first electrode RME1 and the second electrode RME2 extend. In a region where the first blocking portion BP1 and the second blocking portion BP2 are spaced apart to face each other, the light emitting element ED may be aligned so that at least one of the two ends is located on the first electrode RME1 or the second electrode RME2.

[0156] The light emitting elements ED may be disposed in the first opening OP1 of the bank layer BNL and may be spaced apart from each other. The light emitting elements ED may be spaced apart from each other in the first direction DR1 between the first blocking portion BP1 and the second blocking portion BP2. The light emitting elements ED may be arranged in a line between the first blocking portion BP1 and the second blocking portion BP2, and the light emitting elements ED adjacent to each other in the first direction DR1 may be separated by a random distance.

[0157] The light emitting element ED disposed in the sub-pixel SPXn may emit light of different wavelength bands according to the material forming the semiconductor layer to be described later. However, the present disclosure is not limited thereto, and the light emitting element ED disposed in the sub-pixel SPXn may also emit light of the same color by including a semiconductor layer made of the same material. The light emitting element ED may be electrically connected to the electrode RME and the conductive layer below the via layer VIA through the contact connection electrodes CNE (CNE1 and CNE2), and may emit light of a specific wavelength band in response to an electrical signal.

[0158] The connection electrode CNE may be disposed across the emission area EMA and the sub-area SA in the display area DPA. The connection electrode CNE may include a first connection electrode CNE1 and a second connection electrode CNE2. The first connection electrode CNE1 and the second connection electrode CNE2 may each extend in the first direction DR1 and may be spaced apart from each other in the second direction DR2.

[0159] The first connection electrode CNE1 may overlap the first electrode RME1 in the third direction DR3 in the emission area EMA and the sub-area SA of each pixel PX. The first connection electrode CNE1 may overlap the end of each light emitting element ED in the emission area EMA. The first connection electrode CNE1 may contact the first electrode RME1 through the first contact portion CT1 in the sub-area SA, and may contact the end of each light emitting element ED in the emission area EMA. Since the first connection electrode CNE1 contacts the end of each light emitting element ED and the first electrode RME1, the end of each light emitting element ED and the first electrode RME1 may be electrically connected through the first connection electrode CNE1.

[0160] The second connection electrode CNE2 may overlap the second electrode RME2 in the emission area EMA and the sub-area SA of each pixel PX in the third direction DR3. The second connection electrode CNE2 may overlap the other end of each light emitting element ED in the emission area EMA. The second connection electrode CNE2 may contact the second electrode RME2 in the sub-area SA through the second contact portion CT2, and may contact the other end of each light emitting element ED in the emission area EMA. Since the second connection electrode CNE2 contacts the other end of each light emitting element ED and the second electrode RME2, the other end of each light emitting element ED and the second electrode RME2 may be electrically connected through the second connection electrode CNE2.

[0161] Although the first and second connection electrodes CNE1 and CNE2 contact the first and second electrodes RME1 and RME2 respectively in the sub-area SA in the drawings, the present disclosure is not limited thereto. For example, the first and second connection electrodes CNE1 and CNE2 may also contact the first and second electrodes RME1 and RME2 respectively in the emission area EMA.

[0162] The third pad electrode PE3 may be disposed in the pad area PDA of the non-display area NDA. The third pad electrode PE3 may be disposed on the second insulating layer PAS2 in the pad area PDA. The third pad electrode PE3 may overlap the first pad electrode PE1 and the second pad electrode PE2 in the third direction DR3 in the pad area PDA.

[0163] The third pad electrode PE3 may be electrically connected to the second pad electrode PE2 by contacting the second pad electrode PE2 through a second pad contact hole CTP2 formed through the passivation layer PV, the first insulating layer PAS1, and the second insulating layer PAS2.

[0164] The first connection electrode CNE1, the second connection electrode CNE2, and the third pad electrode PE3 may include the same material and may be disposed at the same layer. The first connection electrode CNE1, the second connection electrode CNE2, and the third pad electrode PE3 may be formed by the same process. In other words, the first connection electrode CNE1, the second connection electrode CNE2, and the third pad electrode PE3 may be formed simultaneously by a single mask process. The first connection electrode CNE1, the second connection electrode CNE2, and the third pad electrode PE3 may include a conductive material. For example, the first connection electrode CNE1, the second connection electrode CNE2, and the third pad electrode PE3 may include ITO, IZO, ITZO, or aluminum (Al), etc.

[0165] Fig.11 is a schematic diagram of a light emitting element ED according to an embodiment.

[0166] Reference Fig.11 , the light emitting element ED may be a light emitting diode. Specifically, the light emitting element ED may be an inorganic light emitting diode having a size in the nanometer or micrometer range and made of an inorganic material. When an electric field is formed in a specific direction between two electrodes facing each other, the light emitting element ED may be aligned between the two electrodes in which polarity is formed.

[0167] The light emitting element ED according to the embodiment may extend in one direction. The light emitting element ED may be made in a shape like a cylinder, a rod, a wire, or a tube, etc. However, the shape of the light emitting element ED is not limited thereto, and the light emitting element ED may also have various shapes including a polygonal prism (such as a cube, a cuboid, or a hexagonal prism) and a shape extending in one direction and having a partially inclined outer surface.

[0168] The light emitting element ED may include a semiconductor layer doped with a dopant of any conductivity type (e.g., p-type or n-type). The semiconductor layer may receive an electrical signal from an external power source and emit light of a specific wavelength band. The light emitting element ED may include a first semiconductor layer 31, a second semiconductor layer 32, a light emitting layer 36, an electrode layer 37, and an insulating film 38.

[0169] The first semiconductor layer 31 may be an n-type semiconductor. The first semiconductor layer 31 may include Al x Ga y In 1-x-y The first semiconductor layer 31 may be a semiconductor material having a chemical formula of N (0≤x≤1, 0≤y≤1, 0≤x+y≤1). For example, the first semiconductor layer 31 may be any one or more of AlGaInN, GaN, AlGaN, InGaN, AlN and InN doped with an n-type dopant. The n-type dopant used to dope the first semiconductor layer 31 may be Si, Ge or Sn, etc.

[0170] The second semiconductor layer 32 is disposed on the first semiconductor layer 31, and the light emitting layer 36 is disposed between the second semiconductor layer 32 and the first semiconductor layer 31. The second semiconductor layer 32 may be a p-type semiconductor. The second semiconductor layer 32 may include Al x Ga y In 1-x-y The second semiconductor layer 32 may be a semiconductor material having a chemical formula of N (0≤x≤1, 0≤y≤1, 0≤x+y≤1). For example, the second semiconductor layer 32 may be any one or more of AlGaInN, GaN, AlGaN, InGaN, AlN, and InN doped with a p-type dopant. The p-type dopant used to dope the second semiconductor layer 32 may be Mg, Zn, Ca, Ba, or the like.

[0171] Although each of the first semiconductor layer 31 and the second semiconductor layer 32 is composed of one layer in the drawings, the present disclosure is not limited thereto. Each of the first semiconductor layer 31 and the second semiconductor layer 32 may also include more layers, for example, a cap layer or a tensile strain barrier reduction (TSBR) layer may be further included according to the material of the light emitting layer 36. For example, the light emitting element ED may also include another semiconductor layer disposed between the first semiconductor layer 31 and the light emitting layer 36 or between the second semiconductor layer 32 and the light emitting layer 36. The semiconductor layer disposed between the first semiconductor layer 31 and the light emitting layer 36 may be any one or more of AlGaInN, GaN, AlGaN, InGaN, AlN, InN, and SLs doped with an n-type dopant. The semiconductor layer disposed between the second semiconductor layer 32 and the light emitting layer 36 may be any one or more of AlGaInN, GaN, AlGaN, InGaN, AlN, and InN doped with a p-type dopant.

[0172] The light emitting layer 36 is disposed between the first semiconductor layer 31 and the second semiconductor layer 32. The light emitting layer 36 may include a material having a single quantum well structure or a multiple quantum well structure. When the light emitting layer 36 includes a material having a multiple quantum well structure, the light emitting layer 36 may have a structure in which a plurality of quantum layers and a plurality of well layers are alternately stacked. The light emitting layer 36 may emit light by recombination of electron-hole pairs according to an electrical signal received through the first semiconductor layer 31 and the second semiconductor layer 32. The light emitting layer 36 may include a material such as AlGaN, AlGaInN or InGaN. In particular, when the light emitting layer 36 has a multiple quantum well structure in which quantum layers and well layers are alternately stacked, the quantum layers may include a material such as AlGaN or AlGaInN, and the well layers may include a material such as GaN or AlInN.

[0173] The light emitting layer 36 may also have a structure in which a semiconductor material having a large energy band gap and a semiconductor material having a small energy band gap are alternately stacked, or may include different Group III to Group V semiconductor materials according to the wavelength band of the light emitted therefrom. The light emitted from the light emitting layer 36 is not limited to the light in the blue wavelength band. In some cases, the light emitting layer 36 may emit light in the red wavelength band or the green wavelength band.

[0174] The electrode layer 37 may be an ohmic connection electrode. However, the present disclosure is not limited thereto, and the electrode layer 37 may also be a Schottky connection electrode. The light emitting element ED may include at least one electrode layer 37. The light emitting element ED may include one or more electrode layers 37, but the present disclosure is not limited thereto, and the electrode layer 37 may also be omitted.

[0175] When the light emitting element ED is electrically connected to an electrode or a connecting electrode in the display device 10, the electrode layer 37 can reduce the resistance between the light emitting element ED and the electrode or the connecting electrode. The electrode layer 37 may include a conductive metal. For example, the electrode layer 37 may include at least any one of aluminum (Al), titanium (Ti), indium (In), gold (Au), silver (Ag), indium tin oxide (ITO), indium zinc oxide (IZO), and indium tin zinc oxide (ITZO).

[0176] The insulating film 38 surrounds the outer surfaces of the semiconductor layer and the electrode layer. For example, the insulating film 38 may surround at least the outer surface of the light emitting layer 36, but may expose both ends of the light emitting element ED in the longitudinal direction. In addition, the cross section of the upper surface of the insulating film 38 in the region adjacent to at least one end of the light emitting element ED may be circular.

[0177] The insulating film 38 may include an insulating material, for example, silicon oxide (SiO x) 、Silicon Nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum nitride (AlN x ), aluminum oxide (AlO x )、ZrO x ), hafnium oxide (HfO x ) and titanium oxide (TiO x ). Although the insulating film 38 is shown as a single layer in the drawings, the present disclosure is not limited thereto. In some embodiments, the insulating film 38 may be formed in a multilayer structure in which a plurality of layers are stacked.

[0178] The insulating film 38 can protect the semiconductor layer and the electrode layer of the light emitting element ED. When the light emitting layer 36 directly contacts the electrode that transmits the electrical signal to the light emitting element ED, the insulating film 38 can prevent an electrical short circuit that may occur in the light emitting layer 36. In addition, the insulating film 38 can prevent the light emitting efficiency of the light emitting element ED from being reduced.

[0179] In addition, the outer surface of the insulating film 38 may be processed. The light emitting element ED may be ejected onto the electrode in a state where it is dispersed in a predetermined ink, and then may be aligned. Here, the surface of the insulating film 38 may be hydrophobically treated or hydrophilically treated so that the light emitting element ED remains separated in the ink without agglomerating with other adjacent light emitting elements ED.

[0180] A method of manufacturing the above-described display device 10 will now be described with reference to other drawings.

[0181] Figures 12 to 22 are cross-sectional views sequentially showing a process of manufacturing the display device 10 according to the embodiment. Figures 12 to 22The process of manufacturing the display device 10 shown in FIG. Figure 4 The display device 10 corresponds to.

[0182] Reference Figures 12 to 22 The method of manufacturing the display device 10 according to the embodiment may include forming a first conductive layer 100, forming a buffer layer BL, forming a semiconductor layer 200, forming a gate insulating layer GI and a second conductive layer 300, forming a passivation layer PV, forming a via layer VIA, forming an electrode RME, forming a first insulating layer PAS1, forming a bank layer BNL, forming a second insulating layer PAS2, aligning a light emitting element ED, and forming a connection electrode CNE. The above operations will now be described sequentially.

[0183] First, refer to Fig.12 , prepare a substrate SUB, and form a first conductive layer 100 on the substrate SUB. The first conductive layer 100 may be formed by depositing a conductive material and performing a patterning process using a mask. For example, a first conductive material layer may be deposited on the entire surface of the substrate SUB, and then the first conductive material layer may be patterned by a photolithography process to form a Fig.12 The first conductive layer 100 is illustrated in FIG. The first conductive layer 100 may include a first voltage wiring VL1, a second voltage wiring VL2, and a bottom metal layer CAS disposed in the display area DPA, and may include a first pad electrode PE1 disposed in the pad area PDA.

[0184] Next, refer to Fig.13 , a buffer layer BL is formed on the entire surface of the substrate SUB on which the first conductive layer 100 is formed, and a semiconductor layer 200 is formed on the buffer layer BL. The buffer layer BL may completely cover the first conductive layer 100. Specifically, the buffer layer BL may completely cover the first voltage wiring VL1, the second voltage wiring VL2, and the bottom metal layer CAS provided in the display area DPA and the first pad electrode PE1 provided in the pad area PDA. The semiconductor layer 200 may be formed by a mask process. For example, a semiconductor material may be deposited on the entire surface of the buffer layer BL, and then the semiconductor material may be patterned by a photolithography process to form a semiconductor layer 200 such as the semiconductor layer 200 of FIG. 1 . Fig.13 The semiconductor layer 200 is shown in FIG. The semiconductor layer 200 may include an active layer ACT of a transistor.

[0185] Next, refer to Fig.14 and Fig.15 A gate insulating layer GI and a second conductive layer 300 are formed on the buffer layer BL on which the semiconductor layer 200 is formed.

[0186] Specifically, a gate insulating material layer GI' that completely covers the semiconductor layer 200 is formed on the buffer layer BL on which the semiconductor layer 200 is formed. Then, a first contact hole CNT1 and a second contact hole CNT2 that expose a portion of the semiconductor layer 200, a third contact hole CNT3 that exposes a portion of the bottom metal layer CAS that is the first conductive layer 100, and a fourth contact hole CNT4 and a fifth contact hole CNT5 that expose the first voltage wiring VL1 and the second voltage wiring VL2, respectively, are formed. In addition, a first pad contact hole CTP1 that exposes a portion of the first pad electrode PE1 that is the first conductive layer 100 is formed. The first contact hole CNT1 and the second contact hole CNT2 that expose a portion of the semiconductor layer 200 may penetrate the gate insulating material layer GI', and the third contact hole CNT3, the fourth contact hole CNT4, the fifth contact hole CNT5, and the first pad contact hole CTP1 that expose a portion of the first conductive layer 100 may penetrate the gate insulating material layer GI' and the buffer layer BL. The first contact hole CNT1 , the second contact hole CNT2 , the third contact hole CNT3 , the fourth contact hole CNT4 , the fifth contact hole CNT5 , and the first pad contact hole CTP1 may be formed through a single mask process.

[0187] Next, if Fig.15 As shown in the figure, a patterned gate insulating layer GI and a second conductive layer 300 are formed on the buffer layer BL. The patterned gate insulating layer GI and the second conductive layer 300 can be formed by a single mask process. Specifically, a second conductive material layer is deposited on the entire surface of the gate insulating material layer GI'. Then, a photoresist layer is applied on the second conductive material layer, and a photoresist pattern is formed by exposure and development. Next, the second conductive material layer and the gate insulating material layer GI' are all etched at one time using the photoresist pattern as an etching mask to form the second conductive layer 300 and the gate insulating layer GI. Since the second conductive material layer and the gate insulating material layer GI' are all etched at one time, the lateral sides of the second conductive layer 300 and the lateral sides of the gate insulating layer GI can be aligned with each other. Subsequently, a process of removing the photoresist pattern can be performed separately. The second conductive layer 300 may include a gate electrode GE, a drain electrode DE, a source electrode SE, a first conductive pattern CDP1, and a second pad electrode PE2.

[0188] The source electrode SE electrically connects the active layer ACT and the bottom metal layer CAS through the first contact hole CNT1 and the third contact hole CNT3. The drain electrode DE electrically connects the active layer ACT and the first voltage wiring VL1 through the second contact hole CNT2 and the fourth contact hole CNT4. The first conductive pattern CDP1 is electrically connected to the second voltage wiring VL2 through the fifth contact hole CNT5. The second pad electrode PE2 is electrically connected to the first pad electrode PE1 through the first pad contact hole CTP1.

[0189] Next, refer to Fig.16 A passivation layer PV is formed on the substrate SUB on which the second conductive layer 300 and the buffer layer BL are formed. The passivation layer PV may be disposed throughout the display area DPA and the non-display area NDA, and may completely cover the second conductive layer 300. In addition, the passivation layer PV may directly contact portions of the active layer ACT exposed by the first contact hole CNT1 and the second contact hole CNT2.

[0190] Next, refer to Fig.17 , a via layer VIA is formed on the substrate SUB on which the passivation layer PV is formed. The via layer VIA may be disposed in the display area DPA, but may not be disposed in the pad area PDA. The via layer VIA may be etched by a mask process to form a first electrode contact hole CTD overlapping the source electrode SE and a second electrode contact hole CTS overlapping the first conductive pattern CDP1 in the display area DPA. In addition, the via layer VIA may be etched by the above-mentioned mask process to expose the passivation layer PV formed in the pad area PDA of the non-display area NDA.

[0191] Next, the passivation layer PV exposed by the first electrode contact hole CTD and the second electrode contact hole CTS is etched using the patterned via layer VIA as a mask. Therefore, the via layer VIA and the passivation layer PV may form the first electrode contact hole CTD and the second electrode contact hole CTS together to expose the source electrode SE and the first conductive pattern CDP1. Therefore, in the process of etching the passivation layer PV to form the first electrode contact hole CTD and the second electrode contact hole CTS, a separate mask process may not be required.

[0192] When the via layer VIA is removed from the pad area PDA, the passivation layer PV disposed on the second pad electrode PE2 may be exposed. When the via layer VIA is removed from the pad area PDA, the second pad electrode PE2 may be covered by the passivation layer PV and thus may not be exposed to the outside. Therefore, an etchant for etching the electrode RME, which will be described later, may not penetrate into the second pad electrode PE2. This may prevent the second pad electrode PE2 from being etched.

[0193] Next, refer to Fig.18 , an electrode RME is formed on the via layer VIA. The electrode RME may be formed by a mask process.

[0194] Specifically, in the process of forming the electrode RME, an electrode material layer may be deposited throughout the display area DPA and the pad area PDA, and then the electrode material layer may be patterned by a photolithography process to form a Fig.18In some embodiments, the patterning of the electrode RME may be performed by wet etching using an etchant. In this case, the passivation layer PV disposed on the second pad electrode PE2 in the pad area PDA may prevent the etchant from penetrating into the second pad electrode PE2, thereby preventing the second pad electrode PE2 from being etched.

[0195] The electrode RME may include a first electrode RME1 and a second electrode RME2. In the display area DPA, the first electrode RME1 may be deposited inside the first electrode contact hole CTD and may be electrically connected to the source electrode SE by contacting the source electrode SE, and the second electrode RME2 may be deposited inside the second electrode contact hole CTS and may be electrically connected to the first conductive pattern CDP1 by contacting the first conductive pattern CDP1.

[0196] Next, refer to Fig.19 , a first insulating layer PAS1 is formed on the substrate SUB on which the electrode RME is formed. Since the first insulating layer PAS1 is formed in the entire display area DPA and the non-display area NDA, the first insulating layer PAS1 may be formed in the pad area PDA as well as in the display area DPA. Therefore, the first insulating layer PAS1 may be disposed on the passivation layer PV disposed on the second pad electrode PE2 disposed in the pad area PDA. As will be described later, the first insulating layer PAS1 may be formed as to The first insulating layer PAS1 may be formed to have a thickness of 1000 to 1000 mm / s so as to protect the electrode RME from the developer of the bank layer BNL and to release the gas degassed from the via layer VIA to the outside. For example, the first insulating layer PAS1 may be formed to have a thickness of 1000 to 1000 mm / s. In addition, the first insulating layer PAS1 may be made of, for example, silicon oxide so that gas can be released.

[0197] Next, refer to Fig. 20 A bank layer BNL is formed on the substrate SUB on which the first insulating layer PAS1 is formed. The bank layer BNL is disposed in the display area DPA and is not disposed in the non-display area NDA. The bank layer BNL is formed into blocking portions BP1 and BP2 and a bank portion BNP through a single mask process.

[0198] Specifically, a dyke material layer is applied on a substrate SUB on which a first insulating layer PAS1 is formed, and a half-tone mask including a transmission area through which light is completely transmitted, a blocking area in which light is blocked, and a semi-transmissive reflection area for controlling the amount of light transmission is aligned. Next, light is irradiated toward the dyke material layer from above the half-tone mask, and then the dyke material layer is developed using a developer to form a dyke layer BNL. Here, a portion of the dyke material layer corresponding to the transmission area is completely removed, and a portion of the dyke material layer corresponding to the blocking area remains intact to form a dyke portion BNP. A portion of the dyke material layer corresponding to the semi-transmissive reflection area is formed as blocking portions BP1 and BP2 having a height lower than that of the dyke portion BNP. In addition, the completely removed portion of the dyke material layer is formed as a first opening OP1 and a second opening OP2.

[0199] In the process of developing the bank material layer, a developer such as TMAH may be used. When the electrode RME is exposed to the developer, electrochemical corrosion may occur, resulting in lifting or breaking. In an embodiment, a first insulating layer PAS1 is formed to completely cover the electrode RME, and a bank layer BNL is formed on the first insulating layer PAS1. Therefore, the developer can be prevented from reaching the electrode RME, thereby preventing the electrode RME from lifting or breaking.

[0200] Next, refer to Fig.21 , a second insulating layer PAS2 is formed on the substrate SUB on which the bank layer BNL is formed. The second insulating layer PAS2 may be formed by a mask process. Specifically, a second insulating material layer may be deposited on the entire surface of the first insulating layer PAS1 on which the bank layer BNL is formed, and then the second insulating material layer may be etched by a photolithography process to form a substrate SUB. Fig.21 The patterned second insulating layer PAS2 is shown in FIG.

[0201] The patterned second insulating layer PAS2 may not overlap the bank portion BNP of the bank layer BNL in the display area DPA, and may overlap the blocking portions BP1 and BP2 of the bank layer BNL. In addition, the second insulating layer PAS2 may be directly disposed on the first insulating layer PAS1 exposed by the first opening OP1 between the blocking portions BP1 and BP2, and may be directly disposed on the first insulating layer PAS1 exposed by the second opening OP2.

[0202] In the above mask process, the second insulating layer PAS2 and the first insulating layer PAS1 may be etched simultaneously to form a first contact portion CT1 and a second contact portion CT2 penetrating the second insulating layer PAS2 and the first insulating layer PAS1 and to form a second pad contact hole CTP2 penetrating the first insulating layer PAS1, the second insulating layer PAS2 and the passivation layer PV in the pad area PDA. Therefore, the first electrode RME1 is exposed by the first contact portion CT1, the second electrode RME2 is exposed by the second contact portion CT2, and the second pad electrode PE2 is exposed by the second pad contact hole CTP2.

[0203] Next, refer to Fig. 22 A plurality of light emitting elements ED are aligned in the first opening OP1 formed between the first and second blocking portions BP1 and BP2. The light emitting elements ED may be placed on the second insulating layer PAS2 located in the first opening OP1 between the first and second blocking portions BP1 and BP2 through an inkjet printing process.

[0204] Specifically, ink in which the light emitting elements ED are dispersed may be ejected to the emission area EMA defined by the bank layer BNL (see FIG. Figure 5 ). Then, the alignment signal may be transmitted to the first electrode RME1 and the second electrode RME2. In this case, the alignment signal may change the position and orientation direction of the light emitting element ED in the ink, thereby placing the light emitting element ED on the second insulating layer PAS2 between the first electrode RME1 and the second electrode RME2.

[0205] Next, a connection electrode material layer is stacked on the second insulating layer PAS2 on which the light emitting element ED and the bank layer BNL are formed, and then the connection electrode material layer is patterned by a photolithography process to form a first connection electrode CNE1 and a second connection electrode CNE2 in the display area DPA, and a third pad electrode PE3 is formed in the pad area PDA. The first connection electrode CNE1 is electrically connected to the first electrode RME1 through the first contact portion CT1, and the second connection electrode CNE2 is electrically connected to the second electrode RME2 through the second contact portion CT2. The third pad electrode PE3 is electrically connected to the second pad electrode PE2 through the second pad contact hole CTP2. Thus, the display device according to the present invention can be manufactured. Figure 5 A display device 10 of an embodiment.

[0206] As described above, in the method of manufacturing the display device 10 according to the embodiment, the first insulating layer PAS1 completely covering the electrode RME is formed, and the bank layer BNL is formed on the first insulating layer PAS1. Therefore, it is possible to prevent the developer from reaching the electrode RME, thereby preventing the electrode RME from being lifted or broken.

[0207] Hereinafter, another embodiment of the display device 10 according to the embodiment will be described. In the following embodiment, the same elements as those of the previously described embodiment are represented by the same reference numerals. In addition, any repeated description will be omitted or briefly given, and the differences will be mainly described.

[0208] Fig.23 is a cross-sectional view of a sub-pixel and a pad portion of a display device according to an embodiment.

[0209] Reference Fig.23 , the current embodiment and Figure 5 The difference of the above embodiment is that the second conductive layer includes a gate electrode, and a third conductive layer including a source electrode, a drain electrode, a first conductive pattern, and a second pad electrode is formed.

[0210] A first conductive layer 100 including a bottom metal layer CAS, a first voltage wiring VL1, a second voltage wiring VL2, and a first pad electrode PE1 is disposed on a substrate SUB. A buffer layer BL is disposed on the first conductive layer 100, and a semiconductor layer 200 including an active layer ACT is disposed on the buffer layer BL. A gate insulating layer GI is disposed on the semiconductor layer 200, and a second conductive layer 300 is disposed on the gate insulating layer GI. The second conductive layer 300 may include a gate electrode GE. Respective side surfaces of the gate electrode GE and the gate insulating layer GI may be aligned with each other.

[0211] An interlayer insulating layer IL covering the second conductive layer 300 is disposed on the second conductive layer 300. The interlayer insulating layer IL may be disposed in the display area DPA and the pad area PDA. The interlayer insulating layer IL may be formed to include an inorganic material (eg, silicon oxide (SiO x ), Silicon Nitride (SiN x ) and silicon oxynitride (SiO x N y )) is a multilayer of inorganic layers alternately stacked.

[0212] In the display area DPA, a first contact hole CNT1 and a second contact hole CNT2 penetrating the interlayer insulating layer IL to expose a portion of the active layer ACT may be provided, and a third contact hole CNT3 penetrating the interlayer insulating layer IL and the buffer layer BL to expose the bottom metal layer CAS may be provided. In addition, a fourth contact hole CNT4 penetrating the interlayer insulating layer IL and the buffer layer BL to expose the first voltage wiring VL1 and a fifth contact hole CNT5 penetrating the interlayer insulating layer IL and the buffer layer BL to expose the second voltage wiring VL2 may be provided. In the pad area PDA, a first pad contact hole CTP1 penetrating the interlayer insulating layer IL and the buffer layer BL to expose the first pad electrode PE1 may be provided.

[0213] The third conductive layer 400 may be disposed on the interlayer insulating layer IL. The third conductive layer 400 may include a source electrode SE, a drain electrode DE, a first conductive pattern CDP1, and a second pad electrode PE2. The source electrode SE may electrically connect the active layer ACT and the bottom metal layer CAS through the first contact hole CNT1 and the third contact hole CNT3, and the drain electrode DE may electrically connect the active layer ACT and the first voltage wiring VL1 through the second contact hole CNT2 and the fourth contact hole CNT4. The first conductive pattern CDP1 may be electrically connected to the second voltage wiring VL2 through the fifth contact hole CNT5, and the second pad electrode PE2 may be electrically connected to the first pad electrode PE1 through the first pad contact hole CTP1. A passivation layer PV covering the third conductive layer 400 may be disposed on the third conductive layer 400, and a display element layer including a via layer VIA may be disposed.

[0214] In the current embodiment, the second conductive layer 300 includes the gate electrode GE, and the third conductive layer 400 includes the source electrode SE, the drain electrode DE, the first conductive pattern CDP1, and the second pad electrode PE2. Figures 5 to 22 The above-described embodiments are also applicable to circuit element layers having different structures.

[0215] At the end of the detailed description, it will be appreciated by those skilled in the art that many changes and modifications may be made to the preferred embodiment without departing substantially from the principles of the present invention. Therefore, the preferred embodiments of the present invention disclosed are intended for general and descriptive purposes only and not for limiting purposes.

Claims

1. A display device, comprising: substrate; A via layer is disposed on the substrate; A first electrode and a second electrode are disposed on the via layer and are spaced apart from each other; A first insulating layer is disposed on the first electrode and the second electrode; a bank layer disposed on the first insulating layer and including a barrier portion and a bank portion having a thickness greater than that of the barrier portion; a second insulating layer, disposed on the bank layer and the first insulating layer; A light emitting element is disposed on the second insulating layer and on the first electrode and the second electrode; as well as a first connection electrode and a second connection electrode, wherein the first connection electrode contacts one end of each light emitting element and the second connection electrode contacts the other end of each light emitting element; The second insulating layer overlaps the blocking portion and does not overlap the bank portion.

2. The display device according to claim 1, wherein: The first insulating layer is directly disposed on the via layer, the first electrode and the second electrode.

3. The display device according to claim 1, wherein: The thickness of the first insulating layer is smaller than the thickness of the second insulating layer.

4. The display device according to claim 3, wherein: The thickness of the first insulating layer is in a range of 30% to 70% of the thickness of the second insulating layer.

5. The display device according to claim 3, wherein: The thickness of the first insulating layer is to 6. The display device according to claim 1, wherein: The first insulating layer and the second insulating layer are in contact with each other in a region overlapping the light emitting element.

7. The display device according to claim 1, wherein: The first insulating layer and the second insulating layer include the same material.

8. The display device according to claim 1, wherein: The blocking portion includes a first blocking portion overlapping the first electrode and a second blocking portion spaced apart from the first blocking portion and overlapping the second electrode, and The bank portion surrounds the first blocking portion and the second blocking portion.

9. The display device according to claim 8, wherein: The bank layer includes a first opening disposed between the first barrier portion and the second barrier portion, and The light emitting element is disposed in the first opening.

10. The display device according to claim 9, wherein: The bank layer separates an emission region in which the light emitting element is disposed and a sub-region spaced apart from the emission region, and the bank layer includes a second opening spaced apart from the first opening, Wherein, the first opening is arranged in the emission region, and the second opening is arranged in the sub-region.

11. A display device, comprising: substrate; A via layer is disposed on the substrate; A first electrode and a second electrode are disposed on the via layer and are spaced apart from each other; A first insulating layer, disposed on the via layer, the first electrode and the second electrode; a bank layer disposed on the first insulating layer and separating an emission region and a sub-region spaced apart from the emission region; a second insulating layer, disposed on the bank layer and the first insulating layer; a light emitting element disposed on the second insulating layer in the emission region and disposed on the first electrode and the second electrode; as well as a first connection electrode and a second connection electrode, wherein the first connection electrode contacts one end of each light emitting element and the second connection electrode contacts the other end of each light emitting element; The second insulating layer does not overlap with any region other than the emission region and the sub-region.

12. The display device according to claim 11, wherein: the bank layer includes a barrier portion and a bank portion having a thickness greater than that of the barrier portion, The blocking portion overlaps the emission region, and the dam portion does not overlap the emission region and the sub-region.

13. The display device according to claim 12, wherein: The second insulating layer does not overlap the bank portion but overlaps the barrier portion.

14. The display device according to claim 12, wherein: The first insulating layer overlaps the bank portion and the barrier portion.

15. The display device according to claim 12, wherein: The blocking portion and the bank portion are integrally formed.

16. The display device according to claim 11, wherein: The first insulating layer and the second insulating layer are in contact with each other in a region overlapping the light emitting element.

17. The display device according to claim 11, further comprising: A first contact portion and a second contact portion penetrate the first insulating layer and the second insulating layer and are arranged in the sub-region to be spaced apart from each other, The first connection electrode is connected to the first electrode through the first contact portion, and the second connection electrode is connected to the second electrode through the second contact portion.

18. The display device according to claim 11, further comprising: a first conductive layer disposed on the substrate and comprising a bottom metal layer, a first power line, a second power line, and a first pad electrode; a semiconductor layer disposed on the first conductive layer and comprising an active layer stacked with the bottom metal layer; a second conductive layer disposed on the semiconductor layer and including a source electrode contacting a portion of the semiconductor layer, a drain electrode contacting the first power line, a gate electrode overlapping the semiconductor layer, a first conductive pattern contacting the second power line, and a second pad electrode overlapping the first pad electrode; as well as The third pad electrode is arranged on the second pad electrode.

19. The display device according to claim 18, wherein: The first electrode is electrically connected to the first power line through the source electrode, and the second electrode is electrically connected to the second power line through the first conductive pattern.

20. The display device according to claim 18, wherein: The first connection electrode, the second connection electrode, and the third pad electrode include the same material.

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