Low-power-consumption circuit of power management chip

Abstract

The invention relates to the technical field of power supply control, and discloses a low power consumption circuit of a power supply management chip, which comprises a first operational amplifier, a third operational amplifier, a seventh trigger, a sixth resistor, a twelfth resistor, a fifteenth resistor, an eighteenth resistor, a first voltage stabilizing diode, a first switch, a first connector and a second connector, the in-phase end of the first operational amplifier is connected with one end of the first switch, the in-phase end of the third operational amplifier and one end of the fifteenth resistor, the other end of the first switch is connected with the end of the second connector, the anti-phase end of the first operational amplifier is connected with one end of the twelfth resistor, and the output end of the first operational amplifier is connected with the other end of the twelfth resistor. The inverting end of the third operational amplifier is connected with one end of a sixth resistor, the output end of the third operational amplifier is connected with the cathode of the first voltage stabilizing diode and the other end of the sixth resistor, a first pin and a fourth pin of a seventh trigger are connected with a power supply, and a third pin of the seventh trigger is connected with a first connector end.

Description

Technical Field

[0001] The present invention relates to the technical field of power supply control, and in particular to a low power consumption circuit of a power supply management chip. Background Art

[0002] In many applications, the power consumption of electronic devices is very demanding. For example, some sensor information acquisition devices are powered by only a small battery and are required to work for several years. In order to ensure the normal operation of the equipment and minimize the power consumption of the equipment, the existing methods of reducing power consumption are to put some functional chips inside the device into sleep mode at a specific time to reduce the power consumption of the entire device. The functional chip will still receive a power signal when it is in sleep mode to ensure that it can be awakened at any time. Therefore, a low-power circuit of a power management chip is proposed. When the functional chip is in sleep mode, the power supply signal of the chip can be reduced to further reduce the power consumption of the entire device. The reference signal can be positively compensated to prevent the chip from being affected by instantaneous interference caused by power fluctuations or the startup of other devices in sleep mode. The circuit can perform low-power adjustment on all functional chips through difference compensation to achieve power consumption management of all functional chips in the device. Summary of the invention

[0003] In view of the above technical problems, the object of the present invention is to provide a low power consumption circuit of a power management chip, including a first operational amplifier U1, a third operational amplifier U3, a seventh trigger U7, a sixth resistor R6, a twelfth resistor R12, a fifteenth resistor R15, an eighteenth resistor R18, a first voltage zener diode D1, a first switch S1, a first connector P1, and a second connector P2; The in-phase end of the first operational amplifier U1 is connected to one end of the first switch S1, the in-phase end of the third operational amplifier U3, and one end of the fifteenth resistor R15, the other end of the first switch S1 is connected to the second connector P2, the inverting end of the first operational amplifier U1 is connected to one end of the twelfth resistor R12, the output end of the first operational amplifier U1 is connected to the other end of the twelfth resistor R12, the inverting end of the third operational amplifier U3 is connected to one end of the sixth resistor R6, the output end of the third operational amplifier U3 is connected to the cathode of the first voltage regulator diode D1 and the other end of the sixth resistor R6, the first pin of the seventh trigger U7, the fourth pin of the seventh trigger U7 are connected to the cathode of the first voltage regulator diode D1 and the other end of the sixth resistor R6, and the first pin of the seventh trigger U7 is connected to the fourth pin of the seventh trigger U7. The pin of the seventh trigger U7 is connected to the power supply, the third pin of the seventh trigger U7 is connected to the end of the first connector P1, the second pin and the sixth pin of the seventh trigger U7 are connected to one end of the eighteenth resistor R18, the fifth pin of the seventh trigger U7 is connected to the positive electrode of the first switch S1, the first pin of the seventh trigger U7 is the reset end, the second pin is the data input end, the third pin is the clock input end, the fourth pin is the set end, the fifth pin and the sixth pin are the signal output ends, the other end of the fifteenth resistor R15, the other end of the eighteenth resistor R18, the anode of the first voltage regulator diode D1, the cathode of the first switch S1 and the ground end are connected.

[0004] Furthermore, it also includes a second operational amplifier U2, a sixth operational amplifier U6, a first resistor R1, a second resistor R2, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a thirteenth resistor R13, a fourteenth resistor R14, and a third connector P3; The non-inverting end of the second operational amplifier U2 is connected to one end of the first resistor R1 and one end of the ninth resistor R9, the inverting end of the second operational amplifier U2 is connected to one end of the second resistor R2 and one end of the thirteenth resistor R13, the output end of the second operational amplifier U2 is connected to the other end of the second resistor R2 and the inverting end of the sixth operational amplifier U6, the non-inverting end of the sixth operational amplifier U6 is connected to the output end of the first operational amplifier U1, the output end of the sixth operational amplifier U6 is connected to one end of the fourteenth resistor R14 and the end of the third connector P3, the other end of the ninth resistor R9 is connected to the cathode of the first voltage zener diode D1, one end of the eleventh resistor R11 is connected to the power supply, the other end of the eleventh resistor R11 is connected to the other end of the first resistor R1 and one end of the tenth resistor R10, the other end of the tenth resistor R10, the other end of the thirteenth resistor R13, and the other end of the fourteenth resistor R14 are connected to the ground.

[0005] Furthermore, it also includes a fourth coupling module U4, a first transistor Q1, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a seventh resistor R7, and a second diode D2; The anode of the fourth coupling module U4 is connected to one end of the fourth resistor R4, the collector of the fourth coupling module U4 is connected to one end of the fifth resistor R5 and the anode of the second diode D2, the emitter of the fourth coupling module U4 is connected to one end of the seventh resistor R7, the collector of the first triode Q1 is connected to one end of the third resistor R3, the emitter of the first triode Q1 is connected to the other end of the fourth resistor R4, the base of the first triode Q1 is connected to the other end of the ninth resistor R9, the other end of the third resistor R3 and the other end of the fifth resistor R5 are connected to the power supply, and the cathode of the fourth coupling module U4 and the other end of the seventh resistor R7 are connected to the ground.

[0006] Furthermore, it also includes a fifth operational amplifier U5, a second field effect transistor Q2, an eighth resistor R8, a seventeenth resistor R17, and a fourth connector P4; The in-phase end of the fifth operational amplifier U5 is connected to the cathode of the second diode D2 and one end of the eighth resistor R8, the inverting end of the fifth operational amplifier U5 is connected to one end of the seventh resistor R7, the output end of the fifth operational amplifier U5 is connected to the drain of the second field effect transistor Q2, the gate of the second field effect transistor Q2 is connected to the fifth pin of the seventh trigger U7, the source of the second field effect transistor Q2 is connected to one end of the seventeenth resistor R17 and the end of the fourth connector P4, and the other end of the eighth resistor R8, the other end of the seventeenth resistor R17 and the ground are connected.

[0007] Furthermore, it also includes a nineteenth resistor R19, a twentieth resistor R20, a second switch S2, a third switch S3, a fifth connector P5, and a sixth connector P6; One end of the second switch S2 is connected to the in-phase end of the second operational amplifier U2, the other end of the second switch S2 is connected to one end of the twentieth resistor R20, the positive electrode of the second switch S2 is connected to the positive electrode of the third switch S3 and the end of the sixth connector P6, one end of the third switch S3 is connected to the inverting end of the second operational amplifier U2, the other end of the third switch S3 is connected to one end of the nineteenth resistor R19, the other end of the twentieth resistor R20 is connected to the end of the fifth connector P5, the negative electrode of the second switch S2, the negative electrode of the third switch S3, and the other end of the nineteenth resistor R19 are connected to the ground end.

[0008] Furthermore, it also includes a sixteenth resistor R16; One end of the sixteenth resistor R16 is connected to the gate of the second field effect transistor Q2, and the other end of the sixteenth resistor R16 is connected to the ground.

[0009] Furthermore, the tenth resistor R10 is an adjustable resistor.

[0010] The beneficial effects of the present invention compared with the prior art are: The present invention can further reduce the power consumption of the functional chip when the chip is in sleep mode, can prevent the chip from being affected by instantaneous interference caused by power supply fluctuations or the moment other devices start up in sleep mode by forward compensation of the reference signal, and can enable the circuit to perform low-power adjustment on all functional chips by difference compensation, thereby realizing power consumption management of all functional chips in the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the prior art and the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0012] Figure 1 This is a circuit structure diagram provided by the present invention. DETAILED DESCRIPTION

[0013] In order to make the objects and advantages of the present invention more clearly understood, the present invention is specifically described below in conjunction with embodiments. It should be understood that the following text is only used to describe one or several specific implementations of the present invention, and does not strictly limit the scope of protection specifically requested by the present invention.

[0014] The present invention discloses a low-power consumption circuit of a power management chip, comprising a first operational amplifier U1, a third operational amplifier U3, a seventh trigger U7, a sixth resistor R6, a twelfth resistor R12, a fifteenth resistor R15, an eighteenth resistor R18, a first voltage stabilizing diode D1, a first switch S1, a first connector P1, and a second connector P2; The in-phase end of the first operational amplifier U1 is connected to one end of the first switch S1, the in-phase end of the third operational amplifier U3, and one end of the fifteenth resistor R15, the other end of the first switch S1 is connected to the second connector P2, the inverting end of the first operational amplifier U1 is connected to one end of the twelfth resistor R12, the output end of the first operational amplifier U1 is connected to the other end of the twelfth resistor R12, the inverting end of the third operational amplifier U3 is connected to one end of the sixth resistor R6, the output end of the third operational amplifier U3 is connected to the cathode of the first voltage regulator diode D1 and the other end of the sixth resistor R6, the first pin of the seventh trigger U7, the fourth pin of the seventh trigger U7 are connected to the cathode of the first voltage regulator diode D1 and the other end of the sixth resistor R6, and the first pin of the seventh trigger U7 is connected to the fourth pin of the seventh trigger U7. The pin of the seventh trigger U7 is connected to the power supply, the third pin of the seventh trigger U7 is connected to the end of the first connector P1, the second pin and the sixth pin of the seventh trigger U7 are connected to one end of the eighteenth resistor R18, the fifth pin of the seventh trigger U7 is connected to the positive electrode of the first switch S1, the first pin of the seventh trigger U7 is the reset end, the second pin is the data input end, the third pin is the clock input end, the fourth pin is the set end, the fifth pin and the sixth pin are the signal output ends, the other end of the fifteenth resistor R15, the other end of the eighteenth resistor R18, the anode of the first voltage regulator diode D1, the cathode of the first switch S1 and the ground end are connected.

[0015] like Figure 1 As shown, specifically, it also includes a second operational amplifier U2, a sixth operational amplifier U6, a first resistor R1, a second resistor R2, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a thirteenth resistor R13, a fourteenth resistor R14, and a third connector P3; The non-inverting end of the second operational amplifier U2 is connected to one end of the first resistor R1 and one end of the ninth resistor R9, the inverting end of the second operational amplifier U2 is connected to one end of the second resistor R2 and one end of the thirteenth resistor R13, the output end of the second operational amplifier U2 is connected to the other end of the second resistor R2 and the inverting end of the sixth operational amplifier U6, the non-inverting end of the sixth operational amplifier U6 is connected to the output end of the first operational amplifier U1, the output end of the sixth operational amplifier U6 is connected to one end of the fourteenth resistor R14 and the end of the third connector P3, the other end of the ninth resistor R9 is connected to the cathode of the first voltage zener diode D1, one end of the eleventh resistor R11 is connected to the power supply, the other end of the eleventh resistor R11 is connected to the other end of the first resistor R1 and one end of the tenth resistor R10, the other end of the tenth resistor R10, the other end of the thirteenth resistor R13, and the other end of the fourteenth resistor R14 are connected to the ground.

[0016] like Figure 1 As shown, specifically, it also includes a fourth coupling module U4, a first transistor Q1, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a seventh resistor R7, and a second diode D2; The anode of the fourth coupling module U4 is connected to one end of the fourth resistor R4, the collector of the fourth coupling module U4 is connected to one end of the fifth resistor R5 and the anode of the second diode D2, the emitter of the fourth coupling module U4 is connected to one end of the seventh resistor R7, the collector of the first triode Q1 is connected to one end of the third resistor R3, the emitter of the first triode Q1 is connected to the other end of the fourth resistor R4, the base of the first triode Q1 is connected to the other end of the ninth resistor R9, the other end of the third resistor R3 and the other end of the fifth resistor R5 are connected to the power supply, and the cathode of the fourth coupling module U4 and the other end of the seventh resistor R7 are connected to the ground.

[0017] like Figure 1 As shown, specifically, it also includes a fifth operational amplifier U5, a second field effect transistor Q2, an eighth resistor R8, a seventeenth resistor R17, and a fourth connector P4; The in-phase end of the fifth operational amplifier U5 is connected to the cathode of the second diode D2 and one end of the eighth resistor R8, the inverting end of the fifth operational amplifier U5 is connected to one end of the seventh resistor R7, the output end of the fifth operational amplifier U5 is connected to the drain of the second field effect transistor Q2, the gate of the second field effect transistor Q2 is connected to the fifth pin of the seventh trigger U7, the source of the second field effect transistor Q2 is connected to one end of the seventeenth resistor R17 and the end of the fourth connector P4, and the other end of the eighth resistor R8, the other end of the seventeenth resistor R17 and the ground are connected.

[0018] like Figure 1 As shown, specifically, it also includes a nineteenth resistor R19, a twentieth resistor R20, a second switch S2, a third switch S3, a fifth connector P5, and a sixth connector P6; One end of the second switch S2 is connected to the in-phase end of the second operational amplifier U2, the other end of the second switch S2 is connected to one end of the twentieth resistor R20, the positive electrode of the second switch S2 is connected to the positive electrode of the third switch S3 and the end of the sixth connector P6, one end of the third switch S3 is connected to the inverting end of the second operational amplifier U2, the other end of the third switch S3 is connected to one end of the nineteenth resistor R19, the other end of the twentieth resistor R20 is connected to the end of the fifth connector P5, the negative electrode of the second switch S2, the negative electrode of the third switch S3, and the other end of the nineteenth resistor R19 are connected to the ground end.

[0019] like Figure 1 As shown, specifically, a sixteenth resistor R16 is also included; One end of the sixteenth resistor R16 is connected to the gate of the second field effect transistor Q2, and the other end of the sixteenth resistor R16 is connected to the ground.

[0020] like Figure 1 As shown, specifically, the tenth resistor R10 is an adjustable resistor.

[0021] The technical principle of the present invention: see the attached Figure 1, the low-power mode signal is fed back by the main control MCU or the user. When the function chip obtains the low-power mode signal feedback, it enters the sleep mode to make its internal components in the lowest power consumption. When the function chip obtains the low-power mode signal feedback, the signal is synchronously fed back to the first connector P1, and the signal at the first connector P1 end is fed back to the third pin of the seventh trigger U7. The second connector P2 end is used to receive the real-time power signal of the function chip. The first pin of the seventh trigger U7 is the reset end, the second pin is the data input end, the third pin is the clock input end, the fourth pin is the set end, and the fifth pin and the sixth pin are the signal output ends. In the initial state, the sixth pin of the seventh trigger U7 is a high level, and the fifth pin of the seventh trigger U7 is a low level. When the first connector P1 end obtains the signal, the levels of the sixth pin and the fifth pin of the seventh trigger U7 are replaced with each other, and the fifth pin of the seventh trigger U7 is a high level. The power input end of the first switch S1 obtains the signal feedback, the first switch S1 is closed, and the signal at the second connector P2 end is fed back to the third operational amplifier U3 and the first operational amplifier U4 through the first switch S1. The in-phase end of an operational amplifier U1, the fifteenth resistor R15 is a pull-down resistor of the in-phase end of the third operational amplifier U3 and the first operational amplifier U1, the output end of the third operational amplifier U3 is negatively feedback connected to the inverting end of the third operational amplifier U3 through the sixth resistor R6, the output end of the third operational amplifier U3 follows the signal at the second connector P2 end, when the amplitude of the signal at the output end of the third operational amplifier U3 is higher than a certain amplitude, the first voltage zener diode D1 is broken down to keep the amplitude of the signal at the output end of the third operational amplifier U3 unchanged, the output end signal of the third operational amplifier U3 when the first voltage zener diode D1 is broken down is a reference signal, the amplitude of the reference signal is the minimum operating voltage allowed by the functional chip, the output end of the first operational amplifier U1 is negatively feedback connected to the inverting end of the first operational amplifier U1 through the twelfth resistor R12, the first operational amplifier U1 follows the signal at the second connector P2 end, the output end signal of the first operational amplifier U1 is the real-time power supply signal of the functional chip, thereby providing the reference signal and the real-time power supply signal obtained by the functional chip to the subsequent circuit when the low-power mode signal is fed back.

[0022] Considering that when the functional chip is in sleep mode, lowering the power supply signal of the chip to its minimum operating voltage can further reduce the power consumption of the entire device. The power supply signal passes through the eleventh resistor R11 and the tenth resistor R10 to the ground terminal. The signal at the end of the tenth resistor R10 is a positive compensation signal of the reference signal. The signal amplitude is higher than the reference signal amplitude, which is used to prevent the voltage of the power supply signal obtained by the functional chip from being lower than the minimum allowable minimum operating voltage when the power supply fluctuates, causing damage to the chip. The signal amplitude at the end of the tenth resistor R10 is changed by adjusting the resistance value of the tenth resistor R10. The resistance value of the tenth resistor R10 can be set as needed. The signal at the end of the tenth resistor R10 is fed back to the in-phase terminal of the second operational amplifier U2 through the first resistor R1. The signal at the output terminal of the third operational amplifier U3 is fed back to the in-phase terminal of the second operational amplifier U2 through the ninth resistor R9. The signal at the output terminal of the second operational amplifier U2 passes through the second resistor R2 and the thirteenth resistor R13 to the ground terminal. The signal at the thirteenth resistor R13 is fed back to the in-phase terminal of the second operational amplifier U2. The first operational amplifier U1 output terminal signal is fed back to the sixth operational amplifier U6 non-inverting terminal, the second operational amplifier U2 output terminal signal is fed back to the sixth operational amplifier U6 inverting terminal, the sixth operational amplifier U6 output terminal signal is fed back to the ground terminal via the fourteenth resistor R14, the fourteenth resistor R14 terminal signal is the power regulation signal of the power regulation module to the functional chip in the low power consumption mode, the signal is fed back to the power regulation module via the third connector P3, when the power regulation module obtains the signal feedback, the power signal amplitude obtained by the functional chip is lowered, when the power signal amplitude obtained by the functional chip is within the compensated reference signal amplitude, the sixth operational amplifier U6 is cut off, the power regulation module stops regulating, so that when the functional chip is in sleep mode, the power supply signal of the chip is reduced to its reference signal after forward compensation to further reduce the power consumption of the entire device.

[0023] Taking into account that the other devices may cause instantaneous interference to the device when starting, so that the amplitude of the instantaneous fluctuation of the power signal obtained by the functional chip is lower than the minimum operating voltage of the functional chip, it is necessary to increase the power signal obtained by the functional chip to prevent the chip from being damaged. The power signal passes through the fifth resistor R5, the second diode D2, and the eighth resistor R8 to the ground terminal. The signal at the eighth resistor R8 end is fed back to the in-phase terminal of the fifth operational amplifier U5. The signal at the output end of the third operational amplifier U3 passes through the base of the first transistor Q1, the emitter of the first transistor Q1, the fourth resistor R4, and the light-emitting diode in the fourth coupling module U4 to the ground terminal. The fourth coupling module U4 is coupled, and the photosensitive transistor in the fourth coupling module U4 is turned on. The source signal passes through the fifth resistor R5, the fourth coupling module U4, and the seventh resistor R7 to the ground terminal. The signal at the end of the seventh resistor R7 is fed back to the inverting terminal of the fifth operational amplifier U5. The signal amplitude obtained at the in-phase terminal of the fifth operational amplifier U5 is the signal amplitude of the collector terminal signal of the photosensitive transistor in the fourth coupling module U4 after the voltage drop of the second diode D2. The inverting terminal of the fifth operational amplifier U5 obtains the emission terminal signal of the photosensitive transistor in the fourth coupling module U4. When the actual power signal of the functional chip is higher than its minimum operating voltage amplitude, the fifth operational amplifier U5 is in a cut-off state. When the actual power signal of the functional chip is lower than its minimum operating voltage amplitude, the first voltage regulator diode D1 cannot be broken down. , the signal at the end of the third operational amplifier U3 follows the actual power signal change, the power signal obtained by the light-emitting diode in the fourth coupling module U4 is reduced, so that the signal amplitude of the emitter end of the photosensitive transistor in the fourth coupling module U4 is higher than the signal amplitude of the collector end of the photosensitive transistor in the fourth coupling module U4 after the voltage drop of the second diode D2, the fifth operational amplifier U5 outputs, the fifth pin end signal of the seventh trigger U7 is fed back to the gate of the second field effect transistor Q2, the voltage difference between the gate and the source of the second field effect transistor Q2 is higher than the conduction threshold, the second field effect transistor Q2 is turned on, the output end signal of the fifth operational amplifier U5 passes through the second field effect transistor Q2 and the seventeenth resistor R17 to the ground end, the seventeenth resistor R17 The end signal is the power regulation signal of the power regulation module to the functional chip in the low power consumption mode. When the power regulation module obtains the signal feedback, the amplitude of the power signal obtained by the functional chip is increased. When the interference ends, the output end of the third operational amplifier U3 is restored to the reference signal amplitude, and the actual power signal obtained by the functional chip is higher than the compensated reference signal. The sixth operational amplifier U6 outputs again, and the power regulation module performs a callback. In this way, when the device is subjected to instantaneous interference and the amplitude of the instantaneous fluctuation of the power signal obtained by the functional chip is lower than the minimum operating voltage of the functional chip, the power signal obtained by the functional chip is increased to prevent the chip from being damaged, and the amplitude is restored to the reference signal amplitude after positive compensation after the interference ends.

[0024] The reference signal amplitude is changed by adjusting the model of the first voltage stabilizing diode D1. The signal amplitude is the minimum operating voltage amplitude allowed by the reference function chip. The reference function chip has the lowest lower threshold of the operating voltage threshold range among all function chips. When low power consumption adjustment is required for another function chip, the main control MCU enables the first connector P1 and the second connector P2 in the circuit to obtain the low power state of the remaining function chips and the real-time power supply signal of the chip, and at the same time, the difference compensation signal of the minimum operating voltage between the reference function chip and another function chip that needs low power consumption adjustment is fed back through the fifth connector P5. The signal is fed back to the fifth Connector P5, and the main control MCU feeds back the switching signal to the sixth connector P6, the signal at the end of the sixth connector P6 is fed back to the power input end of the second switch S2 and the third switch S3, the second switch S2 and the third switch S3 are closed, and the signal at the inverting end of the second operational amplifier U2 is fed back to the ground end via the third switch S3 and the nineteenth resistor R19, and the difference compensation signal is fed back to the in-phase end of the second operational amplifier U2 via the twentieth resistor R20 and the second switch S2, so that the signal output from the output end of the second operational amplifier U2 is the reference signal after difference compensation and forward compensation, so that the circuit can perform low-power adjustment on all functional chips.

[0025] It is obvious to those skilled in the art that the present invention is not limited to the details of the above exemplary embodiments, and that the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention.

Claims

1. A low power consumption circuit of a power management chip, characterized in that: It includes a first operational amplifier, a third operational amplifier, a seventh trigger, a sixth resistor, a twelfth resistor, a fifteenth resistor, an eighteenth resistor, a first voltage stabilizing diode, a first switch, a first connector, and a second connector; The non-inverting end of the first operational amplifier is connected to one end of the first switch, the non-inverting end of the third operational amplifier, and one end of the fifteenth resistor, the other end of the first switch is connected to the second connector end, the inverting end of the first operational amplifier is connected to one end of the twelfth resistor, the output end of the first operational amplifier is connected to the other end of the twelfth resistor, the inverting end of the third operational amplifier is connected to one end of the sixth resistor, the output end of the third operational amplifier is connected to the cathode of the first voltage regulator diode and the other end of the sixth resistor, the first pin and the fourth pin of the seventh trigger are connected to the power supply, the third pin of the seventh trigger is connected to the first connector end, the second pin and the sixth pin of the seventh trigger are connected to one end of the eighteenth resistor, the fifth pin of the seventh trigger is connected to the positive electrode of the first switch, the first pin of the seventh trigger is the reset end, the second pin is the data input end, the third pin is the clock input end, the fourth pin is the set end, the fifth pin and the sixth pin are the signal output ends, the other end of the fifteenth resistor, the other end of the eighteenth resistor, the anode of the first voltage regulator diode, the negative electrode of the first switch and the ground end are connected.

2. The low power consumption circuit of the power management chip according to claim 1, characterized in that: Also includes a second operational amplifier, a sixth operational amplifier, a first resistor, a second resistor, a ninth resistor, a tenth resistor, an eleventh resistor, a thirteenth resistor, a fourteenth resistor, and a third connector; The non-inverting end of the second operational amplifier is connected to one end of the first resistor and one end of the ninth resistor, the inverting end of the second operational amplifier is connected to one end of the second resistor and one end of the thirteenth resistor, the output end of the second operational amplifier is connected to the other end of the second resistor and the inverting end of the sixth operational amplifier, the non-inverting end of the sixth operational amplifier is connected to the output end of the first operational amplifier, the output end of the sixth operational amplifier is connected to one end of the fourteenth resistor and the third connector end, the other end of the ninth resistor is connected to the cathode of the first voltage zener diode, one end of the eleventh resistor is connected to the power supply, the other end of the eleventh resistor is connected to the other end of the first resistor and one end of the tenth resistor, the other end of the tenth resistor, the other end of the thirteenth resistor, and the other end of the fourteenth resistor are connected to the ground.

3. The low power consumption circuit of the power management chip according to claim 2, characterized in that: It also includes a fourth coupling module, a first triode, a third resistor, a fourth resistor, a fifth resistor, a seventh resistor, and a second diode; The anode of the fourth coupling module is connected to one end of the fourth resistor, the collector of the fourth coupling module is connected to one end of the fifth resistor and the anode of the second diode, the emitter of the fourth coupling module is connected to one end of the seventh resistor, the collector of the first triode is connected to one end of the third resistor, the emitter of the first triode is connected to the other end of the fourth resistor, the base of the first triode is connected to the other end of the ninth resistor, the other end of the third resistor and the other end of the fifth resistor are connected to the power supply, and the cathode of the fourth coupling module and the other end of the seventh resistor are connected to the ground.

4. The low power consumption circuit of the power management chip according to claim 3, characterized in that: It also includes a fifth operational amplifier, a second field effect transistor, an eighth resistor, a seventeenth resistor, and a fourth connector; The in-phase end of the fifth operational amplifier is connected to the cathode of the second diode and one end of the eighth resistor, the inverting end of the fifth operational amplifier is connected to one end of the seventh resistor, the output end of the fifth operational amplifier is connected to the drain of the second field effect transistor, the gate of the second field effect transistor is connected to the fifth pin of the seventh trigger, the source of the second field effect transistor is connected to one end of the seventeenth resistor and the end of the fourth connector, and the other end of the eighth resistor, the other end of the seventeenth resistor and the ground end are connected.

5. The low power consumption circuit of the power management chip according to claim 2, characterized in that: Also includes a nineteenth resistor, a twentieth resistor, a second switch, a third switch, a fifth connector, and a sixth connector; One end of the second switch is connected to the in-phase end of the second operational amplifier, the other end of the second switch is connected to one end of the twentieth resistor, the positive electrode of the second switch is connected to the positive electrode of the third switch and the sixth connector end, one end of the third switch is connected to the inverting end of the second operational amplifier, the other end of the third switch is connected to one end of the nineteenth resistor, the other end of the twentieth resistor is connected to the fifth connector end, the negative electrode of the second switch, the negative electrode of the third switch, and the other end of the nineteenth resistor are connected to the ground end.

6. The low power consumption circuit of the power management chip according to claim 4, characterized in that: Also included is a sixteenth resistor; One end of the sixteenth resistor is connected to the gate of the second field effect transistor, and the other end of the sixteenth resistor is connected to the ground.

7. The low power consumption circuit of the power management chip according to claim 2, characterized in that: The tenth resistor is an adjustable resistor.

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