Task execution method based on domain-specific language and software development tool chain

Abstract

The invention relates to a task execution method based on a domain-specific language and a software development tool chain, and the method comprises the steps: carrying out the analysis and translation of an obtained source code through a domain-specific language compiler, and obtaining a first intermediate representation file obtained through the translation of a plurality of analyzed operators in a parallel mode, performing optimization processing on the first intermediate representation file according to each operator to obtain a second intermediate representation file; and compiling the second intermediate representation file by adopting a reconfigurable computing architecture to obtain a target code to indicate a reconfigurable processor to execute a task. According to the method, the operator in the parallel mode is optimized, and the generated second intermediate representation file is further processed, so that the execution efficiency can be improved, and the resource consumption during operation is reduced. And meanwhile, by using a specific language in the field, the codes are more expressive and intuitive, program errors caused by complex universal languages are reduced, and the readability and maintainability of the codes are improved.

Description

Technical Field

[0001] The present application relates to the technical field of programming language design, and in particular to a task execution method based on a domain-specific language and a software development tool chain. Background Art

[0002] As computing demands continue to grow, especially in the fields of artificial intelligence, data processing, and scientific computing, the demand for high-performance computing is becoming more and more urgent. Reconfigurable processors have gradually become an important platform to meet such demands due to their flexibility and high parallelism. However, despite the significant performance advantages of reconfigurable processors, existing programming methods and tools have also exposed many defects when facing this emerging technology.

[0003] In the current programming ecosystem, due to the lack of specific tools and patterns, developers find it difficult to effectively optimize computation and data flow when implementing parallel tasks, which ultimately leads to performance not being improved as expected. Summary of the invention

[0004] Based on this, it is necessary to provide a task execution method and a software development tool chain based on a domain-specific language that can improve the efficiency of task execution in response to the above technical problems.

[0005] In a first aspect, the present application provides a method for executing a task based on a domain-specific language. The method comprises:

[0006] A domain-specific language compiler is used to parse and translate the acquired source code to obtain a first intermediate representation file; the first intermediate representation file is obtained by translating the operators of the parsed multiple parallel modes;

[0007] Optimizing the first intermediate representation file according to each operator to obtain a second intermediate representation file;

[0008] The second intermediate representation file is compiled and processed using a reconfigurable computing architecture to obtain a target code; the target code is used to instruct the reconfigurable processor to execute a task.

[0009] In one embodiment, the above-mentioned optimizing the first intermediate representation file according to each operator to obtain the second intermediate representation file includes:

[0010] Obtaining a data set and an operation function in a first intermediate representation file;

[0011] The data set and the operation function are optimized according to each operator to obtain a second intermediate representation file.

[0012] In one embodiment, the above-mentioned operators include a mapping operator, a reduction operator and a scanning operator; the data set and the operation function are optimized according to each operator to obtain a second intermediate representation file, including:

[0013] A scanning operator is used to perform parallel scanning processing on the data set and the operation function to obtain a first set;

[0014] Using a mapping operator, mapping multiple elements in the first set is performed to obtain a second set;

[0015] A reduction operator is used to perform reduction processing on multiple elements of the second set to obtain a second intermediate representation file.

[0016] In one embodiment, the compiling of the second intermediate representation file to obtain the target code includes:

[0017] Performing recognition processing on the second intermediate representation file to obtain a recognition result; the recognition result includes multiple operators;

[0018] Perform conversion processing on multiple operators to obtain multiple kernel functions;

[0019] Multiple kernel functions and pre-built host codes are integrated to obtain target code.

[0020] In one embodiment, the above-mentioned integration of multiple kernel functions and pre-built host codes to obtain target codes includes:

[0021] Using host code, each kernel function is called and processed to obtain the kernel execution result;

[0022] The kernel execution results and the host code are integrated and processed to obtain the target code.

[0023] In one embodiment, the obtained source code is parsed and translated to obtain a first intermediate representation file, including:

[0024] Parsing the source code to obtain a first abstract syntax tree;

[0025] Correcting the first abstract syntax tree to obtain a second abstract syntax tree;

[0026] The second abstract syntax tree is subjected to code translation processing to obtain a first intermediate representation file.

[0027] In one embodiment, the code translation process of the second abstract syntax tree to obtain the first intermediate representation file includes:

[0028] Performing code translation processing on multiple nodes of the second abstract syntax tree to obtain multiple intermediate codes;

[0029] Mapping the structures of the second abstract syntax trees to obtain a plurality of intermediate file structures; the intermediate file structures include at least one of a function, a variable, and a control flow structure;

[0030] The intermediate codes and the intermediate file structures are integrated to obtain a first intermediate representation file.

[0031] In a second aspect, the present application also provides a task execution device based on a domain-specific language. The device includes:

[0032] A parsing and translating module is used to parse and translate the acquired source code using a domain-specific language compiler to obtain a first intermediate representation file; the first intermediate representation file is obtained by translating the operators of the parsed multiple parallel modes;

[0033] An optimization module, used for optimizing the first intermediate representation file according to each operator to obtain a second intermediate representation file;

[0034] The compiling module is used to compile the second intermediate representation file using a reconfigurable computing architecture to obtain a target code; the target code is used to instruct the reconfigurable processor to execute a task.

[0035] In a third aspect, the present application also provides a software development tool chain, which includes a domain-specific language compiler and a reconfigurable computing architecture compiler;

[0036] A domain-specific language compiler parses and translates the acquired source code to obtain a first intermediate representation file; the first intermediate representation file is obtained by translating the operators of the multiple parallel modes parsed; the first intermediate representation file is optimized according to each operator to obtain a second intermediate representation file;

[0037] The reconfigurable computing architecture is used to compile the second intermediate representation file to obtain a target code; the target code is used to instruct the reconfigurable processor to execute a task.

[0038] In a fourth aspect, the present application further provides a computer device. The computer device includes a memory and a processor, the memory stores a computer program, and the processor implements the following steps when executing the computer program:

[0039] A domain-specific language compiler is used to parse and translate the acquired source code to obtain a first intermediate representation file; the first intermediate representation file is obtained by translating the operators of the parsed multiple parallel modes;

[0040] Optimizing the first intermediate representation file according to each operator to obtain a second intermediate representation file;

[0041] The second intermediate representation file is compiled and processed using a reconfigurable computing architecture to obtain a target code; the target code is used to instruct the reconfigurable processor to execute a task.

[0042] In a fifth aspect, the present application further provides a computer-readable storage medium. The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the following steps are implemented:

[0043] A domain-specific language compiler is used to parse and translate the acquired source code to obtain a first intermediate representation file; the first intermediate representation file is obtained by translating the operators of the multiple parallel modes that are parsed;

[0044] Optimizing the first intermediate representation file according to each operator to obtain a second intermediate representation file;

[0045] The second intermediate representation file is compiled and processed using a reconfigurable computing architecture to obtain a target code; the target code is used to instruct the reconfigurable processor to execute a task.

[0046] In a sixth aspect, the present application further provides a computer program product. The computer program product includes a computer program, and when the computer program is executed by a processor, the following steps are implemented:

[0047] A domain-specific language compiler is used to parse and translate the acquired source code to obtain a first intermediate representation file; the first intermediate representation file is obtained by translating the operators of the multiple parallel modes that are parsed;

[0048] Optimizing the first intermediate representation file according to each operator to obtain a second intermediate representation file;

[0049] The second intermediate representation file is compiled and processed using a reconfigurable computing architecture to obtain a target code; the target code is used to instruct the reconfigurable processor to execute a task.

[0050] The above-mentioned task execution method based on domain-specific language and software development tool chain use a domain-specific language compiler to parse and translate the acquired source code to obtain a first intermediate representation file translated from the parsed multiple parallel mode operators, and then optimize the first intermediate representation file according to each operator to obtain a second intermediate representation file; the second intermediate representation file is compiled using a reconfigurable computing architecture to obtain a target code to instruct the reconfigurable processor to execute the task. This application can optimize the parallel mode operators by parsing and translating the acquired source code, and the generated second intermediate representation file can improve execution efficiency and reduce resource consumption at runtime after further processing. At the same time, the use of domain-specific languages ​​makes the code more expressive and intuitive, reduces program errors caused by complex general languages, and improves the readability and maintainability of the code. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] Figure 1 An application environment diagram of a task execution method based on a domain specific language in one embodiment;

[0052] Figure 2 A flowchart of a method for executing a task based on a domain specific language in one embodiment;

[0053] Figure 3 A schematic diagram of a process of obtaining a second intermediate representation file in one embodiment;

[0054] Figure 4 A schematic diagram of a process of obtaining a second intermediate representation file in another embodiment;

[0055] Figure 5 A schematic diagram of a process for obtaining a target code in one embodiment;

[0056] Figure 6 A schematic diagram of a flow chart for obtaining target code in another embodiment;

[0057] Figure 7 A schematic diagram of a process of obtaining a first intermediate representation file in one embodiment;

[0058] Figure 8 A schematic diagram of a process of obtaining a first intermediate representation file in another embodiment;

[0059] Fig. 9 is a structural block diagram of a task execution device based on a domain specific language in one embodiment;

[0060] Fig.10 is a block diagram of the internal structure of a software development tool chain in one embodiment;

[0061] Fig.11FIG. 4 is a diagram showing the internal structure of a computer device in one embodiment. DETAILED DESCRIPTION

[0062] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0063] First of all, before specifically introducing the technical solution of the embodiments of the present application, the technical background based on the embodiments of the present application is introduced.

[0064] As computing tasks become increasingly complex and diverse, traditional fixed-function processors are unable to meet the ever-changing needs. Reconfigurable processors have gradually become an important means to solve this problem due to their flexible hardware structure and programmable characteristics. In order to better utilize the flexibility of reconfigurable processors, researchers have begun to explore hybrid programming models that support multiple programming models. Different types of applications may be suitable for different programming models, such as scientific computing, image processing, machine learning, etc. Traditional programming models such as instruction-level parallelism and data-level parallelism often work well for specific types of applications, while data flow programming models are more suitable for scenarios such as streaming data processing. Therefore, the emergence of hybrid programming models can better meet the needs of different applications.

[0065] Programming language and compilation technology: The hybrid programming model needs to support multiple programming languages ​​and needs corresponding compilation technology to map high-level language codes to the underlying hardware structure. Therefore, programming language design and compilation technology are important technical fields of the hybrid programming model.

[0066] Runtime system: The hybrid programming model requires a flexible runtime system that can dynamically schedule tasks, manage resources, and support concurrent execution of multiple programming models. Therefore, the design and optimization of the runtime system is also one of the key technical areas of the hybrid programming model.

[0067] Hardware architecture design: The hybrid programming model needs to support multiple computing and communication modes, so a flexible hardware architecture needs to be designed. This may involve designing multifunctional units, flexible on-chip interconnection networks, reconfigurable hardware resources, etc.

[0068] Related technology development:

[0069] Fusion of programming models: Researchers and engineers are constantly exploring ways to fuse different programming models together to achieve more flexible and efficient programming. For example, combining the dataflow programming model with the traditional instruction-level parallel programming model to fully utilize the parallel performance of reconfigurable processors.

[0070] Runtime system optimization: In response to the needs of hybrid programming models, researchers are constantly optimizing the runtime system to improve system performance and energy efficiency. For example, they design smarter task scheduling algorithms and resource management strategies to optimize concurrent execution of tasks and resource utilization.

[0071] Evolution of hardware architecture: As technology develops and requirements change, the hardware architecture of reconfigurable processors is also evolving. New hardware architectures may better support hybrid programming models, such as adding more computing units and improving communication architectures.

[0072] Programming complexity: For developers, mastering multiple programming models and combining them together may increase programming complexity. Writing code that works with mixed programming models may require more skills and experience.

[0073] Performance Challenges: In a hybrid programming model, tasks and resources need to be allocated reasonably to maximize the performance of the system. However, this may face challenges, such as task division and scheduling between different programming models may lead to performance degradation.

[0074] Difficulty debugging and optimizing: Mixed programming models may increase the complexity of debugging and optimization. Because of the involvement of multiple programming models and hardware resources, it may be more difficult to identify performance bottlenecks and optimize them.

[0075] Resource management: In a hybrid programming model, hardware resources need to be managed effectively, including computing units, memory, and communication networks. Proper allocation and management of these resources can be a challenge, especially when faced with complex applications and large-scale data sets.

[0076] Concurrency and synchronization: Different programming models may have different concurrency and synchronization mechanisms. In a mixed programming model, you need to ensure that concurrency and synchronization issues are handled correctly to avoid concurrency errors such as data races and deadlocks.

[0077] Performance predictability: Mixed programming models may affect performance predictability. Due to the involvement of multiple programming models and hardware resources, the performance of the system may be difficult to accurately predict, which may be a problem for some applications with strict performance requirements.

[0078] Software-hardware collaboration: In a hybrid programming model, the interaction and collaboration between software and hardware needs to be managed effectively. This may involve designing appropriate interfaces and communication mechanisms to ensure that the collaboration between software and hardware can be carried out efficiently.

[0079] Based on this, the present application provides a task execution method based on a domain-specific language and a software development tool chain, aiming to solve the above technical problems.

[0080] The task execution method based on domain specific language provided in the embodiment of the present application can be applied to Figure 1 In the application environment shown. Among them, the terminal 102 communicates with the server 104 through the network. The data storage system can store the data that the server 104 needs to process. The data storage system can be integrated on the server 104, or it can be placed on the cloud or other network servers. A domain-specific language compiler is used to parse and translate the acquired source code to obtain a first intermediate representation file translated from the operators of the parsed multiple parallel modes, and then the first intermediate representation file is optimized according to each operator to obtain a second intermediate representation file; the second intermediate representation file is compiled using a reconfigurable computing architecture to obtain a target code to instruct the reconfigurable processor to perform the task. Among them, the terminal 102 can be but is not limited to various personal computers, laptops, smart phones and tablets. The server 104 can be implemented with an independent server or a server cluster consisting of multiple servers.

[0081] In an exemplary embodiment, Figure 2 As shown, the embodiment of the present application provides a task execution method based on a domain specific language, and the method is applied to Figure 1 The terminal in is taken as an example to illustrate, including the following S201 to S203. Among them:

[0082] S201, using a domain specific language compiler to parse and translate the acquired source code to obtain a first intermediate representation file.

[0083] The first intermediate representation file is obtained by translating the operators of the multiple parallel modes that are parsed.

[0084] In the embodiment of the present application, first, the user writes source code that meets the needs of a specific domain, and the code uses a domain-specific language to describe the task. Next, the source code is parsed and translated using a domain-specific language compiler. The compiler analyzes the syntax and semantics of the source code and identifies multiple parallel mode operators therein. In this process, the compiler generates a first intermediate representation file, which represents the parallel mode operators in a structured form, making subsequent processing feasible.

[0085] S202: Optimize the first intermediate representation file according to each operator to obtain a second intermediate representation file.

[0086] In the embodiment of the present application, the first intermediate representation file generated based on the above embodiment then enters the optimization stage. The compiler performs various optimization processes on the first intermediate representation file based on the characteristics of the operators and their mutual relationships in task execution, such as eliminating redundancy, adjusting data flow, improving memory usage, etc. After a series of optimizations, the second intermediate representation file is finally obtained, which has a significant improvement in execution efficiency and resource usage.

[0087] S203, compile the second intermediate representation file using the reconfigurable computing architecture to obtain a target code; the target code is used to instruct the reconfigurable processor to execute the task.

[0088] In the embodiment of the present application, after obtaining the second intermediate representation file based on the above embodiment, the system uses the reconfigurable computing architecture for compilation processing. At this stage, the compiler converts the second intermediate representation file into target code, which contains the low-level instruction set required by the reconfigurable processor to achieve efficient hardware execution. The target code finally generated instructs the reconfigurable processor to perform specific tasks and use its flexible hardware resources to efficiently complete the calculation.

[0089] The above-mentioned task execution method based on domain-specific language uses a domain-specific language compiler to parse and translate the acquired source code to obtain a first intermediate representation file translated from the parsed multiple parallel mode operators, and then optimizes the first intermediate representation file according to each operator to obtain a second intermediate representation file; the second intermediate representation file is compiled using a reconfigurable computing architecture to obtain a target code to instruct the reconfigurable processor to execute the task. The present application can optimize the parallel mode operators by parsing and translating the acquired source code, and the generated second intermediate representation file can improve execution efficiency and reduce resource consumption at runtime after further processing. At the same time, the use of domain-specific languages ​​makes the code more expressive and intuitive, reduces program errors caused by complex general languages, and improves the readability and maintainability of the code.

[0090] In an exemplary embodiment, based on the above embodiment, see Figure 3 The embodiment of the present application involves optimizing the first intermediate representation file according to each operator to obtain the second intermediate representation file, including the following S301 to S302. Among them:

[0091] S301, obtaining a data set and an operation function in a first intermediate representation file.

[0092] In the embodiment of the present application, the terminal first extracts data sets and operation functions from the generated first intermediate representation file. These data sets usually contain data to be processed, and the operation function is an algorithm or method for operating the data set. The system stores the data sets in a structured manner and creates a corresponding operation function call list to ensure that each data set has corresponding operation function support.

[0093] S302: Optimize the data set and the operation function according to each operator to obtain a second intermediate representation file.

[0094] In the embodiment of the present application, the key step of data processing is to optimize the extracted operation functions and data sets to improve execution efficiency. This step will use a specific optimization mechanism based on the characteristics of each operator. For example:

[0095] Operator fusion: Combine multiple operation functions into one to improve data access efficiency and reduce memory read and write times.

[0096] Loop unrolling: Unroll repeated operations to optimize execution time.

[0097] Avoid redundant calculations: Identify and remove unnecessary calculation steps by analyzing data dependencies.

[0098] After a series of optimization processes, the system generates a second intermediate representation file, which contains optimized data sets and operation functions, representing a more efficient computing process.

[0099] The embodiment of the present application improves the speed and efficiency of data operations, especially when processing large-scale data sets, the optimization mechanism significantly reduces the computing time. Through efficient operator optimization, the memory usage and the waste of computing resources are reduced, providing better performance for the system. The generated second intermediate representation file lays a good foundation for subsequent steps (such as compiling into target code), ensuring the efficiency of the final execution.

[0100] In an exemplary embodiment, based on the above embodiment, see Figure 4 The embodiment of the present application includes operators including mapping operators, reduction operators and scanning operators; the embodiment of the present application involves a process of optimizing a data set and an operation function according to each operator to obtain a second intermediate representation file, including the following S401 to S403. Among them:

[0101] S401, using a scanning operator to perform parallel scanning processing on a data set and an operation function to obtain a first set.

[0102] In the embodiment of the present application, the terminal uses a scanning operator to perform parallel scanning on the acquired data set and operation function. The scanning operator can effectively traverse the entire data set, combine each element with the corresponding operation function, and thus generate a processed element set. Through parallel processing, the system can calculate multiple data elements at the same time, significantly reducing the processing time and obtaining the first set. The first set contains the results of preliminary processing, has a better data structure and hierarchy, and is convenient for subsequent processing.

[0103] S402, using a mapping operator to perform mapping processing on multiple elements in the first set to obtain a second set.

[0104] In the embodiment of the present application, after obtaining the first set, the terminal then uses a mapping operator to map multiple elements in the first set. The mapping operator can convert each element in a set into a new form or value through a specified function. This process allows the data elements in the first set to form a second set after being converted by the function, and each element of the second set is the result of mapping the corresponding element in the first set, which expands the expression form of the data.

[0105] S403: Use a reduction operator to reduce multiple elements of the second set to obtain a second intermediate representation file.

[0106] In an embodiment of the present application, the terminal uses a reduction operator to reduce multiple elements in the second set. The reduction operator can aggregate multiple values ​​in the set into a single result through a specified operation function (such as summation, maximum value, etc.). At this stage, the system calculates the summary characteristics of the second set, generates the final output result, and saves it as a second intermediate representation file. This file not only contains the results generated by the reduction operation, but also reflects the efficiency and optimization of data processing.

[0107] In the embodiments of the present application, parallel scanning is used to significantly improve the execution efficiency of data processing, especially when facing large-scale data, the response speed is effectively improved. The combination of mapping and reduction operations not only enriches the data processing methods, but also makes the results more compact and easy to understand, which is helpful for subsequent data analysis and utilization. The generated second intermediate representation file provides an efficient and structured foundation for the subsequent computing process, and improves the availability and flexibility of execution.

[0108] In an exemplary embodiment, based on the above embodiment, see Figure 5 The embodiment of the present application involves compiling the second intermediate representation file, and the process of obtaining the target code includes the following S501 to S503. Among them:

[0109] S501, performing recognition processing on the second intermediate representation file to obtain a recognition result; the recognition result includes multiple operators.

[0110] In the embodiment of the present application, the terminal analyzes the file content line by line through parsing technology and pattern matching algorithm to obtain all relevant operator information. The recognition result includes multiple operators, which will serve as the basic unit of data processing and provide necessary information for subsequent steps.

[0111] S502: Perform conversion processing on multiple operators to obtain multiple kernel functions.

[0112] In the embodiment of the present application, after obtaining the recognition result, the system performs conversion processing on multiple operators. Each identified operator is converted into a corresponding kernel function through a defined conversion rule. The kernel function is a basic unit for performing specific calculations or data processing, and is usually optimized for a specific hardware architecture. The conversion process may include algorithm adjustment, data structure reorganization, etc. to ensure that the generated kernel function has the best execution performance.

[0113] S503, integrating the multiple kernel functions and the pre-built host code to obtain a target code.

[0114] In the embodiment of the present application, the terminal integrates multiple generated kernel functions with the pre-built host code. The integration process includes embedding the kernel function into the appropriate position of the host code to ensure the correctness of the data flow and control flow. The target code finally generated has efficient execution performance and can run smoothly on the specified hardware platform.

[0115] The embodiment of the present application improves the automation of the conversion from the intermediate representation file to the target code and reduces the need for manual intervention. The generated kernel function is optimized for specific hardware to ensure high-performance data processing capabilities. The integrated target code has a clear structure, is easy to maintain, and has good scalability, which can adapt to future functional expansion and optimization needs.

[0116] In an exemplary embodiment, based on the above embodiment, see Figure 6 The embodiment of the present application relates to a process of integrating multiple kernel functions and pre-built host codes to obtain target codes, including the following S601 to S602. Among them:

[0117] S601, using the host code to call and process each kernel function to obtain the kernel execution result.

[0118] In the embodiment of the present application, the terminal first uses the host code to call each kernel function. The kernel function is a high-performance function designed for a specific computing task and can be executed on a parallel computing platform such as a GPU. The host code is responsible for setting the parameters required for the kernel function, configuring computing resources, and calling the kernel function to start execution. During this process, the system collects the execution results of each kernel function, including the output data of the calculation and the running status information. Through parallel processing, the kernel function can take advantage of the parallelism of the hardware to quickly complete complex computing tasks and improve execution efficiency.

[0119] S602, integrating the kernel execution result and the host code to obtain the target code.

[0120] In the embodiment of the present application, after completing the call of the kernel function, the system integrates the kernel execution result with the host code. The purpose of the integration is to combine the result of the kernel calculation with the logic of the host code to form a complete calculation process. The integration process may include steps such as data format conversion, result verification, and final output preparation. After the integration process, all results and codes are optimized and easier to operate subsequently. Finally, the system generates a target code that combines optimizations in many aspects such as memory usage, computing efficiency, and algorithm performance to facilitate further execution and application.

[0121] The embodiment of the present application improves the overall computing performance. By effectively integrating the host code with the execution results of the kernel function, it can maximize the use of computing resources and achieve efficient parallel computing. The generated target code is optimized, has a clear logical structure and efficient data processing capabilities, can cope with complex computing tasks and big data scenarios, provides developers with a flexible code integration method, simplifies the program development process, and enhances the reusability and maintainability of the code.

[0122] In an exemplary embodiment, based on the above embodiment, see Figure 7 The embodiment of the present application relates to a process of parsing and translating the acquired source code to obtain a first intermediate representation file, including the following S701 to S703. Among them:

[0123] S701, parsing the source code to obtain a first abstract syntax tree;

[0124] In the embodiment of the present application,

[0125] S702: Correct the first abstract syntax tree to obtain a second abstract syntax tree.

[0126] In the embodiment of the present application,

[0127] S703: Perform code translation processing on the second abstract syntax tree to obtain a first intermediate representation file.

[0128] In the embodiment of the present application,

[0129] Embodiments of the present application

[0130] In an exemplary embodiment, based on the above embodiment, see Figure 8 The embodiment of the present application relates to a process of performing code translation processing on a second abstract syntax tree to obtain a first intermediate representation file, including the following S801 to S803. Among them:

[0131] S801, performing code translation processing on multiple nodes of the second abstract syntax tree to obtain multiple intermediate codes.

[0132] In the embodiment of the present application, the terminal uses a syntax analysis tool to analyze the structure of the source code line by line according to the grammar specification of the language, thereby constructing a corresponding AST. AST is a tree structure that reflects the syntax elements and hierarchical relationships of the source code and provides a basic data structure for subsequent processing.

[0133] S802: Mapping is performed on the structures of the second abstract syntax trees to obtain a plurality of intermediate file structures.

[0134] The intermediate file structure includes at least one of a function, a variable and a control flow structure.

[0135] In the embodiment of the present application, after obtaining the first abstract syntax tree, the system corrects it and generates a second abstract syntax tree. In this process, the system will check the integrity and accuracy of the AST, and automatically repair possible syntax errors and logical inconsistencies. At the same time, normalization operations will be performed to simplify the tree structure. Ultimately, the second abstract syntax tree will ensure higher accuracy and consistency, providing a clear structural foundation for subsequent code translation.

[0136] S803, integrating each intermediate code and each intermediate file structure to obtain a first intermediate representation file.

[0137] In the embodiment of the present application, after obtaining the second abstract syntax tree, the system performs code translation processing on it to generate a first intermediate representation file. This process involves converting each node and its structure in the AST into a target intermediate representation format to ensure that the semantic information of the source code is retained. The generated first intermediate representation file is usually an intermediate code or intermediate representation data format, which lays the foundation for subsequent optimization and generation of target code.

[0138] The embodiment of the present application improves the efficiency and accuracy of source code parsing, especially in the parsing of complex programs, reducing potential syntax errors and logic problems. The generated second abstract syntax tree can be better understood and operated, making the subsequent intermediate representation generation process smoother. The first intermediate representation file provides a good foundation for subsequent optimization and code generation, which helps to achieve efficient and maintainable final code.

[0139] In an exemplary embodiment, based on the above embodiment, the method of the embodiment of the present application further includes the following steps:

[0140] Step 1: Parse the source code to obtain a first abstract syntax tree; correct the first abstract syntax tree to obtain a second abstract syntax tree;

[0141] Step 2: performing code translation processing on multiple nodes of the second abstract syntax tree to obtain multiple intermediate codes; performing mapping processing on the structure of each second abstract syntax tree to obtain multiple intermediate file structures; and integrating each intermediate code and each intermediate file structure to obtain a first intermediate representation file;

[0142] Step 3: Obtain the data set and operation function in the first intermediate representation file; use the scanning operator to perform parallel scanning processing on the data set and the operation function to obtain the first set; use the mapping operator to map multiple elements in the first set to obtain the second set; use the reduction operator to reduce multiple elements of the second set to obtain the second intermediate representation file;

[0143] Step 4: performing recognition processing on the second intermediate representation file to obtain a recognition result; the recognition result includes multiple operators; performing conversion processing on the multiple operators to obtain multiple kernel functions;

[0144] Step 5: Use the host code to call each kernel function to obtain the kernel execution result; integrate the kernel execution result and the host code to obtain the target code.

[0145] It should be understood that, although the various steps in the flowcharts involved in the above-mentioned embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps does not have a strict order restriction, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-mentioned embodiments can include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0146] Based on the same inventive concept, the embodiment of the present application also provides a domain-specific language-based task execution device for implementing the above-mentioned domain-specific language-based task execution method. The implementation solution provided by the device to solve the problem is similar to the implementation solution recorded in the above-mentioned method, so the specific limitations in the one or more domain-specific language-based task execution device embodiments provided below can refer to the above-mentioned limitations on the domain-specific language-based task execution method, and will not be repeated here.

[0147] In one embodiment, Fig. 9 As shown, the embodiment of the present application provides a task execution device 900 based on a domain specific language, including:

[0148] The parsing and translating module 901 is used to parse and translate the acquired source code using a domain-specific language compiler to obtain a first intermediate representation file; the first intermediate representation file is obtained by translating the operators of the parsed multiple parallel modes;

[0149] An optimization module 902, configured to optimize the first intermediate representation file according to each operator to obtain a second intermediate representation file;

[0150] The compiling module 903 is used to compile the second intermediate representation file using the reconfigurable computing architecture to obtain a target code; the target code is used to instruct the reconfigurable processor to execute a task.

[0151] In one embodiment, the optimization module includes:

[0152] A data acquisition unit, used to acquire a data set and an operation function in a first intermediate representation file;

[0153] The optimization unit is used to optimize the data set and the operation function according to each operator to obtain a second intermediate representation file.

[0154] In one embodiment, the above-mentioned operator includes a mapping operator, a reduction operator and a scanning operator; the optimization unit includes:

[0155] A scanning subunit, configured to use a scanning operator to perform parallel scanning processing on the data set and the operation function to obtain a first set;

[0156] A mapping subunit, used to use a mapping operator to perform mapping processing on multiple elements in the first set to obtain a second set;

[0157] The reduction subunit is used to use a reduction operator to perform reduction processing on multiple elements of the second set to obtain a second intermediate representation file.

[0158] In one embodiment, the compilation module includes:

[0159] The recognition unit is used to perform recognition processing on the second intermediate representation file to obtain a recognition result; the recognition result includes multiple operators;

[0160] A conversion unit, used for performing conversion processing on multiple operators to obtain multiple kernel functions;

[0161] The integration unit is used to integrate multiple kernel functions and pre-built host codes to obtain target codes.

[0162] In one embodiment, the integration unit comprises:

[0163] The calling subunit is used to use the host code to call each kernel function and obtain the kernel execution result;

[0164] The integration subunit is used to integrate the kernel execution result and the host code to obtain the target code.

[0165] In one embodiment, the parsing and translation module includes:

[0166] A parsing unit, used for parsing the source code to obtain a first abstract syntax tree;

[0167] A correction unit, configured to perform correction processing on the first abstract syntax tree to obtain a second abstract syntax tree;

[0168] The translation unit is used to perform code translation processing on the second abstract syntax tree to obtain a first intermediate representation file.

[0169] In one embodiment, the translation unit includes:

[0170] A translation subunit, used for performing code translation processing on multiple nodes of the second abstract syntax tree to obtain multiple intermediate codes;

[0171] A mapping subunit, configured to map the structures of the second abstract syntax trees to obtain a plurality of intermediate file structures; the intermediate file structures comprising at least one of a function, a variable and a control flow structure;

[0172] The integration subunit is used to integrate each intermediate code and each intermediate file structure to obtain a first intermediate representation file.

[0173] Each module in the above-mentioned task execution device based on domain-specific language can be implemented in whole or in part by software, hardware and their combination. Each module can be embedded in or independent of the processor in the computer device in the form of hardware, or can be stored in the memory of the computer device in the form of software, so that the processor can call and execute the operations corresponding to each module above.

[0174] In one embodiment, the present application also provides a software development tool chain, such as Figure 8 As shown, the software development tool chain includes a domain-specific language compiler (DSL compiler), a reconfigurable computing architecture compiler (CGRA compiler), a model compiler (AI compiler), and a driver.

[0175] The language compiler is used to perform language translation processing on the initial compiler file to obtain an intermediate representation file; the reconfigurable computing architecture compiler is used to compile the intermediate representation file to obtain an executable file; the executable file is a file used for the execution of the reconfigurable computing architecture; the model compiler is used to generate the initial compiler file; the driver is used to drive the reconfigurable computing architecture to call the dynamic link library.

[0176] Specifically, the language compiler performs language translation processing on the initial compiler file to generate an intermediate representation file (IR). The language compiler includes grammar design, error handling, DSL compiler front end, semantic analysis, Parallel Patterns, IR design and support, IR Transformation, data flow analysis, loop optimization, parallel computing optimization and memory management.

[0177] The high-level language code written by the user, such as C / C++, Python, etc., is parsed by the language compiler and translated into an intermediate representation file. The intermediate representation file is an architecture-independent representation format that facilitates subsequent processing.

[0178] In the programming model for reconfigurable intelligent computing, concepts such as parallel computing, data flow processing, and task scheduling are usually involved to fully utilize the parallelism and flexibility of reconfigurable hardware. The programming model provides developers with an abstract, easy-to-understand and easy-to-use way to describe the parallelism and data flow of applications, so that developers can develop and optimize applications more conveniently. We designed a domain-specific language (DSL) embedded in the classic programming paradigm to describe the structure and behavior of programs. In the software tool chain for reconfigurable intelligent computing, IR plays the role of a bridge connecting different compiler stages and is the basis for compilers to optimize, transform, and generate target code. It is an intermediate representation that is independent of the hardware architecture and can flexibly represent the characteristics of different programming models and hardware architectures, thereby achieving unified optimization and transformation of different programming models and hardware architectures. At the same time, we will introduce a variety of identifiers at the DSL and IR levels to help the back-end compiler map and optimize the target hardware platform, so that it can generate efficient target code.

[0179] The reconfigurable computing architecture compiler further compiles the intermediate representation file to obtain an executable file. The reconfigurable computing architecture compiler can include: DFG docking, routing node layering, node mapping priority sorting, node topology, row and column register mapping, priority sorting pruning, local register autobiography and pre-mapping.

[0180] The compiler is responsible for optimizing the intermediate representation file and generating executable files for reconfigurable computing architectures (such as FPGAs) in the background. The executable files contain instruction sets for specific hardware and can be directly executed by the reconfigurable computing architecture.

[0181] The specific process includes: program preprocessing: sub-loop processing: eliminating or making special processing to sub-loops to ensure that CGRA is mappable; function processing: eliminating functions called in the loop body (embedded or equivalent code).

[0182] DFG generation: Front-end: Get llvm ir through llvm front-end. Generation: Perform DFG conversion on llvm ir without sub-loops and output equivalent DFG. Optimization: Optimization aims to reduce nodes and generate DFG runtime beats.

[0183] DFG mapping: CGRA structure: read CGRA structure, interconnection and other information through json file. TEC: Since the TEC structure is fixed, it is not stored and is only judged by interconnection. MAPPING: Find the subgraph isomorphism under the minimum II through VF3. Finally, generate assembly code.

[0184] Model compiler, used to generate initial compiler files. Model compiler can include: front end, middle end and back end.

[0185] Users can use the model compiler to create an initial compiled program file that matches the hardware characteristics based on application requirements. This process supports modeling and simulation to ensure that the generated program file can be efficiently executed on the reconfigurable computing architecture.

[0186] The upper layer of the AI ​​compiler is connected to various mainstream open source AI models (multiple front ends), while the back end can be connected to different hardware platforms (CUDA-NV GPU; OPENCL; LLVM-CPU) and specific chips (A100, AMD MI100).

[0187] After unifying different model inputs into IR of a higher abstraction level, it will perform a series of optimizations and function implementations. Some of these functions are not related to hardware but only to the algorithm model itself: such as removing redundant operators, fusing operators (such as conv+prelu), peephole optimization (converting conv1*1 to matmul operator), etc. Some are directly related to hardware features: such as operator fusion (conv+add (needs hardware support) add+add (SIMD chips such as NPU do not support direct fusion)), memory optimization (different chips have different sizes of on-chip memory, and the data size is different when tiling; some chip memories use multiple banks to increase bandwidth, in which case bankconflict needs to be avoided as much as possible), and graph segmentation (when the chip has a large on-chip memory, the model can be segmented into n subgraphs, and the overall intermediate outputs of some subgraphs remain in the on-chip memory. Reducing data in and out of DDR can effectively reduce power consumption and latency). The AI ​​compiler needs to perform these optimizations hierarchically and gradually, optimizing while lowering the IR abstraction level, and then lowering it, and then optimizing it again, until it is connected to the backend software stack.

[0188] Driver, which drives the reconfigurable computing architecture to call the dynamic link library. The driver may include: CGRA MCU subsystem driver, resource management thread, and Linux application.

[0189] The driver interacts with the interface of the reconfigurable computing architecture, allowing the executable file to dynamically load the required dynamic link library (DLL). The driver is responsible for calling library functions and managing resources to achieve fast data processing and computing task allocation.

[0190] For example, in a certain application scenario, developers need to implement an image processing algorithm. First, the corresponding initial compiler file is generated through the model compiler. Then, it is translated into an intermediate representation file using a language compiler. Then, with the help of the reconfigurable computing architecture compiler, the intermediate representation file is compiled into an executable file, which is finally run on the reconfigurable computing architecture, and the driver calls the acceleration module in the dynamic link library to complete the image processing task.

[0191] The software development tool chain of the embodiment of the present application realizes the full-process compilation and management from the language layer to the hardware layer, greatly improving the development efficiency of the reconfigurable computing architecture. Through the use of intermediate representation files and the call of dynamic link libraries, it systematically supports the needs of developers and enhances scalability and modularity.

[0192] In one embodiment, a computer device is provided. The computer device may be a terminal, and its internal structure diagram may be as follows: Fig.11 As shown. The computer device includes a processor, a memory, an input / output interface, a communication interface, a display unit and an input device. The processor, the memory and the input / output interface are connected through a system bus, and the communication interface, the display unit and the input device are connected to the system bus through the input / output interface. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The input / output interface of the computer device is used to exchange information between the processor and the external device. The communication interface of the computer device is used to communicate with an external terminal in a wired or wireless manner, and the wireless manner can be implemented through WIFI, a mobile cellular network, NFC (near field communication) or other technologies. When the computer program is executed by the processor, a task execution method based on a domain-specific language is implemented. The display unit of the computer device is used to form a visually visible picture, which can be a display screen, a projection device or a virtual reality imaging device. The display screen can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer device can be a touch layer covering the display screen, or a button, trackball or touchpad set on the computer device shell, or an external keyboard, touchpad or mouse.

[0193] Those skilled in the art will understand that Fig.11 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0194] In one embodiment, a computer device is provided, including a memory and a processor, wherein a computer program is stored in the memory, and when the processor executes the computer program, the following steps are implemented:

[0195] A domain-specific language compiler is used to parse and translate the acquired source code to obtain a first intermediate representation file; the first intermediate representation file is obtained by translating the operators of the multiple parallel modes that are parsed;

[0196] Optimizing the first intermediate representation file according to each operator to obtain a second intermediate representation file;

[0197] The second intermediate representation file is compiled and processed using a reconfigurable computing architecture to obtain a target code; the target code is used to instruct the reconfigurable processor to execute a task.

[0198] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0199] Obtaining a data set and an operation function in a first intermediate representation file;

[0200] The data set and the operation function are optimized according to each operator to obtain a second intermediate representation file.

[0201] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0202] A scanning operator is used to perform parallel scanning processing on the data set and the operation function to obtain a first set;

[0203] Using a mapping operator, mapping multiple elements in the first set is performed to obtain a second set;

[0204] A reduction operator is used to perform reduction processing on multiple elements of the second set to obtain a second intermediate representation file.

[0205] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0206] Performing recognition processing on the second intermediate representation file to obtain a recognition result; the recognition result includes multiple operators;

[0207] Perform conversion processing on multiple operators to obtain multiple kernel functions;

[0208] Multiple kernel functions and pre-built host codes are integrated to obtain target code.

[0209] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0210] Using host code, each kernel function is called and processed to obtain the kernel execution result;

[0211] The kernel execution results and the host code are integrated and processed to obtain the target code.

[0212] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0213] Parsing the source code to obtain a first abstract syntax tree;

[0214] Correcting the first abstract syntax tree to obtain a second abstract syntax tree;

[0215] The second abstract syntax tree is subjected to code translation processing to obtain a first intermediate representation file.

[0216] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0217] Performing code translation processing on multiple nodes of the second abstract syntax tree to obtain multiple intermediate codes;

[0218] Mapping the structures of the second abstract syntax trees to obtain a plurality of intermediate file structures; the intermediate file structures include at least one of a function, a variable, and a control flow structure;

[0219] The intermediate codes and the intermediate file structures are integrated to obtain a first intermediate representation file.

[0220] In one embodiment, a computer readable storage medium is provided, on which a computer program is stored, and when the computer program is executed by a processor, the following steps are implemented:

[0221] A domain-specific language compiler is used to parse and translate the acquired source code to obtain a first intermediate representation file; the first intermediate representation file is obtained by translating the operators of the multiple parallel modes that are parsed;

[0222] Optimizing the first intermediate representation file according to each operator to obtain a second intermediate representation file;

[0223] The second intermediate representation file is compiled and processed using a reconfigurable computing architecture to obtain a target code; the target code is used to instruct the reconfigurable processor to execute a task.

[0224] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0225] Obtaining a data set and an operation function in a first intermediate representation file;

[0226] The data set and the operation function are optimized according to each operator to obtain a second intermediate representation file.

[0227] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0228] A scanning operator is used to perform parallel scanning processing on the data set and the operation function to obtain a first set;

[0229] Using a mapping operator, mapping multiple elements in the first set is performed to obtain a second set;

[0230] A reduction operator is used to perform reduction processing on multiple elements of the second set to obtain a second intermediate representation file.

[0231] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0232] Performing recognition processing on the second intermediate representation file to obtain a recognition result; the recognition result includes multiple operators;

[0233] Perform conversion processing on multiple operators to obtain multiple kernel functions;

[0234] Multiple kernel functions and pre-built host codes are integrated to obtain target code.

[0235] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0236] Using host code, each kernel function is called and processed to obtain the kernel execution result;

[0237] The kernel execution results and the host code are integrated and processed to obtain the target code.

[0238] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0239] Parsing the source code to obtain a first abstract syntax tree;

[0240] Correcting the first abstract syntax tree to obtain a second abstract syntax tree;

[0241] The second abstract syntax tree is subjected to code translation processing to obtain a first intermediate representation file.

[0242] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0243] Performing code translation processing on multiple nodes of the second abstract syntax tree to obtain multiple intermediate codes;

[0244] Mapping the structures of the second abstract syntax trees to obtain a plurality of intermediate file structures; the intermediate file structures include at least one of a function, a variable, and a control flow structure;

[0245] The intermediate codes and the intermediate file structures are integrated to obtain a first intermediate representation file.

[0246] In one embodiment, a computer program product is provided, comprising a computer program, which, when executed by a processor, implements the following steps:

[0247] A domain-specific language compiler is used to parse and translate the acquired source code to obtain a first intermediate representation file; the first intermediate representation file is obtained by translating the operators of the multiple parallel modes that are parsed;

[0248] Optimizing the first intermediate representation file according to each operator to obtain a second intermediate representation file;

[0249] The second intermediate representation file is compiled and processed using a reconfigurable computing architecture to obtain a target code; the target code is used to instruct the reconfigurable processor to execute a task.

[0250] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0251] Obtaining a data set and an operation function in a first intermediate representation file;

[0252] The data set and the operation function are optimized according to each operator to obtain a second intermediate representation file.

[0253] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0254] A scanning operator is used to perform parallel scanning processing on the data set and the operation function to obtain a first set;

[0255] Using a mapping operator, mapping multiple elements in the first set is performed to obtain a second set;

[0256] A reduction operator is used to perform reduction processing on multiple elements of the second set to obtain a second intermediate representation file.

[0257] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0258] Performing recognition processing on the second intermediate representation file to obtain a recognition result; the recognition result includes multiple operators;

[0259] Perform conversion processing on multiple operators to obtain multiple kernel functions;

[0260] Multiple kernel functions and pre-built host codes are integrated to obtain target code.

[0261] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0262] Using host code, each kernel function is called and processed to obtain the kernel execution result;

[0263] The kernel execution results and the host code are integrated and processed to obtain the target code.

[0264] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0265] Parsing the source code to obtain a first abstract syntax tree;

[0266] Correcting the first abstract syntax tree to obtain a second abstract syntax tree;

[0267] The second abstract syntax tree is subjected to code translation processing to obtain a first intermediate representation file.

[0268] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0269] Performing code translation processing on multiple nodes of the second abstract syntax tree to obtain multiple intermediate codes;

[0270] Mapping the structures of the second abstract syntax trees to obtain a plurality of intermediate file structures; the intermediate file structures include at least one of a function, a variable, and a control flow structure;

[0271] The intermediate codes and the intermediate file structures are integrated to obtain a first intermediate representation file.

[0272] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with relevant laws, regulations and standards of relevant countries and regions.

[0273] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited to this. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, etc., but are not limited to this.

[0274] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0275] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A task execution method based on domain specific language, characterized in that: The method comprises: A domain-specific language compiler is used to parse and translate the acquired source code to obtain a first intermediate representation file; the first intermediate representation file is obtained by translating the operators of the parsed multiple parallel modes; Optimizing the first intermediate representation file according to each of the operators to obtain a second intermediate representation file; The second intermediate representation file is compiled using a reconfigurable computing architecture to obtain a target code; the target code is used to instruct the reconfigurable processor to execute a task.

2. The method according to claim 1, characterized in that The optimizing the first intermediate representation file according to each of the operators to obtain a second intermediate representation file comprises: Obtaining the data set and operation function in the first intermediate representation file; The data set and the operation function are optimized according to each of the operators to obtain the second intermediate representation file.

3. The method according to claim 2, characterized in that The operators include a mapping operator, a reduction operator and a scanning operator; the optimizing process of the data set and the operation function according to each of the operators to obtain the second intermediate representation file includes: Using the scanning operator, performing parallel scanning processing on the data set and the operation function to obtain a first set; Using the mapping operator, mapping a plurality of elements in the first set to obtain a second set; The reduction operator is used to perform reduction processing on multiple elements of the second set to obtain the second intermediate representation file.

4. The method according to claim 1, characterized in that: The compiling the second intermediate representation file to obtain the target code comprises: Performing recognition processing on the second intermediate representation file to obtain a recognition result; the recognition result includes a plurality of the operators; Performing conversion processing on the multiple operators to obtain multiple kernel functions; The plurality of kernel functions and the pre-built host code are integrated to obtain the target code.

5. The method according to claim 4, characterized in that The integrating the plurality of kernel functions and the pre-built host code to obtain the target code comprises: Using the host code, calling and processing each of the kernel functions to obtain a kernel execution result; The kernel execution result and the host code are integrated to obtain the target code.

6. The method according to claim 1, characterized in that The obtained source code is parsed and translated to obtain a first intermediate representation file, including: Parsing the source code to obtain a first abstract syntax tree; Correcting the first abstract syntax tree to obtain a second abstract syntax tree; The second abstract syntax tree is subjected to code translation processing to obtain the first intermediate representation file.

7. The method according to claim 6, characterized in that The performing code translation processing on the second abstract syntax tree to obtain the first intermediate representation file includes: Performing code translation processing on multiple nodes of the second abstract syntax tree to obtain multiple intermediate codes; Mapping the structures of each of the second abstract syntax trees to obtain a plurality of intermediate file structures; the intermediate file structures include at least one of a function, a variable, and a control flow structure; The intermediate codes and the intermediate file structures are integrated to obtain the first intermediate representation file.

8. A software development tool chain, characterized in that: The software development tool chain includes a domain specific language compiler and a reconfigurable computing architecture compiler; The domain-specific language compiler parses and translates the acquired source code to obtain a first intermediate representation file; the first intermediate representation file is obtained by translating the operators of the multiple parallel modes parsed; the first intermediate representation file is optimized according to each of the operators to obtain a second intermediate representation file; The reconfigurable computing architecture is used to compile the second intermediate representation file to obtain a target code; the target code is used to instruct the reconfigurable processor to execute a task.

9. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

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